diff options
-rw-r--r-- | board/oak/board.c | 8 | ||||
-rw-r--r-- | board/oak/board.h | 32 | ||||
-rw-r--r-- | board/oak/build.mk | 1 | ||||
-rw-r--r-- | board/oak/ec.tasklist | 3 | ||||
-rw-r--r-- | board/oak/usb_pd_policy.c | 349 | ||||
-rw-r--r-- | board/oak_pd/board.c | 5 | ||||
-rw-r--r-- | board/oak_pd/board.h | 9 | ||||
-rw-r--r-- | board/oak_pd/ec.tasklist | 3 | ||||
-rw-r--r-- | board/oak_pd/usb_pd_config.h | 316 | ||||
-rw-r--r-- | chip/stm32/usb_pd_phy.c | 2 | ||||
-rw-r--r-- | common/usb_pd_protocol.c | 3 |
11 files changed, 724 insertions, 7 deletions
diff --git a/board/oak/board.c b/board/oak/board.c index abbc1add0c..b902265b62 100644 --- a/board/oak/board.c +++ b/board/oak/board.c @@ -24,6 +24,7 @@ #include "switch.h" #include "task.h" #include "timer.h" +#include "usb_pd_tcpm.h" #include "util.h" #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) @@ -47,12 +48,15 @@ void ap_reset_interrupt(enum gpio_signal signal) void vbus_wake_interrupt(enum gpio_signal signal) { - CPRINTF("VBUS %d\n", gpio_get_level(signal)); + CPRINTF("VBUS %d\n", !gpio_get_level(signal)); + gpio_set_level(GPIO_USB_PD_VBUS_WAKE, + !gpio_get_level(GPIO_VBUS_WAKE_L)); + task_wake(TASK_ID_PD); } void pd_mcu_interrupt(enum gpio_signal signal) { - CPRINTF("PD INT\n"); + hook_call_deferred(tcpc_alert, 0); } #include "gpio_list.h" diff --git a/board/oak/board.h b/board/oak/board.h index 90d88653c0..6f6a1ee2ee 100644 --- a/board/oak/board.h +++ b/board/oak/board.h @@ -31,6 +31,13 @@ #define CONFIG_PMIC_FW_LONG_PRESS_TIMER #define CONFIG_POWER_BUTTON #define CONFIG_POWER_COMMON +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_CUSTOM_VDM +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_PORT_COUNT 1 +#define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_SPI #define CONFIG_STM_HWTIMER32 #define CONFIG_VBOOT_HASH @@ -45,6 +52,9 @@ #undef CONFIG_UART_TX_DMA #undef CONFIG_UART_RX_DMA +#undef DEFERRABLE_MAX_COUNT +#define DEFERRABLE_MAX_COUNT 9 + /* * Allow dangerous commands. * TODO: Remove this config before production. @@ -76,6 +86,7 @@ #define I2C_PORT_CHARGER 0 #define I2C_PORT_PD_MCU 1 #define I2C_PORT_USB_SWITCH 1 +#define I2C_PORT_TCPC 1 /* Timer selection */ #define TIM_CLOCK32 2 @@ -96,6 +107,27 @@ enum pwm_channel { PWM_CH_COUNT }; +enum adc_channel { + ADC_CH_COUNT +}; + +/* start as a sink in case we have no other power supply/battery */ +#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED + +/* TODO: determine the following board specific type-C power constants */ +/* + * delay to turn on the power supply max is ~16ms. + * delay to turn off the power supply max is about ~180ms. + */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* Define typical operating power and max power */ +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + /* Discharge battery when on AC power for factory test. */ int board_discharge_on_ac(int enable); diff --git a/board/oak/build.mk b/board/oak/build.mk index 6beb2374ba..5f438ea75f 100644 --- a/board/oak/build.mk +++ b/board/oak/build.mk @@ -11,3 +11,4 @@ CHIP_FAMILY := stm32f0 CHIP_VARIANT:= stm32f09x board-y = board.o battery.o extpower.o led.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/oak/ec.tasklist b/board/oak/ec.tasklist index 20cac3c317..5cc15a1cfe 100644 --- a/board/oak/ec.tasklist +++ b/board/oak/ec.tasklist @@ -23,4 +23,5 @@ TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \ - TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/oak/usb_pd_policy.c b/board/oak/usb_pd_policy.c new file mode 100644 index 0000000000..73bc31bce3 --- /dev/null +++ b/board/oak/usb_pd_policy.c @@ -0,0 +1,349 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "atomic.h" +#include "charge_manager.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_pd.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP) + +/* TODO: fill in correct source and sink capabilities */ +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(5000, 20000, 15000), + PDO_VAR(5000, 20000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +int pd_is_valid_input_voltage(int mv) +{ + return 1; +} + +int pd_check_requested_voltage(uint32_t rdo) +{ + int max_ma = rdo & 0x3FF; + int op_ma = (rdo >> 10) & 0x3FF; + int idx = rdo >> 28; + uint32_t pdo; + uint32_t pdo_ma; + + if (!idx || idx > pd_src_pdo_cnt) + return EC_ERROR_INVAL; /* Invalid index */ + + /* check current ... */ + pdo = pd_src_pdo[idx - 1]; + pdo_ma = (pdo & 0x3ff); + if (op_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much op current */ + if (max_ma > pdo_ma) + return EC_ERROR_INVAL; /* too much max current */ + + CPRINTF("Requested %d V %d mA (for %d/%d mA)\n", + ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, + ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10); + + return EC_SUCCESS; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +int pd_set_power_supply_ready(int port) +{ + /* + * TODO: this only works on port 0 for now. need to include + * charge manager to manage CHARGE_L + */ + if (port == 0) { + /* Disable charging */ + gpio_set_level(GPIO_USB_C0_CHARGE_L, 1); + /* Provide VBUS */ + gpio_set_level(GPIO_USB_C0_5V_OUT, 1); + } + return EC_SUCCESS; /* we are ready */ +} + +void pd_power_supply_reset(int port) +{ + /* + * TODO: this only works on port 0 for now. need to include + * charge manager to manage CHARGE_L + */ + if (port == 0) { + /* Disable VBUS */ + gpio_set_level(GPIO_USB_C0_5V_OUT, 0); + /* Enable charging */ + gpio_set_level(GPIO_USB_C0_CHARGE_L, 0); + } +} + +void pd_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge); +#endif + /* notify host of power info change */ +} + +void typec_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ +#ifdef CONFIG_CHARGE_MANAGER + struct charge_port_info charge; + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge); +#endif + + /* notify host of power info change */ +} + +int pd_snk_is_vbus_provided(int port) +{ + return !gpio_get_level(GPIO_VBUS_WAKE_L); +} + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_power_swap(int port) +{ + /* + * Allow power swap as long as we are acting as a dual role device, + * otherwise assume our role is fixed (not in S0 or console command + * to fix our role). + */ + return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* Allow data swap if we are a UFP, otherwise don't allow */ + return (data_role == PD_ROLE_UFP) ? 1 : 0; +} + +void pd_execute_data_swap(int port, int data_role) +{ +} + +void pd_check_pr_role(int port, int pr_role, int partner_pr_swap) +{ + /* If sink, and dual role toggling is on, then switch to source */ + if (partner_pr_swap && pr_role == PD_ROLE_SINK && + pd_get_dual_role() == PD_DRP_TOGGLE_ON) + pd_request_power_swap(port); +} + +void pd_check_dr_role(int port, int dr_role, int partner_dr_swap) +{ + /* If UFP, try to switch to DFP */ + if (partner_dr_swap && dr_role == PD_ROLE_UFP) + pd_request_data_swap(port); +} +/* ----------------- Vendor Defined Messages ------------------ */ +const struct svdm_response svdm_rsp = { + .identity = NULL, + .svids = NULL, + .modes = NULL, +}; + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + int cmd = PD_VDO_CMD(payload[0]); + uint16_t dev_id = 0; + int is_rw; + + /* make sure we have some payload */ + if (cnt == 0) + return 0; + + switch (cmd) { + case VDO_CMD_VERSION: + /* guarantee last byte of payload is null character */ + *(payload + cnt - 1) = 0; + CPRINTF("version: %s\n", (char *)(payload+1)); + break; + case VDO_CMD_READ_INFO: + case VDO_CMD_SEND_INFO: + /* copy hash */ + if (cnt == 7) { + dev_id = VDO_INFO_HW_DEV_ID(payload[6]); + is_rw = VDO_INFO_IS_RW(payload[6]); + + CPRINTF("DevId:%d.%d SW:%d RW:%d\n", + HW_DEV_ID_MAJ(dev_id), + HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), + is_rw); + } else if (cnt == 6) { + /* really old devices don't have last byte */ + pd_dev_store_rw_hash(port, dev_id, payload + 1, + SYSTEM_IMAGE_UNKNOWN); + } + break; + case VDO_CMD_CURRENT: + CPRINTF("Current: %dmA\n", payload[1]); + break; + case VDO_CMD_FLIP: + /* board_flip_usb_mux(port); */ + break; +#ifdef CONFIG_USB_PD_LOGGING + case VDO_CMD_GET_LOG: + pd_log_recv_vdm(port, cnt, payload); + break; +#endif /* CONFIG_USB_PD_LOGGING */ + } + + return 0; +} + +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +static int dp_flags[CONFIG_USB_PD_PORT_COUNT]; + +static void svdm_safe_dp_mode(int port) +{ + /* make DP interface safe until configure */ + dp_flags[port] = 0; + /* board_set_usb_mux(port, TYPEC_MUX_NONE, pd_get_polarity(port)); */ +} + +static int svdm_enter_dp_mode(int port, uint32_t mode_caps) +{ + /* Only enter mode if device is DFP_D capable */ + if (mode_caps & MODE_DP_SNK) { + svdm_safe_dp_mode(port); + return 0; + } + + return -1; +} + +static int svdm_dp_status(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_STATUS | VDO_OPOS(opos)); + payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON)), + 0, /* power low? ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON))); + return 2; +}; + +static int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + /* board_set_usb_mux(port, TYPEC_MUX_DP, pd_get_polarity(port)); */ + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(MODE_DP_PIN_E, /* sink pins */ + MODE_DP_PIN_E, /* src pins */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +static void svdm_dp_post_config(int port) +{ + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; +} + +static int svdm_dp_attention(int port, uint32_t *payload) +{ + /* ack */ + return 1; +} + +static void svdm_exit_dp_mode(int port) +{ + svdm_safe_dp_mode(port); + /* gpio_set_level(PORT_TO_HPD(port), 0); */ +} + +static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) +{ + /* Always enter GFU mode */ + return 0; +} + +static void svdm_exit_gfu_mode(int port) +{ +} + +static int svdm_gfu_status(int port, uint32_t *payload) +{ + /* + * This is called after enter mode is successful, send unstructured + * VDM to read info. + */ + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0); + return 0; +} + +static int svdm_gfu_config(int port, uint32_t *payload) +{ + return 0; +} + +static int svdm_gfu_attention(int port, uint32_t *payload) +{ + return 0; +} + +const struct svdm_amode_fx supported_modes[] = { + { + .svid = USB_SID_DISPLAYPORT, + .enter = &svdm_enter_dp_mode, + .status = &svdm_dp_status, + .config = &svdm_dp_config, + .post_config = &svdm_dp_post_config, + .attention = &svdm_dp_attention, + .exit = &svdm_exit_dp_mode, + }, + { + .svid = USB_VID_GOOGLE, + .enter = &svdm_enter_gfu_mode, + .status = &svdm_gfu_status, + .config = &svdm_gfu_config, + .attention = &svdm_gfu_attention, + .exit = &svdm_exit_gfu_mode, + } +}; +const int supported_modes_cnt = ARRAY_SIZE(supported_modes); +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/board/oak_pd/board.c b/board/oak_pd/board.c index 4583d9fdc7..261fdf55cf 100644 --- a/board/oak_pd/board.c +++ b/board/oak_pd/board.c @@ -15,6 +15,7 @@ #include "registers.h" #include "system.h" #include "task.h" +#include "usb_pd.h" #include "util.h" #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) @@ -34,9 +35,7 @@ void pd_send_ec_int(void) void vbus0_evt(enum gpio_signal signal) { -#ifdef HAS_TASK_PD_C0 - task_wake(TASK_ID_PD_C0); -#endif + task_wake(TASK_ID_PD); } void vbus1_evt(enum gpio_signal signal) diff --git a/board/oak_pd/board.h b/board/oak_pd/board.h index 15c8cc5f0e..ac3d6eae64 100644 --- a/board/oak_pd/board.h +++ b/board/oak_pd/board.h @@ -53,6 +53,11 @@ #undef CONFIG_UART_TX_DMA #undef CONFIG_UART_RX_DMA #define CONFIG_UART_TX_BUF_SIZE 128 +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_INTERNAL_COMP +#define CONFIG_USB_PD_PORT_COUNT 1 +#define CONFIG_USB_PD_TCPC +#define CONFIG_USBC_VCONN #define CONFIG_VBOOT_HASH #undef CONFIG_WATCHDOG #undef CONFIG_WATCHDOG_HELP @@ -89,6 +94,10 @@ enum adc_channel { ADC_CH_COUNT }; +/* 1.5A Rp */ +#define PD_SRC_VNC PD_SRC_1_5_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV + #endif /* !__ASSEMBLER__ */ #endif /* __BOARD_H */ diff --git a/board/oak_pd/ec.tasklist b/board/oak_pd/ec.tasklist index c5b5933dd8..c001ade46f 100644 --- a/board/oak_pd/ec.tasklist +++ b/board/oak_pd/ec.tasklist @@ -19,4 +19,5 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/oak_pd/usb_pd_config.h b/board/oak_pd/usb_pd_config.h new file mode 100644 index 0000000000..2f91727cb8 --- /dev/null +++ b/board/oak_pd/usb_pd_config.h @@ -0,0 +1,316 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "chip/stm32/registers.h" +#include "gpio.h" +#include "ec_commands.h" + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 16 +#define TIM_CLOCK_PD_RX_C0 1 +#define TIM_CLOCK_PD_TX_C1 15 +#define TIM_CLOCK_PD_RX_C1 3 + +/* Timer channel */ +#define TIM_TX_CCR_C0 1 +#define TIM_RX_CCR_C0 1 +#define TIM_TX_CCR_C1 2 +#define TIM_RX_CCR_C1 1 + +#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0) +#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0) + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1)) +#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0) + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1)) +#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1)) +#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0) +#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0) + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */ +#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) +static inline void spi_enable_clock(int port) +{ + if (port == 0) + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; + else + STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; +} + +/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */ +#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3) + +/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/ +/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1 +/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */ +#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1 + +#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0) +#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0) +#define TIM_CCR_CS 1 + +/* + * EXTI line 21 is connected to the CMP1 output, + * EXTI line 22 is connected to the CMP2 output, + * C0 uses CMP2, and C1 uses CMP1. + */ +#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22)) + +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */ +#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2) + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + if (port == 0) { + /* 40 MHz pin speed on SPI PB3&4, + * (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0; + /* 40 MHz pin speed on TIM16_CH1 (PB8), + * (USB_C0_TX_CLKOUT) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000; + } else { + /* 40 MHz pin speed on SPI PB13/14, + * (USB_C1_TX_CLKIN & USB_C1_CC1_TX_DATA) + */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000; + /* 40 MHz pin speed on TIM15_CH2 (PB15) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000; + } +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + if (port == 0) { + /* Reset SPI1 */ + STM32_RCC_APB2RSTR |= (1 << 12); + STM32_RCC_APB2RSTR &= ~(1 << 12); + } else { + /* Reset SPI2 */ + STM32_RCC_APB1RSTR |= (1 << 14); + STM32_RCC_APB1RSTR &= ~(1 << 14); + } +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + if (port == 0) { + /* put SPI function on TX pin */ + if (polarity) { + /* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_A, 0x0040, 0); + /* MCU ADC PA4 pin output low */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*4))) /* PA4 disable ADC */ + | (1 << (2*4)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C0_CC2_PD, 0); + } else { + /* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, 0); + /* MCU ADC PA2 pin output low */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + & ~(3 << (2*2))) /* PA2 disable ADC */ + | (1 << (2*2)); /* Set as GPO */ + gpio_set_level(GPIO_USB_C0_CC1_PD, 0); + } + } else { + /* put SPI function on TX pin */ + /* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x4000, 0); + /* TODO: MCU ADC pin output low */ + /* + * There is a pin muxer to select CC1 or CC2 TX_DATA, + * Pin mux is controlled by USB_C1_CC2_TX_SEL pin, + * USB_C1_CC1_TX_DATA will be selected, if polarity is 0, + * USB_C1_CC2_TX_DATA will be selected, if polarity is 1 . + */ + gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity); + } +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + if (port == 0) { + /* output low on SPI TX to disable the FET */ + if (polarity) {/* PA6 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_A, 0x0040, -1); + /* TODO: Set MCU ADC PA4 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*4))) /* PA4 as ADC */ + & ~(1 << (2*4)); /* disable GPO */ + } else {/* PB4 is SPI1 MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, -1); + /* put the low level reference in Hi-Z */ + /* TODO: Set MCU ADC PA2 pin to ADC function (Hi-Z) */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) + | (3 << (2*2))) /* PA2 disable ADC */ + & ~(1 << (2*2)); /* Set as GPO */ + } + } else { + /* Select the pin according to the polarity */ + gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity); + /* output low on SPI TX to disable the FET */ + /* PB14 is SPI2 MISO */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*14))) /* Pin14 disable ADC */ + | (1 << (2*14)); /* Set as GPO */ + /* 00: Input mode (reset state) + * 01: General purpose output mode + * 10: Alternate function mode + * 11: Analog mode + */ + + /* put the low level reference in Hi-Z */ + /* TODO: Set MCU ADC pin to ADC function (Hi-Z) */ + } +} + +/* we know the plug polarity, do the right configuration */ +static inline void pd_select_polarity(int port, int polarity) +{ + uint32_t val = STM32_COMP_CSR; + + /* Use window mode so that COMP1 and COMP2 share non-inverting input */ + val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN; + + if (port == 0) { + /* C0 use the right comparator inverted input for COMP2 */ + STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | + (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ + : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ + } else { + /* C1 use the right comparator inverted input for COMP1 */ + STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | + (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ + : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ + } +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} +static inline void pd_set_host_mode(int port, int enable) +{ + if (port == 0) { + if (enable) { + /* Pull up for host mode */ + gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT); + gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1); + /* High-Z is used for host mode. */ + gpio_set_level(GPIO_USB_C0_CC1_ODL, 1); + gpio_set_level(GPIO_USB_C0_CC2_ODL, 1); + /* Set TX Hi-Z */ + gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT); + gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT); + } else { + /* Set HOST_HIGH to High-Z for device mode. */ + gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT); + /* Pull low for device mode. */ + gpio_set_level(GPIO_USB_C0_CC1_ODL, 0); + gpio_set_level(GPIO_USB_C0_CC2_ODL, 0); + } + } else { + if (enable) { + /* Pull up for host mode */ + gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT); + gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1); + /* High-Z is used for host mode. */ + gpio_set_level(GPIO_USB_C1_CC1_ODL, 1); + gpio_set_level(GPIO_USB_C1_CC2_ODL, 1); + gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); + } else { + /* Set HOST_HIGH to High-Z for device mode. */ + gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT); + /* Pull low for device mode. */ + gpio_set_level(GPIO_USB_C1_CC1_ODL, 0); + gpio_set_level(GPIO_USB_C1_CC2_ODL, 0); + } + } +} + +/** + * Initialize various GPIOs and interfaces to safe state at start of pd_task. + * + * These include: + * VBUS, charge path based on power role. + * Physical layer CC transmit. + * VCONNs disabled. + * + * @param port USB-C port number + * @param power_role Power role of device + */ +static inline void pd_config_init(int port, uint8_t power_role) +{ + /* + * Set CC pull resistors, and charge_en and vbus_en GPIOs to match + * the initial role. + */ + pd_set_host_mode(port, power_role); + + /* Initialize TX pins and put them in Hi-Z */ + pd_tx_init(); + + if (port == 0) { + gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0); + gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0); + } else { + gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0); + gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0); + } +} + +static inline int pd_adc_read(int port, int cc) +{ + if (port == 0) + return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD); + else + return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD); +} + +static inline void pd_set_vconn(int port, int polarity, int enable) +{ + /* Set VCONN on the opposite CC line from the polarity */ + if (port == 0) { + gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN : + GPIO_USB_C0_CC2_VCONN1_EN, enable); + /* Set TX_DATA pin to Hi-Z */ + gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA : + GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT); + } else { + gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN : + GPIO_USB_C1_CC2_VCONN1_EN, enable); + /* Set TX_DATA pin to Hi-Z */ + gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT); + } +} + +#endif /* __USB_PD_CONFIG_H */ diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index e3156e79d6..18f8da9938 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -536,6 +536,8 @@ void pd_hw_init_rx(int port) /* Timer ICx input configuration */ if (TIM_RX_CCR_IDX(port) == 1) phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0; + else if (TIM_RX_CCR_IDX(port) == 2) + phy->tim_rx->ccmr1 |= TIM_CCR_CS << 8; else if (TIM_RX_CCR_IDX(port) == 4) phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8; else diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c index ec0b441da7..0b86991349 100644 --- a/common/usb_pd_protocol.c +++ b/common/usb_pd_protocol.c @@ -2377,6 +2377,9 @@ void tcpc_alert(void) } } } +#ifndef CONFIG_USB_PD_TCPC +DECLARE_DEFERRED(tcpc_alert); +#endif #ifdef CONFIG_USB_PD_DUAL_ROLE static void dual_role_on(void) |