diff options
-rw-r--r-- | chip/stm32/config-stm32ts60.h | 33 | ||||
-rw-r--r-- | chip/stm32/config_chip.h | 3 | ||||
-rw-r--r-- | chip/stm32/registers.h | 22 |
3 files changed, 0 insertions, 58 deletions
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h deleted file mode 100644 index e284b0aa7c..0000000000 --- a/chip/stm32/config-stm32ts60.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x8000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 /* TODO */ -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* TODO erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* TODO minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002800 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 59 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 - -/* Only USART2 support */ -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 2 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 571f8ae015..fd69af32d7 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -36,9 +36,6 @@ #elif defined(CHIP_VARIANT_STM32F03X) /* STM32F03x */ #include "config-stm32f03x.h" -#elif defined(CHIP_VARIANT_STM32TS60) -/* STM32TS60 */ -#include "config-stm32ts60.h" #else #error "Unsupported chip variant" #endif diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 617abd98f9..a435a10173 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -68,11 +68,6 @@ #define STM32_IRQ_DMA_CHANNEL_5 15 #define STM32_IRQ_DMA_CHANNEL_6 16 #define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_DMA_CHANNEL_8 18 /* STM32TS60 only */ - -#ifdef CHIP_VARIANT_STM32TS60 -#define STM32_IRQ_ADC_1 21 -#endif #ifdef CHIP_VARIANT_STM32F373 #define STM32_IRQ_USB_HP 74 @@ -94,13 +89,10 @@ #endif #define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_ADC_2 22 /* STM32TS60 only */ #define STM32_IRQ_EXTI9_5 23 #define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_PMAD 24 /* STM32TS60 only */ #define STM32_IRQ_TIM15 24 /* STM32F373 only */ #define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_PMSE 25 /* STM32TS60 only */ #define STM32_IRQ_TIM16 25 /* STM32F373 only */ #define STM32_IRQ_TIM10 26 /* STM32L15X only */ #define STM32_IRQ_TIM17 26 /* STM32F373 only */ @@ -834,15 +826,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #endif /* --- ADC --- */ - -#if defined(CHIP_VARIANT_STM32TS60) -#define STM32_ADC1_BASE 0x40013800 -#define STM32_ADC2_BASE 0x40013c00 -#define STM32_ADC_BASE(x) (0x40013800 + 0x400 * (x)) -#else /* !CHIP_VARIANT_STM32TS60 */ #define STM32_ADC1_BASE 0x40012400 #define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#endif #if defined(CHIP_VARIANT_STM32F373) #define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) @@ -860,13 +845,6 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) #define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) #define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) -#elif defined(CHIP_VARIANT_STM32TS60) -#define STM32_ADC_SR(x) REG32(STM32_ADC_BASE(x) + 0x00) -#define STM32_ADC_CR1(x) REG32(STM32_ADC_BASE(x) + 0x04) -#define STM32_ADC_CR2(x) REG32(STM32_ADC_BASE(x) + 0x08) -#define STM32_ADC_SMPR2(x) REG32(STM32_ADC_BASE(x) + 0x10) -#define STM32_ADC_SQR3(x) REG32(STM32_ADC_BASE(x) + 0x34) -#define STM32_ADC_DR(x) REG32(STM32_ADC_BASE(x) + 0x4c) #elif defined(CHIP_FAMILY_STM32F0) #define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) #define STM32_ADC_ISR_ADRDY (1 << 0) |