summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
l---------board/lars_pd1
l---------board/lars_pd/Makefile1
-rw-r--r--board/lars_pd/board.c156
-rw-r--r--board/lars_pd/board.h121
-rw-r--r--board/lars_pd/build.mk16
-rw-r--r--board/lars_pd/ec.tasklist24
-rw-r--r--board/lars_pd/gpio.inc67
-rw-r--r--board/lars_pd/usb_pd_config.h327
8 files changed, 712 insertions, 1 deletions
diff --git a/board/lars_pd b/board/lars_pd
deleted file mode 120000
index eb83ce01b0..0000000000
--- a/board/lars_pd
+++ /dev/null
@@ -1 +0,0 @@
-glados_pd/ \ No newline at end of file
diff --git a/board/lars_pd/Makefile b/board/lars_pd/Makefile
new file mode 120000
index 0000000000..94aaae2c4d
--- /dev/null
+++ b/board/lars_pd/Makefile
@@ -0,0 +1 @@
+../../Makefile \ No newline at end of file
diff --git a/board/lars_pd/board.c b/board/lars_pd/board.c
new file mode 100644
index 0000000000..3dd7950759
--- /dev/null
+++ b/board/lars_pd/board.c
@@ -0,0 +1,156 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* lars_pd board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+
+/* Indicate which source is driving the ec_int line. */
+static uint32_t ec_int_status;
+
+static uint32_t pd_status_flags;
+
+void pd_send_ec_int(void)
+{
+ /* If any sources are active, then drive the line low */
+ gpio_set_level(GPIO_EC_INT, !ec_int_status);
+}
+
+void board_config_pre_init(void)
+{
+ /* enable SYSCFG clock */
+ STM32_RCC_APB2ENR |= 1 << 0;
+ /*
+ * the DMA mapping is :
+ * Chan 2 : TIM1_CH1 (C0 RX)
+ * Chan 3 : SPI1_TX (C0 TX)
+ * Chan 4 : TIM3_CH1 (C1 RX)
+ * Chan 5 : SPI2_TX (C1 TX)
+ */
+}
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+static void board_init(void)
+{
+ /* Enable interrupts on VBUS transitions. */
+ gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
+ gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
+
+ /* Set PD MCU system status bits */
+ if (system_jumped_to_this_image())
+ pd_status_flags |= PD_STATUS_JUMPED_TO_IMAGE;
+ if (system_get_image_copy() == SYSTEM_IMAGE_RW)
+ pd_status_flags |= PD_STATUS_IN_RW;
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+ /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+ [ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
+ [ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
+ [ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+ [ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+ {"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+void tcpc_alert(int port)
+{
+ /*
+ * This function is called when the TCPC sets one of
+ * bits in the Alert register and that bit's corresponding
+ * location in the Alert_Mask register is set.
+ */
+ atomic_or(&ec_int_status, port ?
+ PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
+ pd_send_ec_int();
+}
+
+void tcpc_alert_clear(int port)
+{
+ /*
+ * The TCPM has acknowledged all Alert bits and the
+ * Alert# line needs to be set inactive. Clear
+ * the corresponding port's bit in the static variable.
+ */
+ atomic_clear(&ec_int_status, port ?
+ PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
+ pd_send_ec_int();
+}
+
+static void system_hibernate_deferred(void)
+{
+ ccprintf("EC requested hibernate\n");
+ cflush();
+ system_hibernate(0, 0);
+}
+DECLARE_DEFERRED(system_hibernate_deferred);
+
+/****************************************************************************/
+/* Console commands */
+static int command_ec_int(int argc, char **argv)
+{
+ /* Indicate that ec_int gpio is active due to host command */
+ atomic_or(&ec_int_status, PD_STATUS_HOST_EVENT);
+ pd_send_ec_int();
+
+ return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
+ "",
+ "Toggle EC interrupt line",
+ NULL);
+
+static int ec_status_host_cmd(struct host_cmd_handler_args *args)
+{
+ const struct ec_params_pd_status *p = args->params;
+ struct ec_response_pd_status *r = args->response;
+
+ /*
+ * ec_int_status is used to store state for HOST_EVENT,
+ * TCPC 0 Alert, and TCPC 1 Alert bits.
+ */
+ r->status = ec_int_status | pd_status_flags;
+ args->response_size = sizeof(*r);
+
+ /* Have the PD follow the EC into hibernate. */
+ if (p->status & EC_STATUS_HIBERNATING)
+ hook_call_deferred(system_hibernate_deferred, 0);
+
+ /*
+ * If the source of the EC int line was HOST_EVENT, it has
+ * been acknowledged so can always clear HOST_EVENT bit
+ * from the ec_int_status variable
+ */
+ atomic_clear(&ec_int_status, PD_STATUS_HOST_EVENT);
+
+ return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_PD_EXCHANGE_STATUS, ec_status_host_cmd,
+ EC_VER_MASK(EC_VER_PD_EXCHANGE_STATUS));
+
diff --git a/board/lars_pd/board.h b/board/lars_pd/board.h
new file mode 100644
index 0000000000..6831979149
--- /dev/null
+++ b/board/lars_pd/board.h
@@ -0,0 +1,121 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* lars_pd board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/*
+ * The console task is too big to include in both RO and RW images. Therefore,
+ * if the console task is defined, then only build an RW image. This can be
+ * useful for debugging to have a full console. Otherwise, without this task,
+ * a full RO and RW is built with a limited one-way output console.
+ */
+#ifdef HAS_TASK_CONSOLE
+/*
+ * The flash size is only 32kB.
+ * No space for 2 partitions,
+ * put only RW at the beginning of the flash
+ */
+#undef CONFIG_FW_INCLUDE_RO
+#undef CONFIG_RW_MEM_OFF
+#define CONFIG_RW_MEM_OFF 0
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE 0
+/* Fake full size if we had a RO partition */
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
+#endif /* HAS_TASK_CONSOLE */
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#define CONFIG_ADC
+#undef CONFIG_ADC_WATCHDOG
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_COMMON_GPIO_SHORTNAMES
+#undef CONFIG_DEBUG_ASSERT
+#define CONFIG_FORCE_CONSOLE_RESUME
+#define CONFIG_HIBERNATE
+#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP2
+#undef CONFIG_HOSTCMD_EVENTS
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#define CONFIG_I2C_SLAVE
+#undef CONFIG_LID_SWITCH
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LTO
+#define CONFIG_STM_HWTIMER32
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
+#define CONFIG_UART_TX_BUF_SIZE 128
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_INTERNAL_COMP
+#define CONFIG_USB_PD_PORT_COUNT 2
+#define CONFIG_USB_PD_TCPC
+#define CONFIG_USB_PD_TCPM_VBUS
+#define CONFIG_USBC_VCONN
+#define CONFIG_VBOOT_HASH
+#define CONFIG_WATCHDOG
+#undef CONFIG_WATCHDOG_HELP
+
+#ifdef HAS_TASK_CONSOLE
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_CONSOLE_HISTORY 2
+
+#else
+#undef CONFIG_CONSOLE_CMDHELP
+#define CONFIG_DEBUG_PRINTF
+#define UARTN CONFIG_UART_CONSOLE
+#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
+#endif /* HAS_TASK_CONSOLE */
+
+/* Use PSTATE embedded in the RO image, not in its own erase block */
+#undef CONFIG_FLASH_PSTATE_BANK
+#undef CONFIG_FW_PSTATE_SIZE
+#define CONFIG_FW_PSTATE_SIZE 0
+
+/* I2C ports configuration */
+#define I2C_PORT_SLAVE 0
+#define I2C_PORT_EC I2C_PORT_SLAVE
+
+/* slave address for host commands */
+#ifdef HAS_TASK_HOSTCMD
+#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR CONFIG_USB_PD_I2C_SLAVE_ADDR
+#endif
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC 3
+
+#include "gpio_signal.h"
+
+/* ADC signal */
+enum adc_channel {
+ ADC_C1_CC1_PD = 0,
+ ADC_C0_CC1_PD,
+ ADC_C0_CC2_PD,
+ ADC_C1_CC2_PD,
+ /* Number of ADC channels */
+ ADC_CH_COUNT
+};
+
+/* 1.5A Rp */
+#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/lars_pd/build.mk b/board/lars_pd/build.mk
new file mode 100644
index 0000000000..ef1c9f1a91
--- /dev/null
+++ b/board/lars_pd/build.mk
@@ -0,0 +1,16 @@
+# -*- makefile -*-
+# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F051C8T
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f05x
+
+board-y=board.o
+
+# This target builds RW only. Therefore, remove RO from dependencies.
+all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/lars_pd/ec.tasklist b/board/lars_pd/ec.tasklist
new file mode 100644
index 0000000000..6401c10057
--- /dev/null
+++ b/board/lars_pd/ec.tasklist
@@ -0,0 +1,24 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+ TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+ /* TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) */ \
+ TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE) \
+ TASK_ALWAYS(PD_C1, pd_task, NULL, TASK_STACK_SIZE)
diff --git a/board/lars_pd/gpio.inc b/board/lars_pd/gpio.inc
new file mode 100644
index 0000000000..689b37d052
--- /dev/null
+++ b/board/lars_pd/gpio.inc
@@ -0,0 +1,67 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, pd_vbus_evt_p0)
+GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, pd_vbus_evt_p1)
+
+/* PD RX/TX */
+GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG)
+GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG)
+GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG)
+GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG)
+GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG)
+
+GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT)
+GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT)
+GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */
+GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT)
+GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT)
+
+GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH)
+GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW)
+GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW)
+GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW)
+GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW)
+
+GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW)
+GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW)
+GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW)
+GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW)
+GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
+GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
+
+#ifdef BOARD_OAK_PD
+GPIO(EC_INT, PIN(B, 5), GPIO_OUT_HIGH)
+#else
+GPIO(EC_INT, PIN(A, 14), GPIO_OUT_HIGH)
+#endif
+
+UNIMPLEMENTED(WP_L)
+UNIMPLEMENTED(ENTERING_RW)
+
+#if 0
+/* Alternate functions */
+GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW)
+GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW)
+GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW)
+GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW)
+#endif
+
+ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
+ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
+ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */
+ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
+ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */
diff --git a/board/lars_pd/usb_pd_config.h b/board/lars_pd/usb_pd_config.h
new file mode 100644
index 0000000000..8df3f84dc1
--- /dev/null
+++ b/board/lars_pd/usb_pd_config.h
@@ -0,0 +1,327 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "chip/stm32/registers.h"
+#include "gpio.h"
+#include "ec_commands.h"
+
+/* USB Power delivery board configuration */
+
+#ifndef __CROS_EC_USB_PD_CONFIG_H
+#define __CROS_EC_USB_PD_CONFIG_H
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX_C0 16
+#define TIM_CLOCK_PD_RX_C0 1
+#define TIM_CLOCK_PD_TX_C1 15
+#define TIM_CLOCK_PD_RX_C1 3
+
+/* Timer channel */
+#define TIM_TX_CCR_C0 1
+#define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C1 2
+#define TIM_RX_CCR_C1 1
+
+#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0)
+#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0)
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1))
+#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0)
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1))
+#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1))
+#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0)
+#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0)
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */
+#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
+static inline void spi_enable_clock(int port)
+{
+ if (port == 0)
+ STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+ else
+ STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
+}
+
+/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */
+#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3)
+
+/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
+/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */
+#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
+/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */
+#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
+
+#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
+#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
+#define TIM_CCR_CS 1
+
+/*
+ * EXTI line 21 is connected to the CMP1 output,
+ * EXTI line 22 is connected to the CMP2 output,
+ * C0 uses CMP2, and C1 uses CMP1.
+ */
+#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
+
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */
+#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2)
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(int port)
+{
+ if (port == 0) {
+ /* 40 MHz pin speed on SPI PB3&4,
+ * (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA)
+ */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
+ /* 40 MHz pin speed on TIM16_CH1 (PB8),
+ * (USB_C0_TX_CLKOUT)
+ */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
+ } else {
+ /* 40 MHz pin speed on SPI PB13/14,
+ * (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA)
+ */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
+ /* 40 MHz pin speed on TIM15_CH2 (PB15) */
+ STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
+ }
+}
+
+/* Reset SPI peripheral used for TX */
+static inline void pd_tx_spi_reset(int port)
+{
+ if (port == 0) {
+ /* Reset SPI1 */
+ STM32_RCC_APB2RSTR |= (1 << 12);
+ STM32_RCC_APB2RSTR &= ~(1 << 12);
+ } else {
+ /* Reset SPI2 */
+ STM32_RCC_APB1RSTR |= (1 << 14);
+ STM32_RCC_APB1RSTR &= ~(1 << 14);
+ }
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int port, int polarity)
+{
+ if (port == 0) {
+ /* put SPI function on TX pin */
+ if (polarity) {
+ /* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */
+ gpio_set_alternate_function(GPIO_A, 0x0040, 0);
+ /* MCU ADC PA4 pin output low */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ & ~(3 << (2*4))) /* PA4 disable ADC */
+ | (1 << (2*4)); /* Set as GPO */
+ gpio_set_level(GPIO_USB_C0_CC2_PD, 0);
+ } else {
+ /* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */
+ gpio_set_alternate_function(GPIO_B, 0x0010, 0);
+ /* MCU ADC PA2 pin output low */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ & ~(3 << (2*2))) /* PA2 disable ADC */
+ | (1 << (2*2)); /* Set as GPO */
+ gpio_set_level(GPIO_USB_C0_CC1_PD, 0);
+ }
+ } else {
+ /* put SPI function on TX pin */
+ /* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */
+ gpio_set_alternate_function(GPIO_B, 0x4000, 0);
+ /* MCU ADC pin output low */
+ if (polarity) {
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ & ~(3 << (2*5))) /* PA5 disable ADC */
+ | (1 << (2*5)); /* Set as GPO */
+ gpio_set_level(GPIO_USB_C1_CC2_PD, 0);
+ } else {
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ & ~(3 << (2*0))) /* PA0 disable ADC */
+ | (1 << (2*0)); /* Set as GPO */
+ gpio_set_level(GPIO_USB_C1_CC1_PD, 0);
+ }
+
+ /*
+ * There is a pin muxer to select CC1 or CC2 TX_DATA,
+ * Pin mux is controlled by USB_C1_CC2_TX_SEL pin,
+ * USB_C1_CC1_TX_DATA will be selected, if polarity is 0,
+ * USB_C1_CC2_TX_DATA will be selected, if polarity is 1 .
+ */
+ gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity);
+ }
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int port, int polarity)
+{
+ if (port == 0) {
+ if (polarity) {
+ /* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ & ~(3 << (2*6)));
+ /* set ADC PA4 pin to ADC function (Hi-Z) */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ | (3 << (2*4))); /* PA4 as ADC */
+ } else {
+ /* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */
+ STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
+ & ~(3 << (2*4)));
+ /* set ADC PA2 pin to ADC function (Hi-Z) */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ | (3 << (2*2))); /* PA2 as ADC */
+ }
+ } else {
+ /* Set TX_DATA (PB14) Hi-Z */
+ STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
+ & ~(3 << (2*14)));
+ if (polarity) {
+ /* set ADC PA5 pin to ADC function (Hi-Z) */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ | (3 << (2*5))); /* PA5 as ADC */
+ } else {
+ /* set ADC PA0 pin to ADC function (Hi-Z) */
+ STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+ | (3 << (2*0))); /* PA0 as ADC */
+ }
+ }
+}
+
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int port, int polarity)
+{
+ uint32_t val = STM32_COMP_CSR;
+
+ /* Use window mode so that COMP1 and COMP2 share non-inverting input */
+ val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
+
+ if (port == 0) {
+ /* C0 use the right comparator inverted input for COMP2 */
+ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
+ (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */
+ : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
+ } else {
+ /* C1 use the right comparator inverted input for COMP1 */
+ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
+ (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */
+ : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
+ }
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+ gpio_config_module(MODULE_USB_PD, 1);
+}
+static inline void pd_set_host_mode(int port, int enable)
+{
+ if (port == 0) {
+ if (enable) {
+ /* Pull up for host mode */
+ gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT);
+ gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1);
+ /* High-Z is used for host mode. */
+ gpio_set_level(GPIO_USB_C0_CC1_ODL, 1);
+ gpio_set_level(GPIO_USB_C0_CC2_ODL, 1);
+ /* Set TX Hi-Z */
+ gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT);
+ gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
+ } else {
+ /* Set HOST_HIGH to High-Z for device mode. */
+ gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT);
+ /* Pull low for device mode. */
+ gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
+ gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
+ }
+ } else {
+ if (enable) {
+ /* Pull up for host mode */
+ gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT);
+ gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1);
+ /* High-Z is used for host mode. */
+ gpio_set_level(GPIO_USB_C1_CC1_ODL, 1);
+ gpio_set_level(GPIO_USB_C1_CC2_ODL, 1);
+ /* Set TX Hi-Z */
+ gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
+ } else {
+ /* Set HOST_HIGH to High-Z for device mode. */
+ gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT);
+ /* Pull low for device mode. */
+ gpio_set_level(GPIO_USB_C1_CC1_ODL, 0);
+ gpio_set_level(GPIO_USB_C1_CC2_ODL, 0);
+ }
+ }
+}
+
+/**
+ * Initialize various GPIOs and interfaces to safe state at start of pd_task.
+ *
+ * These include:
+ * VBUS, charge path based on power role.
+ * Physical layer CC transmit.
+ * VCONNs disabled.
+ *
+ * @param port USB-C port number
+ * @param power_role Power role of device
+ */
+static inline void pd_config_init(int port, uint8_t power_role)
+{
+ /*
+ * Set CC pull resistors, and charge_en and vbus_en GPIOs to match
+ * the initial role.
+ */
+ pd_set_host_mode(port, power_role);
+
+ /* Initialize TX pins and put them in Hi-Z */
+ pd_tx_init();
+
+ if (port == 0) {
+ gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0);
+ gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0);
+ } else {
+ gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0);
+ gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0);
+ }
+}
+
+static inline int pd_adc_read(int port, int cc)
+{
+ if (port == 0)
+ return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
+ else
+ return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD);
+}
+
+static inline void pd_set_vconn(int port, int polarity, int enable)
+{
+ /* Set VCONN on the opposite CC line from the polarity */
+ if (port == 0) {
+ gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN :
+ GPIO_USB_C0_CC2_VCONN1_EN, enable);
+ /* Set TX_DATA pin to Hi-Z */
+ gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA :
+ GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
+ } else {
+ gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN :
+ GPIO_USB_C1_CC2_VCONN1_EN, enable);
+ /* Set TX_DATA pin to Hi-Z */
+ gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
+ }
+}
+
+#endif /* __CROS_EC_USB_PD_CONFIG_H */
+
View Lorry Controller Status