diff options
-rw-r--r-- | board/eve/board.h | 2 | ||||
-rw-r--r-- | board/kahlee/board.h | 2 | ||||
-rw-r--r-- | board/kevin/board.h | 2 | ||||
-rw-r--r-- | board/npcx_evb/board.c | 17 | ||||
-rw-r--r-- | board/npcx_evb/board.h | 11 | ||||
-rw-r--r-- | board/npcx_evb/gpio.inc | 18 | ||||
-rw-r--r-- | board/npcx_evb_arm/board.h | 2 | ||||
-rw-r--r-- | board/poppy/board.h | 2 | ||||
-rw-r--r-- | board/reef/board.h | 2 | ||||
-rw-r--r-- | board/wheatley/board.h | 2 | ||||
-rw-r--r-- | chip/npcx/gpio.c | 8 | ||||
-rw-r--r-- | chip/npcx/registers.h | 11 |
12 files changed, 57 insertions, 22 deletions
diff --git a/board/eve/board.h b/board/eve/board.h index 39c29957de..e9949f91e7 100644 --- a/board/eve/board.h +++ b/board/eve/board.h @@ -171,7 +171,7 @@ /* Optional feature to configure npcx chip */ #define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ #define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 diff --git a/board/kahlee/board.h b/board/kahlee/board.h index 8e76d2c4c0..a81e4fb2ee 100644 --- a/board/kahlee/board.h +++ b/board/kahlee/board.h @@ -159,7 +159,7 @@ /* Optional feature - used by nuvoton */ #define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ #define I2C_PORT_THERMAL NPCX_I2C_PORT1 diff --git a/board/kevin/board.h b/board/kevin/board.h index b84d9efd37..28a54b5f65 100644 --- a/board/kevin/board.h +++ b/board/kevin/board.h @@ -168,7 +168,7 @@ /* Optional feature - used by nuvoton */ #define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ #define NPCX_SHI_CS_PU #define NPCX_SHI_BYPASS_OVER_256B diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c index 570d615d01..cca0692a85 100644 --- a/board/npcx_evb/board.c +++ b/board/npcx_evb/board.c @@ -46,6 +46,9 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, +#if (CONFIG_FANS == 2) + [PWM_CH_FAN2] = { 2, 0, 25000 }, +#endif [PWM_CH_KBLIGHT] = { 1, 0, 10000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -62,6 +65,17 @@ const struct fan_t fans[] = { .pgood_gpio = GPIO_PGOOD_FAN, .enable_gpio = -1, }, +#if (CONFIG_FANS == 2) + [FAN_CH_1] = { + .flags = FAN_USE_RPM_MODE, + .rpm_min = 1000, + .rpm_start = 1000, + .rpm_max = 4300, + .ch = 1,/* Use MFT id to control fan */ + .pgood_gpio = -1, + .enable_gpio = -1, + }, +#endif }; BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); @@ -69,6 +83,9 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /* MFT channels. These are logically separate from mft_channels. */ const struct mft_t mft_channels[] = { [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, +#if (CONFIG_FANS == 2) + [MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2}, +#endif }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h index 265a5544e3..4ca106bf8c 100644 --- a/board/npcx_evb/board.h +++ b/board/npcx_evb/board.h @@ -45,7 +45,7 @@ /* Optional feature - used by nuvoton */ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Optional for testing */ #undef CONFIG_PSTORE @@ -66,6 +66,9 @@ enum adc_channel { enum pwm_channel { PWM_CH_FAN, +#if (CONFIG_FANS == 2) + PWM_CH_FAN2, +#endif PWM_CH_KBLIGHT, /* Number of PWM channels */ PWM_CH_COUNT @@ -73,12 +76,18 @@ enum pwm_channel { enum fan_channel { FAN_CH_0, +#if (CONFIG_FANS == 2) + FAN_CH_1, +#endif /* Number of FAN channels */ FAN_CH_COUNT }; enum mft_channel { MFT_CH_0, +#if (CONFIG_FANS == 2) + MFT_CH_1, +#endif /* Number of MFT channels */ MFT_CH_COUNT }; diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc index 25454bd7fb..9259b7bb5f 100644 --- a/board/npcx_evb/gpio.inc +++ b/board/npcx_evb/gpio.inc @@ -73,13 +73,21 @@ ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO ALTERNATE(PIN_MASK(C, 0x04), 1, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */ /* Alternative functionality for FANS */ #ifdef CONFIG_FANS -ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */ +ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */ #if NPCX_TACH_SEL2 -ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */ +ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* TA1_SL2 GPIO93 for tachometer input */ #else -ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */ -#endif -#endif +ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* TA1_SL1 GPIO40 for tachometer input */ +#endif /* NPCX_TACH_SEL2 */ +#if (CONFIG_FANS == 2) +ALTERNATE(PIN_MASK(C, 0x10), 1, MODULE_PWM, 0) /* PWM2 for PWM/FAN Test GPIOC4 */ +#if NPCX_TACH_SEL2 +ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0) /* TA2_SL2 GPIOA6 for tachometer input */ +#else +ALTERNATE(PIN_MASK(7, 0x08), 1, MODULE_PWM, 0) /* TA2_SL1 GPIO73 for tachometer input */ +#endif /* NPCX_TACH_SEL2 */ +#endif /* (CONFIG_FANS == 2) */ +#endif /* CONFIG_FANS */ /* Keyboard Columns */ ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, 0) diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index 932aa663f0..dae3af8fb0 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -42,7 +42,7 @@ /* Optional feature - used by nuvoton */ #define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ #define NPCX_SHI_CS_PU /* Enable bypass since shi outputs invalid data when across 256B boundary */ diff --git a/board/poppy/board.h b/board/poppy/board.h index c70d2c3fa6..150dd2f99f 100644 --- a/board/poppy/board.h +++ b/board/poppy/board.h @@ -154,7 +154,7 @@ /* Optional feature to configure npcx chip */ #define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ #define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 diff --git a/board/reef/board.h b/board/reef/board.h index c5e246bbe6..4e6666d28b 100644 --- a/board/reef/board.h +++ b/board/reef/board.h @@ -183,7 +183,7 @@ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ /* FIXME(dhendrix): these pins are just normal GPIOs on Reef. Do we need * to change some other setting to put them in GPIO mode? */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ #define I2C_PORT_GYRO NPCX_I2C_PORT1 diff --git a/board/wheatley/board.h b/board/wheatley/board.h index aea3a287ea..cb38371f7b 100644 --- a/board/wheatley/board.h +++ b/board/wheatley/board.h @@ -102,7 +102,7 @@ #define NPCX_I2C0_BUS2 0 /* 0:GPIOB4/B5 1:GPIOB2/B3 as I2C0 */ #define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ #define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* * Allow dangerous commands. diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index d49872c808..a9706ba787 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -105,11 +105,11 @@ const struct gpio_alt_map gpio_alt_table[] = { { NPCX_GPIO(6, 0), NPCX_ALT(4, PWM7_SL)}, /* PWM7 */ /* MFT Module */ #if NPCX_TACH_SEL2 - { NPCX_GPIO(9, 3), NPCX_ALT(C, TA1_TACH1_SL2)},/* TA1_TACH1 */ - { NPCX_GPIO(D, 3), NPCX_ALT(C, TB1_TACH2_SL2)},/* TB1_TACH2 */ + { NPCX_GPIO(9, 3), NPCX_ALT(C, TA1_SL2)},/* TA1_SEL2 */ + { NPCX_GPIO(A, 6), NPCX_ALT(C, TA2_SL2)},/* TA2_SEL2 */ #else - { NPCX_GPIO(4, 0), NPCX_ALT(3, TA1_TACH1_SL1)},/* TA1_TACH1 */ - { NPCX_GPIO(A, 4), NPCX_ALT(3, TB1_TACH2_SL1)},/* TB1_TACH2 */ + { NPCX_GPIO(4, 0), NPCX_ALT(3, TA1_SL1)},/* TA1_SEL1 */ + { NPCX_GPIO(7, 3), NPCX_ALT(3, TA2_SL1)},/* TA2_SEL1 */ #endif /* Keyboard Scan Module (Inputs) */ { NPCX_GPIO(3, 1), NPCX_ALT_INV(7, NO_KSI0_SL)},/* KSI0 */ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3144117b97..2f263de0a0 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -526,8 +526,8 @@ enum { #define NPCX_DEVALT3_PS2_1_SL 1 #define NPCX_DEVALT3_PS2_2_SL 2 #define NPCX_DEVALT3_PS2_3_SL 3 -#define NPCX_DEVALT3_TA1_TACH1_SL1 4 -#define NPCX_DEVALT3_TB1_TACH2_SL1 5 +#define NPCX_DEVALT3_TA1_SL1 4 +#define NPCX_DEVALT3_TB1_SL1 5 #define NPCX_DEVALT3_TA2_SL1 6 #define NPCX_DEVALT3_TB2_SL1 7 @@ -591,8 +591,8 @@ enum { #define NPCX_DEVALTC_UART_SL2 0 #define NPCX_DEVALTC_SHI_SL 1 #define NPCX_DEVALTC_PS2_3_SL2 3 -#define NPCX_DEVALTC_TA1_TACH1_SL2 4 -#define NPCX_DEVALTC_TB1_TACH2_SL2 5 +#define NPCX_DEVALTC_TA1_SL2 4 +#define NPCX_DEVALTC_TB1_SL2 5 #define NPCX_DEVALTC_TA2_SL2 6 #define NPCX_DEVALTC_TB2_SL2 7 @@ -791,7 +791,8 @@ enum NPCX_PMC_PWDWN_CTL_T { /* TODO: set PD masks based upon actual peripheral usage */ #define CGC_KBS_MASK (1 << NPCX_PWDWN_CTL1_KBS_PD) #define CGC_UART_MASK (1 << NPCX_PWDWN_CTL1_UART_PD) -#define CGC_FAN_MASK (1 << NPCX_PWDWN_CTL1_MFT1_PD) +#define CGC_FAN_MASK ((1 << NPCX_PWDWN_CTL1_MFT1_PD) | \ + (1 << NPCX_PWDWN_CTL1_MFT2_PD)) #define CGC_FIU_MASK (1 << NPCX_PWDWN_CTL1_FIU_PD) #define CGC_I2C_MASK ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \ (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \ |