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-rw-r--r--chip/lm4/adc.c8
-rw-r--r--chip/lm4/gpio.c2
-rw-r--r--chip/lm4/hwtimer.c2
-rw-r--r--chip/lm4/i2c.c12
-rw-r--r--chip/lm4/keyboard_raw.c2
-rw-r--r--chip/lm4/lpc.c3
-rw-r--r--chip/lm4/system.c2
-rw-r--r--chip/lm4/uart.c4
-rw-r--r--chip/mec1322/adc.c2
-rw-r--r--chip/mec1322/gpio.c2
-rw-r--r--chip/mec1322/hwtimer.c4
-rw-r--r--chip/mec1322/i2c.c8
-rw-r--r--chip/mec1322/lpc.c8
-rw-r--r--chip/mec1322/system.c2
-rw-r--r--chip/mec1322/uart.c2
-rw-r--r--chip/stm32/clock-stm32f.c4
-rw-r--r--chip/stm32/dma.c8
-rw-r--r--chip/stm32/gpio-stm32f.c2
-rw-r--r--chip/stm32/gpio-stm32l.c2
-rw-r--r--chip/stm32/hwtimer.c2
-rw-r--r--chip/stm32/i2c-stm32f.c4
-rw-r--r--chip/stm32/uart.c2
-rw-r--r--common/extpower_spring.c2
-rw-r--r--core/cortex-m/irq_handler.h39
-rw-r--r--core/host/irq_handler.h29
-rw-r--r--core/nds32/irq_handler.h25
-rw-r--r--include/task.h30
27 files changed, 141 insertions, 71 deletions
diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
index 19548b12bd..e58945605e 100644
--- a/chip/lm4/adc.c
+++ b/chip/lm4/adc.c
@@ -192,10 +192,10 @@ static void handle_interrupt(int ss)
task_wake(id);
}
-static void ss0_interrupt(void) { handle_interrupt(0); }
-static void ss1_interrupt(void) { handle_interrupt(1); }
-static void ss2_interrupt(void) { handle_interrupt(2); }
-static void ss3_interrupt(void) { handle_interrupt(3); }
+void ss0_interrupt(void) { handle_interrupt(0); }
+void ss1_interrupt(void) { handle_interrupt(1); }
+void ss2_interrupt(void) { handle_interrupt(2); }
+void ss3_interrupt(void) { handle_interrupt(3); }
DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index 58d7665f20..e5236e31d2 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -318,7 +318,7 @@ static void gpio_interrupt(int port, uint32_t mis)
* the port, then call the master handler above.
*/
#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \
- static void irqfunc(void) \
+ void irqfunc(void) \
{ \
uint32_t mis = LM4_GPIO_MIS(gpiobase); \
LM4_GPIO_ICR(gpiobase) = mis; \
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
index 088bd5713b..17d9c3e6ea 100644
--- a/chip/lm4/hwtimer.c
+++ b/chip/lm4/hwtimer.c
@@ -42,7 +42,7 @@ void __hw_clock_source_set(uint32_t ts)
LM4_TIMER_TAV(6) = 0xffffffff - ts;
}
-static void __hw_clock_source_irq(void)
+void __hw_clock_source_irq(void)
{
uint32_t status = LM4_TIMER_RIS(6);
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
index e888b31361..f50296678b 100644
--- a/chip/lm4/i2c.c
+++ b/chip/lm4/i2c.c
@@ -436,12 +436,12 @@ static void handle_interrupt(int port)
task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
}
-static void i2c0_interrupt(void) { handle_interrupt(0); }
-static void i2c1_interrupt(void) { handle_interrupt(1); }
-static void i2c2_interrupt(void) { handle_interrupt(2); }
-static void i2c3_interrupt(void) { handle_interrupt(3); }
-static void i2c4_interrupt(void) { handle_interrupt(4); }
-static void i2c5_interrupt(void) { handle_interrupt(5); }
+void i2c0_interrupt(void) { handle_interrupt(0); }
+void i2c1_interrupt(void) { handle_interrupt(1); }
+void i2c2_interrupt(void) { handle_interrupt(2); }
+void i2c3_interrupt(void) { handle_interrupt(3); }
+void i2c4_interrupt(void) { handle_interrupt(4); }
+void i2c5_interrupt(void) { handle_interrupt(5); }
DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c
index 06f592b64c..66d66de1fa 100644
--- a/chip/lm4/keyboard_raw.c
+++ b/chip/lm4/keyboard_raw.c
@@ -108,7 +108,7 @@ void keyboard_raw_enable_interrupt(int enable)
/**
* Interrupt handler for the entire GPIO bank of keyboard rows.
*/
-static void keyboard_raw_interrupt(void)
+void keyboard_raw_interrupt(void)
{
/* Clear all pending keyboard interrupts */
LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index aa15e1fbfe..f2fd650016 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -401,7 +401,6 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type)
*
* @param is_cmd Is write command (is_cmd=1) or data (is_cmd=0)
*/
-__attribute__((noinline)) /* TODO(crosbug.com/p/24515) */
static void handle_acpi_write(int is_cmd)
{
uint8_t value, result;
@@ -520,7 +519,7 @@ static void handle_host_write(int is_cmd)
/**
* LPC interrupt handler
*/
-static void lpc_interrupt(void)
+void lpc_interrupt(void)
{
uint32_t mis = LM4_LPC_LPCMIS;
uint32_t st;
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
index 0741d0c7f3..6a55b2941e 100644
--- a/chip/lm4/system.c
+++ b/chip/lm4/system.c
@@ -316,7 +316,7 @@ void system_reset_rtc_alarm(void)
/**
* Hibernate module interrupt
*/
-static void __hibernate_irq(void)
+void __hibernate_irq(void)
{
system_reset_rtc_alarm();
}
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
index 95c9bdba32..befe0ec398 100644
--- a/chip/lm4/uart.c
+++ b/chip/lm4/uart.c
@@ -111,7 +111,7 @@ void uart_enable_interrupt(void)
/**
* Interrupt handler for UART0
*/
-static void uart_ec_interrupt(void)
+void uart_ec_interrupt(void)
{
/* Clear transmit and receive interrupt status */
LM4_UART_ICR(0) = 0x70;
@@ -128,7 +128,7 @@ DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
/**
* Interrupt handler for Host UART
*/
-static void uart_host_interrupt(void)
+void uart_host_interrupt(void)
{
/* Clear transmit and receive interrupt status */
LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c
index e000e01cce..5b35307268 100644
--- a/chip/mec1322/adc.c
+++ b/chip/mec1322/adc.c
@@ -96,7 +96,7 @@ static void adc_init(void)
}
DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_DEFAULT);
-static void adc_interrupt(void)
+void adc_interrupt(void)
{
/* Clear interrupt status bit */
MEC1322_ADC_CTRL |= 1 << 7;
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c
index 9094401f61..73b584a943 100644
--- a/chip/mec1322/gpio.c
+++ b/chip/mec1322/gpio.c
@@ -225,7 +225,7 @@ static void gpio_interrupt(int girq, int port_offset)
}
#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset) \
- static void irqfunc(void) \
+ void irqfunc(void) \
{ \
gpio_interrupt(girq, port_offset); \
}
diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c
index 51fa28647b..be9ffac1ea 100644
--- a/chip/mec1322/hwtimer.c
+++ b/chip/mec1322/hwtimer.c
@@ -50,9 +50,9 @@ static void __hw_clock_source_irq(int timer_id)
process_timers(timer_id == 0);
}
-static void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
+void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-static void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
+void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
static void configure_timer(int timer_id)
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
index feaade3813..8eaf861382 100644
--- a/chip/mec1322/i2c.c
+++ b/chip/mec1322/i2c.c
@@ -403,10 +403,10 @@ static void handle_interrupt(int port)
task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
}
-static void i2c0_interrupt(void) { handle_interrupt(0); }
-static void i2c1_interrupt(void) { handle_interrupt(1); }
-static void i2c2_interrupt(void) { handle_interrupt(2); }
-static void i2c3_interrupt(void) { handle_interrupt(3); }
+void i2c0_interrupt(void) { handle_interrupt(0); }
+void i2c1_interrupt(void) { handle_interrupt(1); }
+void i2c2_interrupt(void) { handle_interrupt(2); }
+void i2c3_interrupt(void) { handle_interrupt(3); }
DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2);
DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2);
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
index 2e76b6c39e..db57c9235e 100644
--- a/chip/mec1322/lpc.c
+++ b/chip/mec1322/lpc.c
@@ -225,13 +225,13 @@ static void lpc_init(void)
*/
DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-static void emi_interrupt(void)
+void emi_interrupt(void)
{
port_80_write(MEC1322_EMI_H2E_MBX);
}
DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1);
-static void acpi_0_interrupt(void)
+void acpi_0_interrupt(void)
{
uint8_t value, result, is_cmd;
@@ -258,7 +258,7 @@ static void acpi_0_interrupt(void)
}
DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
-static void acpi_1_interrupt(void)
+void acpi_1_interrupt(void)
{
uint8_t st = MEC1322_ACPI_EC_STATUS(1);
if (!(st & EC_LPC_STATUS_FROM_HOST) ||
@@ -305,7 +305,7 @@ static void acpi_1_interrupt(void)
DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
#ifdef HAS_TASK_KEYPROTO
-static void kb_ibf_interrupt(void)
+void kb_ibf_interrupt(void)
{
if (lpc_keyboard_input_pending())
keyboard_host_write(MEC1322_8042_H2E,
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index 0b7565c641..f8295c9ff9 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -300,7 +300,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
_system_reset(0, 1);
}
-static void htimer_interrupt(void)
+void htimer_interrupt(void)
{
/* Time to wake up */
_system_reset(0, 1);
diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
index 351541de9d..00865c841b 100644
--- a/chip/mec1322/uart.c
+++ b/chip/mec1322/uart.c
@@ -97,7 +97,7 @@ void uart_enable_interrupt(void)
/**
* Interrupt handler for UART
*/
-static void uart_ec_interrupt(void)
+void uart_ec_interrupt(void)
{
/* Read input FIFO until empty, then fill output FIFO */
uart_process_input();
diff --git a/chip/stm32/clock-stm32f.c b/chip/stm32/clock-stm32f.c
index a9fd61fcf0..21380c492a 100644
--- a/chip/stm32/clock-stm32f.c
+++ b/chip/stm32/clock-stm32f.c
@@ -101,13 +101,13 @@ uint32_t reset_rtc_alarm(void)
return rtc_stamp;
}
-static void __rtc_wakeup_irq(void)
+void __rtc_wakeup_irq(void)
{
reset_rtc_alarm();
}
DECLARE_IRQ(STM32_IRQ_RTC_WAKEUP, __rtc_wakeup_irq, 1);
-static void __rtc_alarm_irq(void)
+void __rtc_alarm_irq(void)
{
reset_rtc_alarm();
}
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index 06da15e1b6..f6dfd89aa8 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -238,7 +238,7 @@ void dma_clear_isr(enum dma_channel channel)
dma->ifcr |= STM32_DMA_ISR_ALL(channel);
}
-static void dma_event_interrupt_channel_4(void)
+void dma_event_interrupt_channel_4(void)
{
dma_clear_isr(STM32_DMAC_CH4);
if (id[STM32_DMAC_CH4] != TASK_ID_INVALID)
@@ -246,7 +246,7 @@ static void dma_event_interrupt_channel_4(void)
}
DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3);
-static void dma_event_interrupt_channel_5(void)
+void dma_event_interrupt_channel_5(void)
{
dma_clear_isr(STM32_DMAC_CH5);
if (id[STM32_DMAC_CH5] != TASK_ID_INVALID)
@@ -254,7 +254,7 @@ static void dma_event_interrupt_channel_5(void)
}
DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3);
-static void dma_event_interrupt_channel_6(void)
+void dma_event_interrupt_channel_6(void)
{
dma_clear_isr(STM32_DMAC_CH6);
if (id[STM32_DMAC_CH6] != TASK_ID_INVALID)
@@ -262,7 +262,7 @@ static void dma_event_interrupt_channel_6(void)
}
DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3);
-static void dma_event_interrupt_channel_7(void)
+void dma_event_interrupt_channel_7(void)
{
dma_clear_isr(STM32_DMAC_CH7);
if (id[STM32_DMAC_CH7] != TASK_ID_INVALID)
diff --git a/chip/stm32/gpio-stm32f.c b/chip/stm32/gpio-stm32f.c
index 8ab72cc635..9e6c6799b6 100644
--- a/chip/stm32/gpio-stm32f.c
+++ b/chip/stm32/gpio-stm32f.c
@@ -220,7 +220,7 @@ int gpio_enable_interrupt(enum gpio_signal signal)
/*****************************************************************************/
/* Interrupt handler */
-static void gpio_interrupt(void)
+void gpio_interrupt(void)
{
int bit;
const struct gpio_info *g;
diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c
index c141a2fd58..7283526d89 100644
--- a/chip/stm32/gpio-stm32l.c
+++ b/chip/stm32/gpio-stm32l.c
@@ -228,7 +228,7 @@ int gpio_enable_interrupt(enum gpio_signal signal)
/*****************************************************************************/
/* Interrupt handler */
-static void gpio_interrupt(void)
+void gpio_interrupt(void)
{
int bit;
const struct gpio_info *g;
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
index 0d238b53d4..79df1dd9e0 100644
--- a/chip/stm32/hwtimer.c
+++ b/chip/stm32/hwtimer.c
@@ -143,7 +143,7 @@ void __hw_clock_source_set(uint32_t ts)
STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff;
}
-static void __hw_clock_source_irq(void)
+void __hw_clock_source_irq(void)
{
uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB);
diff --git a/chip/stm32/i2c-stm32f.c b/chip/stm32/i2c-stm32f.c
index c75660b07e..6c7f58556c 100644
--- a/chip/stm32/i2c-stm32f.c
+++ b/chip/stm32/i2c-stm32f.c
@@ -299,7 +299,7 @@ static void i2c_event_handler(int port)
}
}
}
-static void i2c2_event_interrupt(void) { i2c_event_handler(I2C2); }
+void i2c2_event_interrupt(void) { i2c_event_handler(I2C2); }
DECLARE_IRQ(STM32_IRQ_I2C2_EV, i2c2_event_interrupt, 3);
static void i2c_error_handler(int port)
@@ -318,7 +318,7 @@ static void i2c_error_handler(int port)
STM32_I2C_SR1(port) &= ~0xdf00;
}
-static void i2c2_error_interrupt(void) { i2c_error_handler(I2C2); }
+void i2c2_error_interrupt(void) { i2c_error_handler(I2C2); }
DECLARE_IRQ(STM32_IRQ_I2C2_ER, i2c2_error_interrupt, 2);
/* board-specific setup for post-I2C module init */
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
index 5e21a128d4..4fe1214934 100644
--- a/chip/stm32/uart.c
+++ b/chip/stm32/uart.c
@@ -149,7 +149,7 @@ void uart_enable_interrupt(void)
}
/* Interrupt handler for console USART */
-static void uart_interrupt(void)
+void uart_interrupt(void)
{
#ifdef CONFIG_UART_TX_DMA
/* Disable transmission complete interrupt if DMA done */
diff --git a/common/extpower_spring.c b/common/extpower_spring.c
index 3be307bc7e..0acaca4256 100644
--- a/common/extpower_spring.c
+++ b/common/extpower_spring.c
@@ -725,7 +725,7 @@ void extpower_interrupt(enum gpio_signal signal)
/*****************************************************************************/
/* Hooks */
-static void adc_watchdog_interrupt(void)
+void adc_watchdog_interrupt(void)
{
switch (current_watchdog) {
case ADC_WATCH_USB:
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
new file mode 100644
index 0000000000..098e9850ef
--- /dev/null
+++ b/core/cortex-m/irq_handler.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helper to declare IRQ handling routines */
+
+#ifndef __IRQ_HANDLER_H
+#define __IRQ_HANDLER_H
+
+#ifdef CONFIG_TASK_PROFILING
+#define bl_task_start_irq_handler "bl task_start_irq_handler\n"
+#else
+#define bl_task_start_irq_handler ""
+#endif
+
+/* Helper macros to build the IRQ handler and priority struct names */
+#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
+#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
+/*
+ * Macro to connect the interrupt handler "routine" to the irq number "irq" and
+ * ensure it is enabled in the interrupt controller with the right priority.
+ */
+#define DECLARE_IRQ(irq, routine, priority) \
+ void IRQ_HANDLER(irq)(void) __attribute__((naked)); \
+ void IRQ_HANDLER(irq)(void) \
+ { \
+ asm volatile("mov r0, lr\n" \
+ "push {r0, lr}\n" \
+ bl_task_start_irq_handler \
+ "bl "#routine"\n" \
+ "pop {r0, lr}\n" \
+ "b task_resched_if_needed\n" \
+ ); \
+ } \
+ const struct irq_priority IRQ_PRIORITY(irq) \
+ __attribute__((section(".rodata.irqprio"))) \
+ = {irq, priority}
+#endif /* __IRQ_HANDLER_H */
diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h
new file mode 100644
index 0000000000..d778ccf253
--- /dev/null
+++ b/core/host/irq_handler.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helper to declare IRQ handling routines */
+
+#ifndef __IRQ_HANDLER_H
+#define __IRQ_HANDLER_H
+
+/* Helper macros to build the IRQ handler and priority struct names */
+#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
+#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
+/*
+ * Macro to connect the interrupt handler "routine" to the irq number "irq" and
+ * ensure it is enabled in the interrupt controller with the right priority.
+ */
+#define DECLARE_IRQ(irq, routine, priority) \
+ void IRQ_HANDLER(irq)(void) \
+ { \
+ void *ret = __builtin_return_address(0); \
+ task_start_irq_handler(ret); \
+ routine(); \
+ task_resched_if_needed(ret); \
+ } \
+ const struct irq_priority IRQ_PRIORITY(irq) \
+ __attribute__((section(".rodata.irqprio"))) \
+ = {irq, priority}
+#endif /* __IRQ_HANDLER_H */
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
new file mode 100644
index 0000000000..c3d22cc177
--- /dev/null
+++ b/core/nds32/irq_handler.h
@@ -0,0 +1,25 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Helper to declare IRQ handling routines */
+
+#ifndef __IRQ_HANDLER_H
+#define __IRQ_HANDLER_H
+
+/* Helper macros to build the IRQ handler and priority struct names */
+#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
+#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
+/*
+ * Macro to connect the interrupt handler "routine" to the irq number "irq" and
+ * ensure it is enabled in the interrupt controller with the right priority.
+ */
+#define DECLARE_IRQ(irq, routine, priority) \
+ void IRQ_HANDLER(CPU_INT(irq))(void) \
+ __attribute__ ((alias(STRINGIFY(routine)))); \
+ const struct irq_priority IRQ_PRIORITY(CPU_INT(irq)) \
+ __attribute__((section(".rodata.irqprio"))) \
+ = {CPU_INT(irq), priority}
+
+#endif /* __IRQ_HANDLER_H */
diff --git a/include/task.h b/include/task.h
index f2df173501..4cbd60b857 100644
--- a/include/task.h
+++ b/include/task.h
@@ -201,32 +201,10 @@ struct irq_priority {
uint8_t priority;
};
-/* Helper macros to build the IRQ handler and priority struct names */
-#define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
-#define IRQ_PRIORITY(irqname) CONCAT2(prio_, irqname)
/*
- * Macro to connect the interrupt handler "routine" to the irq number "irq" and
- * ensure it is enabled in the interrupt controller with the right priority.
- */
-#ifdef __nds32__
-#define DECLARE_IRQ(irq, routine, priority) \
- void IRQ_HANDLER(CPU_INT(irq))(void) \
- __attribute__ ((alias(STRINGIFY(routine)))); \
- const struct irq_priority IRQ_PRIORITY(CPU_INT(irq)) \
- __attribute__((section(".rodata.irqprio"))) \
- = {CPU_INT(irq), priority}
-#else
-#define DECLARE_IRQ(irq, routine, priority) \
- void IRQ_HANDLER(irq)(void) \
- { \
- void *ret = __builtin_return_address(0); \
- task_start_irq_handler(ret); \
- routine(); \
- task_resched_if_needed(ret); \
- } \
- const struct irq_priority IRQ_PRIORITY(irq) \
- __attribute__((section(".rodata.irqprio"))) \
- = {irq, priority}
-#endif
+ * Implement the DECLARE_IRQ(irq, routine, priority) macro which is
+ * a core specific helper macro to declare an interrupt handler "routine".
+ */
+#include "irq_handler.h"
#endif /* __CROS_EC_TASK_H */
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