diff options
| -rw-r--r-- | chip/npcx/lpc.c | 31 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 9 | ||||
| -rw-r--r-- | include/lpc.h | 4 | ||||
| -rw-r--r-- | power/skylake.c | 4 |
4 files changed, 46 insertions, 2 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 40ce230d9a..7c08062e1e 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -799,7 +799,34 @@ DECLARE_DEFERRED(lpc_chipset_reset); int lpc_get_pltrst_asserted(void) { /* Read current PLTRST status */ - return (NPCX_MSWCTL1 & 0x04) ? 1 : 0; + return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT); +} + +void lpc_host_reset(void) +{ + /* Host Reset Control will assert KBRST# (LPC) or RCIN# VW (eSPI) */ +#ifdef CONFIG_ESPI_VW_SIGNALS + int timeout = 100; /* 100 * 10us = 1ms */ + + /* Assert RCIN# VW to host */ + SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); + + /* Poll for dirty bit to clear to indicate VW read by host */ + while ((NPCX_VWEVSM(2) & VWEVSM_DIRTY(1))) { + if (!timeout--) { + CPRINTS("RCIN# VW Timeout"); + break; + } + udelay(10); + } + + /* Deassert RCIN# VW to host */ + CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); +#else + SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); + udelay(10); + CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); +#endif } #ifndef CONFIG_ESPI @@ -855,7 +882,7 @@ static void lpc_init(void) NPCX_DEVCNT |= 0x04; #endif /* Enable 4E/4F */ - if (!IS_BIT_SET(NPCX_MSWCTL1, 3)) { + if (!IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_VHCFGA)) { NPCX_HCBAL = 0x4E; NPCX_HCBAH = 0x0; } diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index b73a183131..2889837b3b 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -428,6 +428,15 @@ enum { #define NPCX_SID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x020) #define NPCX_DEVICE_ID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x022) +/* MSWC register fields */ +#define NPCX_MSWCTL1_HRSTOB 0 +#define NPCS_MSWCTL1_HWPRON 1 +#define NPCX_MSWCTL1_PLTRST_ACT 2 +#define NPCX_MSWCTL1_VHCFGA 3 +#define NPCX_MSWCTL1_HCFGLK 4 +#define NPCX_MSWCTL1_PWROFFB 6 +#define NPCX_MSWCTL1_A20MB 7 + /******************************************************************************/ /* System Configuration (SCFG) Registers */ #define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) diff --git a/include/lpc.h b/include/lpc.h index 3b77736f00..4408b71327 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -113,6 +113,10 @@ void lpc_clear_acpi_status_mask(uint8_t mask); */ int lpc_get_pltrst_asserted(void); +/** + * Reset the host with KBRST# or RCIN# + */ +void lpc_host_reset(void); /* Disable LPC ACPI interrupts */ void lpc_disable_acpi_interrupts(void); diff --git a/power/skylake.c b/power/skylake.c index 7ac5146d93..718ff5aeca 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -131,9 +131,13 @@ void chipset_reset(int cold_reset) */ /* Pulse must be at least 16 PCI clocks long = 500 ns */ +#ifdef CONFIG_ESPI_VW_SIGNALS + lpc_host_reset(); +#else gpio_set_level(GPIO_PCH_RCIN_L, 0); udelay(10); gpio_set_level(GPIO_PCH_RCIN_L, 1); +#endif } } |