diff options
-rw-r--r-- | chip/npcx/clock.c | 7 | ||||
-rw-r--r-- | chip/npcx/clock_chip.h | 3 | ||||
-rw-r--r-- | chip/npcx/uart.c | 50 |
3 files changed, 33 insertions, 27 deletions
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 449e4dd8bd..40ffa205dc 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -26,7 +26,6 @@ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) #define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) -#define OSC_CLK 48000000 /* Default is 40MHz (target is 48MHz) */ #define WAKE_INTERVAL 61 /* Unit: 61 usec */ #define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */ @@ -47,6 +46,12 @@ #elif (OSC_CLK == 33000000) #define HFCGMH 0x07 #define HFCGML 0xDE +#elif (OSC_CLK == 24000000) +#define HFCGMH 0x05 +#define HFCGML 0xB8 +#elif (OSC_CLK == 16000000) +#define HFCGMH 0x03 +#define HFCGML 0xDC #else #error "Unsupported FMCLK Clock Frequency" #endif diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h index 3b2b847dc0..810543afb4 100644 --- a/chip/npcx/clock_chip.h +++ b/chip/npcx/clock_chip.h @@ -8,6 +8,9 @@ #ifndef __CROS_EC_CLOCK_CHIP_H #define __CROS_EC_CLOCK_CHIP_H +/* Default is 40MHz (target is 16MHz) */ +#define OSC_CLK 16000000 + /** * Return the current APB1 clock frequency in Hz. */ diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index 51ef975bc3..c25b2fd01e 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -145,9 +145,6 @@ DECLARE_IRQ(NPCX_IRQ_UART, uart_ec_interrupt, 1); static void uart_config(void) { - uint32_t div, opt_dev, min_deviation, clk, calc_baudrate, deviation; - uint8_t prescalar, opt_prescalar, i; - /* Configure pins from GPIOs to CR_UART */ gpio_config_module(MODULE_UART, 1); /* Enable MIWU IRQ of UART*/ @@ -158,29 +155,30 @@ static void uart_config(void) #endif - /* Calculated UART baudrate , clock source from APB2 */ - opt_prescalar = opt_dev = 0; - prescalar = 10; - min_deviation = 0xFFFFFFFF; - clk = clock_get_apb2_freq(); - for (i = 1; i < 31; i++) { - div = (clk * 10) / (16 * CONFIG_UART_BAUD_RATE * prescalar); - if (div != 0) { - calc_baudrate = (clk * 10) / (16 * div * prescalar); - deviation = (calc_baudrate > CONFIG_UART_BAUD_RATE) ? - (calc_baudrate - CONFIG_UART_BAUD_RATE) : - (CONFIG_UART_BAUD_RATE - calc_baudrate); - if (deviation < min_deviation) { - min_deviation = deviation; - opt_prescalar = i; - opt_dev = div; - } - } - prescalar += 5; - } - opt_dev--; - NPCX_UPSR = ((opt_prescalar<<3) & 0xF8) | ((opt_dev >> 8) & 0x7); - NPCX_UBAUD = (uint8_t)opt_dev; + /* Fix baud rate to 115200 */ +#if (OSC_CLK == 50000000) + NPCX_UPSR = 0x10; + NPCX_UBAUD = 0x08; +#elif (OSC_CLK == 48000000) + NPCX_UPSR = 0x08; + NPCX_UBAUD = 0x0C; +#elif (OSC_CLK == 40000000) + NPCX_UPSR = 0x30; + NPCX_UBAUD = 0x02; +#elif (OSC_CLK == 33000000) + NPCX_UPSR = 0x08; + NPCX_UBAUD = 0x08; +#elif (OSC_CLK == 24000000) + NPCX_UPSR = 0x60; + NPCX_UBAUD = 0x00; +#elif (OSC_CLK == 16000000) + NPCX_UPSR = 0x10; + NPCX_UBAUD = 0x02; +#else +#error "Unsupported FMCLK Clock Frequency" +#endif + + /* * 8-N-1, FIFO enabled. Must be done after setting * the divisor for the new divisor to take effect. |