diff options
Diffstat (limited to 'baseboard')
182 files changed, 2604 insertions, 2787 deletions
diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c index 1a86950281..3a881c275a 100644 --- a/baseboard/asurada/baseboard.c +++ b/baseboard/asurada/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -71,34 +71,26 @@ int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -111,15 +103,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h index 21a29cf942..62f74e1f57 100644 --- a/baseboard/asurada/baseboard.h +++ b/baseboard/asurada/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -83,10 +83,10 @@ #define CONFIG_I2C_VIRTUAL_BATTERY #define I2C_PORT_CHARGER IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_POWER IT83XX_I2C_CH_A +#define I2C_PORT_POWER IT83XX_I2C_CH_A #define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY @@ -171,13 +171,12 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* And the MKBP events */ #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT)) + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT)) #include "baseboard_common.h" diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h index 0245ae42bf..4b8892e5b7 100644 --- a/baseboard/asurada/baseboard_common.h +++ b/baseboard/asurada/baseboard_common.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,12 +9,12 @@ #define __CROS_EC_BASEBOARD_COMMON_H /* GPIO name remapping */ -#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 +#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 +#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 #define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2 -#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 -#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 -#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 +#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 +#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 +#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 #ifndef __ASSEMBLER__ diff --git a/baseboard/asurada/board_chipset.c b/baseboard/asurada/board_chipset.c index 4d12fb0334..24754f597f 100644 --- a/baseboard/asurada/board_chipset.c +++ b/baseboard/asurada/board_chipset.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c index 642785034c..9a316d8d40 100644 --- a/baseboard/asurada/board_id.c +++ b/baseboard/asurada/board_id.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,21 +34,8 @@ * 14 | 47 | 680 | 3086.7 */ const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, + 136, 388, 584, 785, 993, 1220, 1432, 1650, + 1875, 2084, 2273, 2461, 2672, 2888, 3086, }; const int threshold_mv = 100; diff --git a/baseboard/asurada/build.mk b/baseboard/asurada/build.mk index ce7b7272bd..ac4f1489d2 100644 --- a/baseboard/asurada/build.mk +++ b/baseboard/asurada/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c index b26bd44adc..60b191d3e6 100644 --- a/baseboard/asurada/hibernate.c +++ b/baseboard/asurada/hibernate.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ __override void board_hibernate_late(void) */ if (board_get_version() <= 1) { if (IS_ENABLED(BOARD_ASURADA) || - (IS_ENABLED(CONFIG_ZEPHYR) && - IS_ENABLED(CONFIG_BOARD_ASURADA))) + (IS_ENABLED(CONFIG_ZEPHYR) && + IS_ENABLED(CONFIG_BOARD_ASURADA))) return; } diff --git a/baseboard/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c index 9ee59a5cc3..fc2cefd208 100644 --- a/baseboard/asurada/it5205_sbu.c +++ b/baseboard/asurada/it5205_sbu.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -12,8 +12,8 @@ #include "timer.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define OVP_RETRY_DELAY_US_MIN (100 * MSEC) diff --git a/baseboard/asurada/it5205_sbu.h b/baseboard/asurada/it5205_sbu.h index 8dc59520dd..2a17506cad 100644 --- a/baseboard/asurada/it5205_sbu.h +++ b/baseboard/asurada/it5205_sbu.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c index 35670bda82..e2731c8385 100644 --- a/baseboard/asurada/regulator.c +++ b/baseboard/asurada/regulator.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,13 +7,12 @@ #include "bc12/mt6360_public.h" /* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) +int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages, + uint16_t *voltages_mv) { enum mt6360_regulator_id id = index; - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); + return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv); } int board_regulator_enable(uint32_t index, uint8_t enable) diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c index 03993fcbbe..afec537330 100644 --- a/baseboard/asurada/usb_pd_policy.c +++ b/baseboard/asurada/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #error Asurada reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) int svdm_get_hpd_gpio(int port) { @@ -79,8 +79,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) if (lvl) gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port); - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -147,7 +146,7 @@ __override void svdm_exit_dp_mode(int port) svdm_set_hpd_gpio(port, 0); #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c index 89cb24ff12..0be43d343a 100644 --- a/baseboard/asurada/usbc_config.c +++ b/baseboard/asurada/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -37,9 +37,9 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -56,7 +56,7 @@ static void baseboard_init(void) gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE); } -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1); +DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1); /* Sub-board */ @@ -193,14 +193,14 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); void usb_a0_interrupt(enum gpio_signal signal) { enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; for (int i = 0; i < USB_PORT_COUNT; i++) usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); } -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; int reg = 0; @@ -227,33 +227,45 @@ static int board_ps8743_mux_set(const struct usb_mux *me, return ps8743_write(me, PS8743_REG_MODE, reg); } -const struct usb_mux usbc0_virtual_mux = { - .usb_port = 0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, +const struct usb_mux_chain usbc0_virtual_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = 0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; -const struct usb_mux usbc1_virtual_mux = { - .usb_port = 1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, +const struct usb_mux_chain usbc1_virtual_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = 1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { - .usb_port = 0, - .i2c_port = I2C_PORT_USB_MUX0, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .next_mux = &usbc0_virtual_mux, + .mux = + &(const struct usb_mux){ + .usb_port = 0, + .i2c_port = I2C_PORT_USB_MUX0, + .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, + .driver = &it5205_usb_mux_driver, + }, + .next = &usbc0_virtual_mux, }, { - .usb_port = 1, - .i2c_port = I2C_PORT_USB_MUX1, - .i2c_addr_flags = PS8743_I2C_ADDR0_FLAG, - .driver = &ps8743_usb_mux_driver, - .next_mux = &usbc1_virtual_mux, - .board_set = &board_ps8743_mux_set, + .mux = + &(const struct usb_mux){ + .usb_port = 1, + .i2c_port = I2C_PORT_USB_MUX1, + .i2c_addr_flags = PS8743_I2C_ADDR0_FLAG, + .driver = &ps8743_usb_mux_driver, + .board_set = &board_ps8743_mux_set, + }, + .next = &usbc1_virtual_mux, }, }; @@ -297,8 +309,8 @@ void board_reset_pd_mcu(void) */ } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); @@ -422,9 +434,9 @@ int ppc_get_alert_status(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) - return ADC_VBUS_C0; + return ADC_VBUS_C0; if (port == 1) - return ADC_VBUS_C1; + return ADC_VBUS_C1; CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; } diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c index 2e60b565f8..5a96ba49ca 100644 --- a/baseboard/brask/baseboard.c +++ b/baseboard/brask/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,6 +9,5 @@ #include "gpio_signal.h" /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h index 15a451473d..83a02bec2e 100644 --- a/baseboard/brask/baseboard.h +++ b/baseboard/brask/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,16 +11,16 @@ /* * By default, enable all console messages excepted HC */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) /* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* * This defines which pads (GPIO10/11 or GPIO64/65) are connected to * the "UART1" (NPCX_UART_PORT0) controller when used for * CONSOLE_UART. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ /* CrOS Board Info */ #define CONFIG_CBI_EEPROM @@ -42,9 +42,9 @@ /* Host communication */ #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 -#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST /* LED */ #define CONFIG_LED_COMMON @@ -59,7 +59,7 @@ /* Support Barrel Jack */ #undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000 /* Chipset config */ #define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 @@ -86,8 +86,8 @@ /* ADL has new low-power features that requires extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ -#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US +#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100 /* Buttons */ #define CONFIG_DEDICATED_RECOVERY_BUTTON @@ -137,7 +137,7 @@ #define CONFIG_USB_PD_TCPM_NCT38XX #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -145,7 +145,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h index 1b3d9e5d3f..8ebf4f9b6a 100644 --- a/baseboard/brask/baseboard_usbc_config.h +++ b/baseboard/brask/baseboard_usbc_config.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk index e29bcaf4ac..4b540d94ad 100644 --- a/baseboard/brask/build.mk +++ b/baseboard/brask/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/brask/cbi.c b/baseboard/brask/cbi.c index 038a491f05..0dcfcca253 100644 --- a/baseboard/brask/cbi.c +++ b/baseboard/brask/cbi.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,8 +10,8 @@ #include "cros_board_info.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static uint8_t board_id; diff --git a/baseboard/brask/cbi.h b/baseboard/brask/cbi.h index 5fa41feadd..219718763f 100644 --- a/baseboard/brask/cbi.h +++ b/baseboard/brask/cbi.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c index ddff378ae2..0503415a9d 100644 --- a/baseboard/brask/usb_pd_policy.c +++ b/baseboard/brask/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,6 +15,7 @@ #include "console.h" #include "ec_commands.h" #include "gpio.h" +#include "timer.h" #include "usbc_ppc.h" #include "usb_mux.h" #include "usb_pd.h" @@ -24,8 +25,8 @@ #include "usb_pd_vdo.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -80,54 +81,44 @@ int board_vbus_source_enabled(int port) return ppc_is_sourcing_vbus(port); } +#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE /* ----------------- Vendor Defined Messages ------------------ */ /* Responses specifically for the enablement of TBT mode in the role of UFP */ #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { @@ -166,8 +157,24 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) } } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +/* Track whether we've been enabled to ACK TBT EnterModes requests */ +static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT]; + +__override enum ec_status +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) +{ + /* Note: Host command has already bounds-checked port */ + if (reply == TYPEC_TBT_UFP_REPLY_ACK) + tbt_ufp_ack_allowed[port] = true; + else if (reply == TYPEC_TBT_UFP_REPLY_NAK) + tbt_ufp_ack_allowed[port] = false; + else + return EC_RES_INVALID_PARAM; + + return EC_RES_SUCCESS; +} + +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -175,20 +182,34 @@ static int svdm_tbt_compat_response_enter_mode( if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) return 0; /* NAK */ + /* Do not enter mode while policy disallows it */ + if (!tbt_ufp_ack_allowed[port]) + return 0; /* NAK */ + if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); /* * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence - * UFP (responder) should be in USB mode or safe mode before sending - * Enter Mode Command response. + * UFP (responder) should be in USB mode or safe mode before entering a + * Mode that requires the reconfiguring of any pins. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); + + /* + * Ref: Above figure 6-21: UFP (responder) should be in the new + * mode before sending the ACK. However, our mux set sequence + * may exceed tVDMEnterMode, so wait as long as we can + * before sending the reply without violating that timer. + */ + if (!usb_mux_set_completed(port)) + usleep(PD_T_VDM_E_MODE / 2); + CPRINTS("UFP Enter TBT mode"); return 1; /* ACK */ } @@ -205,3 +226,4 @@ const struct svdm_response svdm_rsp = { .amode = NULL, .exit_mode = NULL, }; +#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */ diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c index 7b9e3c2e00..e65a384578 100644 --- a/baseboard/brya/baseboard.c +++ b/baseboard/brya/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -41,5 +41,5 @@ __override void lid_angle_peripheral_enable(int enable) */ if (!chipset_in_state(CHIPSET_STATE_ON)) keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE); - } + } } diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index bc44a9d642..84fefa9b53 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,18 +12,18 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* * This defines which pads (GPIO10/11 or GPIO64/65) are connected to * the "UART1" (NPCX_UART_PORT0) controller when used for * CONSOLE_UART. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ /* EC Defines */ #define CONFIG_LTO @@ -46,8 +46,8 @@ /* Host communication */ #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 /* * TODO(b/179648721): implement sensors @@ -68,7 +68,7 @@ #define CONFIG_CHARGE_MANAGER #define CONFIG_CHARGER #define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CMD_CHARGER_DUMP @@ -79,8 +79,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Common battery defines */ #define CONFIG_BATTERY_SMART @@ -113,7 +113,7 @@ #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE #define CONFIG_LOW_POWER_IDLE -#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST +#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST #define CONFIG_BOARD_HAS_RTC_RESET #undef CONFIG_S5_EXIT_WAIT @@ -124,8 +124,8 @@ /* ADL has new lower-power features that require extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ -#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US +#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100 /* Buttons / Switches */ #define CONFIG_VOLUME_BUTTONS @@ -181,7 +181,7 @@ #define CONFIG_USB_PD_TCPM_NCT38XX #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -189,7 +189,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD @@ -230,13 +230,13 @@ * bytes. Task stack sizes not listed here use more generic values (see * ec.tasklist). */ -#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088 -#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088 -#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152 -#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800 -#define BASEBOARD_PD_TASK_STACK_SIZE 1216 -#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088 -#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048 +#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088 +#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088 +#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152 +#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800 +#define BASEBOARD_PD_TASK_STACK_SIZE 1216 +#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088 +#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048 #ifndef __ASSEMBLER__ @@ -248,7 +248,6 @@ #include "baseboard_usbc_config.h" #include "extpower.h" - /* * Check battery disconnect state. * This function will return if battery is initialized or not. diff --git a/baseboard/brya/baseboard_usbc_config.h b/baseboard/brya/baseboard_usbc_config.h index f8b9fab35c..6d0cf828a3 100644 --- a/baseboard/brya/baseboard_usbc_config.h +++ b/baseboard/brya/baseboard_usbc_config.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c index 94c9926820..1e4ab4ed44 100644 --- a/baseboard/brya/battery_presence.c +++ b/baseboard/brya/battery_presence.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -18,8 +18,9 @@ __overridable bool board_battery_is_initialized(void) { int batt_status; - return battery_status(&batt_status) != EC_SUCCESS ? false : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) != EC_SUCCESS ? + false : + !!(batt_status & STATUS_INITIALIZED); } /* diff --git a/baseboard/brya/build.mk b/baseboard/brya/build.mk index 2ed0186242..c6e93c63f2 100644 --- a/baseboard/brya/build.mk +++ b/baseboard/brya/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c index ded310bffc..7bc8dad117 100644 --- a/baseboard/brya/cbi.c +++ b/baseboard/brya/cbi.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,8 +10,8 @@ #include "cros_board_info.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static uint8_t board_id; diff --git a/baseboard/brya/cbi.h b/baseboard/brya/cbi.h index 2ad70aff96..37e02806bd 100644 --- a/baseboard/brya/cbi.h +++ b/baseboard/brya/cbi.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c index 184cc68eaa..a4fa209246 100644 --- a/baseboard/brya/charger_bq25720.c +++ b/baseboard/brya/charger_bq25720.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) #ifndef CONFIG_ZEPHYR /* Charger Chip Configuration */ @@ -86,7 +85,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } diff --git a/baseboard/brya/prochot.c b/baseboard/brya/prochot.c index 666f2ca35b..f89ec5a263 100644 --- a/baseboard/brya/prochot.c +++ b/baseboard/brya/prochot.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,10 +16,10 @@ #include "task.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -#define ADT_RATING_W (PD_MAX_POWER_MW / 1000) -#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0) +#define ADT_RATING_W (PD_MAX_POWER_MW / 1000) +#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0) struct batt_para { int battery_continuous_discharge_mw; @@ -80,8 +80,9 @@ static int get_batt_parameter(void) rv |= sb_read(SB_DESIGN_VOLTAGE, &battery_design_voltage_mv); rv |= sb_read(SB_DESIGN_CAPACITY, &battery_design_capacity_mAh); - batt_params.battery_design_mWh = (battery_design_voltage_mv * - battery_design_capacity_mAh) / 1000; + batt_params.battery_design_mWh = + (battery_design_voltage_mv * battery_design_capacity_mAh) / + 1000; if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_params.state_of_charge)) batt_params.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE; @@ -109,7 +110,7 @@ static int set_register_charge_option(void) int rv; rv = i2c_read16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS, - BQ25710_REG_CHARGE_OPTION_0, ®); + BQ25710_REG_CHARGE_OPTION_0, ®); if (rv == EC_SUCCESS) { reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, IADP_GAIN, 1, reg); /* if AC only, disable IDPM, @@ -127,7 +128,7 @@ static int set_register_charge_option(void) } return i2c_write16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS, - BQ25710_REG_CHARGE_OPTION_0, reg); + BQ25710_REG_CHARGE_OPTION_0, reg); } static void assert_prochot(void) @@ -154,7 +155,7 @@ static void assert_prochot(void) /* When battery is discharging, the battery current will be negative */ if (batt_params.battery_continuous_discharge_mw < 0) { total_W = adpt_mw + - ABS(batt_params.battery_continuous_discharge_mw); + ABS(batt_params.battery_continuous_discharge_mw); } else { /* we won't assert prochot when battery is charging. */ total_W = adpt_mw; @@ -177,15 +178,18 @@ static void assert_prochot(void) if (!battery_hw_present()) { gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { - batt_params.battery_continuous_discharge_mw = - ABS(batt_params.battery_continuous_discharge_mw); + batt_params.battery_continuous_discharge_mw = ABS( + batt_params.battery_continuous_discharge_mw); if ((batt_params.battery_continuous_discharge_mw / - 1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_ASSERTION_BATTERY_RATIO / 100) + 1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_ASSERTION_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if ((batt_params.battery_continuous_discharge_mw - / 1000) < BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_DEASSERTION_BATTERY_RATIO / 100) + else if ((batt_params.battery_continuous_discharge_mw / + 1000) < + BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_DEASSERTION_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } return; @@ -195,42 +199,48 @@ static void assert_prochot(void) /* if adapter >= 60W */ /* if no battery or battery < 10% */ if (!battery_hw_present() || - batt_params.state_of_charge <= 10) { - if (total_W > ADT_RATING_W * - PROCHOT_ASSERTION_PD_RATIO / 100) + batt_params.state_of_charge <= 10) { + if (total_W > + ADT_RATING_W * PROCHOT_ASSERTION_PD_RATIO / 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W <= ADT_RATING_W * - PROCHOT_DEASSERTION_PD_RATIO / 100) + else if (total_W <= + ADT_RATING_W * PROCHOT_DEASSERTION_PD_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { /* AC + battery */ - if (total_W > (ADT_RATING_W + - BATT_MAX_CONTINUE_DISCHARGE_WATT)) + if (total_W > + (ADT_RATING_W + BATT_MAX_CONTINUE_DISCHARGE_WATT)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W < (ADT_RATING_W + - BATT_MAX_CONTINUE_DISCHARGE_WATT) * - PROCHOT_DEASSERTION_PD_BATTERY_RATIO / 100) + else if (total_W < + (ADT_RATING_W + + BATT_MAX_CONTINUE_DISCHARGE_WATT) * + PROCHOT_DEASSERTION_PD_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } } else { /* if adapter < 60W */ /* if no battery or battery < 10% */ if (!battery_hw_present() || - batt_params.state_of_charge <= 10) { + batt_params.state_of_charge <= 10) { if (total_W > (adapter_wattage * - PROCHOT_ASSERTION_ADAPTER_RATIO / 100)) + PROCHOT_ASSERTION_ADAPTER_RATIO / 100)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W <= (adapter_wattage * - PROCHOT_DEASSERTION_ADAPTER_RATIO / 100)) + else if (total_W <= + (adapter_wattage * + PROCHOT_DEASSERTION_ADAPTER_RATIO / 100)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { /* AC + battery */ if (total_W > (adapter_wattage + - BATT_MAX_CONTINUE_DISCHARGE_WATT)) + BATT_MAX_CONTINUE_DISCHARGE_WATT)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W < (adapter_wattage + - (BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO / 100))) + else if (total_W < + (adapter_wattage + + (BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO / + 100))) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } } diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c index e3e85539bf..e902fbc4a6 100644 --- a/baseboard/brya/usb_pd_policy.c +++ b/baseboard/brya/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -25,8 +25,8 @@ #include "usb_pd_vdo.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -81,80 +81,86 @@ int board_vbus_source_enabled(int port) return ppc_is_sourcing_vbus(port); } +#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE /* ----------------- Vendor Defined Messages ------------------ */ /* Responses specifically for the enablement of TBT mode in the role of UFP */ #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { - /* TODO(b/154962766): Get an XID */ - payload[VDO_I(CSTAT)] = VDO_CSTAT(0); - payload[VDO_I(PRODUCT)] = vdo_product; - - if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { - /* PD Revision 3.0 */ - payload[VDO_I(IDH)] = vdo_idh_rev30; - payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1; - /* TODO(b/181620145): Customize for brya */ - payload[VDO_I(PTYPE_UFP2_VDO)] = 0; - payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp; - return VDO_I(PTYPE_DFP_VDO) + 1; - } + /* + * For PD 3.1 compliance test TEST.PD.VDM.SRC.2, + * we should return NAK if we cannot recognized the incoming SVID. + */ + if (PD_VDO_VID(payload[0]) == USB_SID_PD) { + /* TODO(b/154962766): Get an XID */ + payload[VDO_I(CSTAT)] = VDO_CSTAT(0); + payload[VDO_I(PRODUCT)] = vdo_product; + + if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { + /* PD Revision 3.0 */ + payload[VDO_I(IDH)] = vdo_idh_rev30; + payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1; + /* TODO(b/181620145): Customize for brya */ + payload[VDO_I(PTYPE_UFP2_VDO)] = 0; + payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp; + return VDO_I(PTYPE_DFP_VDO) + 1; + } - /* PD Revision 2.0 */ - payload[VDO_I(IDH)] = vdo_idh; - return VDO_I(PRODUCT) + 1; + /* PD Revision 2.0 */ + payload[VDO_I(IDH)] = vdo_idh; + return VDO_I(PRODUCT) + 1; + } else { + return 0; /* NAK */ + } } static int svdm_tbt_compat_response_svids(int port, uint32_t *payload) { - payload[1] = VDO_SVID(USB_VID_INTEL, 0); - return 2; + /* + * For PD 3.1 compliance test TEST.PD.VDM.SRC.2, + * we should return NAK if we cannot recognized the incoming SVID. + */ + if (PD_VDO_VID(payload[0]) == USB_SID_PD) { + payload[1] = VDO_SVID(USB_VID_INTEL, 0); + return 2; + } else { + return 0; /* NAK */ + } } static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) @@ -170,8 +176,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) /* Track whether we've been enabled to ACK TBT EnterModes requests */ static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT]; -__override enum ec_status board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply) +__override enum ec_status +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) { /* Note: Host command has already bounds-checked port */ if (reply == TYPEC_TBT_UFP_REPLY_ACK) @@ -184,8 +190,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port, return EC_RES_SUCCESS; } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -198,7 +203,7 @@ static int svdm_tbt_compat_response_enter_mode( return 0; /* NAK */ if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); @@ -208,7 +213,7 @@ static int svdm_tbt_compat_response_enter_mode( * Mode that requires the reconfiguring of any pins. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); @@ -237,3 +242,4 @@ const struct svdm_response svdm_rsp = { .amode = NULL, .exit_mode = NULL, }; +#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */ diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c index 83c169c636..3f5f5c0e64 100644 --- a/baseboard/cherry/baseboard.c +++ b/baseboard/cherry/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -52,8 +52,8 @@ static void xhci_init_done_interrupt(enum gpio_signal signal); #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Wake-up pins for hibernate */ enum gpio_signal hibernate_wake_pins[] = { @@ -76,10 +76,10 @@ static void baseboard_charger_init(void) { /* b/198707662#comment9 */ int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP) - << ISL9238_INPUT_VOLTAGE_REF_SHIFT; + << ISL9238_INPUT_VOLTAGE_REF_SHIFT; i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS, - ISL9238_REG_INPUT_VOLTAGE, reg); + ISL9238_REG_INPUT_VOLTAGE, reg); } DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2); @@ -113,14 +113,14 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal) /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0}, - {"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1}, - {"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2}, + { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 }, + { "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, + { "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, /* AMON/BMON gain = 17.97 */ - {"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH3}, - {"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6}, - {"TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7}, + { "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH3 }, + { "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 }, + { "TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -210,7 +210,8 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal) { enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; for (int i = 0; i < USB_PORT_COUNT; i++) usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); @@ -246,34 +247,26 @@ __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal) /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 1000, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 1000, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -315,26 +308,30 @@ __override int board_rt1718s_init(int port) /* gpio 1/2 output high when receiving frx signal */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL, - RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); + RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, - RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); + RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); /* Turn on SBU switch */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | - RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | - RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, - 0xFF)); + RETURN_ERROR( + rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, + RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | + RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | + RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, + 0xFF)); /* Trigger GPIO 1/2 change when FRS signal received */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_FRS_CTRL3, + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1)); /* Set FRS signal detect time to 46.875us */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1, - RT1718S_FRS_CTRL1_FRSWAPRX_MASK, - 0xFF)); + RT1718S_FRS_CTRL1_FRSWAPRX_MASK, + 0xFF)); return EC_SUCCESS; } @@ -371,13 +368,6 @@ void board_reset_pd_mcu(void) /* C1: Add code if TCPC chips need a reset */ } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) { /* @@ -452,13 +442,12 @@ int ppc_get_alert_status(int port) return 0; } /* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) +int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages, + uint16_t *voltages_mv) { enum mt6360_regulator_id id = index; - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); + return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv); } int board_regulator_enable(uint32_t index, uint8_t enable) @@ -508,7 +497,7 @@ __override int board_rt1718s_set_frs_enable(int port, int enable) * FRS path. */ rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS, - enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); + enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); return EC_SUCCESS; } diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h index a03c5c5dbd..2b0d03a436 100644 --- a/baseboard/cherry/baseboard.h +++ b/baseboard/cherry/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -93,13 +93,13 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_PASSTHRU_RESTRICTED #define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E -#define I2C_PORT_USB0 IT83XX_I2C_CH_C -#define I2C_PORT_USB1 IT83XX_I2C_CH_E +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A +#define I2C_PORT_ACCEL IT83XX_I2C_CH_B +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E +#define I2C_PORT_USB0 IT83XX_I2C_CH_C +#define I2C_PORT_USB1 IT83XX_I2C_CH_E #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY @@ -155,7 +155,7 @@ #define PD_MAX_VOLTAGE_MV 20000 #define PD_OPERATING_POWER_MW 15000 #define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* USB-A */ @@ -202,13 +202,12 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* And the MKBP events */ #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT)) + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT)) #ifndef __ASSEMBLER__ @@ -217,11 +216,11 @@ #include "power/mt8192.h" enum adc_channel { - ADC_VBUS, /* ADC 0 */ - ADC_BOARD_ID, /* ADC 1 */ - ADC_SKU_ID, /* ADC 2 */ - ADC_CHARGER_AMON_R, /* ADC 3 */ - ADC_CHARGER_PMON, /* ADC 6 */ + ADC_VBUS, /* ADC 0 */ + ADC_BOARD_ID, /* ADC 1 */ + ADC_SKU_ID, /* ADC 2 */ + ADC_CHARGER_AMON_R, /* ADC 3 */ + ADC_CHARGER_PMON, /* ADC 6 */ ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */ /* Number of ADC channels */ @@ -239,7 +238,7 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal); /* RT1718S gpio to pin name mapping */ #define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1 #define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2 -#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 +#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/cherry/build.mk b/baseboard/cherry/build.mk index ae82c1ca68..74609511c3 100644 --- a/baseboard/cherry/build.mk +++ b/baseboard/cherry/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c index 1e7664bab9..450f5c06d7 100644 --- a/baseboard/cherry/usb_pd_policy.c +++ b/baseboard/cherry/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #error Cherry reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) /* The port that the aux channel is on. */ static enum { @@ -90,8 +90,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) dp_status[port] = payload[1]; - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -164,7 +163,7 @@ __override void svdm_exit_dp_mode(int port) svdm_set_hpd_gpio(port, 0); #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) baseboard_mst_enable_control(port, 0); @@ -204,16 +203,11 @@ int pd_snk_is_vbus_provided(int port) void pd_power_supply_reset(int port) { - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - /* Disable VBUS. */ ppc_vbus_source_enable(port, 0); /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); + pd_set_vbus_discharge(port, 1); if (port == 1) rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0); diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c index 60b3949e93..cd55f37588 100644 --- a/baseboard/dedede/baseboard.c +++ b/baseboard/dedede/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ #include "usb_pd.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /******************************************************************************/ /* @@ -81,7 +81,6 @@ const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { }; const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); - /* * Dedede does not use hibernate wake pins, but the super low power "Z-state" * instead in which the EC is powered off entirely. Power will be restored to @@ -149,8 +148,8 @@ __override int intel_x86_get_pg_ec_dsw_pwrok(void) } /* Store away PP300_A good status before sysjumps */ -#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ -#define BASEBOARD_HOOK_VERSION 1 +#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ +#define BASEBOARD_HOOK_VERSION 1 static void pp3300_a_pgood_preserve(void) { @@ -167,13 +166,13 @@ static void baseboard_prepare_power_signals(void) stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG, &version, &size); if (stored && (version == BASEBOARD_HOOK_VERSION) && - (size == sizeof(pp3300_a_pgood))) + (size == sizeof(pp3300_a_pgood))) /* Valid PP3300 status found, restore before CHIPSET init */ pp3300_a_pgood = *stored; /* Restore pull-up on PG_PP1050_ST_OD */ if (system_jumped_to_this_image() && - gpio_get_level(GPIO_PG_EC_RSMRST_ODL)) + gpio_get_level(GPIO_PG_EC_RSMRST_ODL)) board_after_rsmrst(1); } DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST); @@ -191,8 +190,8 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void) * PGOOD. */ return gpio_get_level(GPIO_PG_PP1050_ST_OD) && - gpio_get_level(GPIO_PG_DRAM_OD) && - gpio_get_level(GPIO_PG_VCCIO_EXT_OD); + gpio_get_level(GPIO_PG_DRAM_OD) && + gpio_get_level(GPIO_PG_VCCIO_EXT_OD); } __override int power_signal_get_level(enum gpio_signal signal) @@ -209,7 +208,6 @@ __override int power_signal_get_level(enum gpio_signal signal) return espi_vw_get_wire((enum espi_vw_signal)signal); } return gpio_get_level(signal); - } void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) @@ -220,8 +218,8 @@ void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) * driver to. * Early protos do not pull VCCST_PWRGD below Vil in hardware logic, * so we need to do the same for this signal. - * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during - * SLP_S3_L assertion. + * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW + * during SLP_S3_L assertion. */ if (!gpio_get_level(GPIO_SLP_S3_L)) { gpio_set_level(GPIO_ALL_SYS_PWRGD, 0); @@ -259,9 +257,9 @@ void board_hibernate_late(void) /* Disable any pull-ups on C0 and C1 interrupt lines */ gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT); - #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); - #endif +#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 + gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); +#endif /* * Turn on the Z state. This will not return as it will cut power to * the EC. @@ -296,7 +294,7 @@ int board_is_i2c_port_powered(int port) return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; } -int extpower_is_present(void) +__overridable int extpower_is_present(void) { int port; int rv; diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index 0085c48ec3..e581a0e8d0 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,11 +8,13 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H +#define CONFIG_LTO + /* * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -20,39 +22,37 @@ * Variant EC defines. Pick one: * VARIANT_DEDEDE_EC_NPCX796FC */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \ - defined(VARIANT_KEEBY_EC_NPCX797FC) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* No tach. */ - - /* Internal SPI flash on NPCX7 */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_A - #define I2C_PORT_BATTERY IT83XX_I2C_CH_B - #define I2C_PORT_SENSOR IT83XX_I2C_CH_C - #define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_C0 IT83XX_I2C_CH_F - - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - #define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ - - #undef CONFIG_UART_TX_BUF_SIZE /* UART */ - #define CONFIG_UART_TX_BUF_SIZE 4096 - - /* - * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at - * 48MHz core cpu clock. - */ - #define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 +#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || defined(VARIANT_KEEBY_EC_NPCX797FC) +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ +#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320) +/* IT83XX config */ +#define CONFIG_IT83XX_VCC_1P8V +/* I2C Bus Configuration */ +#define I2C_PORT_EEPROM IT83XX_I2C_CH_A +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_SENSOR IT83XX_I2C_CH_C +#define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_C0 IT83XX_I2C_CH_F + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ + +#undef CONFIG_UART_TX_BUF_SIZE /* UART */ +#define CONFIG_UART_TX_BUF_SIZE 4096 + +/* + * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at + * 48MHz core cpu clock. + */ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 #else #error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!" #endif @@ -71,36 +71,36 @@ * Remapping of schematic GPIO names to common GPIO names expected (hardcoded) * in the EC code base. */ -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L -#define GPIO_EN_PP5000 GPIO_EN_PP5000_U -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L +#define GPIO_EN_PP5000 GPIO_EN_PP5000_U +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV #if !KEEBY_VARIANT -#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE +#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE #endif -#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK -#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK +#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L #if KEEBY_VARIANT -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL #else -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL #endif -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD -#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_WP GPIO_EC_WP_OD -#define GPIO_TABLET_MODE_L GPIO_LID_360_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD +#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_WP GPIO_EC_WP_OD +#define GPIO_TABLET_MODE_L GPIO_LID_360_L /* Common EC defines */ @@ -175,7 +175,7 @@ /* Backlight */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD +#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD /* LED */ #define CONFIG_LED_COMMON @@ -206,7 +206,7 @@ /* Temp Sensor */ #define CONFIG_TEMP_SENSOR_POWER -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A #define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 /* USB PD */ @@ -238,14 +238,13 @@ #endif /* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 45000 #define PD_OPERATING_POWER_MW 15000 /* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ #ifndef __ASSEMBLER__ @@ -255,13 +254,8 @@ /* Common enums */ #if defined(VARIANT_DEDEDE_EC_NPCX796FC) -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - enum board_vcmp { - VCMP_SNS_PP3300_LOW, - VCMP_SNS_PP3300_HIGH, - VCMP_COUNT - }; +#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320) +enum board_vcmp { VCMP_SNS_PP3300_LOW, VCMP_SNS_PP3300_HIGH, VCMP_COUNT }; #endif /* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */ diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk index 6d7452081e..af71eb2222 100644 --- a/baseboard/dedede/build.mk +++ b/baseboard/dedede/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c index 65a8cbaad9..612c51700d 100644 --- a/baseboard/dedede/cbi_fw_config.c +++ b/baseboard/dedede/cbi_fw_config.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -35,36 +35,36 @@ enum fw_config_db get_cbi_fw_config_db(void) enum fw_config_stylus get_cbi_fw_config_stylus(void) { - return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) - >> FW_CONFIG_STYLUS_OFFSET); + return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) >> + FW_CONFIG_STYLUS_OFFSET); } enum fw_config_kblight_type get_cbi_fw_config_kblight(void) { - return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) - >> FW_CONFIG_KB_BL_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >> + FW_CONFIG_KB_BL_OFFSET); } enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void) { - return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) - >> FW_CONFIG_TABLET_MODE_OFFSET); + return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) >> + FW_CONFIG_TABLET_MODE_OFFSET); } int get_cbi_fw_config_keyboard(void) { - return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) - >> FW_CONFIG_KB_LAYOUT_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >> + FW_CONFIG_KB_LAYOUT_OFFSET); } enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void) { - return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) - >> FW_CONFIG_KB_NUMPAD_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) >> + FW_CONFIG_KB_NUMPAD_OFFSET); } enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void) { - return ((cached_fw_config & FW_CONFIG_HDMI_MASK) - >> FW_CONFIG_HDMI_OFFSET); + return ((cached_fw_config & FW_CONFIG_HDMI_MASK) >> + FW_CONFIG_HDMI_OFFSET); } diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h index 90cc5e5fbe..80712f2849 100644 --- a/baseboard/dedede/cbi_fw_config.h +++ b/baseboard/dedede/cbi_fw_config.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -24,8 +24,8 @@ enum fw_config_db { DB_1C, DB_1A_HDMI_LTE, }; -#define FW_CONFIG_DB_OFFSET 0 -#define FW_CONFIG_DB_MASK GENMASK(3, 0) +#define FW_CONFIG_DB_OFFSET 0 +#define FW_CONFIG_DB_MASK GENMASK(3, 0) /* * Stylus (1 bit) @@ -34,8 +34,8 @@ enum fw_config_stylus { STYLUS_ABSENT = 0, STYLUS_PRESENT = 1, }; -#define FW_CONFIG_STYLUS_OFFSET 4 -#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4) +#define FW_CONFIG_STYLUS_OFFSET 4 +#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4) /* * Keyboard backlight (1 bit) @@ -44,8 +44,8 @@ enum fw_config_kblight_type { KB_BL_ABSENT = 0, KB_BL_PRESENT = 1, }; -#define FW_CONFIG_KB_BL_OFFSET 8 -#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) +#define FW_CONFIG_KB_BL_OFFSET 8 +#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) /* * Keyboard numeric pad (1 bit) @@ -54,8 +54,8 @@ enum fw_config_numeric_pad_type { NUMERIC_PAD_ABSENT = 0, NUMERIC_PAD_PRESENT = 1, }; -#define FW_CONFIG_KB_NUMPAD_OFFSET 9 -#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) +#define FW_CONFIG_KB_NUMPAD_OFFSET 9 +#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) /* * Tablet Mode (1 bit) @@ -64,11 +64,11 @@ enum fw_config_tablet_mode_type { TABLET_MODE_ABSENT = 0, TABLET_MODE_PRESENT = 1, }; -#define FW_CONFIG_TABLET_MODE_OFFSET 10 -#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) +#define FW_CONFIG_TABLET_MODE_OFFSET 10 +#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) -#define FW_CONFIG_KB_LAYOUT_OFFSET 12 -#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) +#define FW_CONFIG_KB_LAYOUT_OFFSET 12 +#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) /* * Hdmi (1 bit) @@ -77,8 +77,8 @@ enum fw_config_hdmi_type { HDMI_ABSENT = 0, HDMI_PRESENT = 1, }; -#define FW_CONFIG_HDMI_OFFSET 17 -#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) +#define FW_CONFIG_HDMI_OFFSET 17 +#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) enum fw_config_db get_cbi_fw_config_db(void); enum fw_config_stylus get_cbi_fw_config_stylus(void); diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c index 29c7758c6a..37929ceb0b 100644 --- a/baseboard/dedede/variant_ec_it8320.c +++ b/baseboard/dedede/variant_ec_it8320.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,7 +16,7 @@ #include "power.h" #include "registers.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) static void pp3300_a_pgood_low(void) { @@ -75,47 +75,37 @@ BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT); /* I2C Ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, -#ifdef HAS_TASK_MOTIONSENSE - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, +#if defined(HAS_TASK_MOTIONSENSE) || defined(BOARD_SHOTZO) + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, #endif #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c index aa2709b33b..366fca878e 100644 --- a/baseboard/dedede/variant_ec_npcx796fc.c +++ b/baseboard/dedede/variant_ec_npcx796fc.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,8 +21,8 @@ #include "timer.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) void pp3300_a_pgood_high(void) { @@ -79,7 +79,7 @@ static void set_up_adc_irqs(void) npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); } -DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1); +DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC + 1); static void disable_adc_irqs_deferred(void) { @@ -144,8 +144,8 @@ static void enable_adc_irqs(void) if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) { CPRINTS("%s", __func__); hook_call_deferred(&disable_adc_irqs_deferred_data, -1); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, - 1); + npcx_set_adc_repetitive( + adc_channels[ADC_VSNS_PP3300_A].input_ch, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); } @@ -162,56 +162,44 @@ DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT); /* I2C Ports */ __attribute__((weak)) const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 1000, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 1000, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, #ifdef HAS_TASK_MOTIONSENSE - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, #endif - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif #ifdef BOARD_BUGZZY - { - .name = "lcd", - .port = I2C_PORT_LCD, - .kbps = 400, - .scl = GPIO_EC_I2C_LCD_SCL, - .sda = GPIO_EC_I2C_LCD_SDA - }, + { .name = "lcd", + .port = I2C_PORT_LCD, + .kbps = 400, + .scl = GPIO_EC_I2C_LCD_SCL, + .sda = GPIO_EC_I2C_LCD_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c index d51b881753..f70f070fac 100644 --- a/baseboard/goroh/baseboard.c +++ b/baseboard/goroh/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -48,8 +48,8 @@ #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Wake-up pins for hibernate */ enum gpio_signal hibernate_wake_pins[] = { @@ -68,11 +68,9 @@ const struct charger_config_t chg_chips[] = { }; /* BC12 skeleton to make build happy. */ -struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { -}; +struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {}; -const int usb_port_enable[USB_PORT_COUNT] = { -}; +const int usb_port_enable[USB_PORT_COUNT] = {}; /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) @@ -109,34 +107,26 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -145,7 +135,6 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY); } - void board_overcurrent_event(int port, int is_overcurrented) { /* TODO: check correct operation for GOROH */ @@ -155,21 +144,25 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h index c0246e9970..1488bb6fcf 100644 --- a/baseboard/goroh/baseboard.h +++ b/baseboard/goroh/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -73,20 +73,20 @@ #define CONFIG_KEYBOARD_BACKLIGHT #define CONFIG_PWM_KBLIGHT #define CONFIG_KBLIGHT_ENABLE_PIN -#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X +#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X /* I2C */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_PASSTHRU_RESTRICTED #define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define I2C_PORT_EEPROM IT83XX_I2C_CH_A #define I2C_PORT_CHARGER IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_A #define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C +#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define CONFIG_SMBUS_PEC @@ -128,14 +128,14 @@ #define CONFIG_USB_PD_TCPMV2 #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PID 0x5566 /* TODO: update PID */ +#define CONFIG_USB_PID 0x5566 /* TODO: update PID */ #define CONFIG_USB_POWER_DELIVERY #define PD_MAX_CURRENT_MA 3000 #define PD_MAX_VOLTAGE_MV 20000 #define PD_OPERATING_POWER_MW 15000 #define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* USB-A */ @@ -174,13 +174,13 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* GPIO name remapping */ -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD #ifndef __ASSEMBLER__ diff --git a/baseboard/goroh/baseboard_usbc_config.h b/baseboard/goroh/baseboard_usbc_config.h index b5e76644ee..7da00c17d6 100644 --- a/baseboard/goroh/baseboard_usbc_config.h +++ b/baseboard/goroh/baseboard_usbc_config.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c index fd2001d8a3..7bc77d5229 100644 --- a/baseboard/goroh/board_id.c +++ b/baseboard/goroh/board_id.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -34,21 +34,8 @@ * 14 | 47 | 680 | 3086.7 */ const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, + 136, 388, 584, 785, 993, 1220, 1432, 1650, + 1875, 2084, 2273, 2461, 2672, 2888, 3086, }; const int threshold_mv = 100; diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk index 4488c4b395..6a3a386efb 100644 --- a/baseboard/goroh/build.mk +++ b/baseboard/goroh/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c index 5030489ec8..e92ced5e89 100644 --- a/baseboard/goroh/usb_pd_policy.c +++ b/baseboard/goroh/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,8 +15,8 @@ #error Goroh reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) void svdm_set_hpd_gpio(int port, int en) { diff --git a/baseboard/goroh/usbc_config.c b/baseboard/goroh/usbc_config.c index 5a49d2ee2d..9d162ca783 100644 --- a/baseboard/goroh/usbc_config.c +++ b/baseboard/goroh/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,14 +14,14 @@ #include "hooks.h" #include "driver/tcpm/it8xxx2_pd_public.h" #include "driver/ppc/syv682x_public.h" -#include "driver/retimer/ps8818.h" +#include "driver/retimer/ps8818_public.h" #include "driver/tcpm/tcpci.h" #include "usb_pd.h" #include "usbc_ppc.h" #include "gpio.h" #include "gpio_signal.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(pin, lvl) gpio_set_level_verbose(CC_USBPD, pin, lvl) @@ -62,7 +62,6 @@ static int goroh_usb_c0_set_mux(const struct usb_mux *me, mux_state_t mux_state, mux_state = mux_state ^ USB_PD_MUX_POLARITY_INVERTED; return virtual_usb_mux_driver.set(me, mux_state, ack_required); - } static int goroh_usb_c0_get_mux(const struct usb_mux *me, @@ -77,25 +76,32 @@ static struct usb_mux_driver goroh_usb_c0_mux_driver = { .get = goroh_usb_c0_get_mux, }; -static const struct usb_mux goroh_usb_c1_ps8818_retimer = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_C1, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .next_mux = NULL, +static const struct usb_mux_chain goroh_usb_c1_ps8818_retimer = { + .mux = + &(const struct usb_mux){ + .usb_port = USBC_PORT_C1, + .i2c_port = I2C_PORT_USB_C1, + .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, + .driver = &ps8818_usb_retimer_driver, + }, + .next = NULL, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .driver = &goroh_usb_c0_mux_driver, - .hpd_update = &virtual_hpd_update, + .mux = &(const struct usb_mux) { + .usb_port = USBC_PORT_C0, + .driver = &goroh_usb_c0_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }, [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, - .next_mux = &goroh_usb_c1_ps8818_retimer, + .mux = &(const struct usb_mux) { + .usb_port = USBC_PORT_C1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, + .next = &goroh_usb_c1_ps8818_retimer, }, }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); @@ -128,7 +134,6 @@ void ppc_interrupt(enum gpio_signal signal) syv682x_interrupt(1); } - static void board_tcpc_init(void) { gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL); diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c index b1f110033a..5fbf2823be 100644 --- a/baseboard/grunt/baseboard.c +++ b/baseboard/grunt/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -47,34 +47,29 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_TEMP_SENSOR_SOC] = { - "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_VBUS] = { - "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID1] = { - "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID2] = { - "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, + [ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_SOC] = { "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_SKU_ID1] = { "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_SKU_ID2] = { "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, - {GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"}, - {GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"}, - {GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"}, + { GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED" }, + { GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED" }, + { GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD" }, + { GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -156,7 +151,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -278,46 +273,48 @@ static uint32_t sku_id; static int ps8751_tune_mux(const struct usb_mux *me) { /* Tune USB mux registers for treeya's port 1 Rx measurement */ - if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) + if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf) mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40); return EC_SUCCESS; } -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { #ifdef VARIANT_GRUNT_TCPC_0_ANX3429 [USB_PD_PORT_ANX74XX] = { - .usb_port = USB_PD_PORT_ANX74XX, - .driver = &anx74xx_tcpm_usb_mux_driver, - .hpd_update = &anx74xx_tcpc_update_hpd_status, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_ANX74XX, + .driver = &anx74xx_tcpm_usb_mux_driver, + .hpd_update = &anx74xx_tcpc_update_hpd_status, + }, }, #elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) [USB_PD_PORT_ANX74XX] = { - .usb_port = USB_PD_PORT_ANX74XX, - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_ANX74XX, + .driver = &anx7447_usb_mux_driver, + .hpd_update = &anx7447_tcpc_update_hpd_status, + }, }, #endif [USB_PD_PORT_PS8751] = { - .usb_port = USB_PD_PORT_PS8751, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_PS8751, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .board_init = &ps8751_tune_mux, + }, } }; struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -338,8 +335,8 @@ int ppc_get_alert_status(int port) void board_overcurrent_event(int port, int is_overcurrented) { - enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L - : GPIO_USB_C1_OC_L; + enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L : + GPIO_USB_C1_OC_L; /* Note that the levels are inverted because the pin is active low. */ int lvl = is_overcurrented ? 0 : 1; @@ -371,7 +368,6 @@ const struct charger_config_t chg_chips[] = { }, }; - const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_5V, GPIO_EN_USB_A1_5V, @@ -393,7 +389,6 @@ static void baseboard_chipset_resume(void) { /* Allow display backlight to turn on. See above backlight comment */ gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0); - } DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); @@ -469,17 +464,16 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 95% negotiated limit, * to account for the charger chip margin. */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /* Keyboard scan setting */ @@ -513,19 +507,19 @@ __override struct keyboard_scan_config keyscan_config = { * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. */ static const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} + { 2761 / THERMISTOR_SCALING_FACTOR, 0 }, + { 2492 / THERMISTOR_SCALING_FACTOR, 10 }, + { 2167 / THERMISTOR_SCALING_FACTOR, 20 }, + { 1812 / THERMISTOR_SCALING_FACTOR, 30 }, + { 1462 / THERMISTOR_SCALING_FACTOR, 40 }, + { 1146 / THERMISTOR_SCALING_FACTOR, 50 }, + { 878 / THERMISTOR_SCALING_FACTOR, 60 }, + { 665 / THERMISTOR_SCALING_FACTOR, 70 }, + { 500 / THERMISTOR_SCALING_FACTOR, 80 }, + { 434 / THERMISTOR_SCALING_FACTOR, 85 }, + { 376 / THERMISTOR_SCALING_FACTOR, 90 }, + { 326 / THERMISTOR_SCALING_FACTOR, 95 }, + { 283 / THERMISTOR_SCALING_FACTOR, 100 } }; static const struct thermistor_info thermistor_info = { @@ -537,8 +531,8 @@ static const struct thermistor_info thermistor_info = { static int board_get_temp(int idx, int *temp_k) { /* idx is the sensor index set below in temp_sensors[] */ - int mv = adc_read_channel( - idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER); + int mv = adc_read_channel(idx ? ADC_TEMP_SENSOR_SOC : + ADC_TEMP_SENSOR_CHARGER); int temp_c; if (mv < 0) @@ -550,9 +544,9 @@ static int board_get_temp(int idx, int *temp_k) } const struct temp_sensor_t temp_sensors[] = { - {"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0}, - {"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1}, - {"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0}, + { "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0 }, + { "SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1 }, + { "CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -655,11 +649,11 @@ __override void lid_angle_peripheral_enable(int enable) static const int sku_thresh_mv[] = { /* Vin = 3.3V, Ideal voltage, R2 values listed below */ /* R1 = 51.1 kOhm */ - 200, /* 124 mV, 2.0 Kohm */ - 366, /* 278 mV, 4.7 Kohm */ - 550, /* 456 mV, 8.2 Kohm */ - 752, /* 644 mV, 12.4 Kohm */ - 927, /* 860 mV, 18.0 Kohm */ + 200, /* 124 mV, 2.0 Kohm */ + 366, /* 278 mV, 4.7 Kohm */ + 550, /* 456 mV, 8.2 Kohm */ + 752, /* 644 mV, 12.4 Kohm */ + 927, /* 860 mV, 18.0 Kohm */ 1073, /* 993 mV, 22.0 Kohm */ 1235, /* 1152 mV, 27.4 Kohm */ 1386, /* 1318 mV, 34.0 Kohm */ @@ -706,10 +700,9 @@ static uint32_t board_get_adc_sku_id(void) static int board_get_gpio_board_version(void) { - return - (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | - (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | - (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); + return (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | + (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | + (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); } static int board_version; @@ -767,8 +760,8 @@ int board_is_convertible(void) /* Kasumi360: 82 */ /* Treeya360: a8-af, be, bf*/ return (sku_id == 6 || sku_id == 82 || - ((sku_id >= 0xa8) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf); + ((sku_id >= 0xa8) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf); } int board_is_lid_angle_tablet_mode(void) @@ -782,13 +775,11 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) * Remove keyboard backlight feature for devices that don't support it. * All Treeya and Treeya360 models do not support keyboard backlight. */ - if (sku_id == 16 || sku_id == 17 || - sku_id == 20 || sku_id == 21 || - sku_id == 32 || sku_id == 33 || - sku_id == 40 || sku_id == 41 || + if (sku_id == 16 || sku_id == 17 || sku_id == 20 || sku_id == 21 || + sku_id == 32 || sku_id == 33 || sku_id == 40 || sku_id == 41 || sku_id == 44 || sku_id == 45 || - ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) + ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf) return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); else return flags0; diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index 5a79c48c63..1c19c05330 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,15 +8,15 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H -#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \ - + defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1 +#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) + \ + defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1 #error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447 #endif /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ /* Flash is 1MB but reserve half for future use. */ @@ -85,7 +85,7 @@ * ACOK from ISL9238 sometimes has a negative pulse after connecting * USB-C power. We want to ignore it. b/77455171 */ -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_POWER_COMMON @@ -101,7 +101,6 @@ */ #define CONFIG_BOARD_RESET_AFTER_POWER_ON - #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 @@ -139,13 +138,13 @@ #define CONFIG_USB_PORT_POWER_DUMB #define USB_PORT_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Require PD negotiation to be complete when we are in a low-battery condition @@ -158,15 +157,15 @@ #undef CONFIG_PORT80_HISTORY_LEN #define CONFIG_PORT80_HISTORY_LEN 256 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* Sensors */ #define CONFIG_MKBP_EVENT @@ -184,8 +183,8 @@ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #endif /* VARIANT_GRUNT_NO_SENSORS */ -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 #ifndef __ASSEMBLER__ diff --git a/baseboard/grunt/build.mk b/baseboard/grunt/build.mk index cb9d607c36..c8a02aa85d 100644 --- a/baseboard/grunt/build.mk +++ b/baseboard/grunt/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Copyright 2018 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c index 7c4fff953c..9cae485bc9 100644 --- a/baseboard/grunt/usb_pd_policy.c +++ b/baseboard/grunt/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,11 +17,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) int pd_check_vconn_swap(int port) { @@ -118,11 +118,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -142,8 +142,8 @@ __override void svdm_dp_post_config(int port) /* set the minimum time delay (2ms) for the next HPD IRQ */ svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, + USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED); } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h index 2eea7a158f..a9504a6b45 100644 --- a/baseboard/guybrush/base_fw_config.h +++ b/baseboard/guybrush/base_fw_config.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc index 6fd90ed0d3..82b042f890 100644 --- a/baseboard/guybrush/base_gpio.inc +++ b/baseboard/guybrush/base_gpio.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c index 6a390b0a43..5d36f5be9a 100644 --- a/baseboard/guybrush/baseboard.c +++ b/baseboard/guybrush/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,11 +16,11 @@ #include "chip/npcx/ps2_chip.h" #include "chip/npcx/pwm_chip.h" #include "chipset.h" -#include "driver/ppc/aoz1380.h" +#include "driver/ppc/aoz1380_public.h" #include "driver/ppc/nx20p348x.h" #include "driver/retimer/anx7491.h" #include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" +#include "driver/retimer/ps8818_public.h" #include "driver/tcpm/nct38xx.h" #include "driver/usb_mux/anx7451.h" #include "driver/usb_mux/amd_fp6.h" @@ -40,10 +40,10 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format ## args) +#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format##args) static void reset_nct38xx_port(int port); @@ -53,7 +53,7 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* Power Signal Input List */ const struct power_signal_info power_signal_list[] = { @@ -145,8 +145,6 @@ const struct i2c_port_t i2c_ports[] = { }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - - const struct charger_config_t chg_chips[] = { { .i2c_port = I2C_PORT_CHARGER, @@ -235,7 +233,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); -static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t); +static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t); __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) @@ -244,7 +242,7 @@ __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, return 0; } -struct usb_mux usbc1_ps8818 = { +const struct usb_mux usbc1_ps8818 = { .usb_port = USBC_PORT_C1, .i2c_port = I2C_PORT_TCPC1, .flags = USB_MUX_FLAG_RESETS_IN_G3, @@ -260,7 +258,7 @@ __overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, return 0; } -struct usb_mux usbc1_anx7451 = { +const struct usb_mux usbc1_anx7451 = { .usb_port = USBC_PORT_C1, .i2c_port = I2C_PORT_TCPC1, .flags = USB_MUX_FLAG_RESETS_IN_G3, @@ -269,20 +267,27 @@ struct usb_mux usbc1_anx7451 = { .board_set = &board_c1_anx7451_mux_set, }; -struct usb_mux usb_muxes[] = { +/* Filled in by setup_mux based on fw_config */ +struct usb_mux_chain usbc1_mux1; + +struct usb_mux_chain usb_muxes[] = { [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .board_set = &fsusb42umx_set_mux, + .mux = &(const struct usb_mux) { + .usb_port = USBC_PORT_C0, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, + .driver = &amd_fp6_usb_mux_driver, + .board_set = &fsusb42umx_set_mux, + }, }, [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ + .mux = &(const struct usb_mux) { + .usb_port = USBC_PORT_C1, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, + .driver = &amd_fp6_usb_mux_driver, + }, + .next = &usbc1_mux1, } }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); @@ -375,22 +380,22 @@ static void setup_mux(void) switch (board_get_usb_c1_mux()) { case USB_C1_MUX_PS8818: CPRINTSUSB("C1: Setting PS8818 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818; + usbc1_mux1.mux = &usbc1_ps8818; break; case USB_C1_MUX_ANX7451: CPRINTSUSB("C1: Setting ANX7451 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; + usbc1_mux1.mux = &usbc1_anx7451; break; default: CPRINTSUSB("C1: Mux is unknown"); + usb_muxes[USBC_PORT_C1].next = NULL; } } DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; @@ -404,7 +409,7 @@ int board_set_active_charge_port(int port) * ahead and reset it so EN_SNK responds properly. */ if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } @@ -453,7 +458,7 @@ int board_set_active_charge_port(int port) * change because we'll brown out. */ if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } else { @@ -505,7 +510,9 @@ int board_is_i2c_port_powered(int port) case I2C_PORT_THERMAL_AP: /* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */ return chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1; + CHIPSET_STATE_ANY_SUSPEND) ? + 0 : + 1; default: return 1; } @@ -516,8 +523,7 @@ int board_is_i2c_port_powered(int port) * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; @@ -528,12 +534,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port, return rv; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void sbu_fault_interrupt(enum ioex_signal signal) @@ -571,10 +576,10 @@ void tcpc_alert_event(enum gpio_signal signal) static void reset_nct38xx_port(int port) { int rv; - int saved_state[IOEX_COUNT] = {0}; + int saved_state[IOEX_COUNT] = { 0 }; enum gpio_signal reset_gpio_l = (port == USBC_PORT_C0) ? - GPIO_USB_C0_TCPC_RST_L : - GPIO_USB_C1_TCPC_RST_L; + GPIO_USB_C0_TCPC_RST_L : + GPIO_USB_C1_TCPC_RST_L; if (port < 0 || port > USBC_PORT_COUNT) { CPRINTSUSB("%s invalid port %d", __func__, port); @@ -877,9 +882,9 @@ static void baseboard_set_en_pwr_pcore(void) * EN_PWR_S0_R. */ gpio_set_level(GPIO_EN_PWR_PCORE_S0_R, - gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) && - gpio_get_level(GPIO_PG_GROUPC_S0_OD) && - gpio_get_level(GPIO_EN_PWR_S0_R)); + gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) && + gpio_get_level(GPIO_PG_GROUPC_S0_OD) && + gpio_get_level(GPIO_EN_PWR_S0_R)); } void baseboard_en_pwr_pcore_signal(enum gpio_signal signal) @@ -891,19 +896,17 @@ static void baseboard_check_groupc_low(void) { /* Warn if we see unexpected sequencing here */ if (!gpio_get_level(GPIO_EN_PWR_S0_R) && - gpio_get_level(GPIO_PG_GROUPC_S0_OD)) + gpio_get_level(GPIO_PG_GROUPC_S0_OD)) CPRINTSCHIP("WARN: PG_GROUPC_S0_OD high while EN_PWR_S0_R low"); - } DECLARE_DEFERRED(baseboard_check_groupc_low); void baseboard_en_pwr_s0(enum gpio_signal signal) { - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ gpio_set_level(GPIO_EN_PWR_S0_R, - gpio_get_level(GPIO_SLP_S3_L) && - gpio_get_level(GPIO_PG_PWR_S5)); + gpio_get_level(GPIO_SLP_S3_L) && + gpio_get_level(GPIO_PG_PWR_S5)); /* * If we set EN_PWR_S0_R low, then check PG_GROUPC_S0_OD went low as @@ -973,7 +976,7 @@ __override void power_board_handle_sleep_hang(enum sleep_hang_type hang_type) ccprints("Consecutive(%d) hard sleep hangs detected!", hard_sleep_hang_count); ccprints("AP will be force shutdown in %dms if hang persists", - HARD_SLEEP_HANG_TIMEOUT); + HARD_SLEEP_HANG_TIMEOUT); } hook_call_deferred(&board_handle_hard_sleep_hang_data, @@ -999,7 +1002,7 @@ static void board_handle_hard_sleep_hang(void) /* If AP reset does not break hang, force a shutdown */ shutdown_on_hard_hang = true; ccprints("AP will be shutdown in %dms if hang persists", - HARD_SLEEP_HANG_TIMEOUT); + HARD_SLEEP_HANG_TIMEOUT); hook_call_deferred(&board_handle_hard_sleep_hang_data, HARD_SLEEP_HANG_TIMEOUT * MSEC); chipset_reset(CHIPSET_RESET_HANG_REBOOT); diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h index 2e30dfcc27..04b1e10c97 100644 --- a/baseboard/guybrush/baseboard.h +++ b/baseboard/guybrush/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,8 +10,8 @@ /* NPCX9 config */ #define CONFIG_PORT80_4_BYTE -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Optional features */ #define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT @@ -32,8 +32,8 @@ #define CONFIG_VBOOT_HASH #define CONFIG_VSTORE #define CONFIG_VSTORE_SLOT_COUNT 1 -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE /* CBI Config */ #define CONFIG_CBI_EEPROM @@ -41,7 +41,7 @@ /* Power Config */ #define CONFIG_CHIPSET_X86_RSMRST_DELAY -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_HIBERNATE_PSL @@ -54,19 +54,19 @@ #define CONFIG_POWER_SLEEP_FAILURE_DETECTION #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE #define G3_TO_PWRBTN_DELAY_MS 16 -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 -#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD -#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD -#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 +#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD +#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD +#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L #define SAFE_RESET_VBUS_DELAY_MS 900 #define SAFE_RESET_VBUS_MV 5000 /* @@ -86,12 +86,12 @@ #define CONFIG_TEMP_SENSOR_SB_TSI #define CONFIG_THERMISTOR #define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL /* Flash Config */ /* See config_chip-npcx9.h for SPI flash configuration */ #undef CONFIG_SPI_FLASH /* Don't enable external flash interface */ -#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_WP_L GPIO_EC_WP_L /* Host communication */ #define CONFIG_CMD_APTHROTTLE @@ -99,7 +99,7 @@ #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT -#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L +#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L /* Chipset config */ #define CONFIG_CHIPSET_CEZANNE @@ -114,15 +114,15 @@ #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_KEYBOARD_VIVALDI #define CONFIG_KBLIGHT_ENABLE_PIN -#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* Sensors */ #ifdef HAS_TASK_MOTIONSENSE #define CONFIG_TABLET_MODE #define CONFIG_GMR_TABLET_MODE -#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE +#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -138,7 +138,7 @@ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) -#endif /* HAS_TASK_MOTIONSENSE */ +#endif /* HAS_TASK_MOTIONSENSE */ /* Backlight config */ #define CONFIG_BACKLIGHT_LID @@ -146,7 +146,7 @@ #define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL /* Battery Config */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_REVIVE_DISCONNECT @@ -172,7 +172,7 @@ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on * Depthcharge to boot OS. */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000 /* * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging @@ -226,8 +226,8 @@ #define CONFIG_IO_EXPANDER_NCT38XX #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* USB-A config */ #define USB_PORT_COUNT USBA_PORT_COUNT @@ -260,21 +260,21 @@ #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_UPDATE_IF_CHANGED -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT4_1 -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT4_1 +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Volume Button Config */ #define CONFIG_VOLUME_BUTTONS -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL /* Fan Config */ #define CONFIG_FANS FAN_CH_COUNT @@ -290,30 +290,22 @@ /* Power input signals */ enum power_signal { - X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ + X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ + X86_SLP_S3_N, /* SOC -> SLP_S3_L */ + X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ + X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ + X86_S5_PGOOD, /* PMIC -> S5_PWROK */ /* Number of X86 signals */ POWER_SIGNAL_COUNT, }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* TMP112 sensors */ enum tmp112_sensor { @@ -322,12 +314,7 @@ enum tmp112_sensor { TMP112_COUNT, }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* PWM Channels */ enum pwm_channel { diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk index dff52adc93..8110e6e6c4 100644 --- a/baseboard/guybrush/build.mk +++ b/baseboard/guybrush/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c index 6d66b826dc..6ce6fe0eb7 100644 --- a/baseboard/guybrush/cbi.c +++ b/baseboard/guybrush/cbi.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -50,10 +50,9 @@ uint32_t get_fw_config(void) return UNINITIALIZED_FW_CONFIG; fw_config = val; } - return fw_config; + return fw_config; } - int get_fw_config_field(uint8_t offset, uint8_t width) { uint32_t fw_config = get_fw_config(); @@ -64,7 +63,6 @@ int get_fw_config_field(uint8_t offset, uint8_t width) return (fw_config >> offset) & ((1 << width) - 1); } - __overridable void board_cbi_init(void) { } diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c index 79725e827a..8acb2c7a23 100644 --- a/baseboard/guybrush/usb_pd_policy.c +++ b/baseboard/guybrush/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c index bdbeb36a3c..f5376700c5 100644 --- a/baseboard/hatch/baseboard.c +++ b/baseboard/hatch/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -31,11 +31,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* Wake up pins */ @@ -52,85 +52,65 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { #ifdef CONFIG_ACCEL_FIFO - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, #endif - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, #endif - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, #ifdef BOARD_AKEMI - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif #ifdef BOARD_JINLON - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif #ifdef BOARD_MUSHU - { - .name = "f75303_temp", - .port = I2C_PORT_THERMAL, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "gpu_temp", - .port = I2C_PORT_GPU, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "f75303_temp", + .port = I2C_PORT_THERMAL, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "gpu_temp", + .port = I2C_PORT_GPU, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 100, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -202,17 +182,13 @@ void board_hibernate(void) /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, #endif }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -270,8 +246,8 @@ uint16_t tcpc_get_alert_status(void) return status; } -static void reset_pd_port(int port, enum gpio_signal reset_gpio, - int hold_delay, int finish_delay) +static void reset_pd_port(int port, enum gpio_signal reset_gpio, int hold_delay, + int finish_delay) { int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH); @@ -308,8 +284,7 @@ void board_reset_pd_mcu(void) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_valid_port && port != CHARGE_PORT_NONE) @@ -365,20 +340,19 @@ int ppc_get_alert_status(int port) if (port == USB_PD_PORT_TCPC_0) return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; return port == USB_PD_PORT_TCPC_0 ? - gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 : + gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 : #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; + gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; #else - EC_SUCCESS; + EC_SUCCESS; #endif } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } #ifdef USB_PD_PORT_TCPC_MST diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h index dc39fcf8ac..d5d680e7bf 100644 --- a/baseboard/hatch/baseboard.h +++ b/baseboard/hatch/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,13 +15,13 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS @@ -111,14 +111,14 @@ /* Common battery defines */ #define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_HW_PRESENT_CUSTOM #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_SMART -#undef CONFIG_BATT_HOST_FULL_FACTOR -#define CONFIG_BATT_HOST_FULL_FACTOR 100 +#undef CONFIG_BATT_HOST_FULL_FACTOR +#define CONFIG_BATT_HOST_FULL_FACTOR 100 /* USB Type C and USB PD defines */ #define CONFIG_USB_POWER_DELIVERY @@ -153,9 +153,9 @@ /* Include CLI command needed to support CCD testing. */ #define CONFIG_CMD_CHARGEN -#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_0 0 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 -#define USB_PD_PORT_TCPC_1 1 +#define USB_PD_PORT_TCPC_1 1 #endif /* BC 1.2 */ @@ -167,32 +167,32 @@ #endif /* TODO(b/122273953): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* TODO(b/122273953): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER /* Other common defines */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD +#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c index 063aa3721d..5ae92e8ec8 100644 --- a/baseboard/hatch/battery.c +++ b/baseboard/hatch/battery.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -32,8 +32,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* diff --git a/baseboard/hatch/build.mk b/baseboard/hatch/build.mk index 864225f605..f98ffdcb3f 100644 --- a/baseboard/hatch/build.mk +++ b/baseboard/hatch/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c index a66bfefe87..6abb6e4454 100644 --- a/baseboard/hatch/usb_pd_policy.c +++ b/baseboard/hatch/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c index 41d40dd7ae..fca6e9c66d 100644 --- a/baseboard/herobrine/baseboard.c +++ b/baseboard/herobrine/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h index ae5b2a3d33..0782612cb8 100644 --- a/baseboard/herobrine/baseboard.h +++ b/baseboard/herobrine/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,12 +13,12 @@ * The sensor stack is generating a lot of activity. * They can be enabled through the console command 'chan'. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_SPI_FLASH_REGS @@ -140,13 +140,13 @@ #define CONFIG_CMD_ACCEL_INFO /* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Chipset */ #define CONFIG_CHIPSET_SC7280 @@ -163,56 +163,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* I2C Ports */ #define I2C_PORT_BATTERY I2C_PORT_POWER #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_RTC NPCX_I2C_PORT4_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_RTC NPCX_I2C_PORT4_1 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* UART */ #define CONFIG_CMD_CHARGEN /* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) /* And the MKBP events */ #ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #else #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) + (BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #endif #endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk index f007fd7118..67c2e2143f 100644 --- a/baseboard/herobrine/build.mk +++ b/baseboard/herobrine/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c index 7ca2688aef..9fa725c845 100644 --- a/baseboard/herobrine/usb_pd_policy.c +++ b/baseboard/herobrine/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -231,16 +228,16 @@ __override int svdm_dp_attention(int port, uint32_t *payload) gpio_set_level(hpd, 1); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; } else { gpio_set_level(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -255,7 +252,7 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); } } diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c index f5ee9c157d..2ebb8ae029 100644 --- a/baseboard/herobrine/usbc_config.c +++ b/baseboard/herobrine/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c index e7df1b6ef4..506eb6f265 100644 --- a/baseboard/honeybuns/baseboard.c +++ b/baseboard/honeybuns/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,20 +18,17 @@ #include "driver/tcpm/tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define POWER_BUTTON_SHORT_USEC (300 * MSEC) #define POWER_BUTTON_LONG_USEC (5000 * MSEC) #define POWER_BUTTON_DEBOUNCE_USEC (30) -#define BUTTON_EVT_CHANGE BIT(0) -#define BUTTON_EVT_INFO BIT(1) +#define BUTTON_EVT_CHANGE BIT(0) +#define BUTTON_EVT_INFO BIT(1) -enum power { - POWER_OFF, - POWER_ON -}; +enum power { POWER_OFF, POWER_ON }; enum button { BUTTON_RELEASE, @@ -66,7 +63,7 @@ __maybe_unused static void board_power_sequence(int enable) int i; if (enable) { - for(i = 0; i < board_power_seq_count; i++) { + for (i = 0; i < board_power_seq_count; i++) { gpio_set_level(board_power_seq[i].signal, board_power_seq[i].level); CPRINTS("power seq: rail = %d", i); @@ -74,7 +71,7 @@ __maybe_unused static void board_power_sequence(int enable) msleep(board_power_seq[i].delay_ms); } } else { - for(i = board_power_seq_count - 1; i >= 0; i--) { + for (i = board_power_seq_count - 1; i >= 0; i--) { gpio_set_level(board_power_seq[i].signal, !board_power_seq[i].level); CPRINTS("sequence[%d]: level = %d", i, @@ -89,20 +86,16 @@ __maybe_unused static void board_power_sequence(int enable) /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "i2c1", - .port = I2C_PORT_I2C1, - .kbps = 400, - .scl = GPIO_EC_I2C1_SCL, - .sda = GPIO_EC_I2C1_SDA - }, - { - .name = "i2c3", - .port = I2C_PORT_I2C3, - .kbps = 400, - .scl = GPIO_EC_I2C3_SCL, - .sda = GPIO_EC_I2C3_SDA - }, + { .name = "i2c1", + .port = I2C_PORT_I2C1, + .kbps = 400, + .scl = GPIO_EC_I2C1_SCL, + .sda = GPIO_EC_I2C1_SDA }, + { .name = "i2c3", + .port = I2C_PORT_I2C3, + .kbps = 400, + .scl = GPIO_EC_I2C3_SCL, + .sda = GPIO_EC_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -246,7 +239,7 @@ static void baseboard_init(void) #else /* Set up host port usbc to present Rd on CC lines */ - if(baseboard_usbc_init(USB_PD_PORT_HOST)) + if (baseboard_usbc_init(USB_PD_PORT_HOST)) CPRINTS("usbc: Failed to set up sink path"); else CPRINTS("usbc: sink path configure success!"); @@ -381,11 +374,11 @@ void power_button_task(void *u) * Default wait state: Only need to check if the button * is pressed and start the short press timer. */ - if (evt & BUTTON_EVT_CHANGE && button_level == - BUTTON_PRESSED_LEVEL) { + if (evt & BUTTON_EVT_CHANGE && + button_level == BUTTON_PRESSED_LEVEL) { state = BUTTON_PRESS; timer_us = (POWER_BUTTON_SHORT_USEC - - POWER_BUTTON_DEBOUNCE_USEC); + POWER_BUTTON_DEBOUNCE_USEC); } break; case BUTTON_PRESS: @@ -399,7 +392,7 @@ void power_button_task(void *u) } else { /* Start long press timer */ timer_us = POWER_BUTTON_LONG_USEC - - POWER_BUTTON_SHORT_USEC; + POWER_BUTTON_SHORT_USEC; /* * If dock is currently off, then change to the * power on state. If dock is already on, then @@ -407,7 +400,7 @@ void power_button_task(void *u) */ if (dock_state == POWER_OFF) { baseboard_power_on(); - state = BUTTON_PRESS_POWER_ON; + state = BUTTON_PRESS_POWER_ON; } else { state = BUTTON_PRESS_SHORT; } @@ -474,9 +467,8 @@ void baseboard_power_button_evt(int level) POWER_BUTTON_DEBOUNCE_USEC); } -static int command_pwr_btn(int argc, char **argv) +static int command_pwr_btn(int argc, const char **argv) { - if (argc == 1) { task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO); return EC_SUCCESS; @@ -494,8 +486,7 @@ static int command_pwr_btn(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, - "<on|off|mf>", +DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, "<on|off|mf>", "Simulate Power Button Press"); #endif diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h index a22be156fe..4dd218f57d 100644 --- a/baseboard/honeybuns/baseboard.h +++ b/baseboard/honeybuns/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -40,30 +40,30 @@ /* Do not use a dedicated PSTATE bank */ #undef CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (64*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (64 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 #define CONFIG_STM_HWTIMER32 #define TIM_CLOCK32 2 -#define TIM_CLOCK_MSB 3 +#define TIM_CLOCK_MSB 3 #define TIM_CLOCK_LSB 15 #define TIM_WATCHDOG 7 @@ -80,7 +80,7 @@ #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX /* CBI Configs */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_CBI_EEPROM #define CONFIG_BOARD_VERSION_CBI #define CONFIG_CMD_CBI @@ -101,12 +101,12 @@ #define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_UPDATE 1 -#define USB_EP_COUNT 2 +#define USB_EP_CONTROL 0 +#define USB_EP_UPDATE 1 +#define USB_EP_COUNT 2 -#define USB_IFACE_UPDATE 0 -#define USB_IFACE_COUNT 1 +#define USB_IFACE_UPDATE 0 +#define USB_IFACE_COUNT 1 #ifndef __ASSEMBLER__ /* USB string indexes */ @@ -197,14 +197,14 @@ enum usb_strings { #define CONFIG_SHA256 /* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 5000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 5000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 15000 #define PD_OPERATING_POWER_MW 15000 /* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* I2C Bus Configuration */ #define CONFIG_I2C @@ -216,8 +216,8 @@ enum usb_strings { * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_WP_L #ifndef __ASSEMBLER__ @@ -226,8 +226,8 @@ enum usb_strings { struct power_seq { enum gpio_signal signal; /* power/reset gpio_signal to control */ - int level; /* level to set in power sequence */ - unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */ + int level; /* level to set in power sequence */ + unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */ }; enum mf_preference { @@ -239,9 +239,7 @@ enum mf_preference { * This is required as adc_channel is included in adc.h which ends up being * included when TCPMv2 functions are included */ -enum adc_channel { - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_COUNT }; extern const struct power_seq board_power_seq[]; extern const size_t board_power_seq_count; @@ -279,7 +277,6 @@ int baseboard_config_usbc_usb3_ppc(void); */ void baseboard_usb3_check_state(void); - /* * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected * by the host in the DP Configure SVDM message. @@ -323,7 +320,7 @@ int c1_ps8805_is_sourcing_vbus(int port); * @param port: The Type-C port number. * @param enable: 1: Turn on VBUS, 0: turn off VBUS. * @return EC_SUCCESS on success, error otherwise. - */ + */ int c1_ps8805_vbus_source_enable(int port, int enable); #endif /* !__ASSEMBLER__ */ diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk index 2868911925..57e93b0587 100644 --- a/baseboard/honeybuns/build.mk +++ b/baseboard/honeybuns/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c index ab95a7f9b6..956a73e7fb 100644 --- a/baseboard/honeybuns/usb_pd_policy.c +++ b/baseboard/honeybuns/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,45 +21,46 @@ #include "usb_tc_sm.h" #include "usbc_ppc.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define MP4245_VOLTAGE_WINDOW BIT(2) #define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1) -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \ + PDO_FIXED_UNCONSTRAINED) /* Voltage indexes for the PDOs */ enum volt_idx { - PDO_IDX_5V = 0, - PDO_IDX_9V = 1, - PDO_IDX_15V = 2, - PDO_IDX_20V = 3, + PDO_IDX_5V = 0, + PDO_IDX_9V = 1, + PDO_IDX_15V = 2, + PDO_IDX_20V = 3, PDO_IDX_COUNT }; /* PDOs */ const uint32_t pd_src_host_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), - [PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0), - [PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0), - [PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0), + [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + [PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0), + [PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0), + [PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0), }; BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT); #ifdef BOARD_C1_1A5_LIMIT const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), }; #else const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), }; #endif const uint32_t pd_snk_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); @@ -68,13 +69,12 @@ static int src_host_pdo_cnt_override; #define PD_DR_SWAP_ATTEMPT_MAX 3 static int pd_dr_swap_attempt_count[CONFIG_USB_PD_PORT_MAX_COUNT]; -static int command_hostpdo(int argc, char **argv) +static int command_hostpdo(int argc, const char **argv) { char *e; int limit; if (argc >= 2) { - limit = strtoi(argv[1], &e, 10); if ((limit < 0) || (limit > PDO_IDX_COUNT)) return EC_ERROR_PARAM1; @@ -85,8 +85,7 @@ static int command_hostpdo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, - "<0|1|2|3|4>", +DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, "<0|1|2|3|4>", "Limit number of PDOs for C0"); int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) @@ -94,7 +93,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) int pdo_cnt = 0; if (port == USB_PD_PORT_HOST) { - *src_pdo = pd_src_host_pdo; + *src_pdo = pd_src_host_pdo; pdo_cnt = ARRAY_SIZE(pd_src_host_pdo); /* * This override is only active via a console command. Only used @@ -105,7 +104,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) if (src_host_pdo_cnt_override) pdo_cnt = src_host_pdo_cnt_override; } else { - *src_pdo = pd_src_display_pdo; + *src_pdo = pd_src_display_pdo; pdo_cnt = ARRAY_SIZE(pd_src_display_pdo); } @@ -118,15 +117,15 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap */ -__override bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag) +__override bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr, + bool dr_swap_flag) { /* * Port0: test if role is DFP * Port1: test if role is UFP */ - enum pd_data_role role_test = - (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : PD_ROLE_UFP; + enum pd_data_role role_test = (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : + PD_ROLE_UFP; /* * Request data role swap if not in the port's desired data role and if @@ -135,8 +134,8 @@ __override bool port_discovery_dr_swap_policy(int port, * rejects data role swap requests (eg compliance tester), want to limit * how many DR swap requests are attempted. */ - if (dr == role_test && (pd_dr_swap_attempt_count[port]++ < - PD_DR_SWAP_ATTEMPT_MAX)) + if (dr == role_test && + (pd_dr_swap_attempt_count[port]++ < PD_DR_SWAP_ATTEMPT_MAX)) return true; /* Do not perform a DR swap */ @@ -148,8 +147,7 @@ __override bool port_discovery_dr_swap_policy(int port, * * 1) No need to Vconn swap. This board does not require any cable information. */ -__override bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag) +__override bool port_discovery_vconn_swap_policy(int port, bool vconn_swap_flag) { return false; } @@ -193,8 +191,7 @@ void pd_power_supply_reset(int port) * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next * attached.src condition. */ - pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, - &unused_mv); + pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, &unused_mv); mp4245_set_voltage_out(mv); /* Ensure voltage is back to 5V */ pd_transition_voltage(1); @@ -243,8 +240,7 @@ void pd_transition_voltage(int idx) * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st * PDO of SRC_CAP which must always be 5V fixed supply. */ - pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, - &mv); + pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, &mv); /* Initialize sample delay buffer */ for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++) @@ -327,11 +323,9 @@ int board_vbus_source_enabled(int port) void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) { - } -int pd_check_data_swap(int port, - enum pd_data_role data_role) +int pd_check_data_swap(int port, enum pd_data_role data_role) { int swap = 0; @@ -345,7 +339,6 @@ int pd_check_data_swap(int port, int pd_check_power_swap(int port) { - if (pd_get_power_role(port) == PD_ROLE_SINK) return 1; @@ -394,7 +387,7 @@ static void usb_tc_disconnect(void) DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT); __override bool pd_can_charge_from_device(int port, const int pdo_cnt, - const uint32_t *pdos) + const uint32_t *pdos) { /* * This function is called to determine if this port can be charged by @@ -421,22 +414,17 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ USB_VID_GOOGLE); static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 0, /* Data caps as USB host */ - 1, /* Data caps as USB device */ - IDH_PTYPE_HUB, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_UNDEFINED, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); + 0, /* Data caps as USB host */ + 1, /* Data caps as USB device */ + IDH_PTYPE_HUB, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_UNDEFINED, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_RECONFIGURE, - USB_R30_SS_U32_U40_GEN2); +static const uint32_t vdo_ufp1 = + VDO_UFP1((VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE, + USB_R30_SS_U32_U40_GEN2); static int svdm_response_identity(int port, uint32_t *payload) { @@ -479,14 +467,17 @@ static int svdm_response_svids(int port, uint32_t *payload) #define OPOS_DP 1 -const uint32_t vdo_dp_modes[1] = { +const uint32_t vdo_dp_modes[1] = { VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */ MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, - 0, /* DFP pin cfg supported */ - 0, /* usb2.0 signalling in AMode may be req */ - CABLE_RECEPTACLE, /* its a receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + 0, /* DFP pin + cfg + supported + */ + 0, /* usb2.0 signalling in AMode may be req */ + CABLE_RECEPTACLE, /* its a receptacle */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; static int svdm_response_modes(int port, uint32_t *payload) @@ -508,13 +499,12 @@ static int amode_dp_status(int port, uint32_t *payload) if (opos != OPOS_DP) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - mf, /* MF pref */ - vdm_is_dp_enabled(port), - 0, /* power low */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + mf, /* MF pref */ + vdm_is_dp_enabled(port), 0, /* power low */ 0x2); return 2; } @@ -536,8 +526,8 @@ static void svdm_configure_demux(int port, int enable, int mf) * stored in bit 0 of CBI fw_config. */ baseboard_set_mst_lane_control(mf); - CPRINTS("DP[%d]: DFP-D selected pin config %s", - port, mf ? "D" : "C"); + CPRINTS("DP[%d]: DFP-D selected pin config %s", port, + mf ? "D" : "C"); } else { demux &= ~USB_PD_MUX_DP_ENABLED; demux |= USB_PD_MUX_USB_ENABLED; @@ -573,7 +563,6 @@ static int svdm_enter_mode(int port, uint32_t *payload) /* SID & mode request is valid */ if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) && (PD_VDO_OPOS(payload[0]) == OPOS_DP)) { - /* Store valid object position to indicate mode is active */ pd_ufp_set_dp_opos(port, OPOS_DP); @@ -623,8 +612,7 @@ const struct svdm_response svdm_rsp = { .exit_mode = &svdm_exit_mode, }; -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) +int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload) { /* We don't support, so ignore this message */ return 0; diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c index c03e94f076..db68ad527c 100644 --- a/baseboard/honeybuns/usbc_support.c +++ b/baseboard/honeybuns/usbc_support.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ #include "registers.h" #include "ucpd-stm32gx.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) enum usbc_states { UNATTACHED_SNK, @@ -39,7 +39,7 @@ static int usbc_vbus; static enum tcpc_cc_voltage_status cc1_v; static enum tcpc_cc_voltage_status cc2_v; -__maybe_unused static __const_data const char * const usbc_state_names[] = { +__maybe_unused static __const_data const char *const usbc_state_names[] = { [UNATTACHED_SNK] = "Unattached.SNK", [ATTACH_WAIT_SNK] = "AttachWait.SNK", [ATTACHED_SNK] = "Attached.SNK", @@ -48,17 +48,13 @@ __maybe_unused static __const_data const char * const usbc_state_names[] = { static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int baseboard_ppc_enable_sink_path(int port) @@ -126,9 +122,9 @@ static void baseboard_ucpd_apply_rd(int port) */ cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); + STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | + STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | + STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); STM32_UCPD_CFGR1(port) = cfgr1_reg; /* Enable ucpd */ @@ -147,9 +143,8 @@ static void baseboard_ucpd_apply_rd(int port) STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; } - static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int vstate_cc1; int vstate_cc2; @@ -163,7 +158,7 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, * * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, * but needs to be modified slightly for case ANAMODE = 0. - * + * * If presenting Rp (source), then need to to a circular shift of * vstate_ccx value: * vstate_cc | cc_state @@ -178,9 +173,9 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, /* Get Rp or Rd active */ anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; + STM32_UCPD_SR_VSTATE_CC1_SHIFT; vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; + STM32_UCPD_SR_VSTATE_CC2_SHIFT; /* Do circular shift if port == source */ if (anamode) { @@ -325,10 +320,8 @@ int c1_ps8805_is_sourcing_vbus(int port) return level; } - int c1_ps8805_vbus_source_enable(int port, int enable) { - return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable); } @@ -358,12 +351,13 @@ static void baseboard_usb3_manage_vbus(void) ppc_ocp_count = 0; #ifdef GPIO_USB_HUB_OCP_NOTIFY - /* - * In the case of an OCP event on this port, the usb hub should be - * notified via a GPIO signal. Following, an OCP, the attached.src state - * for the usb3 only port is checked again. If it's attached, then make - * sure the OCP notify signal is reset. - */ + /* + * In the case of an OCP event on this port, the usb hub should + * be notified via a GPIO signal. Following, an OCP, the + * attached.src state for the usb3 only port is checked again. + * If it's attached, then make sure the OCP notify signal is + * reset. + */ gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1); #endif } @@ -436,8 +430,9 @@ static void baseboard_usbc_usb3_handle_interrupt(void) CPRINTS("usb3_ppc: VBUS OC!"); gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0); if (++ppc_ocp_count < 5) - hook_call_deferred(&baseboard_usb3_manage_vbus_data, - USB_HUB_OCP_RESET_MSEC); + hook_call_deferred( + &baseboard_usb3_manage_vbus_data, + USB_HUB_OCP_RESET_MSEC); else CPRINTS("usb3_ppc: VBUS OC limit reached!"); } @@ -466,7 +461,6 @@ static void baseboard_usbc_usb3_handle_interrupt(void) /* Clear the interrupt sources. */ write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise); write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall); - } } DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt); diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c index 4d97418d23..6f301be986 100644 --- a/baseboard/intelrvp/adlrvp.c +++ b/baseboard/intelrvp/adlrvp.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -26,8 +26,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -93,94 +93,123 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* USB-C retimer Configuration */ -struct usb_mux usbc0_tcss_usb_mux = { +struct usb_mux bb_retimer0_usb_mux = { .usb_port = TYPE_C_PORT_0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc0_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #if defined(HAS_TASK_PD_C1) -struct usb_mux usbc1_tcss_usb_mux = { +struct usb_mux bb_retimer1_usb_mux = { .usb_port = TYPE_C_PORT_1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc1_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_1, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif #if defined(HAS_TASK_PD_C2) -struct usb_mux usbc2_tcss_usb_mux = { +struct usb_mux bb_retimer2_usb_mux = { .usb_port = TYPE_C_PORT_2, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_2, + .i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR, +}; +struct usb_mux_chain usbc2_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_2, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif #if defined(HAS_TASK_PD_C3) -struct usb_mux usbc3_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_3, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, +struct usb_mux_chain usbc3_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_3, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, }; #endif /* USB muxes Configuration */ -struct usb_mux usb_muxes[] = { +struct usb_mux_chain usb_muxes[] = { [TYPE_C_PORT_0] = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, + .mux = &bb_retimer0_usb_mux, + .next = &usbc0_tcss_usb_mux, }, #if defined(HAS_TASK_PD_C1) [TYPE_C_PORT_1] = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, + .mux = &bb_retimer1_usb_mux, + .next = &usbc1_tcss_usb_mux, }, #endif #if defined(HAS_TASK_PD_C2) [TYPE_C_PORT_2] = { - .usb_port = TYPE_C_PORT_2, - .next_mux = &usbc2_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_2, - .i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR, + .mux = &bb_retimer2_usb_mux, + .next = &usbc2_tcss_usb_mux, }, #endif #if defined(HAS_TASK_PD_C3) [TYPE_C_PORT_3] = { - .usb_port = TYPE_C_PORT_3, - .next_mux = &usbc3_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_3, - .i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR, + .mux = &(const struct usb_mux) { + .usb_port = TYPE_C_PORT_3, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_3, + .i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR, + }, + .next = &usbc3_tcss_usb_mux, }, #endif }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); /* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ -struct usb_mux soc_side_bb_retimer0_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, +struct usb_mux_chain soc_side_bb_retimer0_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_0, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, + }, + .next = &usbc0_tcss_usb_mux, }; #if defined(HAS_TASK_PD_C1) -struct usb_mux soc_side_bb_retimer1_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, +struct usb_mux_chain soc_side_bb_retimer1_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = TYPE_C_PORT_1, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, + }, + .next = &usbc1_tcss_usb_mux, }; #endif @@ -253,8 +282,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -340,11 +369,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -353,8 +382,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -379,22 +407,20 @@ static void configure_retimer_usbmux(void) case ADLN_LP5_ERB_SKU_BOARD_ID: case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ - usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; - usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; + bb_retimer0_usb_mux.i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS; + bb_retimer0_usb_mux.driver = &tusb1064_usb_mux_driver; + bb_retimer0_usb_mux.hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].driver = NULL; - usb_muxes[TYPE_C_PORT_1].hpd_update = NULL; + bb_retimer1_usb_mux.driver = NULL; + bb_retimer1_usb_mux.hpd_update = NULL; #endif break; case ADLP_LP5_T4_RVP_SKU_BOARD_ID: /* No retimer on Port-2 */ #if defined(HAS_TASK_PD_C2) - usb_muxes[TYPE_C_PORT_2].driver = NULL; + bb_retimer2_usb_mux.driver = NULL; #endif break; @@ -404,15 +430,13 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + usb_muxes[TYPE_C_PORT_0].next = &soc_side_bb_retimer0_usb_mux; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + usb_muxes[TYPE_C_PORT_1].next = &soc_side_bb_retimer1_usb_mux; #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index 9e7db0081c..3e062db223 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,14 +15,14 @@ /* RVP Board ids */ #define CONFIG_BOARD_VERSION_GPIO -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) /* MECC config */ #define CONFIG_INTEL_RVP_MECC_VERSION_1_0 @@ -35,8 +35,8 @@ /* ADL has new low-power features that require extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ -#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US +#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100 /* USB PD config */ #if defined(HAS_TASK_PD_C3) @@ -50,7 +50,7 @@ #endif #define CONFIG_USB_MUX_VIRTUAL #define CONFIG_USB_MUX_TUSB1044 -#define PD_MAX_POWER_MW 100000 +#define PD_MAX_POWER_MW 100000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY @@ -58,10 +58,10 @@ /* Support NXP PCA9675 I/O expander. */ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_PCA9675 -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* DC Jack charge ports */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT @@ -69,38 +69,38 @@ #define CONFIG_USBC_PPC_SN5S330 #define CONFIG_USB_PD_VBUS_DETECT_PPC #define CONFIG_USB_PD_DISCHARGE_PPC -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 /* TCPC */ #define CONFIG_USB_PD_DISCHARGE #define CONFIG_USB_PD_TCPM_FUSB302 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 /* Config BB retimer */ #define CONFIG_USBC_RETIMER_INTEL_BB #define CONFIG_USBC_RETIMER_FW_UPDATE /* Connector side BB retimers */ -#define I2C_PORT0_BB_RETIMER_ADDR 0x56 +#define I2C_PORT0_BB_RETIMER_ADDR 0x56 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_ADDR 0x57 +#define I2C_PORT1_BB_RETIMER_ADDR 0x57 #endif #if defined(HAS_TASK_PD_C2) -#define I2C_PORT2_BB_RETIMER_ADDR 0x58 +#define I2C_PORT2_BB_RETIMER_ADDR 0x58 #endif #if defined(HAS_TASK_PD_C3) -#define I2C_PORT3_BB_RETIMER_ADDR 0x59 +#define I2C_PORT3_BB_RETIMER_ADDR 0x59 #endif /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif /* I2C EEPROM */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO /* Enable CBI */ #define CONFIG_CBI_EEPROM @@ -122,9 +122,9 @@ #define CONFIG_USB_PD_TCPC_LOW_POWER /* Config Fan */ -#define CONFIG_FANS 1 -#define BOARD_FAN_MIN_RPM 3000 -#define BOARD_FAN_MAX_RPM 10000 +#define CONFIG_FANS 1 +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 /* Charger Configs */ #define CONFIG_CHARGER_RUNTIME_CONFIG @@ -133,15 +133,15 @@ /* Charger chip on ADL-N */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* Port 80 */ -#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS /* Board Id */ -#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 /* * Frequent watchdog timer resets are seen, with the @@ -160,7 +160,7 @@ * Support for EC_CMD_BATTERY_GET_STATIC version 1. */ #define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 +#define CONFIG_BATTERY_COUNT 1 #define CONFIG_HOSTCMD_BATTERY_V2 /* Config to indicate battery type doesn't auto detect */ @@ -210,7 +210,7 @@ enum adlrvp_bitbang_i2c_channel { I2C_BITBANG_CHAN_IOEX_0, I2C_BITBANG_CHAN_COUNT }; -#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT +#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); void extpower_interrupt(enum gpio_signal signal); diff --git a/baseboard/intelrvp/adlrvp_battery.c b/baseboard/intelrvp/adlrvp_battery.c index e5bf95827e..f7107cb1a4 100644 --- a/baseboard/intelrvp/adlrvp_battery.c +++ b/baseboard/intelrvp/adlrvp_battery.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc index 4519d3d853..b62dcf53a3 100644 --- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc +++ b/baseboard/intelrvp/adlrvp_ioex_gpio.inc @@ -1,6 +1,6 @@ /* -*- mode:c -*- * - * Copyright 2021 The Chromium OS Authors. All rights reserved. + * Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c index 87b43f2297..e1e0a06943 100644 --- a/baseboard/intelrvp/baseboard.c +++ b/baseboard/intelrvp/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -86,14 +86,12 @@ const static struct ec_thermal_config thermal_a = { }; struct ec_thermal_config thermal_params[] = { - [TEMP_SNS_AMBIENT] = thermal_a, - [TEMP_SNS_BATTERY] = thermal_a, + [TEMP_SNS_AMBIENT] = thermal_a, [TEMP_SNS_BATTERY] = thermal_a, [TEMP_SNS_DDR] = thermal_a, #ifdef CONFIG_PECI [TEMP_SNS_PECI] = thermal_a, #endif - [TEMP_SNS_SKIN] = thermal_a, - [TEMP_SNS_VR] = thermal_a, + [TEMP_SNS_SKIN] = thermal_a, [TEMP_SNS_VR] = thermal_a, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); #endif /* CONFIG_TEMP_SENSOR */ @@ -144,12 +142,12 @@ int ioexpander_read_intelrvp_version(int *port0, int *port1) for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { rv = pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_0, port0); + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_0, port0); if (!rv && !pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_1, port1)) + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_1, port1)) return 0; msleep(1); diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 9b497568e7..b927632fc5 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,22 +12,27 @@ #include "stdbool.h" #ifdef VARIANT_INTELRVP_EC_IT8320 - #include "ite_ec.h" +#include "ite_ec.h" #elif defined(VARIANT_INTELRVP_EC_MCHP) - #include "mchp_ec.h" +#include "mchp_ec.h" #elif defined(VARIANT_INTELRVP_EC_NPCX) - #include "npcx_ec.h" +#include "npcx_ec.h" #else - #error "Define EC chip variant" +#error "Define EC chip variant" #endif /* + * TODO: b/241322365 - Watchdog error are observed if LTO is enabled + * hence disabled it. Enable LTO once the fix is found. + */ + +/* * Allow dangerous commands. * TODO: Remove this config before production. */ #define CONFIG_SYSTEM_UNLOCKED -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE /* @@ -51,7 +56,7 @@ #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 /* Battery */ #define CONFIG_BATTERY_CUT_OFF @@ -66,7 +71,7 @@ #define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CHARGER_SENSE_RESISTOR 5 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_TRICKLE_CHARGING @@ -75,8 +80,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Keyboard */ @@ -109,16 +114,16 @@ /* USB MUX */ #ifdef CONFIG_USB_MUX_VIRTUAL - #define CONFIG_HOSTCMD_LOCATE_CHIP +#define CONFIG_HOSTCMD_LOCATE_CHIP #endif #define CONFIG_USBC_SS_MUX /* SoC / PCH */ #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_POWER_BUTTON @@ -152,13 +157,13 @@ /* Temperature sensor */ #ifdef CONFIG_TEMP_SENSOR - #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B - #define CONFIG_TEMP_SENSOR_POWER - #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A - #define CONFIG_THERMISTOR - #define CONFIG_THROTTLE_AP +#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B +#define CONFIG_TEMP_SENSOR_POWER +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define CONFIG_THERMISTOR +#define CONFIG_THROTTLE_AP #ifdef CONFIG_PECI - #define CONFIG_PECI_COMMON +#define CONFIG_PECI_COMMON #endif /* CONFIG_PECI */ #endif /* CONFIG_TEMP_SENSOR */ @@ -177,10 +182,7 @@ FORWARD_DECLARE_ENUM(tcpc_rp_value); /* PWM channels */ -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT }; /* FAN channels */ enum fan_channel { @@ -211,13 +213,13 @@ enum temp_sensor_id { }; /* TODO(b:132652892): Verify the below numbers. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* Define typical operating power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000) #define DC_JACK_MAX_VOLTAGE_MV 19000 /* TCPC gpios */ diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk index 21b4a7b0ec..b4cacf4cc2 100644 --- a/baseboard/intelrvp/build.mk +++ b/baseboard/intelrvp/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Copyright 2018 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c index 1eb82b6688..95aeea0441 100644 --- a/baseboard/intelrvp/chg_usb_pd.c +++ b/baseboard/intelrvp/chg_usb_pd.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) bool is_typec_port(int port) { @@ -43,8 +43,8 @@ static void board_dc_jack_handle(void) /* System is booted from DC Jack */ if (board_dc_jack_present()) { - charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) / - DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; } else { charge_dc_jack.current = 0; @@ -52,7 +52,7 @@ static void board_dc_jack_handle(void) } charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, &charge_dc_jack); + DEDICATED_CHARGE_PORT, &charge_dc_jack); } #endif @@ -75,7 +75,7 @@ static void board_charge_init(void) for (port = 0; port < CHARGE_PORT_COUNT; port++) { for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++) charge_manager_update_charge(supplier, port, - &charge_init); + &charge_init); } #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 @@ -88,8 +88,7 @@ int board_set_active_charge_port(int port) { int i; /* charge port is a realy physical port */ - int is_real_port = (port >= 0 && - port < CHARGE_PORT_COUNT); + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); /* check if we are source vbus on that port */ int source = board_vbus_source_enabled(port); @@ -127,9 +126,9 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c index 38bd3cef9e..cbc61e8402 100644 --- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c +++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,8 +19,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Reset PD MCU */ void board_reset_pd_mcu(void) @@ -97,7 +97,7 @@ void ppc_interrupt(enum gpio_signal signal) for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { if (tcpc_aic_gpios[i].ppc_intr_handler && - signal == tcpc_aic_gpios[i].ppc_alert) { + signal == tcpc_aic_gpios[i].ppc_alert) { tcpc_aic_gpios[i].ppc_intr_handler(i); break; } @@ -107,6 +107,6 @@ void ppc_interrupt(enum gpio_signal signal) void board_charging_enable(int port, int enable) { if (ppc_vbus_sink_enable(port, enable)) - CPRINTS("C%d: sink path %s failed", - port, enable ? "en" : "dis"); + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); } diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c index bafddc5f9e..76703d4f82 100644 --- a/baseboard/intelrvp/ite_ec.c +++ b/baseboard/intelrvp/ite_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -139,15 +139,15 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) * enabling the VCONN on respective CC line */ gpio_set_level(tcpc_gpios[port].vconn.cc1_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); gpio_set_level(tcpc_gpios[port].vconn.cc2_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); if (enabled) gpio_set_level((cc_pin != USBPD_CC_PIN_1) ? - tcpc_gpios[port].vconn.cc2_pin : - tcpc_gpios[port].vconn.cc1_pin, - tcpc_gpios[port].vconn.pin_pol); + tcpc_gpios[port].vconn.cc2_pin : + tcpc_gpios[port].vconn.cc1_pin, + tcpc_gpios[port].vconn.pin_pol); #endif } #endif diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h index c773a48b21..7ad147a5f9 100644 --- a/baseboard/intelrvp/ite_ec.h +++ b/baseboard/intelrvp/ite_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,13 +13,13 @@ #define CONFIG_IT83XX_VCC_1P8V /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 #ifdef CONFIG_USBC_VCONN - #define CONFIG_USBC_VCONN_SWAP - /* delay to turn on/off vconn */ +#define CONFIG_USBC_VCONN_SWAP +/* delay to turn on/off vconn */ #endif #endif /* __CROS_EC_ITE_EC_H */ diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c index add2ebbe43..10e4e08e63 100644 --- a/baseboard/intelrvp/led.c +++ b/baseboard/intelrvp/led.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,30 +19,30 @@ const int led_charge_lvl_1 = 5; const int led_charge_lvl_2 = 97; struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC } }, }; const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -51,15 +51,15 @@ void led_set_color_power(enum ec_led_colors color) if (color == EC_LED_COLOR_WHITE) #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_ON_LVL); + LED_ON_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ else - /* LED_OFF and unsupported colors */ + /* LED_OFF and unsupported colors */ #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_OFF_LVL); + LED_OFF_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ @@ -70,32 +70,28 @@ void led_set_color_battery(enum ec_led_colors color) switch (color) { case EC_LED_COLOR_RED: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_AMBER: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_GREEN: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ break; default: /* LED_OFF and other unsupported colors */ #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c index 5f8768bdd9..8629085c4f 100644 --- a/baseboard/intelrvp/led_states.c +++ b/baseboard/intelrvp/led_states.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,11 +15,11 @@ #include "led_common.h" #include "led_states.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) static enum led_states led_get_state(void) { - int charge_lvl; + int charge_lvl; enum led_states new_state = LED_NUM_STATES; switch (charge_get_state()) { @@ -55,10 +55,10 @@ static enum led_states led_get_state(void) new_state = STATE_CHARGING_FULL_CHARGE; break; case PWR_STATE_IDLE: /* External power connected in IDLE */ - if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) - new_state = STATE_FACTORY_TEST; - else - new_state = STATE_DISCHARGE_S0; + new_state = STATE_DISCHARGE_S0; + break; + case PWR_STATE_FORCED_IDLE: + new_state = STATE_FACTORY_TEST; break; default: /* Other states don't alter LED behavior */ @@ -88,14 +88,14 @@ static void led_update_battery(void) ticks = 0; period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - + led_bat_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for battery state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_battery(LED_OFF); return; } @@ -104,8 +104,8 @@ static void led_update_battery(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ @@ -141,14 +141,14 @@ static void led_update_power(void) ticks = 0; period = led_pwr_state_table[led_state][LED_PHASE_0].time + - led_pwr_state_table[led_state][LED_PHASE_1].time; - + led_pwr_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for power state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_power(LED_OFF); return; } @@ -157,8 +157,8 @@ static void led_update_power(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h index 907ff5c8b8..3b584c6efc 100644 --- a/baseboard/intelrvp/led_states.h +++ b/baseboard/intelrvp/led_states.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -10,19 +10,15 @@ #include "ec_commands.h" -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT /* * All LED states should have one phase defined, * and an additional phase can be defined for blinking */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; /* * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 @@ -51,10 +47,8 @@ struct led_descriptor { uint8_t time; }; - /* Charging LED state table - defined in board's led.c */ -extern struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; +extern struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; /* Charging LED state level 1 - defined in board's led.c */ extern const int led_charge_lvl_1; @@ -71,8 +65,8 @@ enum pwr_led_states { }; /* Power LED state table - defined in board's led.c */ -extern const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; +extern const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES] + [LED_NUM_PHASES]; /** * Set battery LED color - defined in board's led.c diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c index f1eb4678c1..7ede17569b 100644 --- a/baseboard/intelrvp/mchp_ec.c +++ b/baseboard/intelrvp/mchp_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h index 227ccaef6d..ec1e47c030 100644 --- a/baseboard/intelrvp/mchp_ec.h +++ b/baseboard/intelrvp/mchp_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,10 @@ #define __CROS_EC_MCHP_EC_H /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 /* * ADC maximum voltage is a board level configuration. diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c index d6eca2e55b..a90442e8b1 100644 --- a/baseboard/intelrvp/npcx_ec.c +++ b/baseboard/intelrvp/npcx_ec.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h index 52bcb2dae6..5fe6aa9786 100644 --- a/baseboard/intelrvp/npcx_ec.h +++ b/baseboard/intelrvp/npcx_ec.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,20 +19,20 @@ enum mft_channel { #endif /* __ASSEMBLER__ */ /* ADC channels */ -#define ADC_MAX_MVOLT ADC_MAX_VOLT -#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 -#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 -#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 +#define ADC_MAX_MVOLT ADC_MAX_VOLT +#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 +#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 +#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 /* KSO2 is inverted */ -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* Fan */ #define CONFIG_PWM -#define PWN_FAN_CHANNEL 3 +#define PWN_FAN_CHANNEL 3 /* GPIO64/65 are used as UART pins. */ -#define NPCX_UART_MODULE2 1 +#define NPCX_UART_MODULE2 1 #endif /* __CROS_EC_NPCX_EC_H */ diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c index 8e06c9f0b3..303d176405 100644 --- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c +++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c index 00459b12bc..70f50f054b 100644 --- a/baseboard/ite_evb/baseboard.c +++ b/baseboard/ite_evb/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -42,8 +42,10 @@ const struct fan_rpm fan_rpm_0 = { }; const struct fan_t fans[] = { - { .conf = &fan_conf_0, - .rpm = &fan_rpm_0, }, + { + .conf = &fan_conf_0, + .rpm = &fan_rpm_0, + }, }; BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS); @@ -123,11 +125,9 @@ __override struct keyboard_scan_config keyscan_config = { #if defined(CONFIG_SPI_FLASH_PORT) /* SPI devices */ const struct spi_device_t spi_devices[] = { - [CONFIG_SPI_FLASH_PORT] = { - .port = CONFIG_SPI_FLASH_PORT, - .div = 0, - .gpio_cs = -1 - }, + [CONFIG_SPI_FLASH_PORT] = { .port = CONFIG_SPI_FLASH_PORT, + .div = 0, + .gpio_cs = -1 }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); #endif @@ -139,9 +139,8 @@ static void board_init(void) DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_POWER_BUTTON_L, GPIO_LID_OPEN -}; +const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, + GPIO_LID_OPEN }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* diff --git a/baseboard/ite_evb/baseboard.h b/baseboard/ite_evb/baseboard.h index 23b3f80fba..e16e708078 100644 --- a/baseboard/ite_evb/baseboard.h +++ b/baseboard/ite_evb/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/ite_evb/build.mk b/baseboard/ite_evb/build.mk index 507222e6b3..38a49ff8b6 100644 --- a/baseboard/ite_evb/build.mk +++ b/baseboard/ite_evb/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/ite_evb/usb_pd_pdo.c b/baseboard/ite_evb/usb_pd_pdo.c index 24cbc8b996..0da735e458 100644 --- a/baseboard/ite_evb/usb_pd_pdo.c +++ b/baseboard/ite_evb/usb_pd_pdo.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,8 +7,9 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | \ + PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), diff --git a/baseboard/ite_evb/usb_pd_pdo.h b/baseboard/ite_evb/usb_pd_pdo.h index ce3300cc7d..4b19ca32d3 100644 --- a/baseboard/ite_evb/usb_pd_pdo.h +++ b/baseboard/ite_evb/usb_pd_pdo.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c index b5462bd1e2..71af9d2b1c 100644 --- a/baseboard/ite_evb/usb_pd_policy.c +++ b/baseboard/ite_evb/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -20,8 +20,8 @@ #include "usb_mux.h" #include "usb_pd_pdo.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_is_max_request_allowed(void) { @@ -62,7 +62,6 @@ void pd_power_supply_reset(int port) board_pd_vbus_ctrl(port, 0); } - __override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap: we can be DFP or UFP for USB */ @@ -107,7 +106,7 @@ __override void svdm_exit_dp_mode(int port) } __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { /* Return length 0, means nothing needn't tx */ return 0; diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c index b06547106a..e929e5449c 100644 --- a/baseboard/kalista/baseboard.c +++ b/baseboard/kalista/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -48,8 +48,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint8_t board_version; static uint32_t oem; @@ -99,14 +99,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* TODO: Verify fan control and mft */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_FAN_PWR_EN, }; @@ -123,46 +124,36 @@ const struct fan_t fans[] = { BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "backlight", - .port = I2C_PORT_BACKLIGHT, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "pmic", - .port = I2C_PORT_PMIC, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "backlight", + .port = I2C_PORT_BACKLIGHT, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "pmic", + .port = I2C_PORT_PMIC, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -186,12 +177,15 @@ static int ps8751_tune_mux(const struct usb_mux *me) return EC_SUCCESS; } -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { - .usb_port = 0, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, + .mux = + &(const struct usb_mux){ + .usb_port = 0, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .board_init = &ps8751_tune_mux, + }, }, }; @@ -234,14 +228,14 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) && - gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) + gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) return PD_STATUS_TCPC_ALERT_0; return 0; } @@ -254,10 +248,10 @@ uint16_t tcpc_get_alert_status(void) * src/mainboard/google/${board}/acpi/dptf.asl */ const struct temp_sensor_t temp_sensors[] = { - {"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, + { "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -270,9 +264,11 @@ struct ec_thermal_config thermal_params[] = { * {Twarn, Thigh, X }, <off> * fan_off, fan_max */ - {{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0}, - C_TO_K(4), C_TO_K(76)}, /* TMP431_Internal */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* TMP431_Sensor_1 */ + { { 0, C_TO_K(80), C_TO_K(81) }, + { 0, C_TO_K(78), 0 }, + C_TO_K(4), + C_TO_K(76) }, /* TMP431_Internal */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); @@ -441,9 +437,9 @@ int64_t get_time_dsw_pwrok(void) } const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -455,21 +451,20 @@ struct fan_step { /* Note: Do not make the fan on/off point equal to 0 or 100 */ static const struct fan_step fan_table0[] = { - {.on = 0, .off = 5, .rpm = 0}, - {.on = 30, .off = 5, .rpm = 2180}, - {.on = 49, .off = 46, .rpm = 2680}, - {.on = 53, .off = 50, .rpm = 3300}, - {.on = 58, .off = 54, .rpm = 3760}, - {.on = 63, .off = 59, .rpm = 4220}, - {.on = 68, .off = 64, .rpm = 4660}, - {.on = 75, .off = 70, .rpm = 4900}, + { .on = 0, .off = 5, .rpm = 0 }, + { .on = 30, .off = 5, .rpm = 2180 }, + { .on = 49, .off = 46, .rpm = 2680 }, + { .on = 53, .off = 50, .rpm = 3300 }, + { .on = 58, .off = 54, .rpm = 3760 }, + { .on = 63, .off = 59, .rpm = 4220 }, + { .on = 68, .off = 64, .rpm = 4660 }, + { .on = 75, .off = 70, .rpm = 4900 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) static const struct fan_step *fan_table = fan_table0; - static void cbi_init(void) { uint32_t val; @@ -489,8 +484,8 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); static void setup_bj(void) { - enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? - BJ_135W_19V : BJ_90W_19V; + enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? BJ_135W_19V : + BJ_90W_19V; gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V); } @@ -537,8 +532,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h index 717d26b313..e3696ae48d 100644 --- a/baseboard/kalista/baseboard.h +++ b/baseboard/kalista/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,7 +12,7 @@ * Allow dangerous commands. * TODO: Remove this config before production. */ -#undef CONFIG_SYSTEM_UNLOCKED +#undef CONFIG_SYSTEM_UNLOCKED #define CONFIG_USB_PD_COMM_LOCKED /* EC */ @@ -32,7 +32,7 @@ #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_POWER_BUTTON_IGNORE_LID #define CONFIG_PWM #define CONFIG_LTO @@ -47,7 +47,7 @@ #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE #define CEC_GPIO_OUT GPIO_CEC_OUT -#define CEC_GPIO_IN GPIO_CEC_IN +#define CEC_GPIO_IN GPIO_CEC_IN #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP #define CONFIG_FANS 1 #define CONFIG_FAN_RPM_CUSTOM @@ -64,13 +64,13 @@ #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 @@ -105,20 +105,20 @@ #define USB_PORT_COUNT 4 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 -#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 +#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_TCPC0_FLAGS 0x0b -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_TCPC0_FLAGS 0x0b +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Verify and jump to RW image on boot */ #define CONFIG_VBOOT_EFS @@ -140,23 +140,22 @@ * end of RW_A and RW_B, respectively. */ #define CONFIG_RW_B -#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF -#undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) -#undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE) -#define CONFIG_RW_A_SIGN_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define CONFIG_RW_B_SIGN_STORAGE_OFF (CONFIG_RW_B_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#undef CONFIG_RW_SIZE +#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF +#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE) +#define CONFIG_RW_A_SIGN_STORAGE_OFF \ + (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_SIGN_STORAGE_OFF \ + (CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) #undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE #undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE #define CONFIG_RWSIG #define CONFIG_RWSIG_TYPE_RWSIG @@ -182,15 +181,12 @@ enum charge_port { }; enum temp_sensor_id { - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ TEMP_SENSOR_COUNT }; -enum adc_channel { - ADC_VBUS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_LED_RED, @@ -223,8 +219,8 @@ enum OEM_ID { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk index fb844b19f1..6bb55b2023 100644 --- a/baseboard/kalista/build.mk +++ b/baseboard/kalista/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Copyright 2018 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c index e04eecf5e3..c72ce84bb0 100644 --- a/baseboard/kalista/led.c +++ b/baseboard/kalista/led.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -15,7 +15,7 @@ #include "timer.h" #include "util.h" -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by <duty_inc> every * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented @@ -181,7 +181,7 @@ void led_critical(void) set_color(EC_LED_ID_POWER_LED, LED_RED, 100); } -static int command_led(int argc, char **argv) +static int command_led(int argc, const char **argv) { enum ec_led_id id = EC_LED_ID_POWER_LED; diff --git a/baseboard/kalista/usb_pd_pdo.c b/baseboard/kalista/usb_pd_pdo.c index 0addbcc51c..067b8eb9e7 100644 --- a/baseboard/kalista/usb_pd_pdo.c +++ b/baseboard/kalista/usb_pd_pdo.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,9 +7,8 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \ - PDO_FIXED_DATA_SWAP | \ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), diff --git a/baseboard/kalista/usb_pd_pdo.h b/baseboard/kalista/usb_pd_pdo.h index 1dad035d3d..119658b8a5 100644 --- a/baseboard/kalista/usb_pd_pdo.h +++ b/baseboard/kalista/usb_pd_pdo.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c index 85b26aac76..017c340a1b 100644 --- a/baseboard/kalista/usb_pd_policy.c +++ b/baseboard/kalista/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. +/* Copyright 2017 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ #include "usb_pd_pdo.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int board_vbus_source_enabled(int port) { @@ -58,8 +58,7 @@ int pd_snk_is_vbus_provided(int port) return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L); } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c index 55da56f687..a3ccf4d507 100644 --- a/baseboard/kukui/base_detect_kukui.c +++ b/baseboard/kukui/base_detect_kukui.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,7 +14,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) /* Krane base detection code */ @@ -41,11 +41,11 @@ enum kukui_pogo_device_type { struct { int mv_low, mv_high; } static const pogo_detect_table[] = { - [DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */ + [DEVICE_TYPE_DETACHED] = { 2700, 3500 }, /* 10K, NC, around 3.3V */ #ifdef VARIANT_KUKUI_POGO_DOCK - [DEVICE_TYPE_DOCK] = {141, 173}, /* 10K, 0.5K ohm */ + [DEVICE_TYPE_DOCK] = { 141, 173 }, /* 10K, 0.5K ohm */ #endif - [DEVICE_TYPE_KEYBOARD] = {270, 400}, /* 10K, 1K ohm */ + [DEVICE_TYPE_KEYBOARD] = { 270, 400 }, /* 10K, 1K ohm */ }; BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT); @@ -71,7 +71,7 @@ static enum kukui_pogo_device_type get_device_type(int mv) for (i = 0; i < DEVICE_TYPE_COUNT; i++) { if (pogo_detect_table[i].mv_low <= mv && - mv <= pogo_detect_table[i].mv_high) + mv <= pogo_detect_table[i].mv_high) return i; } @@ -82,17 +82,17 @@ static void enable_charge(int enable) { #ifdef VARIANT_KUKUI_POGO_DOCK if (enable) { - struct charge_port_info info = { - .voltage = 5000, .current = 1500}; + struct charge_port_info info = { .voltage = 5000, + .current = 1500 }; /* * Set supplier type to PD to have same priority as type c * port. */ - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + CHARGE_PORT_POGO, &info); } else { - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + CHARGE_PORT_POGO, NULL); } pd_send_host_event(PD_EVENT_POWER_CHANGE); #endif @@ -112,7 +112,7 @@ static void base_set_device_type(enum kukui_pogo_device_type device_type) case DEVICE_TYPE_ERROR: case DEVICE_TYPE_UNKNOWN: hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_RETRY_US); + BASE_DETECT_RETRY_US); break; case DEVICE_TYPE_DETACHED: @@ -210,11 +210,11 @@ void base_force_state(enum ec_set_base_state_cmd state) gpio_disable_interrupt(GPIO_POGO_ADC_INT_L); pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED); - base_set_device_type(state == EC_SET_BASE_STATE_ATTACH - ? DEVICE_TYPE_KEYBOARD - : DEVICE_TYPE_DETACHED); - CPRINTS("BD forced %sconnected", state == EC_SET_BASE_STATE_ATTACH ? - "" : "dis"); + base_set_device_type(state == EC_SET_BASE_STATE_ATTACH ? + DEVICE_TYPE_KEYBOARD : + DEVICE_TYPE_DETACHED); + CPRINTS("BD forced %sconnected", + state == EC_SET_BASE_STATE_ATTACH ? "" : "dis"); } #ifdef VARIANT_KUKUI_POGO_DOCK diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c index c9831ed300..04e444aad0 100644 --- a/baseboard/kukui/baseboard.c +++ b/baseboard/kukui/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ #include "registers.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #ifndef CONFIG_CHARGER_RUNTIME_CONFIG #if defined(VARIANT_KUKUI_CHARGER_MT6370) @@ -54,11 +54,11 @@ void board_config_pre_init(void) * Ch4: USART1_TX / Ch5: USART1_RX (1000) * Ch6: SPI2_RX / Ch7: SPI2_TX (0011) */ - STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | - (3 << 20) | (3 << 24); + STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) | + (3 << 24); #elif defined(VARIANT_KUKUI_EC_STM32L431) -#ifdef CONFIG_DMA +#ifdef CONFIG_DMA dma_init(); #endif /* @@ -102,43 +102,43 @@ enum kukui_board_version { /* map from kukui_board_version to board id voltage in mv */ #ifdef VARIANT_KUKUI_EC_IT81202 const int16_t kukui_board_id_map[] = { - 136, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 388, /* 51.1k , 6.8K ohm */ - 584, /* 51.1K , 11K ohm */ - 785, /* 56K , 17.4K ohm */ - 993, /* 51.1K , 22K ohm */ - 1221, /* 51.1K , 30K ohm */ - 1433, /* 51.1K , 39.2K ohm */ - 1650, /* 56K , 56K ohm */ - 1876, /* 47K , 61.9K ohm */ - 2084, /* 47K , 80.6K ohm */ - 2273, /* 56K , 124K ohm */ - 2461, /* 51.1K , 150K ohm */ - 2672, /* 47K , 200K ohm */ - 2889, /* 47K , 330K ohm */ - 3086, /* 47K , 680K ohm */ - 3300, /* 56K , NC */ + 136, /* 51.1K , 2.2K(gru 3.3K) ohm */ + 388, /* 51.1k , 6.8K ohm */ + 584, /* 51.1K , 11K ohm */ + 785, /* 56K , 17.4K ohm */ + 993, /* 51.1K , 22K ohm */ + 1221, /* 51.1K , 30K ohm */ + 1433, /* 51.1K , 39.2K ohm */ + 1650, /* 56K , 56K ohm */ + 1876, /* 47K , 61.9K ohm */ + 2084, /* 47K , 80.6K ohm */ + 2273, /* 56K , 124K ohm */ + 2461, /* 51.1K , 150K ohm */ + 2672, /* 47K , 200K ohm */ + 2889, /* 47K , 330K ohm */ + 3086, /* 47K , 680K ohm */ + 3300, /* 56K , NC */ }; #define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */ #else const int16_t kukui_board_id_map[] = { - 109, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 211, /* 51.1k , 6.8K ohm */ - 319, /* 51.1K , 11K ohm */ - 427, /* 56K , 17.4K ohm */ - 542, /* 51.1K , 22K ohm */ - 666, /* 51.1K , 30K ohm */ - 781, /* 51.1K , 39.2K ohm */ - 900, /* 56K , 56K ohm */ - 1023, /* 47K , 61.9K ohm */ - 1137, /* 47K , 80.6K ohm */ - 1240, /* 56K , 124K ohm */ - 1343, /* 51.1K , 150K ohm */ - 1457, /* 47K , 200K ohm */ - 1576, /* 47K , 330K ohm */ - 1684, /* 47K , 680K ohm */ - 1800, /* 56K , NC */ + 109, /* 51.1K , 2.2K(gru 3.3K) ohm */ + 211, /* 51.1k , 6.8K ohm */ + 319, /* 51.1K , 11K ohm */ + 427, /* 56K , 17.4K ohm */ + 542, /* 51.1K , 22K ohm */ + 666, /* 51.1K , 30K ohm */ + 781, /* 51.1K , 39.2K ohm */ + 900, /* 56K , 56K ohm */ + 1023, /* 47K , 61.9K ohm */ + 1137, /* 47K , 80.6K ohm */ + 1240, /* 56K , 124K ohm */ + 1343, /* 51.1K , 150K ohm */ + 1457, /* 47K , 200K ohm */ + 1576, /* 47K , 330K ohm */ + 1684, /* 47K , 680K ohm */ + 1800, /* 56K , NC */ }; #define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */ @@ -178,7 +178,7 @@ int board_get_version(void) * for this board. */ if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 && - version != BOARD_VERSION_UNKNOWN) + version != BOARD_VERSION_UNKNOWN) adc_disable(); #endif @@ -216,8 +216,7 @@ __override void lid_angle_peripheral_enable(int enable) * ignore input devices or not. */ if (!chipset_in_s0) - keyboard_scan_enable(0, - KB_SCAN_DISABLE_LID_ANGLE); + keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE); } } #endif diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h index 59e161571f..fc87b3441b 100644 --- a/baseboard/kukui/baseboard.h +++ b/baseboard/kukui/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ #if defined(VARIANT_KUKUI_BATTERY_MAX17055) #define CONFIG_BATTERY_MAX17055 #define CONFIG_BATTERY_MAX17055_ALERT -#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ +#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ #elif defined(VARIANT_KUKUI_BATTERY_MM8013) #define CONFIG_BATTERY_MM8013 #elif defined(VARIANT_KUKUI_BATTERY_BQ27541) @@ -47,7 +47,7 @@ #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE /* TCPC MT6370 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* @@ -64,7 +64,7 @@ #define CONFIG_CHARGE_RAMP_HW /* TCPC FUSB302 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* b/2230219: 15V has better charging performance than 20V */ @@ -115,16 +115,16 @@ #define PD_OPERATING_POWER_MW 30000 -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) #else /* !VARIANT_KUKUI_JACUZZI */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #endif /* VARIANT_KUKUI_JACUZZI */ @@ -144,9 +144,9 @@ /* Optional modules */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_CHIPSET_MT8183 -#undef CONFIG_CMD_ACCELS +#undef CONFIG_CMD_ACCELS #define CONFIG_EMULATED_SYSRQ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -207,8 +207,8 @@ #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096 -#define GPIO_LID_OPEN GPIO_HALL_INT_L -#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT +#define GPIO_LID_OPEN GPIO_HALL_INT_L +#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT #ifndef VARIANT_KUKUI_NO_SENSORS #define CONFIG_ACCEL_FIFO @@ -241,11 +241,11 @@ #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_REVIVE_DISCONNECT -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) #ifdef BOARD_KODAMA -#define PD_MAX_CURRENT_MA 2000 +#define PD_MAX_CURRENT_MA 2000 #else -#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_CURRENT_MA 3000 #endif /* Optional for testing */ @@ -263,7 +263,7 @@ */ #if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431) /* Timer selection */ -#define TIM_CLOCK32 2 +#define TIM_CLOCK32 2 #define TIM_WATCHDOG 7 /* 48 MHz SYSCLK clock frequency */ @@ -273,11 +273,11 @@ #define CPU_CLOCK 48000000 #endif -#undef CONFIG_HIBERNATE +#undef CONFIG_HIBERNATE #define CONFIG_SPI_CONTROLLER #define CONFIG_STM_HWTIMER32 #define CONFIG_WATCHDOG_HELP -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 #define CONFIG_UART_RX_DMA diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c index 94f46b3326..453d5e984f 100644 --- a/baseboard/kukui/battery_bq27541.c +++ b/baseboard/kukui/battery_bq27541.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -6,6 +6,7 @@ */ #include "battery.h" +#include "builtin/assert.h" #include "charge_state.h" #include "charger_mt6370.h" #include "console.h" @@ -25,12 +26,9 @@ #define BAT_LEVEL_PD_LIMIT 85 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_CPT = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_CPT = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_CPT] = { @@ -105,7 +103,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } @@ -143,7 +141,7 @@ int charger_profile_override(struct charge_state_data *curr) rcv_cycle = 150; /* Check SOH to decrease charging voltage. */ if (!battery_full_charge_capacity(&full_cap) && - !battery_design_capacity(&design_cap)) + !battery_design_capacity(&design_cap)) soh = ((full_cap * 100) / design_cap); if (soh > 70 && soh <= 75) rcv_soh = 50; @@ -159,15 +157,13 @@ int charger_profile_override(struct charge_state_data *curr) curr->requested_voltage -= rcv; /* Should not keep charging voltage > 4250mV for 48hrs. */ - if ((curr->state == ST_DISCHARGE) || - curr->chg.voltage < 4250) { + if ((curr->state == ST_DISCHARGE) || curr->chg.voltage < 4250) { deadline_48.val = 0; - /* Starting count 48hours */ - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { + /* Starting count 48hours */ + } else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) { if (deadline_48.val == 0) deadline_48.val = get_time().val + - CHARGER_LIMIT_TIMEOUT_HOURS * HOUR; + CHARGER_LIMIT_TIMEOUT_HOURS * HOUR; /* If charging voltage keep > 4250 for 48hrs, * set charging voltage = 4250 */ @@ -177,14 +173,13 @@ int charger_profile_override(struct charge_state_data *curr) /* Should not keeep battery voltage > 4100mV and * battery temperature > 45C for two hour */ - if (curr->state == ST_DISCHARGE || - curr->batt.voltage < 4100 || - bat_temp_c < 450) { + if (curr->state == ST_DISCHARGE || curr->batt.voltage < 4100 || + bat_temp_c < 450) { deadline_2.val = 0; - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { + } else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) { if (deadline_2.val == 0) - deadline_2.val = get_time().val + + deadline_2.val = + get_time().val + CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR; else if (timestamp_expired(deadline_2, NULL)) { /* Set discharge and charging voltage = 4100mV */ @@ -216,7 +211,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param, int get_battery_manufacturer_name(char *dest, int size) { - static const char * const name[] = { + static const char *const name[] = { [BATTERY_CPT] = "AS1XXXD3Ka", }; ASSERT(dest); diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c index 53e72766a7..5ebb220b0c 100644 --- a/baseboard/kukui/battery_max17055.c +++ b/baseboard/kukui/battery_max17055.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -6,6 +6,7 @@ */ #include "battery.h" +#include "builtin/assert.h" #include "charge_state.h" #include "charger_mt6370.h" #include "console.h" @@ -20,12 +21,9 @@ #define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0 #define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_SIMPLO = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_SIMPLO = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_SIMPLO] = { @@ -132,7 +130,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } @@ -178,7 +176,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param, int get_battery_manufacturer_name(char *dest, int size) { - static const char * const name[] = { + static const char *const name[] = { [BATTERY_SIMPLO] = "SIMPLO", }; ASSERT(dest); diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c index e7f422e561..26507d5915 100644 --- a/baseboard/kukui/battery_mm8013.c +++ b/baseboard/kukui/battery_mm8013.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -22,12 +22,9 @@ #define BAT_LEVEL_PD_LIMIT 85 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_SCUD = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_SCUD = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_SCUD] = { @@ -100,7 +97,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c index ba2af17443..b924b2e3a9 100644 --- a/baseboard/kukui/battery_smart.c +++ b/baseboard/kukui/battery_smart.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -98,39 +98,30 @@ __override void board_battery_compensate_params(struct batt_params *batt) /* return cached values for at most CACHE_INVALIDATION_TIME_US */ fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE, - &batt_cache.state_of_charge, - &batt->state_of_charge); + &batt_cache.state_of_charge, &batt->state_of_charge); fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE, - &batt_cache.voltage, - &batt->voltage); + &batt_cache.voltage, &batt->voltage); fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT, - &batt_cache.current, - &batt->current); + &batt_cache.current, &batt->current); fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE, - &batt_cache.desired_voltage, - &batt->desired_voltage); + &batt_cache.desired_voltage, &batt->desired_voltage); fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT, - &batt_cache.desired_current, - &batt->desired_current); + &batt_cache.desired_current, &batt->desired_current); fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY, - &batt_cache.remaining_capacity, - &batt->remaining_capacity); + &batt_cache.remaining_capacity, + &batt->remaining_capacity); fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY, - &batt_cache.full_capacity, - &batt->full_capacity); - fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, - &batt_cache.status, - &batt->status); + &batt_cache.full_capacity, &batt->full_capacity); + fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, &batt_cache.status, + &batt->status); fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE, - &batt_cache.temperature, - &batt->temperature); + &batt_cache.temperature, &batt->temperature); /* * If battery_compensate_params() didn't calculate display_charge * for us, also update it with last good value. */ - fix_single_param(batt->display_charge == 0, - &batt_cache.display_charge, - &batt->display_charge); + fix_single_param(batt->display_charge == 0, &batt_cache.display_charge, + &batt->display_charge); /* remove bad flags after applying cached values */ batt->flags &= ~BATT_FLAG_BAD_ANY; diff --git a/baseboard/kukui/build.mk b/baseboard/kukui/build.mk index c64f6978c8..f35ed1f4ce 100644 --- a/baseboard/kukui/build.mk +++ b/baseboard/kukui/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c index 99e51aead2..398473bfc8 100644 --- a/baseboard/kukui/charger_mt6370.c +++ b/baseboard/kukui/charger_mt6370.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -51,7 +51,7 @@ static void update_plt_resume(void) } DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT); -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* wait time to evaluate charger thermal status */ static timestamp_t thermal_wait_until; @@ -155,7 +155,7 @@ thermal_exit: thermal_wait_until.val = get_time().val + (3 * SECOND); } -static int command_jc(int argc, char **argv) +static int command_jc(int argc, const char **argv) { static int prev_jc_temp; int jc_temp; @@ -304,8 +304,8 @@ void mt6370_charger_profile_override(struct charge_state_data *curr) * and TE function. */ hook_call_deferred( - &charge_enable_eoc_and_te_data, - (4.5 * SECOND)); + &charge_enable_eoc_and_te_data, + (4.5 * SECOND)); } } } @@ -339,7 +339,6 @@ void mt6370_charger_profile_override(struct charge_state_data *curr) curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL, curr->batt.state_of_charge); } - } #ifndef CONFIG_BATTERY_SMART @@ -352,13 +351,12 @@ static void board_charge_termination(void) te = 1; } } -DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, - board_charge_termination, +DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination, HOOK_PRIO_DEFAULT); #endif -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { prev_charge_limit = charge_ma; prev_charge_mv = charge_mv; diff --git a/baseboard/kukui/charger_mt6370.h b/baseboard/kukui/charger_mt6370.h index 880b00a1a8..1de4e66b0b 100644 --- a/baseboard/kukui/charger_mt6370.h +++ b/baseboard/kukui/charger_mt6370.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c index 68953d8923..8731d7259c 100644 --- a/baseboard/kukui/emmc.c +++ b/baseboard/kukui/emmc.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -43,8 +43,8 @@ #include "bootblock_data.h" -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #if EMMC_SPI_PORT == 1 #define STM32_SPI_EMMC_REGS STM32_SPI1_REGS @@ -68,7 +68,7 @@ static timestamp_t boot_deadline; /* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */ #define SPI_RX_BUF_BYTES 1024 -#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4) +#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES / 4) static uint32_t in_msg[SPI_RX_BUF_WORDS]; /* Macros to advance in the circular buffer. */ @@ -92,7 +92,7 @@ static const struct dma_option dma_tx_option = { static const struct dma_option dma_rx_option = { STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC + STM32_DMA_CCR_CIRC }; /* Setup DMA to transfer bootblock. */ @@ -123,7 +123,7 @@ static void bootblock_stop(void) */ start = __hw_clock_source_read(); while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL && - __hw_clock_source_read() - start < timeout) + __hw_clock_source_read() - start < timeout) ; /* Then flush SPI FIFO, and make sure DAT line stays idle (high). */ @@ -152,8 +152,8 @@ static enum emmc_cmd emmc_parse_command(int index) /* Number of leading ones. */ shift0 = __builtin_clz(~data[0]); - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); + data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0)); + data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0)); if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { /* 400000000095 GO_IDLE_STATE */ @@ -177,7 +177,6 @@ static enum emmc_cmd emmc_parse_command(int index) return EMMC_ERROR; } - /* * Wake the EMMC task when there is a falling edge on the CMD line, so that we * can capture the command. diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c index b0e1f6b3de..2767199be0 100644 --- a/baseboard/kukui/emmc_ite.c +++ b/baseboard/kukui/emmc_ite.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,7 +17,7 @@ #include "bootblock_data.h" -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) enum emmc_cmd { EMMC_ERROR = -1, @@ -129,7 +129,7 @@ static void emmc_bootblock_transfer(void) /* Wait for FIFO1 or FIFO2 have been transmitted */ start = __hw_clock_source_read(); while (!(IT83XX_SPI_TXFSR & BIT(0)) && - (__hw_clock_source_read() - start < timeout_us)) + (__hw_clock_source_read() - start < timeout_us)) ; /* Abort an ongoing transfer due to a command is received. */ if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) @@ -147,16 +147,16 @@ static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0) uint32_t data[3]; data[0] = htobe32(cmd0[index]); - data[1] = htobe32(cmd0[index+1]); - data[2] = htobe32(cmd0[index+2]); + data[1] = htobe32(cmd0[index + 1]); + data[2] = htobe32(cmd0[index + 2]); if ((data[0] & 0xff000000) != 0x40000000) { /* Figure out alignment (cmd starts with 01) */ /* Number of leading ones. */ shift0 = __builtin_clz(~data[0]); - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); + data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0)); + data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0)); } if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c index 28ef005ee8..2f2c141510 100644 --- a/baseboard/kukui/usb_pd_policy.c +++ b/baseboard/kukui/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,8 +16,8 @@ #include "usb_pd_policy.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static int board_get_polarity(int port) { @@ -30,8 +30,8 @@ static int board_get_polarity(int port) static uint8_t vbus_en; -#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */ -#define VBUS_EN_HOOK_VERSION 1 +#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */ +#define VBUS_EN_HOOK_VERSION 1 static void vbus_en_preserve_state(void) { @@ -45,11 +45,11 @@ static void vbus_en_restore_state(void) const uint8_t *prev_vbus_en; int size, version; - prev_vbus_en = (const uint8_t *)system_get_jump_tag( - VBUS_EN_SYSJUMP_TAG, &version, &size); + prev_vbus_en = (const uint8_t *)system_get_jump_tag(VBUS_EN_SYSJUMP_TAG, + &version, &size); if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION && - size == sizeof(*prev_vbus_en)) { + size == sizeof(*prev_vbus_en)) { memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en)); } } @@ -89,7 +89,8 @@ int pd_set_power_supply_ready(int port) gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1); gpio_set_level(GPIO_EN_PP5000_USBC, 1); - if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C)) + if (IS_ENABLED(CONFIG_CHARGER_OTG) && + IS_ENABLED(CONFIG_CHARGER_ISL9238C)) charger_set_current(CHARGER_SOLO, 0); /* notify host of power info change */ @@ -142,7 +143,7 @@ __overridable int board_has_virtual_mux(void) } static void board_usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_mode, int polarity) + enum usb_switch usb_mode, int polarity) { usb_mux_set(port, mux_mode, usb_mode, polarity); @@ -163,8 +164,9 @@ __override void svdm_safe_dp_mode(int port) __override int svdm_enter_dp_mode(int port, uint32_t mode_caps) { /* Kukui/Krane doesn't support superspeed lanes. */ - const uint32_t support_pin_mode = board_has_virtual_mux() ? - (MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL; + const uint32_t support_pin_mode = + board_has_virtual_mux() ? (MODE_DP_PIN_C | MODE_DP_PIN_E) : + MODE_DP_PIN_ALL; /** * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane) @@ -205,11 +207,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, board_get_polarity(port)); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -227,8 +229,8 @@ __override void svdm_dp_post_config(int port) /* set the minimum time delay (2ms) for the next HPD IRQ */ svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, + USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED); } __override int svdm_dp_attention(int port, uint32_t *payload) @@ -267,8 +269,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) #endif /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; /* nak */ @@ -278,8 +280,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) board_set_dp_mux_control(lvl, board_get_polarity(port)); #endif /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } /* ack */ @@ -293,6 +295,6 @@ __override void svdm_exit_dp_mode(int port) board_set_dp_mux_control(0, 0); #endif usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/kukui/usb_pd_policy.h b/baseboard/kukui/usb_pd_policy.h index 78e0213f53..62d6bda062 100644 --- a/baseboard/kukui/usb_pd_policy.h +++ b/baseboard/kukui/usb_pd_policy.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c index ac261c3aa8..c86ef15ad7 100644 --- a/baseboard/mtscp-rv32i/baseboard.c +++ b/baseboard/mtscp-rv32i/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -7,28 +7,31 @@ #include "cache.h" #include "csr.h" #include "hooks.h" +#include "panic.h" #include "registers.h" #define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { /* SRAM (for most code, data) */ - {0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, + { 0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R }, /* SRAM (for IPI shared buffer) */ - {SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R}, - /* For AP domain */ + { SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R }, +/* For AP domain */ #ifdef CHIP_VARIANT_MT8195 - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P}, + { 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P }, #else - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R }, #endif /* For SCP sys */ - {0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R }, #ifdef CHIP_VARIANT_MT8195 - {0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, - {CONFIG_PANIC_DRAM_BASE, CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, MPU_ATTR_W | MPU_ATTR_R}, + { 0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R }, + { CONFIG_PANIC_DRAM_BASE, + CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, + MPU_ATTR_W | MPU_ATTR_R }, #else - {0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R }, #endif }; @@ -37,7 +40,7 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { #ifdef CONFIG_PANIC_CONSOLE_OUTPUT static void report_previous_panic(void) { - struct panic_data * panic = panic_get_data(); + struct panic_data *panic = panic_get_data(); if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0) return; @@ -48,11 +51,8 @@ static void report_previous_panic(void) } else { ccprintf("No panic data\n"); } - ccprintf("Latch PC:%x LR:%x SP:%x\n", - SCP_CORE0_MON_PC_LATCH, - SCP_CORE0_MON_LR_LATCH, - SCP_CORE0_MON_SP_LATCH); - + ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE0_MON_PC_LATCH, + SCP_CORE0_MON_LR_LATCH, SCP_CORE0_MON_SP_LATCH); } DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT); #endif diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h index 3af9fe1af9..49a18c8d9d 100644 --- a/baseboard/mtscp-rv32i/baseboard.h +++ b/baseboard/mtscp-rv32i/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,8 +21,8 @@ /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 -#define CONFIG_IPC_SHARED_OBJ_ADDR \ - (SCP_FW_END - \ +#define CONFIG_IPC_SHARED_OBJ_ADDR \ + (SCP_FW_END - \ (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) #define CONFIG_IPI #define CONFIG_RPMSG_NAME_SERVICE @@ -62,7 +62,8 @@ #define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */ #ifdef CHIP_VARIANT_MT8195 -#define CONFIG_PANIC_DATA_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) +#define CONFIG_PANIC_DATA_BASE \ + (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) #endif /* MPU settings */ diff --git a/baseboard/mtscp-rv32i/build.mk b/baseboard/mtscp-rv32i/build.mk index 420a3a4e08..90b8ded4a1 100644 --- a/baseboard/mtscp-rv32i/build.mk +++ b/baseboard/mtscp-rv32i/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c index b0756a797a..4c054dc029 100644 --- a/baseboard/mtscp-rv32i/mdp.c +++ b/baseboard/mtscp-rv32i/mdp.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,19 +19,23 @@ static void event_mdp_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_MDP_SERVICE); } static struct consumer const event_mdp_consumer; -static struct queue const event_mdp_queue = QUEUE_DIRECT(4, - struct mdp_msg_service, null_producer, event_mdp_consumer); +static struct queue const event_mdp_queue = QUEUE_DIRECT( + 4, struct mdp_msg_service, null_producer, event_mdp_consumer); static struct consumer const event_mdp_consumer = { .queue = &event_mdp_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_mdp_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void mdp_common_init(void) {} -void mdp_ipi_task_handler(void *pvParameters) {} +void mdp_common_init(void) +{ +} +void mdp_ipi_task_handler(void *pvParameters) +{ +} #endif static void mdp_ipi_handler(int id, void *data, unsigned int len) diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h index eea3ffb289..48f4937ace 100644 --- a/baseboard/mtscp-rv32i/mdp.h +++ b/baseboard/mtscp-rv32i/mdp.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,10 +11,10 @@ struct mdp_msg_service { unsigned char msg[20]; }; BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void mdp_common_init(void); void mdp_ipi_task_handler(void *pvParameters); -#endif /* __CROS_EC_SCP_MDP_H */ +#endif /* __CROS_EC_SCP_MDP_H */ diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c index c3f5f5a9cf..7ff98fff10 100644 --- a/baseboard/mtscp-rv32i/vdec.c +++ b/baseboard/mtscp-rv32i/vdec.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,11 +21,11 @@ static void event_vdec_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_VDEC_SERVICE); } static struct consumer const event_vdec_consumer; -static struct queue const event_vdec_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_consumer); +static struct queue const event_vdec_queue = + QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer); static struct consumer const event_vdec_consumer = { .queue = &event_vdec_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_vdec_written, }), }; @@ -36,19 +36,23 @@ static void event_vdec_core_written(struct consumer const *consumer, task_wake(TASK_ID_VDEC_CORE_SERVICE); } static struct consumer const event_vdec_core_consumer; -static struct queue const event_vdec_core_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_core_consumer); +static struct queue const event_vdec_core_queue = QUEUE_DIRECT( + 8, struct vdec_msg, null_producer, event_vdec_core_consumer); static struct consumer const event_vdec_core_consumer = { .queue = &event_vdec_core_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_vdec_core_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void vdec_msg_handler(void *data) {} -void vdec_core_msg_handler(void *data) {} +void vdec_msg_handler(void *data) +{ +} +void vdec_core_msg_handler(void *data) +{ +} #endif static void vdec_h264_ipi_handler(int id, void *data, uint32_t len) diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h index cdc16ba9e0..c203c09fae 100644 --- a/baseboard/mtscp-rv32i/vdec.h +++ b/baseboard/mtscp-rv32i/vdec.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,7 +19,7 @@ struct vdec_msg { unsigned char msg[48]; }; BUILD_ASSERT(member_size(struct vdec_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void vdec_core_msg_handler(void *msg); diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c index 09bb0cbd39..bed2a2dbc6 100644 --- a/baseboard/mtscp-rv32i/venc.c +++ b/baseboard/mtscp-rv32i/venc.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,18 +21,20 @@ static void event_venc_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_VENC_SERVICE); } static struct consumer const event_venc_consumer; -static struct queue const event_venc_queue = QUEUE_DIRECT(8, - struct venc_msg, null_producer, event_venc_consumer); +static struct queue const event_venc_queue = + QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer); static struct consumer const event_venc_consumer = { .queue = &event_venc_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_venc_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void venc_h264_msg_handler(void *data) {} +void venc_h264_msg_handler(void *data) +{ +} #endif static void venc_h264_ipi_handler(int id, void *data, uint32_t len) diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h index 47454c4507..c5c7df3883 100644 --- a/baseboard/mtscp-rv32i/venc.h +++ b/baseboard/mtscp-rv32i/venc.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,7 +18,7 @@ struct venc_msg { unsigned char msg[288]; }; BUILD_ASSERT(member_size(struct venc_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void venc_h264_msg_handler(void *data); diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c index 15e46f006e..53c42e5a26 100644 --- a/baseboard/nucleo-f412zg/base-board.c +++ b/baseboard/nucleo-f412zg/base-board.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h index d41cdfd207..0ce6c226e2 100644 --- a/baseboard/nucleo-f412zg/base-board.h +++ b/baseboard/nucleo-f412zg/base-board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -50,28 +50,28 @@ #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (128 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */ -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * We want to prevent flash readout, and use it as indicator of protection @@ -116,7 +116,7 @@ */ #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE #ifdef SECTION_IS_RW - #undef CONFIG_ROLLBACK_UPDATE +#undef CONFIG_ROLLBACK_UPDATE #endif /*-------------------------------------------------------------------------* @@ -124,9 +124,9 @@ *-------------------------------------------------------------------------*/ #ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ - #define CONFIG_RSA - #define CONFIG_RWSIG +/* RO verifies the RW partition signature */ +#define CONFIG_RSA +#define CONFIG_RWSIG #endif /* SECTION_IS_RO */ #define CONFIG_RSA_KEY_SIZE 3072 #define CONFIG_RSA_EXPONENT_3 @@ -164,7 +164,7 @@ #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_RNG #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED @@ -172,27 +172,27 @@ #define CONFIG_WP_ACTIVE_HIGH #ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ - #define CONFIG_SPI +/* TODO(hesling): Fix the illogical dependency between spi.c + * and host_command.c + * + * Currently, the chip/stm32/spi.c depends on functions defined in + * common/host_command.c. When unit test builds use their own tasklist + * without the HOSTCMD task, host_command.c is excluded from the build, + * but chip/stm32/spi.c remains (because of CONFIG_SPI). + * This triggers an undefined reference linker error. + * The reproduce case: + * - Allow CONFIG_SPI in TEST_BUILDs + * - make BOARD=nucleo-h743zi tests + */ +#define CONFIG_SPI #endif #ifndef __ASSEMBLER__ - /* Timer selection */ - #define TIM_CLOCK32 2 - #define TIM_WATCHDOG 16 - #include "gpio_signal.h" - void button_event(enum gpio_signal signal); +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_WATCHDOG 16 +#include "gpio_signal.h" +void button_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASE_BOARD_H */ diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc index 4ebd99f91f..d0c48a46e5 100644 --- a/baseboard/nucleo-f412zg/base-gpio.inc +++ b/baseboard/nucleo-f412zg/base-gpio.inc @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk index 1456331fec..d38a618d8c 100644 --- a/baseboard/nucleo-f412zg/build.mk +++ b/baseboard/nucleo-f412zg/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg index 3333d1163a..cbc9fe0218 100644 --- a/baseboard/nucleo-f412zg/openocd-flash.cfg +++ b/baseboard/nucleo-f412zg/openocd-flash.cfg @@ -1,4 +1,4 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg index 589d4400f4..3b286a4ebc 100644 --- a/baseboard/nucleo-f412zg/openocd.cfg +++ b/baseboard/nucleo-f412zg/openocd.cfg @@ -1,4 +1,4 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/baseboard/nucleo-h743zi/base-board.c b/baseboard/nucleo-h743zi/base-board.c index 15e46f006e..53c42e5a26 100644 --- a/baseboard/nucleo-h743zi/base-board.c +++ b/baseboard/nucleo-h743zi/base-board.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h index df5e4bfa8c..eb4b8ac1fa 100644 --- a/baseboard/nucleo-h743zi/base-board.h +++ b/baseboard/nucleo-h743zi/base-board.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -53,25 +53,25 @@ * * We need 2 independently erasable blocks, at a minimum. */ -#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE_BYTES / 2) - \ - CONFIG_ROLLBACK_SIZE) +#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_ROLLBACK_OFF \ + ((CONFIG_FLASH_SIZE_BYTES / 2) - CONFIG_ROLLBACK_SIZE) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* Disabled features */ @@ -92,31 +92,31 @@ #define CONFIG_LOW_POWER_IDLE #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_RNG #define CONFIG_RWSIG_TYPE_RWSIG #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED #undef CONFIG_SHAREDLIB_SIZE -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 #define CONFIG_STM_HWTIMER32 #define CONFIG_WATCHDOG_HELP #define CONFIG_WP_ACTIVE_HIGH #ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ -# define CONFIG_SPI +/* TODO(hesling): Fix the illogical dependency between spi.c + * and host_command.c + * + * Currently, the chip/stm32/spi.c depends on functions defined in + * common/host_command.c. When unit test builds use their own tasklist + * without the HOSTCMD task, host_command.c is excluded from the build, + * but chip/stm32/spi.c remains (because of CONFIG_SPI). + * This triggers an undefined reference linker error. + * The reproduce case: + * - Allow CONFIG_SPI in TEST_BUILDs + * - make BOARD=nucleo-h743zi tests + */ +#define CONFIG_SPI #endif /* @@ -146,10 +146,10 @@ #define CONFIG_CMD_IDLE_STATS #ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ -# define CONFIG_RSA -# define CONFIG_RWSIG -#endif /* SECTION_IS_RO */ +/* RO verifies the RW partition signature */ +#define CONFIG_RSA +#define CONFIG_RWSIG +#endif /* SECTION_IS_RO */ #define CONFIG_RSA_KEY_SIZE 3072 #define CONFIG_RSA_EXPONENT_3 @@ -160,7 +160,7 @@ */ #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE #ifdef SECTION_IS_RW -# undef CONFIG_ROLLBACK_UPDATE +#undef CONFIG_ROLLBACK_UPDATE #endif /* * Add rollback protection @@ -169,11 +169,11 @@ #define CONFIG_ROLLBACK_MPU_PROTECT #ifndef __ASSEMBLER__ - /* Timer selection */ -# define TIM_CLOCK32 2 -# define TIM_WATCHDOG 16 -# include "gpio_signal.h" - void button_event(enum gpio_signal signal); +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_WATCHDOG 16 +#include "gpio_signal.h" +void button_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASE_BOARD_H */ diff --git a/baseboard/nucleo-h743zi/base-ec.tasklist b/baseboard/nucleo-h743zi/base-ec.tasklist index fae8952113..e8e752aa4e 100644 --- a/baseboard/nucleo-h743zi/base-ec.tasklist +++ b/baseboard/nucleo-h743zi/base-ec.tasklist @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/nucleo-h743zi/base-gpio.inc b/baseboard/nucleo-h743zi/base-gpio.inc index ef224cbaf1..ad7d313328 100644 --- a/baseboard/nucleo-h743zi/base-gpio.inc +++ b/baseboard/nucleo-h743zi/base-gpio.inc @@ -1,5 +1,5 @@ /* - * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk index 470214aabc..36c0cfdf50 100644 --- a/baseboard/nucleo-h743zi/build.mk +++ b/baseboard/nucleo-h743zi/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/nucleo-h743zi/openocd-flash.cfg b/baseboard/nucleo-h743zi/openocd-flash.cfg index 4517266d7b..8ee5dd6707 100644 --- a/baseboard/nucleo-h743zi/openocd-flash.cfg +++ b/baseboard/nucleo-h743zi/openocd-flash.cfg @@ -1,4 +1,4 @@ -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/baseboard/nucleo-h743zi/openocd.cfg b/baseboard/nucleo-h743zi/openocd.cfg index 528e8d6cab..9fa8aa89a9 100644 --- a/baseboard/nucleo-h743zi/openocd.cfg +++ b/baseboard/nucleo-h743zi/openocd.cfg @@ -1,4 +1,4 @@ -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c index 4f338ab131..0f012d1352 100644 --- a/baseboard/octopus/baseboard.c +++ b/baseboard/octopus/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -27,8 +27,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* Keyboard scan setting */ @@ -218,9 +218,9 @@ int board_is_i2c_port_powered(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) - return ADC_VBUS_C0; + return ADC_VBUS_C0; if (port == 1) - return ADC_VBUS_C1; + return ADC_VBUS_C1; CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; } @@ -238,27 +238,26 @@ void baseboard_tcpc_init(void) */ for (int port = 0; port < board_get_usb_pd_port_count(); ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } /* Called after the cbi_init (via +2) */ DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; if (!is_valid_port && port != CHARGE_PORT_NONE) return EC_ERROR_INVAL; - if (port == CHARGE_PORT_NONE) { CPRINTSUSB("Disabling all charger ports"); /* Disable all ports. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { + for (i = 0; + (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); + i++) { /* * Do not return early if one fails otherwise we can * get into a boot loop assertion failure. @@ -282,8 +281,7 @@ int board_set_active_charge_port(int port) * Turn off the other ports' sink path FETs, before enabling the * requested charge port. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { + for (i = 0; (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); i++) { if (i == port) continue; @@ -300,8 +298,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Empirically, the charger seems to draw a little more current that @@ -310,9 +308,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, #if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238) charge_ma = (charge_ma * 95) / 100; #endif - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_hibernate(void) diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index da564f5056..724540d0f0 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,11 +12,13 @@ * EC Config */ +#define CONFIG_LTO + /* * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) /* * Variant EC defines. Pick one: @@ -24,59 +26,59 @@ * VARIANT_OCTOPUS_EC_ITE8320 */ #if defined(VARIANT_OCTOPUS_EC_NPCX796FB) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ - #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - - /* Internal SPI flash on NPCX7 */ - /* Flash is 1MB but reserve half for future use. */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 - #define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 - #define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 - #define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 - #define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - /* Enable PSL hibernate mode. */ - #define CONFIG_HIBERNATE_PSL - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - - /* Allow the EC to enter deep sleep in S0 */ - #define CONFIG_LOW_POWER_S0 +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +/* Flash is 1MB but reserve half for future use. */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) + +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* I2C Bus Configuration */ +#define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +/* Enable PSL hibernate mode. */ +#define CONFIG_HIBERNATE_PSL + +/* EC variant determines USB-C variant */ +#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS + +/* Allow the EC to enter deep sleep in S0 */ +#define CONFIG_LOW_POWER_S0 #elif defined(VARIANT_OCTOPUS_EC_ITE8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_SENSOR IT83XX_I2C_CH_B - #define I2C_PORT_USBC0 IT83XX_I2C_CH_C - #define I2C_PORT_USBC1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_F - #define I2C_ADDR_EEPROM_FLAGS 0x50 - #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS - - /* - * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at - * 48MHz core cpu clock. - */ - #define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 +/* IT83XX config */ +#define CONFIG_IT83XX_VCC_1P8V +/* I2C Bus Configuration */ +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ +#define I2C_PORT_SENSOR IT83XX_I2C_CH_B +#define I2C_PORT_USBC0 IT83XX_I2C_CH_C +#define I2C_PORT_USBC1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ +#define I2C_PORT_EEPROM IT83XX_I2C_CH_F +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 + +/* EC variant determines USB-C variant */ +#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS + +/* + * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at + * 48MHz core cpu clock. + */ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 #else - #error Must define a VARIANT_OCTOPUS_EC +#error Must define a VARIANT_OCTOPUS_EC #endif /* VARIANT_OCTOPUS_EC */ /* Common EC defines */ @@ -115,33 +117,33 @@ * VARIANT_OCTOPUS_CHARGER_BQ25703 */ #if defined(VARIANT_OCTOPUS_CHARGER_ISL9238) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - /* - * ISL923x driver sets "Adapter insertion to Switching Debounce" - * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +/* + * ISL923x driver sets "Adapter insertion to Switching Debounce" + * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms + */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703) - #define CONFIG_CHARGER_BQ25703 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 - /* - * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 50 +#define CONFIG_CHARGER_BQ25703 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +/* + * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. + */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 50 #elif defined(CONFIG_CHARGER_RUNTIME_CONFIG) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_BQ25710 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 - #define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 - #define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 - - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_BQ25710 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 + +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #else - #error Must define a VARIANT_OCTOPUS_CHARGER +#error Must define a VARIANT_OCTOPUS_CHARGER #endif /* VARIANT_OCTOPUS_CHARGER */ /* Common charger defines */ @@ -155,7 +157,7 @@ /* Common battery defines */ #define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L #define CONFIG_BATTERY_REVIVE_DISCONNECT @@ -166,38 +168,38 @@ * Automatically defined by VARIANT_OCTOPUS_EC_ variant. */ - /* - * Variant USBC defines. Pick one: - * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) - */ +/* + * Variant USBC defines. Pick one: + * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS + * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) + */ #if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS) - #define CONFIG_USB_PD_TCPC_LOW_POWER - #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - #define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ +#define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ #endif - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ - #define CONFIG_USB_PD_VBUS_DETECT_TCPC - #define CONFIG_USBC_PPC_NX20P3483 +#define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USBC_PPC_NX20P3483 #elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS) - #undef CONFIG_USB_PD_TCPC_LOW_POWER - #undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - #define CONFIG_USB_PD_VBUS_DETECT_PPC - #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ - #define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ - #define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER - #define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ - #define CONFIG_USBC_PPC_VCONN - #define CONFIG_USBC_PPC_DEDICATED_INT +#undef CONFIG_USB_PD_TCPC_LOW_POWER +#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ +#define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ +#define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ +#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER +#define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ +#define CONFIG_USBC_PPC_VCONN +#define CONFIG_USBC_PPC_DEDICATED_INT #else - #error Must define a VARIANT_OCTOPUS_USBC +#error Must define a VARIANT_OCTOPUS_USBC #endif /* VARIANT_OCTOPUS_USBC */ /* Common USB-C defines */ -#define USB_PD_PORT_TCPC_0 0 -#define USB_PD_PORT_TCPC_1 1 +#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_1 1 #define CONFIG_USB_PID 0x5046 #define CONFIG_USB_DRP_ACC_TRYSRC @@ -226,14 +228,14 @@ #define CONFIG_CMD_PPC_DUMP /* TODO(b/76218141): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* TODO(b/76218141): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /******************************************************************************* * USB-A Configs @@ -252,7 +254,7 @@ * SoC / PCH Config */ - /* Common SoC / PCH defines */ +/* Common SoC / PCH defines */ #define CONFIG_CHIPSET_GEMINILAKE #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI @@ -275,7 +277,7 @@ #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI /******************************************************************************* * Sensor Config @@ -287,7 +289,7 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) #ifndef VARIANT_OCTOPUS_NO_SENSORS diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk index bb8a6f8267..696f60d42e 100644 --- a/baseboard/octopus/build.mk +++ b/baseboard/octopus/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Copyright 2018 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c index 80d8614eb5..827d2e045e 100644 --- a/baseboard/octopus/cbi_ssfc.c +++ b/baseboard/octopus/cbi_ssfc.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h index 0b9eafc888..570c240da1 100644 --- a/baseboard/octopus/cbi_ssfc.h +++ b/baseboard/octopus/cbi_ssfc.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,8 +18,8 @@ enum ssfc_tcpc_p1 { SSFC_TCPC_P1_PS8751, SSFC_TCPC_P1_PS8755, }; -#define SSFC_TCPC_P1_OFFSET 0 -#define SSFC_TCPC_P1_MASK GENMASK(2, 0) +#define SSFC_TCPC_P1_OFFSET 0 +#define SSFC_TCPC_P1_MASK GENMASK(2, 0) /* * PPC Port 1 (Bits 3-5) @@ -29,8 +29,8 @@ enum ssfc_ppc_p1 { SSFC_PPC_P1_NX20P348X, SSFC_PPC_P1_SYV682X, }; -#define SSFC_PPC_P1_OFFSET 3 -#define SSFC_PPC_P1_MASK GENMASK(5, 3) +#define SSFC_PPC_P1_OFFSET 3 +#define SSFC_PPC_P1_MASK GENMASK(5, 3) /* * Charger (Bits 8-6) @@ -40,8 +40,8 @@ enum ssfc_charger { SSFC_CHARGER_ISL9238, SSFC_CHARGER_BQ25710, }; -#define SSFC_CHARGER_OFFSET 6 -#define SSFC_CHARGER_MASK GENMASK(8, 6) +#define SSFC_CHARGER_OFFSET 6 +#define SSFC_CHARGER_MASK GENMASK(8, 6) /* * Audio (Bits 11-9) @@ -56,8 +56,8 @@ enum ssfc_sensor { SSFC_SENSOR_ICM426XX, SSFC_SENSOR_BMI260, }; -#define SSFC_SENSOR_OFFSET 12 -#define SSFC_SENSOR_MASK GENMASK(14, 12) +#define SSFC_SENSOR_OFFSET 12 +#define SSFC_SENSOR_MASK GENMASK(14, 12) enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void); enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void); diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c index 3dd6ad29f5..c8b8b96d3a 100644 --- a/baseboard/octopus/usb_pd_policy.c +++ b/baseboard/octopus/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,8 +17,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c index 72c0021e89..e79f4cdb01 100644 --- a/baseboard/octopus/variant_ec_ite8320.c +++ b/baseboard/octopus/variant_ec_ite8320.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,40 +28,30 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "usbc0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "usbc1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, - { - .name = "eeprom", - .port = IT83XX_I2C_CH_F, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, + { .name = "power", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "usbc0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "usbc1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, + { .name = "eeprom", + .port = IT83XX_I2C_CH_F, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c index 8c3cbd2460..23a4f58bae 100644 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ b/baseboard/octopus/variant_ec_npcx796fb.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -31,49 +31,37 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "charger", + .port = I2C_PORT_CHARGER, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #ifndef VARIANT_OCTOPUS_NO_SENSORS - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 100, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 100, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -82,8 +70,9 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP, - .freq = 100 }, + [PWM_CH_KBLIGHT] = { .channel = 3, + .flags = PWM_CONFIG_DSLEEP, + .freq = 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); #endif diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c index 00640168cf..983887bc08 100644 --- a/baseboard/octopus/variant_usbc_ec_tcpcs.c +++ b/baseboard/octopus/variant_usbc_ec_tcpcs.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,8 +22,8 @@ #include "usbc_ppc.h" #include "util.h" -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 +#define USB_PD_PORT_ITE_0 0 +#define USB_PD_PORT_ITE_1 1 /******************************************************************************/ /* USB-C TPCP Configuration */ @@ -49,13 +49,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* TODO(crbug.com/826441): Consolidate this logic with other impls */ static void board_it83xx_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required) + mux_state_t mux_state, bool *ack_required) { int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0; - enum gpio_signal gpio = me->usb_port ? - GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL; + enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1V8_ODL : + GPIO_USB_C0_HPD_1V8_ODL; /* This driver does not use host command ACKs */ *ack_required = false; @@ -72,38 +71,38 @@ static void board_it83xx_hpd_status(const struct usb_mux *me, } /* This configuration might be override by each boards */ -struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USB_PD_PORT_ITE_0] = { - .usb_port = USB_PD_PORT_ITE_0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .hpd_update = &board_it83xx_hpd_status, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_ITE_0, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, + .driver = &it5205_usb_mux_driver, + .hpd_update = &board_it83xx_hpd_status, + }, }, [USB_PD_PORT_ITE_1] = { - .usb_port = USB_PD_PORT_ITE_1, - /* Use PS8751 as mux only */ - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS, - .flags = USB_MUX_FLAG_NOT_TCPC, - .driver = &ps8xxx_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_ITE_1, + /* Use PS8751 as mux only */ + .i2c_port = I2C_PORT_USBC1, + .i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + .flags = USB_MUX_FLAG_NOT_TCPC, + .driver = &ps8xxx_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, } }; /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .i2c_port = I2C_PORT_USBC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_ITE_1] = { - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_ITE_0] = { .i2c_port = I2C_PORT_USBC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_ITE_1] = { .i2c_port = I2C_PORT_USBC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -158,6 +157,6 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) * correctly in the PPC driver via the pd state machine. */ if (ppc_set_vconn(port, enabled) != EC_SUCCESS) - cprints(CC_USBPD, "C%d: Failed %sabling vconn", - port, enabled ? "en" : "dis"); + cprints(CC_USBPD, "C%d: Failed %sabling vconn", port, + enabled ? "en" : "dis"); } diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c index d26e234c4b..abc325dfa3 100644 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -21,8 +21,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* USB-C TPCP Configuration */ @@ -66,22 +66,26 @@ static int ps8751_tune_mux(const struct usb_mux *me) } #endif -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USB_PD_PORT_TCPC_0] = { - .usb_port = USB_PD_PORT_TCPC_0, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_TCPC_0, #if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .board_init = &ps8751_tune_mux, #else - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, + .driver = &anx7447_usb_mux_driver, + .hpd_update = &anx7447_tcpc_update_hpd_status, #endif + }, }, [USB_PD_PORT_TCPC_1] = { - .usb_port = USB_PD_PORT_TCPC_1, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .mux = &(const struct usb_mux) { + .usb_port = USB_PD_PORT_TCPC_1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, } }; diff --git a/baseboard/trogdor/baseboard.c b/baseboard/trogdor/baseboard.c index 6f49ecb4ae..3f3c778ea5 100644 --- a/baseboard/trogdor/baseboard.c +++ b/baseboard/trogdor/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h index d65fb2dc1e..63813c89a0 100644 --- a/baseboard/trogdor/baseboard.h +++ b/baseboard/trogdor/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,12 +13,12 @@ * The sensor stack is generating a lot of activity. * They can be enabled through the console command 'chan'. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_SPI_FLASH_REGS @@ -142,13 +142,13 @@ #define CONFIG_CMD_ACCEL_INFO /* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Chipset */ #define CONFIG_CHIPSET_SC7180 @@ -166,56 +166,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* I2C Ports */ #define I2C_PORT_BATTERY I2C_PORT_POWER #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* UART */ #define CONFIG_CMD_CHARGEN /* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) /* And the MKBP events */ #ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #else #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) + (BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #endif #endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/trogdor/build.mk b/baseboard/trogdor/build.mk index a51c7c7e17..02ed466d2b 100644 --- a/baseboard/trogdor/build.mk +++ b/baseboard/trogdor/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/trogdor/hibernate.c b/baseboard/trogdor/hibernate.c index c28082e75d..19af7cfe2e 100644 --- a/baseboard/trogdor/hibernate.c +++ b/baseboard/trogdor/hibernate.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c index b539539c98..a8076d0ed5 100644 --- a/baseboard/trogdor/power.c +++ b/baseboard/trogdor/power.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -35,4 +35,4 @@ void board_chipset_shutdown_complete(void) gpio_set_level(GPIO_EN_PP3300_A, 0); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c index 56ca4514d5..7954d0a352 100644 --- a/baseboard/trogdor/usb_pd_policy.c +++ b/baseboard/trogdor/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,8 +12,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -233,8 +230,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv IRQ. HPD->1", port); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; @@ -242,8 +239,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl); gpio_set_level(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -259,7 +256,7 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); CPRINTS("C%d: DP exit. HPD->0", port); gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); } diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c index 6b3ad33a35..fd36aef81f 100644 --- a/baseboard/volteer/baseboard.c +++ b/baseboard/volteer/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -23,8 +23,8 @@ #include "usbc_config.h" #endif -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /******************************************************************************/ /* ADC configuration */ @@ -73,21 +73,21 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CHARGER}, - [TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR}, - [TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_DDR_SOC}, - [TEMP_SENSOR_4_FAN] = {.name = "Fan", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_FAN}, + [TEMP_SENSOR_1_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_CHARGER }, + [TEMP_SENSOR_2_PP3300_REGULATOR] = { .name = "PP3300 Regulator", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR }, + [TEMP_SENSOR_3_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_DDR_SOC }, + [TEMP_SENSOR_4_FAN] = { .name = "Fan", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index c7f7c0d047..3b8e475fe5 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -13,11 +13,11 @@ /* * By default, enable all console messages excepted HC */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS @@ -44,8 +44,8 @@ /* Host communication */ #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 /* Chipset config */ #define CONFIG_CHIPSET_TIGERLAKE @@ -94,10 +94,10 @@ #define CONFIG_CMD_ACCEL_INFO /* Thermal features */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_POWER -#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK +#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK #define CONFIG_THERMISTOR #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B #define CONFIG_THROTTLE_AP @@ -107,7 +107,7 @@ #define CONFIG_CHARGE_MANAGER #define CONFIG_CHARGER #define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_INPUT_CURRENT 512 /* * Hardware based charge ramp is broken in the ISL9241 (b/169350714). @@ -115,7 +115,7 @@ #define CONFIG_CHARGE_RAMP_SW #define CONFIG_CHARGER_ISL9241 /* Setting ISL9241 Register Control1 switching frequency to 724kHz. */ -#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ +#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ #define CONFIG_USB_CHARGER #define CONFIG_BC12_DETECT_PI3USB9201 @@ -124,8 +124,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Common battery defines */ #define CONFIG_BATTERY_SMART @@ -140,7 +140,7 @@ /* EDP back-light control defines */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN /* USB Type C and USB PD defines */ /* Enable the new USB-C PD stack */ @@ -169,11 +169,11 @@ #define CONFIG_USB_PD_TCPC_LOW_POWER #define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_USB_PD_TCPM_RT1715 -#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ -#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ +#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ +#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -190,7 +190,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD diff --git a/baseboard/volteer/baseboard_usbc_config.h b/baseboard/volteer/baseboard_usbc_config.h index bf02b1cb34..db5e296d46 100644 --- a/baseboard/volteer/baseboard_usbc_config.h +++ b/baseboard/volteer/baseboard_usbc_config.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c index 4953d7a49e..f143b67c91 100644 --- a/baseboard/volteer/battery_presence.c +++ b/baseboard/volteer/battery_presence.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -24,8 +24,9 @@ static bool battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } __overridable bool board_battery_is_initialized(void) diff --git a/baseboard/volteer/build.mk b/baseboard/volteer/build.mk index 08b68c5816..2b2f4e97b1 100644 --- a/baseboard/volteer/build.mk +++ b/baseboard/volteer/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c index ea446acc4e..28606d7eaf 100644 --- a/baseboard/volteer/cbi.c +++ b/baseboard/volteer/cbi.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -11,8 +11,8 @@ #include "hooks.h" #include "system.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) static uint8_t board_id; diff --git a/baseboard/volteer/cbi.h b/baseboard/volteer/cbi.h index 049c0f65e2..dc940f1edc 100644 --- a/baseboard/volteer/cbi.h +++ b/baseboard/volteer/cbi.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c index e602691aeb..7506278e16 100644 --- a/baseboard/volteer/cbi_ec_fw_config.c +++ b/baseboard/volteer/cbi_ec_fw_config.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,7 +8,7 @@ #include "cbi_ec_fw_config.h" #include "cros_board_info.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union volteer_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h index 0a44e1f9e4..da91dff27b 100644 --- a/baseboard/volteer/cbi_ec_fw_config.h +++ b/baseboard/volteer/cbi_ec_fw_config.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -43,23 +43,20 @@ enum ec_cfg_numeric_pad_type { NUMERIC_PAD_ENABLED = 1 }; -enum ec_cfg_keyboard_layout { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1 -}; +enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 }; union volteer_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t thermal : 4; - uint32_t audio : 3; - enum ec_cfg_tabletmode_type tabletmode : 1; - uint32_t lte_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - enum ec_cfg_numeric_pad_type num_pad : 1; - uint32_t sd_db : 4; - enum ec_cfg_keyboard_layout kb_layout : 2; - uint32_t reserved_2 : 10; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t thermal : 4; + uint32_t audio : 3; + enum ec_cfg_tabletmode_type tabletmode : 1; + uint32_t lte_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + enum ec_cfg_numeric_pad_type num_pad : 1; + uint32_t sd_db : 4; + enum ec_cfg_keyboard_layout kb_layout : 2; + uint32_t reserved_2 : 10; }; uint32_t raw_value; }; diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c index 42b11c4a1c..f68602b558 100644 --- a/baseboard/volteer/cbi_ssfc.c +++ b/baseboard/volteer/cbi_ssfc.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -39,3 +39,8 @@ enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void) { return cached_ssfc.lightbar; } + +enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void) +{ + return cached_ssfc.keyboard; +} diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h index e3431129bc..225ff8670e 100644 --- a/baseboard/volteer/cbi_ssfc.h +++ b/baseboard/volteer/cbi_ssfc.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -40,12 +40,19 @@ enum ec_ssfc_lightbar { SSFC_LIGHTBAR_12_LED = 2 }; +/* + * Keyboard Type (Bit 12) + */ +enum ec_ssfc_keyboard { SSFC_KEYBOARD_DEFAULT = 0, SSFC_KEYBOARD_GAMING = 1 }; + union volteer_cbi_ssfc { struct { enum ec_ssfc_base_sensor base_sensor : 3; enum ec_ssfc_lid_sensor lid_sensor : 3; enum ec_ssfc_lightbar lightbar : 2; - uint32_t reserved_2 : 24; + uint32_t reserved_2 : 4; + enum ec_ssfc_keyboard keyboard : 1; + uint32_t reserved_3 : 19; }; uint32_t raw_value; }; @@ -71,4 +78,11 @@ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); */ enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void); +/** + * Get keyboard type from SSFC_CONFIG. + * + * @return the keyboard type. + */ +enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void); + #endif /* _Volteer_CBI_SSFC__H_ */ diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c index a674b98f41..84fa4e037c 100644 --- a/baseboard/volteer/charger.c +++ b/baseboard/volteer/charger.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,8 +16,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -30,8 +30,7 @@ const struct charger_config_t chg_chips[] = { int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -52,7 +51,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -83,11 +81,10 @@ int board_set_active_charge_port(int port) } __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_overcurrent_event(int port, int is_overcurrented) diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c index b0d6b847ce..882c067b6d 100644 --- a/baseboard/volteer/power.c +++ b/baseboard/volteer/power.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c index 5b9000b3f7..81e02b769f 100644 --- a/baseboard/volteer/usb_pd_policy.c +++ b/baseboard/volteer/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,8 +14,8 @@ #include "usb_pd.h" #include "system.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -74,54 +74,44 @@ int board_vbus_source_enabled(int port) return ppc_is_sourcing_vbus(port); } +#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE /* ----------------- Vendor Defined Messages ------------------ */ /* Responses specifically for the enablement of TBT mode in the role of UFP */ #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT( - CONFIG_USB_PID, CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { @@ -163,8 +153,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) /* Track whether we've been enabled to ACK TBT EnterModes requests */ static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT]; -__override enum ec_status board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply) +__override enum ec_status +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) { /* Note: Host command has already bounds-checked port */ if (reply == TYPEC_TBT_UFP_REPLY_ACK) @@ -177,8 +167,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port, return EC_RES_SUCCESS; } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -191,7 +180,7 @@ static int svdm_tbt_compat_response_enter_mode( return 0; /* NAK */ if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); @@ -201,7 +190,7 @@ static int svdm_tbt_compat_response_enter_mode( * Mode that requires the reconfiguring of any pins. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); @@ -230,3 +219,4 @@ const struct svdm_response svdm_rsp = { .amode = NULL, .exit_mode = NULL, }; +#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */ diff --git a/baseboard/volteer/usbc_config.c b/baseboard/volteer/usbc_config.c index 36ca78d513..001f47e45f 100644 --- a/baseboard/volteer/usbc_config.c +++ b/baseboard/volteer/usbc_config.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c index 0b48d1075b..593bcf1168 100644 --- a/baseboard/zork/baseboard.c +++ b/baseboard/zork/baseboard.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -31,6 +31,7 @@ #include "motion_sense.h" #include "power.h" #include "power_button.h" +#include "printf.h" #include "pwm.h" #include "pwm_chip.h" #include "registers.h" @@ -59,15 +60,15 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* * In the AOZ1380 PPC, there are no programmable features. We use * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -__overridable int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +__overridable int +board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; @@ -96,11 +97,10 @@ static void baseboard_chipset_resume(void) DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /* Keyboard scan setting */ @@ -134,19 +134,19 @@ __override struct keyboard_scan_config keyscan_config = { * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. */ const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} + { 2761 / THERMISTOR_SCALING_FACTOR, 0 }, + { 2492 / THERMISTOR_SCALING_FACTOR, 10 }, + { 2167 / THERMISTOR_SCALING_FACTOR, 20 }, + { 1812 / THERMISTOR_SCALING_FACTOR, 30 }, + { 1462 / THERMISTOR_SCALING_FACTOR, 40 }, + { 1146 / THERMISTOR_SCALING_FACTOR, 50 }, + { 878 / THERMISTOR_SCALING_FACTOR, 60 }, + { 665 / THERMISTOR_SCALING_FACTOR, 70 }, + { 500 / THERMISTOR_SCALING_FACTOR, 80 }, + { 434 / THERMISTOR_SCALING_FACTOR, 85 }, + { 376 / THERMISTOR_SCALING_FACTOR, 90 }, + { 326 / THERMISTOR_SCALING_FACTOR, 95 }, + { 283 / THERMISTOR_SCALING_FACTOR, 100 } }; const struct thermistor_info thermistor_info = { @@ -263,8 +263,10 @@ void board_print_temps(void) { int t, i; int rv; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; - cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + cprintf(CC_THERMAL, "[%s ", ts_str); for (i = 0; i < TEMP_SENSOR_COUNT; ++i) { rv = temp_sensor_read(i, &t); if (rv == EC_SUCCESS) @@ -278,7 +280,7 @@ void board_print_temps(void) temps_interval * SECOND); } -static int command_temps_log(int argc, char **argv) +static int command_temps_log(int argc, const char **argv) { char *e = NULL; @@ -293,8 +295,7 @@ static int command_temps_log(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, - "seconds", +DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, "seconds", "Print temp sensors periodically"); /* diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h index e97bcb4e45..2289c1891b 100644 --- a/baseboard/zork/baseboard.h +++ b/baseboard/zork/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -8,22 +8,21 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H -#if (defined(VARIANT_ZORK_TREMBYLE) \ - + defined(VARIANT_ZORK_DALBOZ)) != 1 +#if (defined(VARIANT_ZORK_TREMBYLE) + defined(VARIANT_ZORK_DALBOZ)) != 1 #error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ #endif /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) /* * Enable 1 slot of secure temporary storage to support @@ -92,7 +91,7 @@ #define CONFIG_CHIPSET_CAN_THROTTLE #define CONFIG_CHIPSET_RESET_HOOK -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_POWER_COMMON @@ -102,9 +101,9 @@ #define CONFIG_THROTTLE_AP #ifdef VARIANT_ZORK_TREMBYLE - #define CONFIG_FANS FAN_CH_COUNT - #undef CONFIG_FAN_INIT_SPEED - #define CONFIG_FAN_INIT_SPEED 50 +#define CONFIG_FANS FAN_CH_COUNT +#undef CONFIG_FAN_INIT_SPEED +#define CONFIG_FAN_INIT_SPEED 50 #endif #define CONFIG_LED_COMMON @@ -122,10 +121,9 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX - #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI /* * USB ID @@ -141,14 +139,14 @@ #define CONFIG_USB_PD_TCPMV2 #ifndef CONFIG_USB_PD_TCPMV2 - #define CONFIG_USB_PD_TCPMV1 +#define CONFIG_USB_PD_TCPMV1 #else - #define CONFIG_USB_PD_DECODE_SOP - #define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_DRP_ACC_TRYSRC - /* Enable TCPMv2 Fast Role Swap */ - /* Turn off until FRSwap is working */ - #undef CONFIG_USB_PD_FRS_TCPC +/* Enable TCPMv2 Fast Role Swap */ +/* Turn off until FRSwap is working */ +#undef CONFIG_USB_PD_FRS_TCPC #endif #define CONFIG_HOSTCMD_PD_CONTROL @@ -165,7 +163,7 @@ * Use a custom HPD function that supports HPD on IO expander. * TODO(b/165622386) remove this when HPD is on EC GPIO. */ -# define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM +#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM #endif #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE @@ -187,19 +185,19 @@ #define CONFIG_USB_MUX_AMD_FP5 #if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_USB_PD_PORT_MAX_COUNT 2 - #define CONFIG_USBC_PPC_NX20P3483 - #define CONFIG_USBC_RETIMER_PS8802 - #define CONFIG_USBC_RETIMER_PS8818 - #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT - #define CONFIG_USB_MUX_RUNTIME_CONFIG - /* USB-A config */ - #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L - #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L - /* PS8818 RX Input Termination - default value */ - #define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USBC_PPC_NX20P3483 +#define CONFIG_USBC_RETIMER_PS8802 +#define CONFIG_USBC_RETIMER_PS8818 +#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT +#define CONFIG_USB_MUX_RUNTIME_CONFIG +/* USB-A config */ +#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L +#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L +/* PS8818 RX Input Termination - default value */ +#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM #elif defined(VARIANT_ZORK_DALBOZ) - #define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT +#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT #endif /* USB-A config */ @@ -209,13 +207,13 @@ #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP #define CONFIG_USB_PORT_POWER_SMART_INVERTED -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ #define ZORK_AC_PROCHOT_CURRENT_MA 3328 @@ -225,7 +223,7 @@ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on * Depthcharge to boot OS. */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 /* Increase length of history buffer for port80 messages. */ #undef CONFIG_PORT80_HISTORY_LEN @@ -235,30 +233,30 @@ #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 -#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_EEPROM I2C_PORT_SENSOR -#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 +#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_EEPROM I2C_PORT_SENSOR +#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 #if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_CHARGER_RUNTIME_CONFIG - #define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 - #define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 +#define CONFIG_CHARGER_RUNTIME_CONFIG +#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 +#define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 +#define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 +#define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 #elif defined(VARIANT_ZORK_DALBOZ) - #define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 +#define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 +#define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 #endif -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_MKBP_EVENT /* Host event is required to wake from sleep */ @@ -310,11 +308,7 @@ enum fan_channel { }; #ifdef VARIANT_ZORK_TREMBYLE -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; #endif enum sensor_id { diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk index e79d60cc91..6cf67a1a39 100644 --- a/baseboard/zork/build.mk +++ b/baseboard/zork/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Copyright 2019 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c index 50a29d3634..4482a5cf40 100644 --- a/baseboard/zork/cbi_ec_fw_config.c +++ b/baseboard/zork/cbi_ec_fw_config.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -28,8 +28,7 @@ uint32_t get_cbi_fw_config(void) */ enum ec_cfg_usb_db_type ec_config_get_usb_db(void) { - return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) - >> EC_CFG_USB_DB_L); + return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) >> EC_CFG_USB_DB_L); } /* @@ -37,8 +36,7 @@ enum ec_cfg_usb_db_type ec_config_get_usb_db(void) */ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void) { - return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) - >> EC_CFG_USB_MB_L); + return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) >> EC_CFG_USB_MB_L); } /* @@ -46,8 +44,8 @@ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void) */ enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void) { - return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) - >> EC_CFG_LID_ACCEL_SENSOR_L); + return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) >> + EC_CFG_LID_ACCEL_SENSOR_L); } /* @@ -55,28 +53,27 @@ enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void) */ enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void) { - return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) - >> EC_CFG_BASE_GYRO_SENSOR_L); + return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) >> + EC_CFG_BASE_GYRO_SENSOR_L); } /* * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0 */ -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void) +enum ec_cfg_pwm_keyboard_backlight_type +ec_config_has_pwm_keyboard_backlight(void) { - return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) - >> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L); + return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) >> + EC_CFG_PWM_KEYBOARD_BACKLIGHT_L); } /* * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0 */ -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void) +enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(void) { - return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) - >> EC_CFG_LID_ANGLE_TABLET_MODE_L); + return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) >> + EC_CFG_LID_ANGLE_TABLET_MODE_L); } /* @@ -84,8 +81,8 @@ enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( */ enum ec_cfg_lte_present_type ec_config_lte_present(void) { - return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) - >> EC_CFG_LTE_PRESENT_L); + return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) >> + EC_CFG_LTE_PRESENT_L); } /* @@ -93,6 +90,6 @@ enum ec_cfg_lte_present_type ec_config_lte_present(void) */ enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void) { - return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) - >> EC_CFG_KEYBOARD_LAYOUT_L); + return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) >> + EC_CFG_KEYBOARD_LAYOUT_L); } diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h index c3ed5b654c..a73e4504bb 100644 --- a/baseboard/zork/cbi_ec_fw_config.h +++ b/baseboard/zork/cbi_ec_fw_config.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -19,11 +19,9 @@ * get_cbi_ec_cfg_usb_db() will return the DB option number. * The option number will be defined in a variant or board level enumeration */ -#define EC_CFG_USB_DB_L 0 -#define EC_CFG_USB_DB_H 3 -#define EC_CFG_USB_DB_MASK \ - GENMASK(EC_CFG_USB_DB_H,\ - EC_CFG_USB_DB_L) +#define EC_CFG_USB_DB_L 0 +#define EC_CFG_USB_DB_H 3 +#define EC_CFG_USB_DB_MASK GENMASK(EC_CFG_USB_DB_H, EC_CFG_USB_DB_L) /* * USB Main Board (4 bits) @@ -31,11 +29,9 @@ * get_cbi_ec_cfg_usb_mb() will return the MB option number. * The option number will be defined in a variant or board level enumeration */ -#define EC_CFG_USB_MB_L 4 -#define EC_CFG_USB_MB_H 7 -#define EC_CFG_USB_MB_MASK \ - GENMASK(EC_CFG_USB_MB_H,\ - EC_CFG_USB_MB_L) +#define EC_CFG_USB_MB_L 4 +#define EC_CFG_USB_MB_H 7 +#define EC_CFG_USB_MB_MASK GENMASK(EC_CFG_USB_MB_H, EC_CFG_USB_MB_L) /* * Lid Accelerometer Sensor (3 bits) @@ -47,22 +43,20 @@ enum ec_cfg_lid_accel_sensor_type { LID_ACCEL_KX022 = 1, LID_ACCEL_LIS2DWL = 2, }; -#define EC_CFG_LID_ACCEL_SENSOR_L 8 -#define EC_CFG_LID_ACCEL_SENSOR_H 10 -#define EC_CFG_LID_ACCEL_SENSOR_MASK \ - GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\ - EC_CFG_LID_ACCEL_SENSOR_L) +#define EC_CFG_LID_ACCEL_SENSOR_L 8 +#define EC_CFG_LID_ACCEL_SENSOR_H 10 +#define EC_CFG_LID_ACCEL_SENSOR_MASK \ + GENMASK(EC_CFG_LID_ACCEL_SENSOR_H, EC_CFG_LID_ACCEL_SENSOR_L) /* * Base Gyro Sensor (3 bits) * * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type */ -#define EC_CFG_BASE_GYRO_SENSOR_L 11 -#define EC_CFG_BASE_GYRO_SENSOR_H 13 -#define EC_CFG_BASE_GYRO_SENSOR_MASK \ - GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\ - EC_CFG_BASE_GYRO_SENSOR_L) +#define EC_CFG_BASE_GYRO_SENSOR_L 11 +#define EC_CFG_BASE_GYRO_SENSOR_H 13 +#define EC_CFG_BASE_GYRO_SENSOR_MASK \ + GENMASK(EC_CFG_BASE_GYRO_SENSOR_H, EC_CFG_BASE_GYRO_SENSOR_L) /* * PWM Keyboard Backlight (1 bit) @@ -73,11 +67,11 @@ enum ec_cfg_pwm_keyboard_backlight_type { PWM_KEYBOARD_BACKLIGHT_NO = 0, PWM_KEYBOARD_BACKLIGHT_YES = 1, }; -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \ - GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\ - EC_CFG_PWM_KEYBOARD_BACKLIGHT_L) +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14 +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14 +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \ + GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H, \ + EC_CFG_PWM_KEYBOARD_BACKLIGHT_L) /* * Lid Angle Tablet Mode (1 bit) @@ -88,11 +82,10 @@ enum ec_cfg_lid_angle_tablet_mode_type { LID_ANGLE_TABLET_MODE_NO = 0, LID_ANGLE_TABLET_MODE_YES = 1, }; -#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15 -#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15 +#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15 +#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15 #define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \ - GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\ - EC_CFG_LID_ANGLE_TABLET_MODE_L) + GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H, EC_CFG_LID_ANGLE_TABLET_MODE_L) /* * LTE Modem Present (1 bit) @@ -103,11 +96,10 @@ enum ec_cfg_lte_present_type { LTE_NONE = 0, LTE_PRESENT = 1, }; -#define EC_CFG_LTE_PRESENT_L 29 -#define EC_CFG_LTE_PRESENT_H 29 +#define EC_CFG_LTE_PRESENT_L 29 +#define EC_CFG_LTE_PRESENT_H 29 #define EC_CFG_LTE_PRESENT_MASK \ - GENMASK(EC_CFG_LTE_PRESENT_H,\ - EC_CFG_LTE_PRESENT_L) + GENMASK(EC_CFG_LTE_PRESENT_H, EC_CFG_LTE_PRESENT_L) /* * Keyboard Layout (2 bit) @@ -118,22 +110,20 @@ enum ec_cfg_keyboard_layout_type { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1, }; -#define EC_CFG_KEYBOARD_LAYOUT_L 30 -#define EC_CFG_KEYBOARD_LAYOUT_H 31 +#define EC_CFG_KEYBOARD_LAYOUT_L 30 +#define EC_CFG_KEYBOARD_LAYOUT_H 31 #define EC_CFG_KEYBOARD_LAYOUT_MASK \ - GENMASK(EC_CFG_KEYBOARD_LAYOUT_H,\ - EC_CFG_KEYBOARD_LAYOUT_L) - + GENMASK(EC_CFG_KEYBOARD_LAYOUT_H, EC_CFG_KEYBOARD_LAYOUT_L) uint32_t get_cbi_fw_config(void); enum ec_cfg_usb_db_type ec_config_get_usb_db(void); enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void); enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void); enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void); -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void); -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void); +enum ec_cfg_pwm_keyboard_backlight_type +ec_config_has_pwm_keyboard_backlight(void); +enum ec_cfg_lid_angle_tablet_mode_type +ec_config_has_lid_angle_tablet_mode(void); enum ec_cfg_lte_present_type ec_config_lte_present(void); enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void); diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c index 1078ec6486..9cc2fdcef3 100644 --- a/baseboard/zork/cbi_ssfc.c +++ b/baseboard/zork/cbi_ssfc.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -38,11 +38,10 @@ enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void) enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void) { return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >> - SSFC_EDP_PHY_ALT_TUNING_OFFSET; + SSFC_EDP_PHY_ALT_TUNING_OFFSET; } enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void) { - return (cached_ssfc & SSFC_C1_MUX_MASK) >> - SSFC_C1_MUX_OFFSET; + return (cached_ssfc & SSFC_C1_MUX_MASK) >> SSFC_C1_MUX_OFFSET; } diff --git a/baseboard/zork/cbi_ssfc.h b/baseboard/zork/cbi_ssfc.h index 1d201594b0..95bf5ba6e4 100644 --- a/baseboard/zork/cbi_ssfc.h +++ b/baseboard/zork/cbi_ssfc.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c index 8dcdfa7635..aeca706eb2 100644 --- a/baseboard/zork/usb_pd_policy.c +++ b/baseboard/zork/usb_pd_policy.c @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -18,8 +18,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c index 10058bb8bc..599f29618b 100644 --- a/baseboard/zork/variant_dalboz.c +++ b/baseboard/zork/variant_dalboz.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -58,7 +58,7 @@ int board_get_temp(int idx, int *temp_k) /* adc power not ready when transition to S5 */ if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_SOFT_OFF)) + CHIPSET_STATE_SOFT_OFF)) return EC_ERROR_NOT_POWERED; channel = ADC_TEMP_SENSOR_SOC; diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c index f9173df05a..9c29e057cc 100644 --- a/baseboard/zork/variant_trembyle.c +++ b/baseboard/zork/variant_trembyle.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -9,10 +9,10 @@ #include "console.h" #include "driver/bc12/pi3usb9201.h" #include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" +#include "driver/ppc/aoz1380_public.h" #include "driver/ppc/nx20p348x.h" #include "driver/retimer/ps8802.h" -#include "driver/retimer/ps8818.h" +#include "driver/retimer/ps8818_public.h" #include "driver/retimer/tusb544.h" #include "driver/tcpm/nct38xx.h" #include "driver/usb_mux/amd_fp5.h" @@ -28,8 +28,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct i2c_port_t i2c_ports[] = { { @@ -160,8 +160,7 @@ __overridable void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -182,7 +181,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -284,7 +282,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -333,18 +330,15 @@ void tcpc_alert_event(enum gpio_signal signal) schedule_deferred_pd_interrupt(port); } - int board_pd_set_frs_enable(int port, int enable) { int rv = EC_SUCCESS; /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -393,8 +387,7 @@ BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT); * PS8802 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8802_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8802_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; @@ -406,11 +399,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2, + PS8802_REG2_USB_SSEQ_LEVEL, + PS8802_USBEQ_LEVEL_UP_MASK, + PS8802_USBEQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -418,11 +410,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE2, + PS8802_REG2_DPEQ_LEVEL, + PS8802_DPEQ_LEVEL_UP_MASK, + PS8802_DPEQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -434,52 +425,46 @@ static int board_ps8802_mux_set(const struct usb_mux *me, * PS8818 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - ZORK_PS8818_RX_INPUT_TERM); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + ZORK_PS8818_RX_INPUT_TERM); if (rv) return rv; } @@ -487,11 +472,10 @@ static int board_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -505,7 +489,7 @@ static int board_ps8818_mux_set(const struct usb_mux *me, return rv; } -const struct usb_mux usbc1_ps8802 = { +struct usb_mux usbc1_ps8802 = { .usb_port = USBC_PORT_C1, .i2c_port = I2C_PORT_TCPC1, .i2c_addr_flags = PS8802_I2C_ADDR_FLAGS, |