diff options
Diffstat (limited to 'baseboard')
181 files changed, 0 insertions, 25168 deletions
diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c deleted file mode 100644 index c89348a562..0000000000 --- a/baseboard/asurada/baseboard.c +++ /dev/null @@ -1,101 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Asurada baseboard-specific configuration */ - -#include "adc.h" -#include "button.h" -#include "charge_manager.h" -#include "charger.h" -#include "charger.h" -#include "charge_state.h" -#include "charge_state_v2.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/accelgyro_bmi_common.h" -#include "driver/accel_lis2dw12.h" -#include "driver/als_tcs3400.h" -#include "driver/bc12/mt6360.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/syv682x.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/temp_sensor/thermistor.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "it5205_sbu.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "motion_sense.h" -#include "power_button.h" -#include "power.h" -#include "regulator.h" -#include "spi.h" -#include "switch.h" -#include "tablet_mode.h" -#include "task.h" -#include "temp_sensor.h" -#include "timer.h" -#include "uart.h" - -#include "gpio_list.h" - -/* Wake-up pins for hibernate */ -enum gpio_signal hibernate_wake_pins[] = { - GPIO_AC_PRESENT, - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, -}; -int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* - * I2C channels (A, B, and C) are using the same timing registers (00h~07h) - * at default. - * In order to set frequency independently for each channels, - * We use timing registers 09h~0Bh, and the supported frequency will be: - * 50KHz, 100KHz, 400KHz, or 1MHz. - * I2C channels (D, E and F) can be set different frequency on different ports. - * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and - * the individual prescale register. - * The frequency of SMBus module is 24MHz on default. - * The allowed range of I2C(D/E/F) frequency is as following setting. - * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1) - * (SMBus Module Freq / 510) <= I2C Freq <= (SMBus Module Freq / 8) - * Channel D has multi-function and can be used as UART interface. - * Channel F is reserved for EC debug. - */ - -/* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - {"bat_chg", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA}, - {"sensor", IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA}, - {"usb0", IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA}, - {"usb1", IT83XX_I2C_CH_E, 400, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY); -} - -const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) -{ - const static struct cc_para_t - cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; - - return &cc_parameter[port]; -} diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h deleted file mode 100644 index f3c0808660..0000000000 --- a/baseboard/asurada/baseboard.h +++ /dev/null @@ -1,196 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Asurada board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* IT81202-bx config */ -/* - * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't - * connect to 1.8v on other versions. - */ -#define CONFIG_IT83XX_VCC_1P8V - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON -#define CONFIG_CHIPSET_MT8192 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE - -/* Chipset */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_CMD_POWERINDEBUG -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LOW_POWER_S0 -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_COMMON -#define CONFIG_PWM -#define CONFIG_VBOOT_HASH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ACTIVE_HIGH - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_BATTERY_SMART - -/* BC12 */ -#define CONFIG_BC12_DETECT_MT6360 -#define CONFIG_BC12_DETECT_PI3USB9201 -#undef CONFIG_BC12_SINGLE_DRIVER -#define CONFIG_USB_CHARGER - -/* Charger */ -#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */ -#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9238C -#define CONFIG_CHARGER_MAINTAIN_VBAT -#define CONFIG_CHARGER_OTG -#define CONFIG_CHARGER_PSYS -#define CONFIG_CHARGER_PSYS_READ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ -#define CONFIG_CMD_CHARGER_ADC_AMON_BMON - -/* Keyboard */ -#define CONFIG_CMD_KEYBOARD -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* I2C */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_POWER IT83XX_I2C_CH_A -#define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E -#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define CONFIG_SMBUS_PEC - -/* LED */ -#define CONFIG_LED_COMMON - -/* PD / USB-C / PPC */ -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_IT83XX_TUNE_CC_PHY -#define CONFIG_USB_MUX_VIRTUAL -#define CONFIG_USBC_PPC -#define CONFIG_USBC_PPC_DEDICATED_INT -#define CONFIG_USBC_PPC_POLARITY -#define CONFIG_USBC_PPC_SYV682C -#define CONFIG_USBC_PPC_VCONN -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_MUX_IT5205 /* C0 */ -#define CONFIG_USB_MUX_PS8743 /* C1 */ -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_DISCHARGE -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_FRS_PPC -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -#define CONFIG_USB_PID 0x5053 -#define CONFIG_USB_POWER_DELIVERY - -/* USB-A */ -#define CONFIG_USB_PORT_POWER_DUMB -#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK -#define USB_PORT_COUNT USBA_PORT_COUNT - -/* UART */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Sensor */ -#ifdef HAS_TASK_MOTIONSENSE -#define CONFIG_CMD_ACCEL_INFO -#define CONFIG_CMD_ACCELS - -#define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#define CONFIG_ACCEL_INTERRUPTS -#endif - -/* SPI / Host Command */ -#define CONFIG_SPI - -/* MKBP */ -#define CONFIG_MKBP_EVENT - -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* Voltage regulator control */ -#define CONFIG_HOSTCMD_REGULATOR - -/* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* And the MKBP events */ -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT)) - -#include "baseboard_common.h" - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "registers.h" -#include "power/mt8192.h" - -void board_reset_pd_mcu(void); -enum board_sub_board board_get_sub_board(void); -void usb_a0_interrupt(enum gpio_signal signal); - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h deleted file mode 100644 index 0245ae42bf..0000000000 --- a/baseboard/asurada/baseboard_common.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Asurada baseboard-specific onfiguration common to ECOS and Zephyr */ - -#ifndef __CROS_EC_BASEBOARD_COMMON_H -#define __CROS_EC_BASEBOARD_COMMON_H - -/* GPIO name remapping */ -#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2 -#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 -#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 -#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" - -enum board_sub_board { - SUB_BOARD_NONE = -1, - SUB_BOARD_TYPEC, - SUB_BOARD_HDMI, - SUB_BOARD_COUNT, -}; - -/** - * board_get_version() - Get the board version - * - * Read the ADC to obtain the board version - * - * @return board version in the range 0 to 14 inclusive - */ -int board_get_version(void); - -void ppc_interrupt(enum gpio_signal signal); -void bc12_interrupt(enum gpio_signal signal); -void x_ec_interrupt(enum gpio_signal signal); - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_COMMON_H */ diff --git a/baseboard/asurada/board_chipset.c b/baseboard/asurada/board_chipset.c deleted file mode 100644 index 4d12fb0334..0000000000 --- a/baseboard/asurada/board_chipset.c +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Asurada baseboard-chipset specific configuration */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" - -/* Called on AP S3 -> S0 transition */ -static void board_chipset_resume(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S3 transition */ -static void board_chipset_suspend(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c deleted file mode 100644 index a4590f3199..0000000000 --- a/baseboard/asurada/board_id.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "timer.h" -#include "util.h" - -/** - * Conversion based on following table: - * - * ID | Rp | Rd | Voltage - * | kOhm | kOhm | mV - * ---+------+------+-------- - * 0 | 51.1 | 2.2 | 136.2 - * 1 | 51.1 | 6.81 | 388.1 - * 2 | 51.1 | 11 | 584.5 - * 3 | 57.6 | 18 | 785.7 - * 4 | 51.1 | 22 | 993.2 - * 5 | 51.1 | 30 | 1220.7 - * 6 | 51.1 | 39.2 | 1432.6 - * 7 | 56 | 56 | 1650.0 - * 8 | 47 | 61.9 | 1875.8 - * 9 | 47 | 80.6 | 2084.5 - * 10 | 56 | 124 | 2273.3 - * 11 | 51.1 | 150 | 2461.5 - * 12 | 47 | 200 | 2672.1 - * 13 | 47 | 330 | 2888.6 - * 14 | 47 | 680 | 3086.7 - */ -const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, -}; - -const int threshold_mv = 100; - -/** - * Convert ADC value to board id using the voltage table above. - * - * @param ch ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1. - * - * @return a non-negative board id, or negative value if error. - */ -static int adc_value_to_numeric_id(enum adc_channel ch) -{ - int mv; - - gpio_set_level(GPIO_EN_EC_ID_ODL, 0); - /* Wait to allow cap charge */ - msleep(10); - - mv = adc_read_channel(ch); - if (mv == ADC_READ_ERROR) - mv = adc_read_channel(ch); - - gpio_set_level(GPIO_EN_EC_ID_ODL, 1); - - if (mv == ADC_READ_ERROR) - return -EC_ERROR_UNKNOWN; - - for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) { - if (IN_RANGE(mv, voltage_map[i] - threshold_mv, - voltage_map[i] + threshold_mv)) - return i; - } - - return -EC_ERROR_UNKNOWN; -} - -static int version = -1; - -/* b/163963220: Cache ADC value before board_hibernate_late() reads it */ -static void board_version_init(void) -{ - version = adc_value_to_numeric_id(ADC_BOARD_ID_0); - if (version < 0) { - ccprints("WARN:BOARD_ID_0"); - ccprints("Assuming board id = 0"); - - version = 0; - } -} -DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1); - -__override int board_get_version(void) -{ - return version; -} diff --git a/baseboard/asurada/build.mk b/baseboard/asurada/build.mk deleted file mode 100644 index ce7b7272bd..0000000000 --- a/baseboard/asurada/build.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-y+=board_chipset.o -baseboard-y+=board_id.o -baseboard-y+=hibernate.o -baseboard-y+=regulator.o -baseboard-y+=usbc_config.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c deleted file mode 100644 index b26bd44adc..0000000000 --- a/baseboard/asurada/hibernate.c +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charger.h" -#include "driver/charger/isl923x_public.h" -#include "gpio.h" -#include "system.h" - -/* Hayato board specific hibernate implementation */ -__override void board_hibernate_late(void) -{ - /* - * Turn off PP5000_A. Required for devices without Z-state. - * Don't care for devices with Z-state. - */ - gpio_set_level(GPIO_EN_PP5000_A, 0); - - /* - * GPIO_EN_SLP_Z not implemented in rev0/1, - * fallback to usual hibernate process. - */ - if (board_get_version() <= 1) { - if (IS_ENABLED(BOARD_ASURADA) || - (IS_ENABLED(CONFIG_ZEPHYR) && - IS_ENABLED(CONFIG_BOARD_ASURADA))) - return; - } - - isl9238c_hibernate(CHARGER_SOLO); - - gpio_set_level(GPIO_EN_SLP_Z, 1); - - /* should not reach here */ - __builtin_unreachable(); -} diff --git a/baseboard/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c deleted file mode 100644 index 9ee59a5cc3..0000000000 --- a/baseboard/asurada/it5205_sbu.c +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IT5205 Type-C SBU OVP handler - */ - -#include "console.h" -#include "hooks.h" -#include "it5205.h" -#include "stdbool.h" -#include "timer.h" -#include "usb_mux.h" - -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -#define OVP_RETRY_DELAY_US_MIN (100 * MSEC) - -static unsigned int ovp_retry_delay_us = OVP_RETRY_DELAY_US_MIN; - -static void reset_retry_delay(void) -{ - CPRINTS("IT5205 SBU OVP cleared"); - ovp_retry_delay_us = OVP_RETRY_DELAY_US_MIN; -} -DECLARE_DEFERRED(reset_retry_delay); - -static void reset_csbu(void) -{ - /* double the retry time up to 1 minute */ - ovp_retry_delay_us = MIN(ovp_retry_delay_us * 2, MINUTE); - /* and reset it if interrupt not triggered in a short period */ - hook_call_deferred(&reset_retry_delay_data, 500 * MSEC); - - /* re-enable sbu interrupt */ - it5205h_enable_csbu_switch(&usb_muxes[0], false); - it5205h_enable_csbu_switch(&usb_muxes[0], true); -} -DECLARE_DEFERRED(reset_csbu); - -static void it5205h_hook_ac_change(void) -{ - int reg; - - /* Check if the board has IT5205H, and read its ovp status */ - if (i2c_read8(I2C_PORT_USB_MUX0, IT5205H_SBU_I2C_ADDR_FLAGS, - IT5205H_REG_ISR, ®)) - return; - - /* - * Re-poll ovp status immediately if AC detached, because ovp will - * likely be recovered. - * - * Always perform the re-poll even when this hook is triggered by - * unrelated events. - */ - if (reg & IT5205H_ISR_CSBU_OVP) - hook_call_deferred(&reset_csbu_data, 0); -} -DECLARE_HOOK(HOOK_AC_CHANGE, it5205h_hook_ac_change, HOOK_PRIO_DEFAULT); - -void it5205h_sbu_interrupt(enum gpio_signal signal) -{ - CPRINTS("IT5205 SBU OVP triggered"); - hook_call_deferred(&reset_csbu_data, ovp_retry_delay_us); - hook_call_deferred(&reset_retry_delay_data, -1); -} diff --git a/baseboard/asurada/it5205_sbu.h b/baseboard/asurada/it5205_sbu.h deleted file mode 100644 index 8dc59520dd..0000000000 --- a/baseboard/asurada/it5205_sbu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IT5205 Type-C SBU OVP handler - */ - -#ifndef __CROS_EC_ASURADA_IT5205_SBU_H -#define __CROS_EC_ASURADA_IT5205_SBU_H - -void it5205h_sbu_interrupt(enum gpio_signal signal); - -#endif /* __CROS_EC_ASURADA_IT5205_SBU_H */ diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c deleted file mode 100644 index 35670bda82..0000000000 --- a/baseboard/asurada/regulator.c +++ /dev/null @@ -1,46 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "bc12/mt6360_public.h" - -/* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); -} - -int board_regulator_enable(uint32_t index, uint8_t enable) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_enable(id, enable); -} - -int board_regulator_is_enabled(uint32_t index, uint8_t *enabled) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_is_enabled(id, enabled); -} - -int board_regulator_set_voltage(uint32_t index, uint32_t min_mv, - uint32_t max_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_set_voltage(id, min_mv, max_mv); -} - -int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_voltage(id, voltage_mv); -} diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c deleted file mode 100644 index f9ba7e5a4d..0000000000 --- a/baseboard/asurada/usb_pd_policy.c +++ /dev/null @@ -1,236 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "adc.h" -#include "atomic.h" -#include "baseboard_common.h" -#include "charge_manager.h" -#include "chipset.h" -#include "timer.h" -#include "usb_dp_alt_mode.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" - -#if CONFIG_USB_PD_3A_PORTS != 1 -#error Asurada reference must have at least one 3.0 A port -#endif - -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) - -int svdm_get_hpd_gpio(int port) -{ - /* HPD is low active, inverse the result */ - return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL); -} - -void svdm_set_hpd_gpio(int port, int en) -{ - /* - * HPD is low active, inverse the en - * TODO: C0&C1 shares the same HPD, implement FCFS policy. - */ - gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en); -} - -/** - * Is the port fine to be muxed its DisplayPort lines? - * - * Only one port can be muxed to DisplayPort at a time. - * - * @param port Port number of TCPC. - * @return 1 is fine; 0 is bad as other port is already muxed; - */ -static int is_dp_muxable(int port) -{ - int i; - - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (i != port) { - if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) - return 0; - } - } - - return 1; -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - int cur_lvl = svdm_get_hpd_gpio(port); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - if (!is_dp_muxable(port)) { - /* TODO(waihong): Info user? */ - CPRINTS("p%d: The other port is already muxed.", port); - return 0; /* nak */ - } - - if (lvl) - gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port); - - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) - /* - * Wake up the AP. IRQ or level high indicates a DP sink is now - * present. - */ - if (IS_ENABLED(CONFIG_MKBP_EVENT)) - pd_notify_dp_alt_mode_entry(port); - - /* Its initial DP status message prior to config */ - if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { - if (lvl) - dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; - return 1; - } - -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - if (irq && !lvl) { - /* - * IRQ can only be generated when the level is high, because - * the IRQ is signaled by a short low pulse from the high level. - */ - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; /* nak */ - } - - if (irq && cur_lvl) { - uint64_t now = get_time().val; - /* wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* generate IRQ_HPD pulse */ - svdm_set_hpd_gpio(port, 0); - /* - * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is - * very short (500us), we can use udelay instead of usleep for - * more stable pulse period. - */ - udelay(HPD_DSTREAM_DEBOUNCE_IRQ); - svdm_set_hpd_gpio(port, 1); - } else { - svdm_set_hpd_gpio(port, lvl); - } - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, lvl); -#endif - - /* ack */ - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - svdm_set_hpd_gpio(port, 0); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, 0); -#endif -} - -int pd_snk_is_vbus_provided(int port) -{ - static int vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT]; - int vbus; - - if ((IS_ENABLED(BOARD_HAYATO) && board_get_version() < 4) || - (IS_ENABLED(BOARD_SPHERION) && board_get_version() < 1)) - return ppc_is_vbus_present(port); - - /* - * (b:181203590#comment20) TODO(yllin): use - * PD_VSINK_DISCONNECT_PD for non-5V case. - */ - vbus = adc_read_channel(board_get_vbus_adc(port)) >= - PD_V_SINK_DISCONNECT_MAX; - -#ifdef CONFIG_USB_CHARGER - /* - * There's no PPC to inform VBUS change for usb_charger, so inform - * the usb_charger now. - */ - if (!!(vbus_prev[port] != vbus)) - usb_charger_vbus_change(port, vbus); - - if (vbus) - atomic_or(&vbus_prev[port], 1); - else - atomic_clear(&vbus_prev[port]); -#endif - return vbus; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* Allow Vconn swap if AP is on. */ - return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c deleted file mode 100644 index e552c97771..0000000000 --- a/baseboard/asurada/usbc_config.c +++ /dev/null @@ -1,431 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Asurada baseboard-specific USB-C configuration */ - -#include "adc.h" -#include "baseboard_common.h" -#include "bc12/pi3usb9201_public.h" -#include "bc12/mt6360_public.h" -#include "button.h" -#include "charger.h" -#include "charge_state_v2.h" -#include "charger/isl923x_public.h" -#include "console.h" -#include "ec_commands.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "lid_switch.h" -#include "task.h" -#include "ppc/syv682x_public.h" -#include "power.h" -#include "power_button.h" -#include "spi.h" -#include "switch.h" -#include "tablet_mode.h" -#include "tcpm/it8xxx2_pd_public.h" -#include "uart.h" -#include "usbc_ppc.h" -#include "usb_charge.h" -#include "usb_mux.h" -#include "usb_mux/ps8743_public.h" -#include "usb_mux/it5205_public.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - -/* Baseboard */ - -static void baseboard_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); - gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE); -} -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1); - -/* Sub-board */ - -enum board_sub_board board_get_sub_board(void) -{ - static enum board_sub_board sub = SUB_BOARD_NONE; - - if (sub != SUB_BOARD_NONE) - return sub; - - /* HDMI board has external pull high. */ - if (gpio_get_level(GPIO_EC_X_GPIO3)) { - sub = SUB_BOARD_HDMI; - /* Only has 1 PPC with HDMI subboard */ - ppc_cnt = 1; - /* EC_X_GPIO1 */ - gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH); - /* X_EC_GPIO2 */ - gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH); - /* EC_X_GPIO3 */ - gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH); - } else { - sub = SUB_BOARD_TYPEC; - /* EC_X_GPIO1 */ - gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW); - /* X_EC_GPIO2 */ - gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL, - GPIO_INT_BOTH | GPIO_PULL_UP); - /* EC_X_GPIO3 */ - gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW); - } - - CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC"); - return sub; -} - -static void sub_board_init(void) -{ - board_get_sub_board(); -} -DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1); - -/* Detect subboard */ -static void board_tcpc_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - /* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */ - gpio_enable_interrupt(GPIO_X_EC_GPIO2); - - /* If this is not a Type-C subboard, disable the task. */ - if (board_get_sub_board() != SUB_BOARD_TYPEC) - task_disable_task(TASK_ID_PD_C1); -} -/* Must be done after I2C and subboard */ -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -/* PPC */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - .frs_en = GPIO_USB_C0_FRS_EN, - }, - { - .i2c_port = I2C_PORT_PPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - .frs_en = GPIO_USB_C1_FRS_EN, - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* BC12 */ -const struct mt6360_config_t mt6360_config = { - .i2c_port = I2C_PORT_POWER, - .i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS, -}; - -const struct pi3usb9201_config_t - pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - /* [0]: unused */ - [1] = { - .i2c_port = I2C_PORT_PPC1, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - } -}; - -struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { .drv = &mt6360_drv }, - { .drv = &pi3usb9201_drv }, -}; - -void bc12_interrupt(enum gpio_signal signal) -{ - if (signal == GPIO_USB_C0_BC12_INT_ODL) - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); - else - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); -} - -static void board_sub_bc12_init(void) -{ - if (board_get_sub_board() == SUB_BOARD_TYPEC) - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L); - else - /* If this is not a Type-C subboard, disable the task. */ - task_disable_task(TASK_ID_USB_CHG_P1); -} -/* Must be done after I2C and subboard */ -DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1); - -void ppc_interrupt(enum gpio_signal signal) -{ - if (signal == GPIO_USB_C0_PPC_INT_ODL) - /* C0: PPC interrupt */ - syv682x_interrupt(0); -} - -__override uint8_t board_get_usb_pd_port_count(void) -{ - if (board_get_sub_board() == SUB_BOARD_TYPEC) - return CONFIG_USB_PD_PORT_MAX_COUNT; - else - return CONFIG_USB_PD_PORT_MAX_COUNT - 1; -} - -/* USB-A */ -const int usb_port_enable[] = { - GPIO_EN_PP5000_USB_A0_VBUS, -}; -BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); - -void usb_a0_interrupt(enum gpio_signal signal) -{ - enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; - - for (int i = 0; i < USB_PORT_COUNT; i++) - usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); -} - -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - int rv = EC_SUCCESS; - int reg = 0; - - rv = ps8743_read(me, PS8743_REG_MODE, ®); - if (rv) - return rv; - - /* Disable FLIP pin, enable I2C control. */ - reg |= PS8743_MODE_FLIP_REG_CONTROL; - /* Disable CE_USB pin, enable I2C control. */ - reg |= PS8743_MODE_USB_REG_CONTROL; - /* Disable CE_DP pin, enable I2C control. */ - reg |= PS8743_MODE_DP_REG_CONTROL; - - /* - * DP specific config - * - * Enable/Disable IN_HPD on the DB. - */ - gpio_set_level(GPIO_USB_C1_DP_IN_HPD, - mux_state & USB_PD_MUX_DP_ENABLED); - - return ps8743_write(me, PS8743_REG_MODE, reg); -} - -const struct usb_mux usbc0_virtual_mux = { - .usb_port = 0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usbc1_virtual_mux = { - .usb_port = 1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .i2c_port = I2C_PORT_USB_MUX0, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .next_mux = &usbc0_virtual_mux, - }, - { - .usb_port = 1, - .i2c_port = I2C_PORT_USB_MUX1, - .i2c_addr_flags = PS8743_I2C_ADDR0_FLAG, - .driver = &ps8743_usb_mux_driver, - .next_mux = &usbc1_virtual_mux, - .board_set = &board_ps8743_mux_set, - }, -}; - -void board_overcurrent_event(int port, int is_overcurrented) -{ - /* TODO: check correct operation for Asurada */ -} - -/* TCPC */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -}; - -uint16_t tcpc_get_alert_status(void) -{ - /* - * C0 & C1: TCPC is embedded in the EC and processes interrupts in the - * chip code (it83xx/intc.c) - */ - return 0; -} - -void board_reset_pd_mcu(void) -{ - /* - * C0 & C1: TCPC is embedded in the EC and processes interrupts in the - * chip code (it83xx/intc.c) - */ -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* - * We ignore the cc_pin and PPC vconn because polarity and PPC vconn - * should already be set correctly in the PPC driver via the pd - * state machine. - */ -} - -int board_set_active_charge_port(int port) -{ - int i; - int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() == - SUB_BOARD_TYPEC); - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - if (port == CHARGE_PORT_NONE) { - CPRINTS("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTS("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTS("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTS("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/** - * Handle PS185 HPD changing state. - */ -int debounced_hpd; - -static void ps185_hdmi_hpd_deferred(void) -{ - const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD); - - /* HPD status not changed, probably a glitch, just return. */ - if (debounced_hpd == new_hpd) - return; - - debounced_hpd = new_hpd; - - gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd); - CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug"); -} -DECLARE_DEFERRED(ps185_hdmi_hpd_deferred); - -#define PS185_HPD_DEBOUCE 250 - -static void hdmi_hpd_interrupt(enum gpio_signal signal) -{ - hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE); -} - -/* HDMI/TYPE-C function shared subboard interrupt */ -void x_ec_interrupt(enum gpio_signal signal) -{ - int sub = board_get_sub_board(); - - if (sub == SUB_BOARD_TYPEC) - /* C1: PPC interrupt */ - syv682x_interrupt(1); - else if (sub == SUB_BOARD_HDMI) - hdmi_hpd_interrupt(signal); - else - CPRINTS("Undetected subboard interrupt."); -} - -int ppc_get_alert_status(int port) -{ - if (port == 0) - return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; - if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC) - return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; - - return 0; -} - -#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -enum adc_channel board_get_vbus_adc(int port) -{ - if (port == 0) - return ADC_VBUS_C0; - if (port == 1) - return ADC_VBUS_C1; - CPRINTSUSB("Unknown vbus adc port id: %d", port); - return ADC_VBUS_C0; -} -#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */ diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c deleted file mode 100644 index 2e60b565f8..0000000000 --- a/baseboard/brask/baseboard.c +++ /dev/null @@ -1,14 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "compile_time_macros.h" - -#include "gpio_signal.h" - -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h deleted file mode 100644 index 4b9d8f386a..0000000000 --- a/baseboard/brask/baseboard.h +++ /dev/null @@ -1,213 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Brask baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted HC - */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) - -/* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -/* - * This defines which pads (GPIO10/11 or GPIO64/65) are connected to - * the "UART1" (NPCX_UART_PORT0) controller when used for - * CONSOLE_UART. - */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ - -/* CrOS Board Info */ -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CRC8 - -/* EC Defines */ -#define CONFIG_LTO -#define CONFIG_FPU - -/* Verified boot configs */ -#define CONFIG_VBOOT_EFS2 -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -/* Work around double CR50 reset by waiting in initial power on. */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Host communication */ -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST - -/* LED */ -#define CONFIG_LED_COMMON - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER - -/* USBC BC1.2 */ -#define CONFIG_USB_CHARGER -#define CONFIG_BC12_DETECT_PI3USB9201 - -/* Support Barrel Jack */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT -#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 -/* - * TODO(b/197475210): Don't allow the system to boot to S0 when - * the power is lower than CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON - * since there is no battery. - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 30000 - -/* Chipset config */ -#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE - -/* - * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM - * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers - * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent - * EC from system shutdown. - */ -/* #define CONFIG_BOARD_HAS_RTC_RESET */ - -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET - -/* Buttons */ -#define CONFIG_DEDICATED_RECOVERY_BUTTON -#define CONFIG_DEDICATED_RECOVERY_BUTTON_2 -#define CONFIG_EMULATED_SYSRQ -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_IGNORE_LID -#define CONFIG_POWER_BUTTON_INIT_IDLE -#define CONFIG_POWER_BUTTON_X86 - -/* Matrix Keyboard Protocol */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_INPUT_DEVICES -#define CONFIG_MKBP_USE_HOST_EVENT - -/* Thermal features */ -#define CONFIG_DPTF -#define CONFIG_THROTTLE_AP - -#define CONFIG_PWM - -/* Enable I2C Support */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER - -/* UART COMMAND */ -#define CONFIG_CMD_CHARGEN - -/* USB Type C and USB PD defines */ -/* Enable the new USB-C PD stack */ -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_REV30 - -#define CONFIG_CMD_HCDEBUG -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_CMD_TCPC_DUMP - -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_ALT_MODE_UFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPM_NCT38XX - -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ -#define CONFIG_CMD_USB_PD_PE - -/* - * The PS8815 TCPC was found to require a 50ms delay to consistently work - * with non-PD chargers. Override the default low-power mode exit delay. - */ -#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) - -/* Enable USB3.2 DRD */ -#define CONFIG_USB_PD_USB32_DRD - -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC - -#define CONFIG_USBC_PPC -/* Note - SN5S330 support automatically adds - * CONFIG_USBC_PPC_POLARITY - * CONFIG_USBC_PPC_SBU - * CONFIG_USBC_PPC_VCONN - */ -#define CONFIG_USBC_PPC_DEDICATED_INT - -#define CONFIG_USBC_SS_MUX -#define CONFIG_USB_MUX_VIRTUAL - -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Enabling SOP* communication */ -#define CONFIG_CMD_USB_PD_CABLE -#define CONFIG_USB_PD_DECODE_SOP - -/* - * USB ID - * This is allocated specifically for Brask - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x5058 -/* Device version of product. */ -#define CONFIG_USB_BCD_DEV 0x0000 - -/* Remove predefined features */ -#undef CONFIG_HIBERNATE -#undef CONFIG_KEYBOARD_BOOT_KEYS -#undef CONFIG_KEYBOARD_RUNTIME_KEYS -#undef CONFIG_LID_SWITCH -#undef CONFIG_KEYBOARD_VIVALDI - -#ifndef __ASSEMBLER__ - -#include <stdbool.h> -#include <stdint.h> - -#include "common.h" -#include "baseboard_usbc_config.h" -#include "extpower.h" - -/* - * Configure run-time data structures and operation based on CBI data. This - * typically includes customization for changes in the BOARD_VERSION and - * FW_CONFIG fields in CBI. This routine is called from the baseboard after - * the CBI data has been initialized. - */ -__override_proto void board_cbi_init(void); - -/* - * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the - * FW_CONFIG to the board specific defaults. - */ -__override_proto void board_init_fw_config(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h deleted file mode 100644 index 1b3d9e5d3f..0000000000 --- a/baseboard/brask/baseboard_usbc_config.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* brask family-specific USB-C configuration */ - -#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H -#define __CROS_EC_BASEBOARD_USBC_CONFIG_H - -#include "gpio_signal.h" - -/* Common definition for the USB PD interrupt handlers. */ -void bc12_interrupt(enum gpio_signal signal); -void ppc_interrupt(enum gpio_signal signal); -void retimer_interrupt(enum gpio_signal signal); -void tcpc_alert_event(enum gpio_signal signal); - -#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */ diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk deleted file mode 100644 index 5ba6b135f9..0000000000 --- a/baseboard/brask/build.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Brask baseboard specific files build -# - -baseboard-y= -baseboard-y+=baseboard.o -baseboard-y+=usb_pd_policy.o diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c deleted file mode 100644 index 33de5ca5eb..0000000000 --- a/baseboard/brask/usb_pd_policy.c +++ /dev/null @@ -1,204 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Brask boards */ - -#include <stddef.h> -#include <stdint.h> - -#include "charge_manager.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "usbc_ppc.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd.h" -#include "usb_pd_tbt.h" -#include "usb_pd_tcpm.h" -#include "usb_pd_vdo.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap after the PP5000_Z1 rail is enabled */ - return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -/* Responses specifically for the enablement of TBT mode in the role of UFP */ - -#define OPOS_TBT 1 - -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); - -/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); - -static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) -{ - /* TODO(b/154962766): Get an XID */ - payload[VDO_I(CSTAT)] = VDO_CSTAT(0); - payload[VDO_I(PRODUCT)] = vdo_product; - - if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { - /* PD Revision 3.0 */ - payload[VDO_I(IDH)] = vdo_idh_rev30; - payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1; - /* TODO(b/181620145): Customize for brya */ - payload[VDO_I(PTYPE_UFP2_VDO)] = 0; - payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp; - return VDO_I(PTYPE_DFP_VDO) + 1; - } - - /* PD Revision 2.0 */ - payload[VDO_I(IDH)] = vdo_idh; - return VDO_I(PRODUCT) + 1; -} - -static int svdm_tbt_compat_response_svids(int port, uint32_t *payload) -{ - payload[1] = VDO_SVID(USB_VID_INTEL, 0); - return 2; -} - -static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) -{ - if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) { - memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes)); - return ARRAY_SIZE(vdo_tbt_modes) + 1; - } else { - return 0; /* NAK */ - } -} - -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) -{ - mux_state_t mux_state = 0; - - /* Do not enter mode while CPU is off. */ - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) - return 0; /* NAK */ - - if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) - return 0; /* NAK */ - - mux_state = usb_mux_get(port); - /* - * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence - * UFP (responder) should be in USB mode or safe mode before sending - * Enter Mode Command response. - */ - if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { - pd_ufp_set_enter_mode(port, payload); - set_tbt_compat_mode_ready(port); - CPRINTS("UFP Enter TBT mode"); - return 1; /* ACK */ - } - - CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state); - return 0; -} - -const struct svdm_response svdm_rsp = { - .identity = &svdm_tbt_compat_response_identity, - .svids = &svdm_tbt_compat_response_svids, - .modes = &svdm_tbt_compat_response_modes, - .enter_mode = &svdm_tbt_compat_response_enter_mode, - .amode = NULL, - .exit_mode = NULL, -}; diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c deleted file mode 100644 index 976831812f..0000000000 --- a/baseboard/brya/baseboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "compile_time_macros.h" - -#include "gpio_signal.h" - -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_ACOK_OD, - GPIO_GSC_EC_PWR_BTN_ODL, - GPIO_LID_OPEN, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h deleted file mode 100644 index 757b504d16..0000000000 --- a/baseboard/brya/baseboard.h +++ /dev/null @@ -1,259 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Brya baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) -#undef CONFIG_HOSTCMD_DEBUG_MODE -#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF - -/* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -/* - * This defines which pads (GPIO10/11 or GPIO64/65) are connected to - * the "UART1" (NPCX_UART_PORT0) controller when used for - * CONSOLE_UART. - */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ - -/* EC Defines */ -#define CONFIG_LTO -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CRC8 -#define CONFIG_DPTF -#define CONFIG_FPU - -/* Verified boot configs */ -#define CONFIG_VBOOT_EFS2 -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -#define CONFIG_HIBERNATE_PSL - -/* Work around double CR50 reset by waiting in initial power on. */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Host communication */ -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 - -/* - * TODO(b/179648721): implement sensors - */ -#define CONFIG_TABLET_MODE -#define CONFIG_TABLET_MODE_SWITCH -#define CONFIG_GMR_TABLET_MODE - -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_HOST_EVENT -#define CONFIG_MKBP_INPUT_DEVICES - -/* LED */ -#define CONFIG_LED_COMMON - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 - -#define CONFIG_CMD_CHARGER_DUMP - -#define CONFIG_USB_CHARGER -#define CONFIG_BC12_DETECT_PI3USB9201 - -/* - * Don't allow the system to boot to S0 when the battery is low and unable to - * communicate on locked systems (which haven't PD negotiated) - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 - -/* Common battery defines */ -#define CONFIG_BATTERY_SMART -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_CUSTOM -#define CONFIG_BATTERY_HW_PRESENT_CUSTOM -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_CMD_BATT_MFG_ACCESS -/* - * Enable support for battery hostcmd, supporting longer strings. - * support for EC_CMD_BATTERY_GET_STATIC version 1. - */ -#define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 -#define CONFIG_HOSTCMD_BATTERY_V2 - -/* Chipset config */ -#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 - -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_LOW_POWER_IDLE - -#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST - -/* - * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM - * disabled coreboot, S5 exit is taking more than 4 seconds, then EC triggers - * system shutdown. This WA deselects CONFIG_BOARD_HAS_RTC_RESET to prevent - * EC from system shutdown. - */ -/* #define CONFIG_BOARD_HAS_RTC_RESET */ - -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET - -/* Buttons / Switches */ -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_SWITCH - -/* Common Keyboard Defines */ -#define CONFIG_CMD_KEYBOARD - -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_KEYPAD -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#ifdef CONFIG_KEYBOARD_VIVALDI -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#else -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 -#endif - -/* Thermal features */ -#define CONFIG_THROTTLE_AP -#define CONFIG_CHIPSET_CAN_THROTTLE - -#define CONFIG_PWM - -/* Enable I2C Support */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER - -/* EDP back-light control defines */ -#define CONFIG_BACKLIGHT_LID - -/* UART COMMAND */ -#define CONFIG_CMD_CHARGEN - -/* USB Type C and USB PD defines */ -/* Enable the new USB-C PD stack */ -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_REV30 - -#define CONFIG_CMD_HCDEBUG -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_CMD_TCPC_DUMP - -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_ALT_MODE_UFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPM_NCT38XX - -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ -#define CONFIG_CMD_USB_PD_PE - -/* - * The PS8815 TCPC was found to require a 50ms delay to consistently work - * with non-PD chargers. Override the default low-power mode exit delay. - */ -#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) - -/* Enable USB3.2 DRD */ -#define CONFIG_USB_PD_USB32_DRD - -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC - -#define CONFIG_USBC_PPC -/* Note - SN5S330 support automatically adds - * CONFIG_USBC_PPC_POLARITY - * CONFIG_USBC_PPC_SBU - * CONFIG_USBC_PPC_VCONN - */ -#define CONFIG_USBC_PPC_DEDICATED_INT - -#define CONFIG_USBC_SS_MUX -#define CONFIG_USB_MUX_VIRTUAL - -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Enabling SOP* communication */ -#define CONFIG_CMD_USB_PD_CABLE -#define CONFIG_USB_PD_DECODE_SOP - -/* - * USB ID - * This is allocated specifically for Brya - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x504F -/* Device version of product. */ -#define CONFIG_USB_BCD_DEV 0x0000 - -#ifndef __ASSEMBLER__ - -#include <stdbool.h> -#include <stdint.h> - -#include "common.h" -#include "baseboard_usbc_config.h" -#include "extpower.h" - -/** - * Configure run-time data structures and operation based on CBI data. This - * typically includes customization for changes in the BOARD_VERSION and - * FW_CONFIG fields in CBI. This routine is called from the baseboard after - * the CBI data has been initialized. - */ -__override_proto void board_cbi_init(void); - -/** - * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the - * FW_CONFIG to the board specific defaults. - */ -__override_proto void board_init_fw_config(void); - -/* - * Check battery disconnect state. - * This function will return if battery is initialized or not. - * @return true - initialized. false - not. - */ -__override_proto bool board_battery_is_initialized(void); - -/* - * Return the board revision number. - */ -uint8_t get_board_id(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/brya/baseboard_usbc_config.h b/baseboard/brya/baseboard_usbc_config.h deleted file mode 100644 index f8b9fab35c..0000000000 --- a/baseboard/brya/baseboard_usbc_config.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* brya family-specific USB-C configuration */ - -#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H -#define __CROS_EC_BASEBOARD_USBC_CONFIG_H - -#include "gpio_signal.h" - -/* Common definition for the USB PD interrupt handlers. */ -void bc12_interrupt(enum gpio_signal signal); -void ppc_interrupt(enum gpio_signal signal); -void retimer_interrupt(enum gpio_signal signal); -void tcpc_alert_event(enum gpio_signal signal); - -#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */ diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c deleted file mode 100644 index 94c9926820..0000000000 --- a/baseboard/brya/battery_presence.c +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Common battery presence checking for Brya family. - * Each board should implement board_battery_info[] to define the specific - * battery packs supported. - */ -#include <stdbool.h> - -#include "battery.h" -#include "battery_smart.h" -#include "common.h" - -static enum battery_present batt_pres_prev = BP_NOT_SURE; - -__overridable bool board_battery_is_initialized(void) -{ - int batt_status; - - return battery_status(&batt_status) != EC_SUCCESS ? false : - !!(batt_status & STATUS_INITIALIZED); -} - -/* - * Physical detection of battery. - */ -static enum battery_present battery_check_present_status(void) -{ - enum battery_present batt_pres; - - if (battery_is_cut_off()) - return BP_NO; - - /* Get the physical hardware status */ - batt_pres = battery_hw_present(); - - /* - * If the battery is not physically connected, then no need to perform - * any more checks. - */ - if (batt_pres == BP_NO) - return BP_NO; - - /* - * If the battery is present now and was present last time we checked, - * return early. - */ - if ((batt_pres == BP_YES) && (batt_pres == batt_pres_prev)) - return BP_YES; - - /* - * Check battery initialization. If the battery is not initialized, - * then return BP_NOT_SURE. Battery could be in ship - * mode and might require pre-charge current to wake it up. BP_NO is not - * returned here because charger state machine will not provide - * pre-charge current assuming that battery is not present. - */ - if (!board_battery_is_initialized()) - return BP_NOT_SURE; - - return BP_YES; -} - -enum battery_present battery_is_present(void) -{ - batt_pres_prev = battery_check_present_status(); - return batt_pres_prev; -} diff --git a/baseboard/brya/build.mk b/baseboard/brya/build.mk deleted file mode 100644 index ca983f26ac..0000000000 --- a/baseboard/brya/build.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Brya baseboard specific files build -# - -baseboard-y= -baseboard-y+=baseboard.o -baseboard-y+=battery_presence.o -baseboard-y+=cbi.o -baseboard-y+=usb_pd_policy.o diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c deleted file mode 100644 index 6d9e2b93fa..0000000000 --- a/baseboard/brya/cbi.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <stdint.h> - -#include "console.h" -#include "common.h" -#include "cros_board_info.h" -#include "hooks.h" - -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) - -static uint8_t board_id; - -uint8_t get_board_id(void) -{ - return board_id; -} - -__overridable void board_cbi_init(void) -{ -} - -__overridable void board_init_fw_config(void) -{ -} - -/* - * Read CBI from I2C EEPROM and initialize variables for board variants. - */ -static void cbi_init(void) -{ - uint32_t cbi_val; - - /* Board ID */ - if (cbi_get_board_version(&cbi_val) != EC_SUCCESS || - cbi_val > UINT8_MAX) - CPRINTS("CBI: Read Board ID failed"); - else - board_id = cbi_val; - - CPRINTS("Board ID: %d", board_id); - - board_init_fw_config(); - - /* Allow the board project to make runtime changes based on CBI data */ - board_cbi_init(); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST); diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c deleted file mode 100644 index 04be67147d..0000000000 --- a/baseboard/brya/charger_bq25720.c +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" - -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "charger.h" -#include "compile_time_macros.h" -#include "console.h" -#include "driver/charger/bq25710.h" -#include "usbc_ppc.h" -#include "usb_pd.h" -#include "util.h" - - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/* Charger Chip Configuration */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, - .drv = &bq25710_drv, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = board_is_usb_pd_port_present(port); - int i; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c deleted file mode 100644 index df291bd9c9..0000000000 --- a/baseboard/brya/usb_pd_policy.c +++ /dev/null @@ -1,204 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Brya boards */ - -#include <stddef.h> -#include <stdint.h> - -#include "charge_manager.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "usbc_ppc.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd.h" -#include "usb_pd_tbt.h" -#include "usb_pd_tcpm.h" -#include "usb_pd_vdo.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap after the PP5000_Z1 rail is enabled */ - return gpio_get_level(GPIO_SEQ_EC_DSW_PWROK); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -/* Responses specifically for the enablement of TBT mode in the role of UFP */ - -#define OPOS_TBT 1 - -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); - -/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); - -static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) -{ - /* TODO(b/154962766): Get an XID */ - payload[VDO_I(CSTAT)] = VDO_CSTAT(0); - payload[VDO_I(PRODUCT)] = vdo_product; - - if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { - /* PD Revision 3.0 */ - payload[VDO_I(IDH)] = vdo_idh_rev30; - payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1; - /* TODO(b/181620145): Customize for brya */ - payload[VDO_I(PTYPE_UFP2_VDO)] = 0; - payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp; - return VDO_I(PTYPE_DFP_VDO) + 1; - } - - /* PD Revision 2.0 */ - payload[VDO_I(IDH)] = vdo_idh; - return VDO_I(PRODUCT) + 1; -} - -static int svdm_tbt_compat_response_svids(int port, uint32_t *payload) -{ - payload[1] = VDO_SVID(USB_VID_INTEL, 0); - return 2; -} - -static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) -{ - if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) { - memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes)); - return ARRAY_SIZE(vdo_tbt_modes) + 1; - } else { - return 0; /* NAK */ - } -} - -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) -{ - mux_state_t mux_state = 0; - - /* Do not enter mode while CPU is off. */ - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) - return 0; /* NAK */ - - if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) - return 0; /* NAK */ - - mux_state = usb_mux_get(port); - /* - * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence - * UFP (responder) should be in USB mode or safe mode before sending - * Enter Mode Command response. - */ - if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { - pd_ufp_set_enter_mode(port, payload); - set_tbt_compat_mode_ready(port); - CPRINTS("UFP Enter TBT mode"); - return 1; /* ACK */ - } - - CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state); - return 0; -} - -const struct svdm_response svdm_rsp = { - .identity = &svdm_tbt_compat_response_identity, - .svids = &svdm_tbt_compat_response_svids, - .modes = &svdm_tbt_compat_response_modes, - .enter_mode = &svdm_tbt_compat_response_enter_mode, - .amode = NULL, - .exit_mode = NULL, -}; diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c deleted file mode 100644 index daf5e218d2..0000000000 --- a/baseboard/cherry/baseboard.c +++ /dev/null @@ -1,597 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Cherry baseboard-specific configuration */ - -#include "adc.h" -#include "button.h" -#include "charge_manager.h" -#include "charger.h" -#include "charge_state.h" -#include "charge_state_v2.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/accelgyro_icm42607.h" -#include "driver/bc12/mt6360.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/rt1718s.h" -#include "driver/ppc/syv682x.h" -#include "driver/retimer/ps8802.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/tcpm/rt1718s.h" -#include "driver/temp_sensor/thermistor.h" -#include "driver/usb_mux/anx3443.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "power_button.h" -#include "power.h" -#include "pwm_chip.h" -#include "pwm.h" -#include "regulator.h" -#include "spi.h" -#include "switch.h" -#include "tablet_mode.h" -#include "task.h" -#include "temp_sensor.h" -#include "timer.h" -#include "uart.h" -#include "usb_charge.h" -#include "usbc_ppc.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" - -static void bc12_interrupt(enum gpio_signal signal); -static void ppc_interrupt(enum gpio_signal signal); -static void usb_a0_interrupt(enum gpio_signal signal); - -#include "gpio_list.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -/* Wake-up pins for hibernate */ -enum gpio_signal hibernate_wake_pins[] = { - GPIO_AC_PRESENT, - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, -}; -int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - -/* Override default setting, called after charger_chips_init */ -static void baseboard_charger_init(void) -{ - /* b/198707662#comment9 */ - int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP) - << ISL9238_INPUT_VOLTAGE_REF_SHIFT; - - i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS, - ISL9238_REG_INPUT_VOLTAGE, reg); -} -DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2); - -__override void board_hibernate_late(void) -{ - /* - * Turn off PP5000_A. Required for devices without Z-state. - * Don't care for devices with Z-state. - */ - gpio_set_level(GPIO_EN_PP5000_A, 0); - isl9238c_hibernate(CHARGER_SOLO); - gpio_set_level(GPIO_EN_SLP_Z, 1); - - /* should not reach here */ - __builtin_unreachable(); -} - -static void board_tcpc_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_INT_ODL); -} -/* Must be done after I2C */ -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -void rt1718s_tcpc_interrupt(enum gpio_signal signal) -{ - schedule_deferred_pd_interrupt(1); -} - -/* ADC channels. Must be in the exactly same order as in enum adc_channel. */ -const struct adc_t adc_channels[] = { - /* Convert to mV (3000mV/1024). */ - {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0}, - {"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1}, - {"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2}, - /* AMON/BMON gain = 17.97 */ - {"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH3}, - {"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6}, - {"TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7}, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER, - }, -}; - -/* PPC */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - .frs_en = GPIO_USB_C0_FRS_EN, - }, - { - .i2c_port = I2C_PORT_PPC1, - .i2c_addr_flags = RT1718S_I2C_ADDR_FLAGS, - .drv = &rt1718s_ppc_drv, - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* BC12 */ -const struct mt6360_config_t mt6360_config = { - .i2c_port = 0, - .i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS, -}; - -__maybe_unused const struct pi3usb9201_config_t - pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [0] = { - .i2c_port = I2C_PORT_USB0, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - } - /* [1]: unused */ -}; - -struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = { -#ifdef CONFIG_BC12_DETECT_PI3USB9201 - { .drv = &pi3usb9201_drv }, -#elif defined(CONFIG_BC12_DETECT_MT6360) - { .drv = &mt6360_drv }, -#else -#error must pick one of PI3USB9201 or MT6360 for port 0 -#endif - { .drv = &rt1718s_bc12_drv }, -}; - -static void bc12_interrupt(enum gpio_signal signal) -{ - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); -} - -static void ppc_interrupt(enum gpio_signal signal) -{ - syv682x_interrupt(0); -} - -/* PWM */ - -/* - * PWM channels. Must be in the exactly same order as in enum pwm_channel. - * There total three 16 bits clock prescaler registers for all pwm channels, - * so use the same frequency and prescaler register setting is required if - * number of pwm channel greater than three. - */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_LED1] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4, - }, - [PWM_CH_LED2] = { - .channel = 1, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4, - }, - [PWM_CH_LED3] = { - .channel = 2, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4, - }, - [PWM_CH_KBLIGHT] = { - .channel = 3, - .flags = 0, - .freq_hz = 10000, /* SYV226 supports 10~100kHz */ - .pcfsr_sel = PWM_PRESCALER_C6, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -/* Called on AP S3 -> S0 transition */ -static void board_chipset_resume(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S3 transition */ -static void board_chipset_suspend(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); - -/* USB-A */ -const int usb_port_enable[] = { - GPIO_EN_PP5000_USB_A0_VBUS_X, -}; -BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); - -__maybe_unused void usb_a0_interrupt(enum gpio_signal signal) -{ - enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; - - for (int i = 0; i < USB_PORT_COUNT; i++) - usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); -} - -/* USB Mux */ - -const struct usb_mux usbc0_virtual_mux = { - .usb_port = 0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usbc1_virtual_mux = { - .usb_port = 1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -static int board_ps8802_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - /* Make sure the PS8802 is awake */ - RETURN_ERROR(ps8802_i2c_wake(me)); - - /* USB specific config */ - if (mux_state & USB_PD_MUX_USB_ENABLED) { - /* Boost the USB gain */ - RETURN_ERROR(ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_19DB)); - } - - /* DP specific config */ - if (mux_state & USB_PD_MUX_DP_ENABLED) { - /* Boost the DP gain */ - RETURN_ERROR(ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_19DB)); - } - - return EC_SUCCESS; -} - -static int board_anx3443_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - gpio_set_level(GPIO_USB_C1_DP_IN_HPD, - mux_state & USB_PD_MUX_DP_ENABLED); - return EC_SUCCESS; -} - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .i2c_port = I2C_PORT_USB_MUX0, - .i2c_addr_flags = PS8802_I2C_ADDR_FLAGS, - .driver = &ps8802_usb_mux_driver, - .next_mux = &usbc0_virtual_mux, - .board_set = &board_ps8802_mux_set, - }, - { - .usb_port = 1, - .i2c_port = I2C_PORT_USB_MUX1, - .i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS, - .driver = &anx3443_usb_mux_driver, - .next_mux = &usbc1_virtual_mux, - .board_set = &board_anx3443_mux_set, - }, -}; - -/* - * I2C channels (A, B, and C) are using the same timing registers (00h~07h) - * at default. - * In order to set frequency independently for each channels, - * We use timing registers 09h~0Bh, and the supported frequency will be: - * 50KHz, 100KHz, 400KHz, or 1MHz. - * I2C channels (D, E and F) can be set different frequency on different ports. - * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and - * the individual prescale register. - * The frequency of SMBus module is 24MHz on default. - * The allowed range of I2C(D/E/F) frequency is as following setting. - * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1) - * (SMBus Module Freq / 510) <= I2C Freq <= (SMBus Module Freq / 8) - * Channel D has multi-function and can be used as UART interface. - * Channel F is reserved for EC debug. - */ - -/* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - {"bat_chg", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA}, - {"sensor", IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA}, - {"usb0", IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA}, - {"usb1", IT83XX_I2C_CH_E, 1000, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY); -} - -/* TCPC */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB1, - .addr_flags = RT1718S_I2C_ADDR_FLAGS, - }, - .drv = &rt1718s_tcpm_drv, - }, -}; - -__override int board_rt1718s_init(int port) -{ - /* set GPIO 1~3 as push pull, as output, output low. */ - rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW); - rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW); - rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW); - - /* gpio 1/2 output high when receiving frx signal */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL, - RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, - RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); - - /* Turn on SBU switch */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | - RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | - RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, - 0xFF)); - /* Trigger GPIO 1/2 change when FRS signal received */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2)); - /* Set FRS signal detect time to 46.875us */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1, - RT1718S_FRS_CTRL1_FRSWAPRX_MASK, - 0xFF)); - - return EC_SUCCESS; -} - -const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) -{ - const static struct cc_para_t cc_parameter = { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }; - - if (port == USBPD_PORT_A) - return &cc_parameter; - return NULL; -} - -uint16_t tcpc_get_alert_status(void) -{ - /* - * C0 TCPC is embedded in the EC and processes interrupts in the - * chip code (it83xx/intc.c) - */ - if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) - return PD_STATUS_TCPC_ALERT_1; - return 0; -} - -void board_reset_pd_mcu(void) -{ - /* - * C0: The internal TCPC on ITE EC does not have a reset signal, - * but it will get reset when the EC gets reset. - */ - /* C1: Add code if TCPC chips need a reset */ -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* - * We ignore the cc_pin and PPC vconn because polarity and PPC vconn - * should already be set correctly in the PPC driver via the pd - * state machine. - */ -} - -int board_set_active_charge_port(int port) -{ - int i; - bool is_valid_port = (port == 0 || port == 1); - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - if (port == CHARGE_PORT_NONE) { - CPRINTS("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("Disabling C%d as sink failed.", i); - } - rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, 1); - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTS("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTS("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTS("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - rt1718s_gpio_set_level(1, GPIO_EN_USB_C1_VBUS_L, !(port == 1)); - - return EC_SUCCESS; -} - -int ppc_get_alert_status(int port) -{ - if (port == 0) - return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; - - /* TODO: add rt1718s */ - return 0; -} -/* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); -} - -int board_regulator_enable(uint32_t index, uint8_t enable) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_enable(id, enable); -} - -int board_regulator_is_enabled(uint32_t index, uint8_t *enabled) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_is_enabled(id, enabled); -} - -int board_regulator_set_voltage(uint32_t index, uint32_t min_mv, - uint32_t max_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_set_voltage(id, min_mv, max_mv); -} - -int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_voltage(id, voltage_mv); -} - -static void baseboard_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); -#ifndef BOARD_CHERRY - gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE); -#endif -} -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1); - -__override int board_pd_set_frs_enable(int port, int enable) -{ - if (port == 1) - /* - * Use set_flags (implemented by a single i2c write) instead - * of set_level (= i2c_update) to save one read operation in - * FRS path. - */ - rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS, - enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); - return EC_SUCCESS; -} - -__override int board_get_vbus_voltage(int port) -{ - int voltage = 0; - - switch (port) { - case 0: - voltage = adc_read_channel(ADC_VBUS); - break; - case 1: - rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage); - break; - default: - return 0; - } - - return voltage; -} diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h deleted file mode 100644 index 8dc1dbfb91..0000000000 --- a/baseboard/cherry/baseboard.h +++ /dev/null @@ -1,242 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Cherry board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* IT81202-bx config */ -/* - * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't - * connect to 1.8v on other versions. - */ -#define CONFIG_IT83XX_VCC_1P8V - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON -#define CONFIG_CHIPSET_MT8192 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE - -/* Chipset */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_CMD_POWERINDEBUG -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LOW_POWER_S0 -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_COMMON -#define CONFIG_PWM -#define CONFIG_PWM_KBLIGHT -#define CONFIG_VBOOT_HASH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ACTIVE_HIGH - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_BATTERY_SMART - -/* BC12 */ -#ifdef BOARD_CHERRY -#define CONFIG_BC12_DETECT_PI3USB9201 -#endif -#define CONFIG_BC12_DETECT_MT6360 -#undef CONFIG_BC12_SINGLE_DRIVER -#define CONFIG_USB_CHARGER - -/* CBI */ -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CBI_EEPROM -#define CONFIG_CMD_CBI -#define I2C_PORT_EEPROM IT83XX_I2C_CH_A -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -/* Charger */ -#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */ -#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9238C -#define CONFIG_CHARGER_MAINTAIN_VBAT -/* Not used in boot flow, set to 0 to suppress system_can_boot_ap warning */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 0 -#define CONFIG_CHARGER_OTG -#define CONFIG_CHARGER_PSYS -#define CONFIG_CHARGER_PSYS_READ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ -#define CONFIG_CMD_CHARGER_ADC_AMON_BMON - -/* Keyboard */ -#define CONFIG_CMD_KEYBOARD -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* I2C */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E -#define I2C_PORT_USB0 IT83XX_I2C_CH_C -#define I2C_PORT_USB1 IT83XX_I2C_CH_E -#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define CONFIG_SMBUS_PEC - -/* LED */ -#define CONFIG_LED_COMMON - -/* PD / USB-C / PPC */ -#define CONFIG_USB_PD_DEBUG_LEVEL 3 -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_IT83XX_TUNE_CC_PHY -#define CONFIG_USBC_PPC -#define CONFIG_USBC_PPC_DEDICATED_INT -#define CONFIG_USBC_PPC_POLARITY -#define CONFIG_USBC_PPC_RT1718S -#define CONFIG_USBC_PPC_SYV682X -#define CONFIG_USBC_PPC_VCONN -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USBC_RETIMER_PS8802 /* C0 */ -#define CONFIG_USB_MUX_ANX3443 /* C1 */ -#define CONFIG_USB_MUX_VIRTUAL -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_DISCHARGE -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DPS -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_FRS_PPC -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_PPC -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP -#define CONFIG_USB_PD_TCPM_RT1718S -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_VBUS_MEASURE_BY_BOARD -#define CONFIG_USB_PID 0x5054 -#define CONFIG_USB_POWER_DELIVERY - -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* USB-A */ -#define CONFIG_USB_PORT_POWER_DUMB -#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK -#define USB_PORT_COUNT USBA_PORT_COUNT - -/* UART */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Sensor */ -#define CONFIG_CMD_ACCEL_INFO -#define CONFIG_CMD_ACCELS - -#define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#define CONFIG_ACCEL_INTERRUPTS - -/* SPI / Host Command */ -#define CONFIG_SPI - -/* MKBP */ -#define CONFIG_MKBP_EVENT - -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* Voltage regulator control */ -#define CONFIG_HOSTCMD_REGULATOR - -/* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "registers.h" -#include "power/mt8192.h" - -enum adc_channel { - ADC_VBUS, /* ADC 0 */ - ADC_BOARD_ID, /* ADC 1 */ - ADC_SKU_ID, /* ADC 2 */ - ADC_CHARGER_AMON_R, /* ADC 3 */ - ADC_CHARGER_PMON, /* ADC 6 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */ - - /* Number of ADC channels */ - ADC_CH_COUNT, -}; - -enum temp_sensor_id { - TEMP_SENSOR_CHARGER, - TEMP_SENSOR_COUNT, -}; - -enum pwm_channel { - PWM_CH_LED1, - PWM_CH_LED2, - PWM_CH_LED3, - PWM_CH_KBLIGHT, - PWM_CH_COUNT, -}; - -void board_reset_pd_mcu(void); -void rt1718s_tcpc_interrupt(enum gpio_signal signal); - -/* RT1718S gpio to pin name mapping */ -#define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1 -#define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2 -#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/cherry/build.mk b/baseboard/cherry/build.mk deleted file mode 100644 index ae82c1ca68..0000000000 --- a/baseboard/cherry/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c deleted file mode 100644 index 0c7f4dcee5..0000000000 --- a/baseboard/cherry/usb_pd_policy.c +++ /dev/null @@ -1,260 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "adc.h" -#include "atomic.h" -#include "charge_manager.h" -#include "chipset.h" -#include "driver/tcpm/rt1718s.h" -#include "driver/tcpm/tcpci.h" -#include "timer.h" -#include "usb_dp_alt_mode.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" - -#if CONFIG_USB_PD_3A_PORTS != 1 -#error Cherry reference must have at least one 3.0 A port -#endif - -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) - -/* The port that the aux channel is on. */ -static enum { - AUX_PORT_NONE = -1, - AUX_PORT_C0 = 0, - AUX_PORT_C1HDMI = 1, -} aux_port = AUX_PORT_NONE; - -int svdm_get_hpd_gpio(int port) -{ - /* HPD is low active, inverse the result */ - return !gpio_get_level(GPIO_EC_AP_DP_HPD_ODL); -} - -void svdm_set_hpd_gpio(int port, int en) -{ - /* - * HPD is low active, inverse the en - * TODO: C0&C1 shares the same HPD, implement FCFS policy. - */ - gpio_set_level(GPIO_EC_AP_DP_HPD_ODL, !en); -} - -static void aux_switch_port(int port) -{ - if (port != AUX_PORT_NONE) - gpio_set_level_verbose(CC_USBPD, GPIO_DP_PATH_SEL, !port); - aux_port = port; -} - -static void aux_display_disconnected(int port) -{ - /* Gets the other port. C0 -> C1, C1 -> C0. */ - int other_port = !port; - - /* If the current port is not the aux port, nothing needs to be done. */ - if (aux_port != port) - return; - - /* If the other port is connected to a external display, switch aux. */ - if (dp_status[other_port] & DP_FLAGS_DP_ON) - aux_switch_port(other_port); - else - aux_switch_port(AUX_PORT_NONE); -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - int cur_lvl = svdm_get_hpd_gpio(port); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) - /* - * Wake up the AP. IRQ or level high indicates a DP sink is now - * present. - */ - if (IS_ENABLED(CONFIG_MKBP_EVENT)) - pd_notify_dp_alt_mode_entry(port); - - /* Its initial DP status message prior to config */ - if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { - if (lvl) - dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; - return 1; - } - -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - if (irq && !lvl) { - /* - * IRQ can only be generated when the level is high, because - * the IRQ is signaled by a short low pulse from the high level. - */ - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; /* nak */ - } - - if (irq && cur_lvl) { - uint64_t now = get_time().val; - /* wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* generate IRQ_HPD pulse */ - svdm_set_hpd_gpio(port, 0); - /* - * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is - * very short (500us), we can use udelay instead of usleep for - * more stable pulse period. - */ - udelay(HPD_DSTREAM_DEBOUNCE_IRQ); - svdm_set_hpd_gpio(port, 1); - } else { - svdm_set_hpd_gpio(port, lvl); - } - - /* - * Cherry can only output to 1 display port at a time. - * This implements FCFS policy by changing the aux channel. If a - * display is connected to the either port (says A), and the port A - * will be served until the display is disconnected from port A. - * It won't output to the other display which connects to port B. - */ - if (lvl && aux_port == AUX_PORT_NONE) - /* - * A display is connected, and no display was plugged on either - * port. - */ - aux_switch_port(port); - else if (!lvl) - aux_display_disconnected(port); - - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, lvl); -#endif - - /* ack */ - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - svdm_set_hpd_gpio(port, 0); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - - aux_display_disconnected(port); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, 0); -#endif -} - -int pd_snk_is_vbus_provided(int port) -{ - static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT]; - int vbus; - - /* - * Use ppc_is_vbus_present for all ports on Cherry, and - * port 1 on other devices. - */ - if (IS_ENABLED(BOARD_CHERRY) || port == 1) - return ppc_is_vbus_present(port); - - /* b/181203590: use ADC for port 0 (syv682x) */ - vbus = (adc_read_channel(ADC_VBUS) >= PD_V_SINK_DISCONNECT_MAX); - -#ifdef CONFIG_USB_CHARGER - /* - * There's no PPC to inform VBUS change for usb_charger, so inform - * the usb_charger now. - */ - if (!!(vbus_prev[port] != vbus)) - usb_charger_vbus_change(port, vbus); - - if (vbus) - atomic_or(&vbus_prev[port], 1); - else - atomic_clear(&vbus_prev[port]); -#endif - return vbus; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - if (port == 1) - rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* Allow Vconn swap if AP is on. */ - return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - if (port == 1) - rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c deleted file mode 100644 index 2f71f03068..0000000000 --- a/baseboard/dedede/baseboard.c +++ /dev/null @@ -1,311 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Dedede family-specific configuration */ - -#include "adc.h" -#include "board_config.h" -#include "cbi_fw_config.h" -#include "charger/isl923x_public.h" -#include "charger/sm5803.h" -#include "chipset.h" -#include "common.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "power/icelake.h" -#include "power/intel_x86.h" -#include "system.h" -#include "usb_pd.h" - -/******************************************************************************/ -/* - * PWROK signal configuration, see the PWROK Generation Flow Diagram in the - * Jasper Lake Platform Design Guide for the list of potential signals. - * - * Dedede boards use this PWROK sequence: - * GPIO_ALL_SYS_PWRGD - turns on VCCIN rail - * GPIO_EC_AP_VCCST_PWRGD_OD - asserts VCCST_PWRGD to AP, requires 2ms - * delay from VCCST stable to meet the tCPU00 platform sequencing - * timing - * GPIO_EC_AP_PCH_PWROK_OD - asserts PMC_PCH_PWROK to the AP. Note that - * PMC_PCH_PWROK is also gated by the IMVP9_VRRDY_OD output from - * the VCCIN voltage rail controller. - * GPIO_EC_AP_SYS_PWROK - asserts PMC_SYS_PWROK to the AP - * - * Both PMC_PCH_PWROK and PMC_SYS_PWROK signals must both be asserted before - * the Jasper Lake SoC deasserts PMC_RLTRST_N. The platform may deassert - * PMC_PCH_PWROK and PMC_SYS_PWROK in any order to optimize overall boot - * latency. - */ -const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { - { - .gpio = GPIO_ALL_SYS_PWRGD, - }, - { - .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, - .delay_ms = 2, - }, - { - .gpio = GPIO_EC_AP_PCH_PWROK_OD, - }, - { - .gpio = GPIO_EC_AP_SYS_PWROK, - }, -}; -const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); - -const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { - /* No delays needed during S0 exit */ - { - .gpio = GPIO_EC_AP_VCCST_PWRGD_OD, - }, - { - .gpio = GPIO_EC_AP_PCH_PWROK_OD, - }, - { - .gpio = GPIO_EC_AP_SYS_PWROK, - }, - /* Turn off the VCCIN rail last */ - { - .gpio = GPIO_ALL_SYS_PWRGD, - }, -}; -const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); - - -/* - * Dedede does not use hibernate wake pins, but the super low power "Z-state" - * instead in which the EC is powered off entirely. Power will be restored to - * the EC once one of the wake up events occurs. These events are ACOK, lid - * open, and a power button press. - */ -const enum gpio_signal hibernate_wake_pins[] = {}; -const int hibernate_wake_pins_used; - -__override void board_after_rsmrst(int rsmrst) -{ - /* - * b:148688874: If RSMRST# is de-asserted, enable the pull-up on - * PG_PP1050_ST_OD. It won't be enabled prior to this signal going high - * because the load switch for PP1050_ST cannot pull the PG low. Once - * it's asserted, disable the pull up so we don't inidicate that the - * power is good before the rail is actually ready. - */ - int flags = rsmrst ? GPIO_PULL_UP : 0; - - flags |= GPIO_INT_BOTH; - - gpio_set_flags(GPIO_PG_PP1050_ST_OD, flags); -} - -/* - * Dedede does not have a GPIO indicating ACOK, therefore the charger or TCPC - * can call this function once it detects a VBUS presence change with which we - * can trigger the HOOK_AC_CHANGE hook. - */ -__override void board_check_extpower(void) -{ - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; -} - -uint32_t pp3300_a_pgood; -__override int intel_x86_get_pg_ec_dsw_pwrok(void) -{ - /* - * The PP3300_A rail is an input to generate DPWROK. Assuming that - * power is good if voltage is at least 80% of nominal level. We cannot - * read the ADC values during an interrupt, therefore, this power good - * value is updated via ADC threshold interrupts. - */ - return pp3300_a_pgood; -} - -/* Store away PP300_A good status before sysjumps */ -#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ -#define BASEBOARD_HOOK_VERSION 1 - -static void pp3300_a_pgood_preserve(void) -{ - system_add_jump_tag(BASEBOARD_SYSJUMP_TAG, BASEBOARD_HOOK_VERSION, - sizeof(pp3300_a_pgood), &pp3300_a_pgood); -} -DECLARE_HOOK(HOOK_SYSJUMP, pp3300_a_pgood_preserve, HOOK_PRIO_DEFAULT); - -static void baseboard_prepare_power_signals(void) -{ - const int *stored; - int version, size; - - stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG, - &version, &size); - if (stored && (version == BASEBOARD_HOOK_VERSION) && - (size == sizeof(pp3300_a_pgood))) - /* Valid PP3300 status found, restore before CHIPSET init */ - pp3300_a_pgood = *stored; - - /* Restore pull-up on PG_PP1050_ST_OD */ - if (system_jumped_to_this_image() && - gpio_get_level(GPIO_RSMRST_L_PGOOD)) - board_after_rsmrst(1); -} -DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST); - -__override int intel_x86_get_pg_ec_all_sys_pwrgd(void) -{ - /* - * SLP_S3_L is a qualifying input signal to ALL_SYS_PWRGD logic. - * So ensure ALL_SYS_PWRGD remains LOW during SLP_S3_L assertion. - */ - if (!gpio_get_level(GPIO_SLP_S3_L)) - return 0; - /* - * ALL_SYS_PWRGD is an AND of DRAM PGOOD, VCCST PGOOD, and VCCIO_EXT - * PGOOD. - */ - return gpio_get_level(GPIO_PG_PP1050_ST_OD) && - gpio_get_level(GPIO_PG_DRAM_OD) && - gpio_get_level(GPIO_PG_VCCIO_EXT_OD); -} - -__override int power_signal_get_level(enum gpio_signal signal) -{ - if (signal == GPIO_PG_EC_DSW_PWROK) - return intel_x86_get_pg_ec_dsw_pwrok(); - - if (signal == GPIO_PG_EC_ALL_SYS_PWRGD) - return intel_x86_get_pg_ec_all_sys_pwrgd(); - - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) { - /* Check signal is from GPIOs or VWs */ - if (espi_signal_is_vw(signal)) - return espi_vw_get_wire(signal); - } - return gpio_get_level(signal); - -} - -void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) -{ - /* - * We need to deassert ALL_SYS_PGOOD within 200us of SLP_S3_L asserting. - * that is why we do this here instead of waiting for the chipset - * driver to. - * Early protos do not pull VCCST_PWRGD below Vil in hardware logic, - * so we need to do the same for this signal. - * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during - * SLP_S3_L assertion. - */ - if (!gpio_get_level(GPIO_SLP_S3_L)) { - gpio_set_level(GPIO_ALL_SYS_PWRGD, 0); - gpio_set_level(GPIO_EN_VCCIO_EXT, 0); - gpio_set_level(GPIO_EC_AP_VCCST_PWRGD_OD, 0); - gpio_set_level(GPIO_EC_AP_PCH_PWROK_OD, 0); - } - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} - -void baseboard_chipset_startup(void) -{ -#ifdef CONFIG_PWM_KBLIGHT - /* Allow keyboard backlight to be enabled */ - gpio_set_level(GPIO_EN_KB_BL, 1); -#endif -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, - HOOK_PRIO_DEFAULT); - -void baseboard_chipset_shutdown(void) -{ -#ifdef CONFIG_PWM_KBLIGHT - /* Turn off the keyboard backlight if it's on. */ - gpio_set_level(GPIO_EN_KB_BL, 0); -#endif -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, - HOOK_PRIO_DEFAULT); - -void board_hibernate_late(void) -{ - volatile uint32_t busy = 0; - - /* Disable any pull-ups on C0 and C1 interrupt lines */ - gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT); - #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); - #endif - /* - * Turn on the Z state. This will not return as it will cut power to - * the EC. - */ - gpio_set_level(GPIO_EN_SLP_Z, 1); - - /* - * Interrupts are disabled at this point, so busy-loop to consume some - * time (something on the order of at least 1 second, depending on EC - * chip being used) - */ - while (busy < 100000) - busy++; - - /* - * Still awake despite turning on zombie state? Reset with AP off is - * the best we can do in this situation. - */ - system_reset(SYSTEM_RESET_LEAVE_AP_OFF); - - /* Await our reset */ - while (1) - ; -} - -int board_is_i2c_port_powered(int port) -{ - if (port != I2C_PORT_SENSOR) - return 1; - - /* Sensor rails are off in S5/G3 */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; -} - -int extpower_is_present(void) -{ - int port; - int rv; - bool acok; - enum ec_error_list (*check_acok)(int port, bool *acok); - - if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) - check_acok = raa489000_is_acok; - else if (IS_ENABLED(CONFIG_CHARGER_SM5803)) - check_acok = sm5803_is_acok; - - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - rv = check_acok(port, &acok); - if ((rv == EC_SUCCESS) && acok) - return 1; - } - - return 0; -} - -__override uint32_t board_override_feature_flags0(uint32_t flags0) -{ - /* - * Remove keyboard backlight feature for devices that don't support it. - */ - if (get_cbi_fw_config_kblight() == KB_BL_ABSENT) - return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); - else - return flags0; -} diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h deleted file mode 100644 index a8a0ed3ff2..0000000000 --- a/baseboard/dedede/baseboard.h +++ /dev/null @@ -1,269 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Dedede board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) - -/* - * Variant EC defines. Pick one: - * VARIANT_DEDEDE_EC_NPCX796FC - */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \ - defined(VARIANT_KEEBY_EC_NPCX797FC) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* No tach. */ - - /* Internal SPI flash on NPCX7 */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_A - #define I2C_PORT_BATTERY IT83XX_I2C_CH_B - #define I2C_PORT_SENSOR IT83XX_I2C_CH_C - #define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_C0 IT83XX_I2C_CH_F - - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - #define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ - - #undef CONFIG_UART_TX_BUF_SIZE /* UART */ - #define CONFIG_UART_TX_BUF_SIZE 4096 -#else -#error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!" -#endif - -/* - * The key difference between Keeby and Dedede is that Keeby variants don't have - * a connection to H1 and therefore do not use EFS2. - */ -#if defined(VARIANT_KEEBY_EC_NPCX797FC) || defined(VARIANT_KEEBY_EC_IT8320) -#define KEEBY_VARIANT 1 -#else -#define KEEBY_VARIANT 0 -#endif - -/* - * Remapping of schematic GPIO names to common GPIO names expected (hardcoded) - * in the EC code base. - */ -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L -#define GPIO_EN_PP5000 GPIO_EN_PP5000_U -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#if !KEEBY_VARIANT -#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE -#endif -#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK -#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L -#if KEEBY_VARIANT -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#else -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#endif -#define GPIO_RSMRST_L_PGOOD GPIO_RSMRST_PWRGD_L -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD -#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_WP GPIO_EC_WP_OD -#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L - -/* Common EC defines */ - -/* Work around double CR50 reset by waiting in initial power on. */ -#if !KEEBY_VARIANT -#define CONFIG_BOARD_RESET_AFTER_POWER_ON -#endif - -/* Optional console commands */ -#define CONFIG_CMD_CHARGER_DUMP - -/* Enable AP Reset command for TPM with old firmware version to detect it. */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET - -/* Enable i2ctrace command */ -#define CONFIG_I2C_DEBUG - -/* Assert CCD when a debug device is connected */ -#if !KEEBY_VARIANT -#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT -#endif - -/* EC Modules */ -#define CONFIG_ADC -#define CONFIG_CRC8 -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_EVENTS -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#if !KEEBY_VARIANT -#define CONFIG_VBOOT_EFS2 -#endif - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATTERY_PRES_ODL -#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -/* Buttons / Switches */ -#define CONFIG_SWITCH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ACTIVE_HIGH - -/* CBI */ -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#if KEEBY_VARIANT -#define CONFIG_EEPROM_CBI_WP -#endif - -/* Charger */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 256 -#define CONFIG_USB_CHARGER -#define CONFIG_TRICKLE_CHARGING - -/* Keyboard */ -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_MKBP_INPUT_DEVICES - -/* Backlight */ -#define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD - -/* LED */ -#define CONFIG_LED_COMMON - -/* Sensors */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT - -/* SoC */ -#define CONFIG_BOARD_HAS_RTC_RESET -#define CONFIG_CHIPSET_JASPERLAKE -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW - -/* USB Type-C */ -#define CONFIG_USB_MUX_PI3USB31532 -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Temp Sensor */ -#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A -#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 - -/* USB PD */ -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TRY_SRC -/* #define CONFIG_USB_PD_VBUS_DETECT_CHARGER */ -#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER -#define CONFIG_USB_PD_DECODE_SOP -#if KEEBY_VARIANT -#define CONFIG_USB_PID 0x5059 -#else -#define CONFIG_USB_PID 0x5042 -#endif -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_HOSTCMD_PD_CONTROL - -#if !KEEBY_VARIANT -/* UART COMMAND */ -#define CONFIG_CMD_CHARGEN -#endif - -/* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 45000 -#define PD_OPERATING_POWER_MW 15000 - -/* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -#ifndef __ASSEMBLER__ - -#include "common.h" -#include "gpio_signal.h" - -/* Common enums */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - enum board_vcmp { - VCMP_SNS_PP3300_LOW, - VCMP_SNS_PP3300_HIGH, - VCMP_COUNT - }; -#endif - -/* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */ -void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal); - -/* Reset all TCPCs */ -void board_reset_pd_mcu(void); - -/* - * Bit to indicate if the PP3000_A rail's power is good. Will be updated by ADC - * interrupt. - */ -extern uint32_t pp3300_a_pgood; - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk deleted file mode 100644 index 6d7452081e..0000000000 --- a/baseboard/dedede/build.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o cbi_fw_config.o -baseboard-$(VARIANT_DEDEDE_EC_NPCX796FC)+=variant_ec_npcx796fc.o -baseboard-$(VARIANT_KEEBY_EC_NPCX797FC)+=variant_ec_npcx796fc.o -baseboard-$(VARIANT_DEDEDE_EC_IT8320)+=variant_ec_it8320.o -baseboard-$(VARIANT_KEEBY_EC_IT8320)+=variant_ec_it8320.o diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c deleted file mode 100644 index 27d23733de..0000000000 --- a/baseboard/dedede/cbi_fw_config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_fw_config.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -/**************************************************************************** - * Dedede CBI FW Configuration - */ - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache FW_CONFIG on init since we don't expect it to change in runtime */ -static uint32_t cached_fw_config; - -static void cbi_fw_config_init(void) -{ - if (cbi_get_fw_config(&cached_fw_config) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_fw_config = 0; - - CPRINTS("FW_CONFIG: 0x%04X", cached_fw_config); -} -DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST); - -enum fw_config_db get_cbi_fw_config_db(void) -{ - return ((cached_fw_config & FW_CONFIG_DB_MASK) >> FW_CONFIG_DB_OFFSET); -} - -enum fw_config_kblight_type get_cbi_fw_config_kblight(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) - >> FW_CONFIG_KB_BL_OFFSET); -} - -enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void) -{ - return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) - >> FW_CONFIG_TABLET_MODE_OFFSET); -} - -int get_cbi_fw_config_keyboard(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) - >> FW_CONFIG_KB_LAYOUT_OFFSET); -} - -enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void) -{ - return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) - >> FW_CONFIG_KB_NUMPAD_OFFSET); -} - -enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void) -{ - return ((cached_fw_config & FW_CONFIG_HDMI_MASK) - >> FW_CONFIG_HDMI_OFFSET); -} diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h deleted file mode 100644 index c9782522fa..0000000000 --- a/baseboard/dedede/cbi_fw_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _DEDEDE_CBI_FW_CONFIG__H_ -#define _DEDEDE_CBI_FW_CONFIG__H_ - -/**************************************************************************** - * Dedede CBI FW Configuration - */ - -/* - * Daughter Board (Bits 0-3) - */ -enum fw_config_db { - DB_NONE, - DB_2C, - DB_1C_LTE, - DB_1A_HDMI, - DB_1C_1A, - DB_LTE_HDMI, - DB_1C_1A_LTE, - DB_1C, - DB_1A_HDMI_LTE, -}; -#define FW_CONFIG_DB_OFFSET 0 -#define FW_CONFIG_DB_MASK GENMASK(3, 0) - -/* - * Keyboard backlight (1 bit) - */ -enum fw_config_kblight_type { - KB_BL_ABSENT = 0, - KB_BL_PRESENT = 1, -}; -#define FW_CONFIG_KB_BL_OFFSET 8 -#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) - -/* - * Keyboard numeric pad (1 bit) - */ -enum fw_config_numeric_pad_type { - NUMERIC_PAD_ABSENT = 0, - NUMERIC_PAD_PRESENT = 1, -}; -#define FW_CONFIG_KB_NUMPAD_OFFSET 9 -#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) - -/* - * Tablet Mode (1 bit) - */ -enum fw_config_tablet_mode_type { - TABLET_MODE_ABSENT = 0, - TABLET_MODE_PRESENT = 1, -}; -#define FW_CONFIG_TABLET_MODE_OFFSET 10 -#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) - -#define FW_CONFIG_KB_LAYOUT_OFFSET 12 -#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) - -/* - * Hdmi (1 bit) - */ -enum fw_config_hdmi_type { - HDMI_ABSENT = 0, - HDMI_PRESENT = 1, -}; -#define FW_CONFIG_HDMI_OFFSET 17 -#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) - -enum fw_config_db get_cbi_fw_config_db(void); -enum fw_config_kblight_type get_cbi_fw_config_kblight(void); -enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void); -enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void); -enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void); - -int get_cbi_fw_config_keyboard(void); - -#endif /* _DEDEDE_CBI_FW_CONFIG__H_ */ diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c deleted file mode 100644 index 59f07da086..0000000000 --- a/baseboard/dedede/variant_ec_it8320.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_[DEDEDE|KEEBY]_IT8320 configuration */ - -#include "adc_chip.h" -#include "atomic.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "power.h" -#include "registers.h" - -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) - -static void pp3300_a_pgood_low(void) -{ - atomic_clear_bits(&pp3300_a_pgood, 1); - - /* Disable low interrupt while asserted */ - vcmp_enable(VCMP_SNS_PP3300_LOW, 0); - - /* Enable high interrupt */ - vcmp_enable(VCMP_SNS_PP3300_HIGH, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -static void pp3300_a_pgood_high(void) -{ - atomic_or(&pp3300_a_pgood, 1); - - /* Disable high interrupt while asserted */ - vcmp_enable(VCMP_SNS_PP3300_HIGH, 0); - - /* Enable low interrupt */ - vcmp_enable(VCMP_SNS_PP3300_LOW, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -const struct vcmp_t vcmp_list[] = { - [VCMP_SNS_PP3300_LOW] = { - .name = "VCMP_SNS_PP3300_LOW", - .threshold = 600, /* mV */ - .flag = LESS_EQUAL_THRESHOLD, - .vcmp_thresh_cb = &pp3300_a_pgood_low, - .scan_period = VCMP_SCAN_PERIOD_600US, - .adc_ch = CHIP_ADC_CH0, - }, - [VCMP_SNS_PP3300_HIGH] = { - .name = "VCMP_SNS_PP3300_HIGH", - .threshold = 2700, /* mV */ - .flag = GREATER_THRESHOLD, - .vcmp_thresh_cb = &pp3300_a_pgood_high, - .scan_period = VCMP_SCAN_PERIOD_600US, - .adc_ch = CHIP_ADC_CH0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(vcmp_list) <= CHIP_VCMP_COUNT); -BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT); - -/* I2C Ports */ -const struct i2c_port_t i2c_ports[] = { - { - "eeprom", I2C_PORT_EEPROM, 400, GPIO_EC_I2C_EEPROM_SCL, - GPIO_EC_I2C_EEPROM_SDA - }, - - { - "battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL, - GPIO_EC_I2C_BATTERY_SDA - }, -#ifdef HAS_TASK_MOTIONSENSE - { - "sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL, - GPIO_EC_I2C_SENSOR_SDA - }, -#endif - -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - "sub_usbc1", I2C_PORT_SUB_USB_C1, 1000, - GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA - }, -#endif - - { - "usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL, - GPIO_EC_I2C_USB_C0_SDA - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c deleted file mode 100644 index 6d9dfb368a..0000000000 --- a/baseboard/dedede/variant_ec_npcx796fc.c +++ /dev/null @@ -1,191 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_[DEDEDE|KEEBY]_NPCX79[6/7]FC configuration */ - -#include "adc.h" -#include "atomic.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "lid_switch.h" -#include "power.h" -#include "registers.h" -#include "task.h" -#include "timer.h" - -/* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -void pp3300_a_pgood_high(void) -{ - atomic_or(&pp3300_a_pgood, 1); - - /* Disable this interrupt while it's asserted. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0); - /* Enable the voltage low interrupt. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -void pp3300_a_pgood_low(void) -{ - atomic_clear_bits(&pp3300_a_pgood, 1); - - /* Disable this interrupt while it's asserted. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0); - /* Enable the voltage high interrupt. */ - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - - /* - * Call power_signal_interrupt() with a fake GPIO in order for the - * chipset task to pick up the change in power sequencing signals. - */ - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} - -const struct npcx_adc_thresh_t adc_pp3300_a_pgood_high = { - .adc_ch = ADC_VSNS_PP3300_A, - .adc_thresh_cb = pp3300_a_pgood_high, - .thresh_assert = 2700, -}; - -const struct npcx_adc_thresh_t adc_pp3300_a_pgood_low = { - .adc_ch = ADC_VSNS_PP3300_A, - .adc_thresh_cb = pp3300_a_pgood_low, - .lower_or_higher = 1, - .thresh_assert = 600, -}; - -static void set_up_adc_irqs(void) -{ - /* Set interrupt thresholds for the ADC. */ - npcx_adc_register_thresh_irq(NPCX_ADC_THRESH1, - &adc_pp3300_a_pgood_high); - npcx_adc_register_thresh_irq(NPCX_ADC_THRESH2, &adc_pp3300_a_pgood_low); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); -} -DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1); - -static void disable_adc_irqs_deferred(void) -{ - CPRINTS("%s", __func__); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 0); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 0); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, 0); - - /* - * If we're already in G3, PP3300_A is already off. Since the ADC - * interrupts were already disabled, this data is stale. Therefore, - * force the PGOOD value to 0 and have the chipset task re-evaluate. - * This should help prevent leakage. - */ - if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - pp3300_a_pgood = 0; - power_signal_interrupt(GPIO_PG_EC_DSW_PWROK); -} -DECLARE_DEFERRED(disable_adc_irqs_deferred); - -/* - * The ADC interrupts are only needed for booting up. The assumption is that - * the PP3300_A rail will not go down during runtime. Therefore, we'll disable - * the ADC interrupts shortly after booting up and also after shutting down. - */ -static void disable_adc_irqs(void) -{ - int delay = 200 * MSEC; - - /* - * The EC stays in S5 for about 10s after shutting before heading down - * to G3. Therefore, we'll postpone disabling the ADC IRQs until after - * this occurs. - */ - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) - delay = 15 * SECOND; - hook_call_deferred(&disable_adc_irqs_deferred_data, delay); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_adc_irqs, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, disable_adc_irqs, HOOK_PRIO_DEFAULT); - -/* - * We only need the ADC interrupts functional when powering up. Therefore, only - * enable them from our wake sources. These will be the power button, or lid - * open. Below is a summary of the ADC interrupt action per power state and - * wake source. - * - * Powering up to S0: ADC interrupts will be disabled after ~200ms. - * S0ix/S3: No action as ADC interrupts are already disabled if suspending. - * Powering down to S5/G3: ADC interrupts will be disabled after ~15s. - * Powering up from S5/G3: ADC interrupts will be enabled. They will be - * disabled ~200ms after passing thru S3. - * Power button press: If the system is in S5/G3, ADC interrupts will be - * enabled. - * Lid open: ADC interrupts will be enabled. - */ -static void enable_adc_irqs(void) -{ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) { - CPRINTS("%s", __func__); - hook_call_deferred(&disable_adc_irqs_deferred_data, -1); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, - 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); - npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); - } -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enable_adc_irqs, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, enable_adc_irqs, HOOK_PRIO_DEFAULT); - -static void enable_adc_irqs_via_lid(void) -{ - if (lid_is_open()) - enable_adc_irqs(); -} -DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT); - -/* I2C Ports */ -__attribute__((weak)) const struct i2c_port_t i2c_ports[] = { - { - "eeprom", I2C_PORT_EEPROM, 1000, GPIO_EC_I2C_EEPROM_SCL, - GPIO_EC_I2C_EEPROM_SDA - }, - - { - "battery", I2C_PORT_BATTERY, 100, GPIO_EC_I2C_BATTERY_SCL, - GPIO_EC_I2C_BATTERY_SDA - }, - -#ifdef HAS_TASK_MOTIONSENSE - { - "sensor", I2C_PORT_SENSOR, 400, GPIO_EC_I2C_SENSOR_SCL, - GPIO_EC_I2C_SENSOR_SDA - }, -#endif - - { - "usbc0", I2C_PORT_USB_C0, 1000, GPIO_EC_I2C_USB_C0_SCL, - GPIO_EC_I2C_USB_C0_SDA - }, -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - "sub_usbc1", I2C_PORT_SUB_USB_C1, 1000, - GPIO_EC_I2C_SUB_USB_C1_SCL, GPIO_EC_I2C_SUB_USB_C1_SDA - }, -#endif -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c deleted file mode 100644 index 933fdc0eff..0000000000 --- a/baseboard/goroh/baseboard.c +++ /dev/null @@ -1,572 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Goroh baseboard-specific configuration */ - -#include "adc.h" -#include "button.h" -#include "charge_manager.h" -#include "charger.h" -#include "charger.h" -#include "charge_state.h" -#include "charge_state_v2.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/accelgyro_bmi_common.h" -#include "driver/accel_lis2dw12.h" -#include "driver/als_tcs3400.h" -#include "driver/bc12/mt6360.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl923x.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/syv682x.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/temp_sensor/thermistor.h" -#include "driver/usb_mux/it5205.h" -#include "driver/usb_mux/ps8743.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "motion_sense.h" -#include "power_button.h" -#include "power.h" -#include "power.h" -#include "regulator.h" -#include "spi.h" -#include "switch.h" -#include "tablet_mode.h" -#include "task.h" -#include "temp_sensor.h" -#include "timer.h" -#include "uart.h" -#include "usb_charge.h" -#include "usbc_ppc.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" - -static void bc12_interrupt(enum gpio_signal signal); -static void ppc_interrupt(enum gpio_signal signal); -static void x_ec_interrupt(enum gpio_signal signal); - -#include "gpio_list.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -static enum board_sub_board board_get_sub_board(void); - -/* Wake-up pins for hibernate */ -enum gpio_signal hibernate_wake_pins[] = { - GPIO_AC_PRESENT, - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, -}; -int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - -__override void board_hibernate_late(void) -{ - /* - * Turn off PP5000_A. Required for devices without Z-state. - * Don't care for devices with Z-state. - */ - gpio_set_level(GPIO_EN_PP5000_A, 0); - - /* - * GPIO_EN_SLP_Z not implemented in rev0/1, - * fallback to usual hibernate process. - */ - if (IS_ENABLED(BOARD_GOROH) && board_get_version() <= 1) - return; - - isl9238c_hibernate(CHARGER_SOLO); - - gpio_set_level(GPIO_EN_SLP_Z, 1); - - /* should not reach here */ - __builtin_unreachable(); -} - -/* Detect subboard */ -static void board_tcpc_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - /* C1: GPIO_USB_C1_PPC_INT_ODL & HDMI: GPIO_PS185_EC_DP_HPD */ - gpio_enable_interrupt(GPIO_X_EC_GPIO2); - - /* If this is not a Type-C subboard, disable the task. */ - if (board_get_sub_board() != SUB_BOARD_TYPEC) - task_disable_task(TASK_ID_PD_C1); -} -/* Must be done after I2C and subboard */ -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -/* PPC */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - .frs_en = GPIO_USB_C0_FRS_EN, - }, - { - .i2c_port = I2C_PORT_PPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - .frs_en = GPIO_USB_C1_FRS_EN, - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* BC12 */ -const struct mt6360_config_t mt6360_config = { - .i2c_port = 0, - .i2c_addr_flags = MT6360_PMU_I2C_ADDR_FLAGS, -}; - -const struct pi3usb9201_config_t - pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - /* [0]: unused */ - [1] = { - .i2c_port = 4, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - } -}; - -struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { .drv = &mt6360_drv }, - { .drv = &pi3usb9201_drv }, -}; - -static void bc12_interrupt(enum gpio_signal signal) -{ - if (signal == GPIO_USB_C0_BC12_INT_ODL) - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); - else - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); -} - -static void board_sub_bc12_init(void) -{ - if (board_get_sub_board() == SUB_BOARD_TYPEC) - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L); - else - /* If this is not a Type-C subboard, disable the task. */ - task_disable_task(TASK_ID_USB_CHG_P1); -} -/* Must be done after I2C and subboard */ -DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_INIT_I2C + 1); - -static void ppc_interrupt(enum gpio_signal signal) -{ - if (signal == GPIO_USB_C0_PPC_INT_ODL) - /* C0: PPC interrupt */ - syv682x_interrupt(0); -} - -/* Sub-board */ - -static enum board_sub_board board_get_sub_board(void) -{ - static enum board_sub_board sub = SUB_BOARD_NONE; - - if (sub != SUB_BOARD_NONE) - return sub; - - /* HDMI board has external pull high. */ - if (gpio_get_level(GPIO_EC_X_GPIO3)) { - sub = SUB_BOARD_HDMI; - /* Only has 1 PPC with HDMI subboard */ - ppc_cnt = 1; - /* EC_X_GPIO1 */ - gpio_set_flags(GPIO_EN_HDMI_PWR, GPIO_OUT_HIGH); - /* X_EC_GPIO2 */ - gpio_set_flags(GPIO_PS185_EC_DP_HPD, GPIO_INT_BOTH); - /* EC_X_GPIO3 */ - gpio_set_flags(GPIO_PS185_PWRDN_ODL, GPIO_ODR_HIGH); - } else { - sub = SUB_BOARD_TYPEC; - /* EC_X_GPIO1 */ - gpio_set_flags(GPIO_USB_C1_FRS_EN, GPIO_OUT_LOW); - /* X_EC_GPIO2 */ - gpio_set_flags(GPIO_USB_C1_PPC_INT_ODL, - GPIO_INT_BOTH | GPIO_PULL_UP); - /* EC_X_GPIO3 */ - gpio_set_flags(GPIO_USB_C1_DP_IN_HPD, GPIO_OUT_LOW); - } - - CPRINTS("Detect %s SUB", sub == SUB_BOARD_HDMI ? "HDMI" : "TYPEC"); - return sub; -} - -static void sub_board_init(void) -{ - board_get_sub_board(); -} -DECLARE_HOOK(HOOK_INIT, sub_board_init, HOOK_PRIO_INIT_I2C - 1); - -__override uint8_t board_get_usb_pd_port_count(void) -{ - if (board_get_sub_board() == SUB_BOARD_TYPEC) - return CONFIG_USB_PD_PORT_MAX_COUNT; - else - return CONFIG_USB_PD_PORT_MAX_COUNT - 1; -} - -/* Called on AP S3 -> S0 transition */ -static void board_chipset_resume(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S3 transition */ -static void board_chipset_suspend(void) -{ - gpio_set_level(GPIO_EC_BL_EN_OD, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); - -/* USB-A */ -const int usb_port_enable[] = { - GPIO_EN_PP5000_USB_A0_VBUS, -}; -BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); - -/* USB Mux */ - -void board_usb_mux_init(void) -{ - if (board_get_sub_board() == SUB_BOARD_TYPEC) - ps8743_tune_usb_eq(&usb_muxes[1], - PS8743_USB_EQ_TX_12_8_DB, - PS8743_USB_EQ_RX_12_8_DB); -} -DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); - -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - int rv = EC_SUCCESS; - int reg = 0; - - rv = ps8743_read(me, PS8743_REG_MODE, ®); - if (rv) - return rv; - - /* Disable FLIP pin, enable I2C control. */ - reg |= PS8743_MODE_FLIP_REG_CONTROL; - /* Disable CE_USB pin, enable I2C control. */ - reg |= PS8743_MODE_USB_REG_CONTROL; - /* Disable CE_DP pin, enable I2C control. */ - reg |= PS8743_MODE_DP_REG_CONTROL; - - /* - * DP specific config - * - * Enable/Disable IN_HPD on the DB. - */ - gpio_set_level(GPIO_USB_C1_DP_IN_HPD, - mux_state & USB_PD_MUX_DP_ENABLED); - - return ps8743_write(me, PS8743_REG_MODE, reg); -} - -const struct usb_mux usbc0_virtual_mux = { - .usb_port = 0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usbc1_virtual_mux = { - .usb_port = 1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .i2c_port = I2C_PORT_USB_MUX0, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .next_mux = &usbc0_virtual_mux, - }, - { - .usb_port = 1, - .i2c_port = I2C_PORT_USB_MUX1, - .i2c_addr_flags = PS8743_I2C_ADDR0_FLAG, - .driver = &ps8743_usb_mux_driver, - .next_mux = &usbc1_virtual_mux, - .board_set = &board_ps8743_mux_set, - }, -}; - -/* - * I2C channels (A, B, and C) are using the same timing registers (00h~07h) - * at default. - * In order to set frequency independently for each channels, - * We use timing registers 09h~0Bh, and the supported frequency will be: - * 50KHz, 100KHz, 400KHz, or 1MHz. - * I2C channels (D, E and F) can be set different frequency on different ports. - * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and - * the individual prescale register. - * The frequency of SMBus module is 24MHz on default. - * The allowed range of I2C(D/E/F) frequency is as following setting. - * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1) - * (SMBus Module Freq / 510) <= I2C Freq <= (SMBus Module Freq / 8) - * Channel D has multi-function and can be used as UART interface. - * Channel F is reserved for EC debug. - */ - -/* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - {"bat_chg", IT83XX_I2C_CH_A, 100, GPIO_I2C_A_SCL, GPIO_I2C_A_SDA}, - {"sensor", IT83XX_I2C_CH_B, 400, GPIO_I2C_B_SCL, GPIO_I2C_B_SDA}, - {"usb0", IT83XX_I2C_CH_C, 400, GPIO_I2C_C_SCL, GPIO_I2C_C_SDA}, - {"usb1", IT83XX_I2C_CH_E, 400, GPIO_I2C_E_SCL, GPIO_I2C_E_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY); -} - - -void board_overcurrent_event(int port, int is_overcurrented) -{ - /* TODO: check correct operation for GOROH */ -} - -/* TCPC */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it8xxx2_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -}; - -const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) -{ - const static struct cc_para_t - cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; - - return &cc_parameter[port]; -} - -uint16_t tcpc_get_alert_status(void) -{ - /* - * C0 & C1: TCPC is embedded in the EC and processes interrupts in the - * chip code (it83xx/intc.c) - */ - return 0; -} - -void board_reset_pd_mcu(void) -{ - /* - * C0 & C1: TCPC is embedded in the EC and processes interrupts in the - * chip code (it83xx/intc.c) - */ -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* - * We ignore the cc_pin and PPC vconn because polarity and PPC vconn - * should already be set correctly in the PPC driver via the pd - * state machine. - */ -} - -int board_set_active_charge_port(int port) -{ - int i; - int is_valid_port = port == 0 || (port == 1 && board_get_sub_board() == - SUB_BOARD_TYPEC); - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - if (port == CHARGE_PORT_NONE) { - CPRINTS("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTS("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTS("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTS("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/** - * Handle PS185 HPD changing state. - */ -int debounced_hpd; - -static void ps185_hdmi_hpd_deferred(void) -{ - const int new_hpd = gpio_get_level(GPIO_PS185_EC_DP_HPD); - - /* HPD status not changed, probably a glitch, just return. */ - if (debounced_hpd == new_hpd) - return; - - debounced_hpd = new_hpd; - - gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !debounced_hpd); - CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug"); -} -DECLARE_DEFERRED(ps185_hdmi_hpd_deferred); - -#define PS185_HPD_DEBOUCE 250 - -static void hdmi_hpd_interrupt(enum gpio_signal signal) -{ - hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE); -} - -/* HDMI/TYPE-C function shared subboard interrupt */ -static void x_ec_interrupt(enum gpio_signal signal) -{ - int sub = board_get_sub_board(); - - if (sub == SUB_BOARD_TYPEC) - /* C1: PPC interrupt */ - syv682x_interrupt(1); - else if (sub == SUB_BOARD_HDMI) - hdmi_hpd_interrupt(signal); - else - CPRINTS("Undetected subboard interrupt."); -} - -int ppc_get_alert_status(int port) -{ - if (port == 0) - return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; - if (port == 1 && board_get_sub_board() == SUB_BOARD_TYPEC) - return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; - - return 0; -} -/* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); -} - -int board_regulator_enable(uint32_t index, uint8_t enable) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_enable(id, enable); -} - -int board_regulator_is_enabled(uint32_t index, uint8_t *enabled) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_is_enabled(id, enabled); -} - -int board_regulator_set_voltage(uint32_t index, uint32_t min_mv, - uint32_t max_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_set_voltage(id, min_mv, max_mv); -} - -int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv) -{ - enum mt6360_regulator_id id = index; - - return mt6360_regulator_get_voltage(id, voltage_mv); -} - -static void baseboard_init(void) -{ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); -} -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1); diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h deleted file mode 100644 index 55fa0ffab7..0000000000 --- a/baseboard/goroh/baseboard.h +++ /dev/null @@ -1,206 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Goroh board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* IT81202-bx config */ -/* - * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't - * connect to 1.8v on other versions. - */ -#define CONFIG_IT83XX_VCC_1P8V - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON -#define CONFIG_CHIPSET_MT8192 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC - -/* Chipset */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_CMD_POWERINDEBUG -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LOW_POWER_S0 -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_COMMON -#define CONFIG_PWM -#define CONFIG_VBOOT_HASH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ACTIVE_HIGH - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_BATTERY_SMART - -/* BC12 */ -#define CONFIG_BC12_DETECT_MT6360 -#define CONFIG_BC12_DETECT_PI3USB9201 -#undef CONFIG_BC12_SINGLE_DRIVER -#define CONFIG_USB_CHARGER - -/* Charger */ -#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */ -#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */ -#define ADC_VBUS ADC_VBUS_C0 /* ADC name remap */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9238C -#define CONFIG_CHARGER_MAINTAIN_VBAT -#define CONFIG_CHARGER_OTG -#define CONFIG_CHARGER_PSYS -#define CONFIG_CHARGER_PSYS_READ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ -#define CONFIG_CMD_CHARGER_ADC_AMON_BMON - -/* Keyboard */ -#define CONFIG_CMD_KEYBOARD -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* I2C */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E -#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define CONFIG_SMBUS_PEC - -/* LED */ -#define CONFIG_LED_COMMON - -/* PD / USB-C / PPC */ -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_IT83XX_TUNE_CC_PHY -#define CONFIG_USB_MUX_VIRTUAL -#define CONFIG_USBC_PPC -#define CONFIG_USBC_PPC_DEDICATED_INT -#define CONFIG_USBC_PPC_POLARITY -#define CONFIG_USBC_PPC_SYV682C -#define CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE -#define CONFIG_USBC_PPC_VCONN -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_MUX_IT5205 /* C0 */ -#define CONFIG_USB_MUX_PS8743 /* C1 */ -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_DISCHARGE -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_FRS_PPC -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -#define CONFIG_USB_PID 0x5566 /* TODO: update PID */ -#define CONFIG_USB_POWER_DELIVERY - -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* USB-A */ -#define CONFIG_USB_PORT_POWER_DUMB -#define USB_PORT_COUNT USBA_PORT_COUNT - -/* UART */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Sensor */ -#ifdef HAS_TASK_MOTIONSENSE -#define CONFIG_CMD_ACCEL_INFO -#define CONFIG_CMD_ACCELS - -#define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#define CONFIG_ACCEL_INTERRUPTS -#endif - -/* SPI / Host Command */ -#define CONFIG_SPI - -/* MKBP */ -#define CONFIG_MKBP_EVENT - -#define CONFIG_KEYBOARD_PROTOCOL_MKBP -#define CONFIG_MKBP_USE_GPIO - -/* Voltage regulator control */ -#define CONFIG_HOSTCMD_REGULATOR - -/* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* GPIO name remapping */ -#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2 -#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 -#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 -#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "registers.h" -#include "power/mt8192.h" - -enum board_sub_board { - SUB_BOARD_NONE = -1, - SUB_BOARD_TYPEC, - SUB_BOARD_HDMI, - SUB_BOARD_COUNT, -}; - -int board_get_version(void); -void board_reset_pd_mcu(void); -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c deleted file mode 100644 index a8bee6d412..0000000000 --- a/baseboard/goroh/board_id.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "timer.h" -#include "util.h" - -/** - * Conversion based on following table: - * - * ID | Rp | Rd | Voltage - * | kOhm | kOhm | mV - * ---+------+------+-------- - * 0 | 51.1 | 2.2 | 136.2 - * 1 | 51.1 | 6.81 | 388.1 - * 2 | 51.1 | 11 | 584.5 - * 3 | 57.6 | 18 | 785.7 - * 4 | 51.1 | 22 | 993.2 - * 5 | 51.1 | 30 | 1220.7 - * 6 | 51.1 | 39.2 | 1432.6 - * 7 | 56 | 56 | 1650.0 - * 8 | 47 | 61.9 | 1875.8 - * 9 | 47 | 80.6 | 2084.5 - * 10 | 56 | 124 | 2273.3 - * 11 | 51.1 | 150 | 2461.5 - * 12 | 47 | 200 | 2672.1 - * 13 | 47 | 330 | 2888.6 - * 14 | 47 | 680 | 3086.7 - */ -const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, -}; - -const int threshold_mv = 100; - -/** - * Convert ADC value to board id using the voltage table above. - * - * @param ch ADC channel to read, usually ADC_BOARD_ID_0 or ADC_BOARD_ID_1. - * - * @return a non-negative board id, or negative value if error. - */ -static int adc_value_to_numeric_id(enum adc_channel ch) -{ - int mv; - - gpio_set_level(GPIO_EN_EC_ID_ODL, 0); - /* Wait to allow cap charge */ - msleep(10); - - mv = adc_read_channel(ch); - if (mv == ADC_READ_ERROR) - mv = adc_read_channel(ch); - - gpio_set_level(GPIO_EN_EC_ID_ODL, 1); - - if (mv == ADC_READ_ERROR) - return -EC_ERROR_UNKNOWN; - - for (int i = 0; i < ARRAY_SIZE(voltage_map); i++) { - if (IN_RANGE(mv, voltage_map[i] - threshold_mv, - voltage_map[i] + threshold_mv)) - return i; - } - - return -EC_ERROR_UNKNOWN; -} - -static int version = -1; - -/* b/163963220: Cache ADC value before board_hibernate_late() reads it */ -static void board_version_init(void) -{ - version = adc_value_to_numeric_id(ADC_BOARD_ID_0); - if (version < 0) { - ccprints("WARN:BOARD_ID_0"); - ccprints("Assuming board id = 0"); - - version = 0; - } -} -DECLARE_HOOK(HOOK_INIT, board_version_init, HOOK_PRIO_INIT_ADC + 1); - -int board_get_version(void) -{ - return version; -} diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk deleted file mode 100644 index 58e9934bc0..0000000000 --- a/baseboard/goroh/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o board_id.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c deleted file mode 100644 index 72213d311c..0000000000 --- a/baseboard/goroh/usb_pd_policy.c +++ /dev/null @@ -1,214 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "charge_manager.h" -#include "chipset.h" -#include "timer.h" -#include "usb_dp_alt_mode.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" - -#if CONFIG_USB_PD_3A_PORTS != 1 -#error Goroh reference must have at least one 3.0 A port -#endif - -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) - -int svdm_get_hpd_gpio(int port) -{ - /* HPD is low active, inverse the result */ - return !gpio_get_level(GPIO_EC_DPBRDG_HPD_ODL); -} - -void svdm_set_hpd_gpio(int port, int en) -{ - /* - * HPD is low active, inverse the en - * TODO: C0&C1 shares the same HPD, implement FCFS policy. - */ - gpio_set_level(GPIO_EC_DPBRDG_HPD_ODL, !en); -} - -/** - * Is the port fine to be muxed its DisplayPort lines? - * - * Only one port can be muxed to DisplayPort at a time. - * - * @param port Port number of TCPC. - * @return 1 is fine; 0 is bad as other port is already muxed; - */ -static int is_dp_muxable(int port) -{ - int i; - - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (i != port) { - if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) - return 0; - } - } - - return 1; -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - int cur_lvl = svdm_get_hpd_gpio(port); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - if (!is_dp_muxable(port)) { - /* TODO(waihong): Info user? */ - CPRINTS("p%d: The other port is already muxed.", port); - return 0; /* nak */ - } - - if (lvl) - gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port); - - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) - /* - * Wake up the AP. IRQ or level high indicates a DP sink is now - * present. - */ - if (IS_ENABLED(CONFIG_MKBP_EVENT)) - pd_notify_dp_alt_mode_entry(port); - - /* Its initial DP status message prior to config */ - if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { - if (lvl) - dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; - return 1; - } - -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - if (irq && !lvl) { - /* - * IRQ can only be generated when the level is high, because - * the IRQ is signaled by a short low pulse from the high level. - */ - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; /* nak */ - } - - if (irq && cur_lvl) { - uint64_t now = get_time().val; - /* wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* generate IRQ_HPD pulse */ - svdm_set_hpd_gpio(port, 0); - /* - * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is - * very short (500us), we can use udelay instead of usleep for - * more stable pulse period. - */ - udelay(HPD_DSTREAM_DEBOUNCE_IRQ); - svdm_set_hpd_gpio(port, 1); - } else { - svdm_set_hpd_gpio(port, lvl); - } - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, lvl); -#endif - - /* ack */ - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ -#ifdef CONFIG_USB_PD_DP_HPD_GPIO - svdm_set_hpd_gpio(port, 0); -#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - -#ifdef USB_PD_PORT_TCPC_MST - if (port == USB_PD_PORT_TCPC_MST) - baseboard_mst_enable_control(port, 0); -#endif -} - -int pd_snk_is_vbus_provided(int port) -{ - /* TODO(yllin): check SNK VBUS detection */ - return ppc_is_vbus_present(port); - - /* - * (b:181203590#comment20) TODO(yllin): use - * PD_VSINK_DISCONNECT_PD for non-5V case. - */ - return charge_manager_get_vbus_voltage(port) >= - PD_V_SINK_DISCONNECT_MAX; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* Allow Vconn swap if AP is on. */ - return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/grunt/analyzestack.yaml b/baseboard/grunt/analyzestack.yaml deleted file mode 100644 index 7ff5f39644..0000000000 --- a/baseboard/grunt/analyzestack.yaml +++ /dev/null @@ -1,2 +0,0 @@ -remove: -- panic_assert_fail diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c deleted file mode 100644 index cf49fc0566..0000000000 --- a/baseboard/grunt/baseboard.c +++ /dev/null @@ -1,815 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Grunt family-specific configuration */ - -#include "adc.h" -#include "button.h" -#include "charge_manager.h" -#include "charge_state.h" -#include "charge_state_v2.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "cros_board_info.h" -#include "driver/accel_kionix.h" -#include "driver/accel_kx022.h" -#include "driver/accelgyro_bmi_common.h" -#include "driver/bc12/max14637.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/sn5s330.h" -#include "driver/tcpm/anx7447.h" -#include "driver/tcpm/anx74xx.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/temp_sensor/sb_tsi.h" -#include "ec_commands.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "motion_sense.h" -#include "power.h" -#include "power_button.h" -#include "registers.h" -#include "switch.h" -#include "system.h" -#include "task.h" -#include "tcpm/tcpci.h" -#include "temp_sensor.h" -#include "temp_sensor/thermistor.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_TEMP_SENSOR_SOC] = { - "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_VBUS] = { - "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID1] = { - "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID2] = { - "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/* Power signal list. Must match order of enum power_signal. */ -const struct power_signal_info power_signal_list[] = { - {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, - {GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"}, - {GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"}, - {GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"}, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 - [USB_PD_PORT_ANX74XX] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = ANX74XX_I2C_ADDR1_FLAGS, - }, - .drv = &anx74xx_tcpm_drv, - /* Alert is active-low, open-drain */ - .flags = TCPC_FLAGS_ALERT_OD, - }, -#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) - [USB_PD_PORT_ANX74XX] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, - }, - .drv = &anx7447_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -#endif - [USB_PD_PORT_PS8751] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC1, - .addr_flags = PS8751_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -}; - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port = -1; - - switch (signal) { - case GPIO_USB_C0_PD_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_PD_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -void board_tcpc_init(void) -{ - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL); - - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL); - -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 - /* Enable CABLE_DET interrupt for ANX3429 wake from standby */ - gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET); -#endif - /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ - for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) { -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 - if (gpio_get_level(GPIO_USB_C0_PD_RST_L)) -#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) - if (!gpio_get_level(GPIO_USB_C0_PD_RST)) -#endif - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C1_PD_RST_L)) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 -static void anx74xx_cable_det_handler(void) -{ - int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET); - int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L); - - /* - * A cable_det low->high transition was detected. If following the - * debounce time, cable_det is high, and reset_n is low, then ANX3429 is - * currently in standby mode and needs to be woken up. Set the - * TCPC_RESET event which will bring the ANX3429 out of standby - * mode. Setting this event is gated on reset_n being low because the - * ANX3429 will always set cable_det when transitioning to normal mode - * and if in normal mode, then there is no need to trigger a tcpc reset. - */ - if (cable_det && !reset_n) - task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET); -} -DECLARE_DEFERRED(anx74xx_cable_det_handler); - -void anx74xx_cable_det_interrupt(enum gpio_signal signal) -{ - /* debounce for 2 msec */ - hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC)); -} - -/** - * Power on (or off) a single TCPC. - * minimum on/off delays are included. - * - * @param port Port number of TCPC. - * @param mode 0: power off, 1: power on. - */ -void board_set_tcpc_power_mode(int port, int mode) -{ - if (port != USB_PD_PORT_ANX74XX) - return; - - switch (mode) { - case ANX74XX_NORMAL_MODE: - gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1); - msleep(ANX74XX_PWR_H_RST_H_DELAY_MS); - gpio_set_level(GPIO_USB_C0_PD_RST_L, 1); - break; - case ANX74XX_STANDBY_MODE: - gpio_set_level(GPIO_USB_C0_PD_RST_L, 0); - msleep(ANX74XX_RST_L_PWR_L_DELAY_MS); - gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0); - msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS); - break; - default: - break; - } -} -#endif /* VARIANT_GRUNT_TCPC_0_ANX3429 */ - -void board_reset_pd_mcu(void) -{ -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 - /* Assert reset to TCPC1 (ps8751) */ - gpio_set_level(GPIO_USB_C1_PD_RST_L, 0); - - /* Assert reset to TCPC0 (anx3429) */ - gpio_set_level(GPIO_USB_C0_PD_RST_L, 0); - - /* TCPC1 (ps8751) requires 1ms reset down assertion */ - msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS)); - - /* Deassert reset to TCPC1 */ - gpio_set_level(GPIO_USB_C1_PD_RST_L, 1); - /* Disable TCPC0 power */ - gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0); - - /* - * anx3429 requires 10ms reset/power down assertion - */ - msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS); - board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1); -#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) - /* Assert reset to TCPC0 (anx3447) */ - gpio_set_level(GPIO_USB_C0_PD_RST, 1); - msleep(ANX74XX_RESET_HOLD_MS); - gpio_set_level(GPIO_USB_C0_PD_RST, 0); - msleep(ANX74XX_RESET_FINISH_MS); - - /* Assert reset to TCPC1 (ps8751) */ - gpio_set_level(GPIO_USB_C1_PD_RST_L, 0); - msleep(PS8XXX_RESET_DELAY_MS); - gpio_set_level(GPIO_USB_C1_PD_RST_L, 1); -#endif -} - -static uint32_t sku_id; - -static int ps8751_tune_mux(const struct usb_mux *me) -{ - /* Tune USB mux registers for treeya's port 1 Rx measurement */ - if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) - mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40); - - return EC_SUCCESS; -} - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 - [USB_PD_PORT_ANX74XX] = { - .usb_port = USB_PD_PORT_ANX74XX, - .driver = &anx74xx_tcpm_usb_mux_driver, - .hpd_update = &anx74xx_tcpc_update_hpd_status, - }, -#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) - [USB_PD_PORT_ANX74XX] = { - .usb_port = USB_PD_PORT_ANX74XX, - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, - }, -#endif - [USB_PD_PORT_PS8751] = { - .usb_port = USB_PD_PORT_PS8751, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, - } -}; - -struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -void ppc_interrupt(enum gpio_signal signal) -{ - int port = (signal == GPIO_USB_C0_SWCTL_INT_ODL) ? 0 : 1; - - sn5s330_interrupt(port); -} - -int ppc_get_alert_status(int port) -{ - if (port == 0) - return gpio_get_level(GPIO_USB_C0_SWCTL_INT_ODL) == 0; - else - return gpio_get_level(GPIO_USB_C1_SWCTL_INT_ODL) == 0; -} - -void board_overcurrent_event(int port, int is_overcurrented) -{ - enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L - : GPIO_USB_C1_OC_L; - /* Note that the levels are inverted because the pin is active low. */ - int lvl = is_overcurrented ? 0 : 1; - - gpio_set_level(signal, lvl); - - CPRINTS("p%d: overcurrent!", port); -} - -/* BC 1.2 chip Configuration */ -const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ANX74XX] = { - .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_L, - .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET, - .flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW, - }, - [USB_PD_PORT_PS8751] = { - .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_L, - .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET, - .flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW, - }, -}; - -/* Charger Chip Configuration */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - - -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_EN_USB_A0_5V, - GPIO_EN_USB_A1_5V, -}; - -static void baseboard_chipset_suspend(void) -{ - /* - * Turn off display backlight. This ensures that the backlight stays off - * in S3, no matter what the AP has it set to. The AP also controls it. - * This is here more for legacy reasons. - */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -static void baseboard_chipset_resume(void) -{ - /* Allow display backlight to turn on. See above backlight comment */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0); - -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -static void baseboard_chipset_startup(void) -{ - /* - * Enable sensor power (lid accel, gyro) in S3 for calculating the lid - * angle (needed on convertibles to disable resume from keyboard in - * tablet mode). - */ - gpio_set_level(GPIO_EN_PP1800_SENSOR, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, - HOOK_PRIO_DEFAULT); - -static void baseboard_chipset_shutdown(void) -{ - /* Disable sensor power (lid accel, gyro) in S5. */ - gpio_set_level(GPIO_EN_PP1800_SENSOR, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, - HOOK_PRIO_DEFAULT); - -int board_is_i2c_port_powered(int port) -{ - if (port != I2C_PORT_SENSOR) - return 1; - - /* Sensor power (lid accel, gyro) is off in S5 (and G3). */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; -} - -int board_set_active_charge_port(int port) -{ - int i; - - CPRINTS("New chg p%d", port); - - if (port == CHARGE_PORT_NONE) { - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("p%d: sink disable failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTF("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTS("p%d: sink disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTS("p%d: sink enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - /* - * Limit the input current to 95% negotiated limit, - * to account for the charger chip margin. - */ - charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80us - */ - .output_settle_us = 80, - .debounce_down_us = 6 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 1500, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = SECOND, - .actual_key_mask = { - 0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -/* - * We use 11 as the scaling factor so that the maximum mV value below (2761) - * can be compressed to fit in a uint8_t. - */ -#define THERMISTOR_SCALING_FACTOR 11 - -/* - * Values are calculated from the "Resistance VS. Temperature" table on the - * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. - */ -static const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} -}; - -static const struct thermistor_info thermistor_info = { - .scaling_factor = THERMISTOR_SCALING_FACTOR, - .num_pairs = ARRAY_SIZE(thermistor_data), - .data = thermistor_data, -}; - -static int board_get_temp(int idx, int *temp_k) -{ - /* idx is the sensor index set below in temp_sensors[] */ - int mv = adc_read_channel( - idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER); - int temp_c; - - if (mv < 0) - return -1; - - temp_c = thermistor_linear_interpolate(mv, &thermistor_info); - *temp_k = C_TO_K(temp_c); - return 0; -} - -const struct temp_sensor_t temp_sensors[] = { - {"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0}, - {"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1}, - {"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0}, -}; -BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - -#ifdef HAS_TASK_MOTIONSENSE - -/* Motion sensors */ -static struct mutex g_lid_mutex; -static struct mutex g_base_mutex; - -/* sensor private data */ -static struct kionix_accel_data g_kx022_data; -static struct bmi_drv_data_t g_bmi160_data; - -/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ -struct motion_sensor_t motion_sensors[] = { - [LID_ACCEL] = { - .name = "Lid Accel", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_KX022, - .type = MOTIONSENSE_TYPE_ACCEL, - .location = MOTIONSENSE_LOC_LID, - .drv = &kionix_accel_drv, - .mutex = &g_lid_mutex, - .drv_data = &g_kx022_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = KX022_ADDR1_FLAGS, - .rot_standard_ref = NULL, - .default_range = 2, /* g, enough for laptop. */ - .min_frequency = KX022_ACCEL_MIN_FREQ, - .max_frequency = KX022_ACCEL_MAX_FREQ, - .config = { - /* EC use accel for angle detection */ - [SENSOR_CONFIG_EC_S0] = { - .odr = 10000 | ROUND_UP_FLAG, - .ec_rate = 100, - }, - /* EC use accel for angle detection */ - [SENSOR_CONFIG_EC_S3] = { - .odr = 10000 | ROUND_UP_FLAG, - }, - }, - }, - - [BASE_ACCEL] = { - .name = "Base Accel", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI160, - .type = MOTIONSENSE_TYPE_ACCEL, - .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi160_drv, - .mutex = &g_base_mutex, - .drv_data = &g_bmi160_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS, - .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/ - .rot_standard_ref = NULL, - .min_frequency = BMI_ACCEL_MIN_FREQ, - .max_frequency = BMI_ACCEL_MAX_FREQ, - .config = { - /* EC use accel for angle detection */ - [SENSOR_CONFIG_EC_S0] = { - .odr = 10000 | ROUND_UP_FLAG, - .ec_rate = 100, - }, - /* EC use accel for angle detection */ - [SENSOR_CONFIG_EC_S3] = { - .odr = 10000 | ROUND_UP_FLAG, - }, - }, - }, - - [BASE_GYRO] = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI160, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi160_drv, - .mutex = &g_base_mutex, - .drv_data = &g_bmi160_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = NULL, - .min_frequency = BMI_GYRO_MIN_FREQ, - .max_frequency = BMI_GYRO_MAX_FREQ, - }, -}; - -unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); - -#endif /* HAS_TASK_MOTIONSENSE */ - -__override void lid_angle_peripheral_enable(int enable) -{ - if (board_is_convertible()) - keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE); -} - -static const int sku_thresh_mv[] = { - /* Vin = 3.3V, Ideal voltage, R2 values listed below */ - /* R1 = 51.1 kOhm */ - 200, /* 124 mV, 2.0 Kohm */ - 366, /* 278 mV, 4.7 Kohm */ - 550, /* 456 mV, 8.2 Kohm */ - 752, /* 644 mV, 12.4 Kohm */ - 927, /* 860 mV, 18.0 Kohm */ - 1073, /* 993 mV, 22.0 Kohm */ - 1235, /* 1152 mV, 27.4 Kohm */ - 1386, /* 1318 mV, 34.0 Kohm */ - 1552, /* 1453 mV, 40.2 Kohm */ - /* R1 = 10.0 kOhm */ - 1739, /* 1650 mV, 10.0 Kohm */ - 1976, /* 1827 mV, 12.4 Kohm */ - 2197, /* 2121 mV, 18.0 Kohm */ - 2344, /* 2269 mV, 22.0 Kohm */ - 2484, /* 2418 mV, 27.4 Kohm */ - 2636, /* 2550 mV, 34.0 Kohm */ - 2823, /* 2721 mV, 47.0 Kohm */ -}; - -static int board_read_sku_adc(enum adc_channel chan) -{ - int mv; - int i; - - mv = adc_read_channel(chan); - - if (mv == ADC_READ_ERROR) - return -1; - - for (i = 0; i < ARRAY_SIZE(sku_thresh_mv); i++) - if (mv < sku_thresh_mv[i]) - return i; - - return -1; -} - -static uint32_t board_get_adc_sku_id(void) -{ - int sku_id1, sku_id2; - - sku_id1 = board_read_sku_adc(ADC_SKU_ID1); - sku_id2 = board_read_sku_adc(ADC_SKU_ID2); - - if (sku_id1 < 0 || sku_id2 < 0) - return 0; - - return (sku_id2 << 4) | sku_id1; -} - -static int board_get_gpio_board_version(void) -{ - return - (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | - (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | - (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); -} - -static int board_version; - -static void cbi_init(void) -{ - board_version = board_get_gpio_board_version(); - sku_id = board_get_adc_sku_id(); - - /* - * Use board version and SKU ID from CBI EEPROM if the board supports - * it and the SKU ID set via resistors + ADC is not valid. - */ -#ifdef CONFIG_CBI_EEPROM - if (sku_id == 0 || sku_id == 0xff) { - uint32_t val; - - if (cbi_get_board_version(&val) == EC_SUCCESS) - board_version = val; - if (cbi_get_sku_id(&val) == EC_SUCCESS) - sku_id = val; - } -#endif - -#ifdef HAS_TASK_MOTIONSENSE - board_update_sensor_config_from_sku(); -#endif - - ccprints("Board Version: %d (0x%x)", board_version, board_version); - ccprints("SKU: %d (0x%x)", sku_id, sku_id); -} -/* - * Reading the SKU resistors requires the ADC module. If we are using EEPROM - * then we also need the I2C module, but that is available before ADC. - */ -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_ADC + 1); - -__override uint32_t board_get_sku_id(void) -{ - return sku_id; -} - -int board_get_version(void) -{ - return board_version; -} - -/* - * Returns 1 for boards that are convertible into tablet mode, and zero for - * clamshells. - */ -int board_is_convertible(void) -{ - /* Grunt: 6 */ - /* Kasumi360: 82 */ - /* Treeya360: a8-af, be, bf*/ - return (sku_id == 6 || sku_id == 82 || - ((sku_id >= 0xa8) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf); -} - -int board_is_lid_angle_tablet_mode(void) -{ - return board_is_convertible(); -} - -__override uint32_t board_override_feature_flags0(uint32_t flags0) -{ - /* - * Remove keyboard backlight feature for devices that don't support it. - * All Treeya and Treeya360 models do not support keyboard backlight. - */ - if (sku_id == 16 || sku_id == 17 || - sku_id == 20 || sku_id == 21 || - sku_id == 32 || sku_id == 33 || - sku_id == 40 || sku_id == 41 || - sku_id == 44 || sku_id == 45 || - ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) - return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); - else - return flags0; -} - -void board_hibernate(void) -{ - /* - * Some versions of some boards keep the port 0 PPC powered on while - * the EC hibernates (so Closed Case Debugging keeps working). - * Make sure the source FET is off and turn on the sink FET, so that - * plugging in AC will wake the EC. This matches the dead-battery - * behavior of the powered off PPC. - */ - ppc_vbus_source_enable(0, 0); - ppc_vbus_sink_enable(0, 1); - - /* - * If CCD not active, set port 0 SBU_EN=0 to avoid power leakage during - * hibernation (b/175674973). - */ - if (gpio_get_level(GPIO_CCD_MODE_ODL)) - ppc_set_sbu(0, 0); -} diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h deleted file mode 100644 index c97ece285f..0000000000 --- a/baseboard/grunt/baseboard.h +++ /dev/null @@ -1,260 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Grunt family-specific configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \ - + defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1 -#error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447 -#endif - -/* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - -/* Internal SPI flash on NPCX7 */ -/* Flash is 1MB but reserve half for future use. */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - -/* - * Enable 1 slot of secure temporary storage to support - * suspend/resume with read/write memory training. - */ -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -#define CONFIG_ADC -#define CONFIG_BACKLIGHT_LID -#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HIBERNATE_PSL -#define CONFIG_HOSTCMD_LPC -#define CONFIG_HOSTCMD_SKUID -#define CONFIG_I2C -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_I2C_CONTROLLER -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LOW_POWER_S0 -#define CONFIG_LTO -#define CONFIG_PWM -#define CONFIG_PWM_KBLIGHT -#define CONFIG_TEMP_SENSOR -#define CONFIG_THERMISTOR_NCP15WB -#define CONFIG_VBOOT_HASH -#define CONFIG_VOLUME_BUTTONS - -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -#define CONFIG_BC12_DETECT_MAX14637 -#define CONFIG_CHARGER -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC - -/* - * This limit impairs compatibility with BC1.2 chargers that are not actually - * capable of supplying 500 mA of current. When the charger is paralleled with - * the battery, raising this limit allows the power system to draw more current - * from the charger during startup. This improves compatibility with system - * batteries that may become excessively imbalanced after extended periods of - * rest. - * - * See also b/111214767 - */ -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9238 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_USB_CHARGER - -#define CONFIG_CHIPSET_STONEY -#define CONFIG_CHIPSET_RESET_HOOK -/* - * ACOK from ISL9238 sometimes has a negative pulse after connecting - * USB-C power. We want to ignore it. b/77455171 - */ -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - - -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_8042 - -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV1 -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_COMM_LOCKED -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#ifdef VARIANT_GRUNT_TCPC_0_ANX3429 -#define CONFIG_USB_PD_TCPM_ANX3429 -#elif defined(VARIANT_GRUNT_TCPC_0_ANX3447) -#define CONFIG_USB_PD_TCPM_ANX7447 -#endif -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_PS8751 -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USBC_PPC_SN5S330 -#define CONFIG_USBC_PPC_DEDICATED_INT -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* USB-A config */ -#define CONFIG_USB_PORT_POWER_DUMB -#define USB_PORT_COUNT 2 - -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ - -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/* - * Require PD negotiation to be complete when we are in a low-battery condition - * prior to releasing depthcharge to the kernel. - */ -#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15001 -#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3 - -/* Increase length of history buffer for port80 messages. */ -#undef CONFIG_PORT80_HISTORY_LEN -#define CONFIG_PORT80_HISTORY_LEN 256 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 -/* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR - -/* Sensors */ -#define CONFIG_MKBP_EVENT -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT - -/* Thermal */ -#define CONFIG_TEMP_SENSOR_SB_TSI - -#ifndef VARIANT_GRUNT_NO_SENSORS -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is a power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs. */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#endif /* VARIANT_GRUNT_NO_SENSORS */ - -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "math_util.h" -#include "registers.h" - -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_VBUS, - ADC_SKU_ID1, - ADC_SKU_ID2, - ADC_CH_COUNT -}; - -enum power_signal { - X86_SLP_S3_N, - X86_SLP_S5_N, - X86_S0_PGOOD, - X86_S5_PGOOD, - POWER_SIGNAL_COUNT -}; - -enum temp_sensor_id { - TEMP_SENSOR_CHARGER = 0, - TEMP_SENSOR_SOC, - TEMP_SENSOR_CPU, - TEMP_SENSOR_COUNT -}; - -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT, -}; - -/* - * Matrix to rotate accelerators into the standard reference frame. The default - * is the identity which is correct for the reference design. Variations of - * Grunt may need to change it for manufacturability. - * For the lid: - * +x to the right - * +y up - * +z out of the page - * - * The principle axes of the body are aligned with the lid when the lid is in - * the 180 degree position (open, flat). - * - * Boards within the Grunt family may need to modify this definition at - * board_init() time. - */ -extern mat33_fp_t grunt_base_standard_ref; - -/* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) - -void board_reset_pd_mcu(void); - -/* Common definition for the USB PD interrupt handlers. */ -void tcpc_alert_event(enum gpio_signal signal); -void ppc_interrupt(enum gpio_signal signal); -void anx74xx_cable_det_interrupt(enum gpio_signal signal); - -int board_get_version(void); -int board_is_convertible(void); -void board_update_sensor_config_from_sku(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/grunt/build.mk b/baseboard/grunt/build.mk deleted file mode 100644 index cb9d607c36..0000000000 --- a/baseboard/grunt/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c deleted file mode 100644 index 7c4fff953c..0000000000 --- a/baseboard/grunt/usb_pd_policy.c +++ /dev/null @@ -1,149 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Grunt boards */ - -#include "charge_manager.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) - -int pd_check_vconn_swap(int port) -{ - /* in G3, do not allow vconn swap since 5V rail is off */ - return gpio_get_level(GPIO_S5_PGOOD); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -#ifdef CONFIG_USB_PD_ALT_MODE_DFP -mux_state_t svdm_dp_mux_mode(int port) -{ - int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); - int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); - /* - * Multi-function operation is only allowed if that pin config is - * supported. - */ - if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref) - return USB_PD_MUX_DOCK; - else - return USB_PD_MUX_DP_ENABLED; -} - -__override int svdm_dp_config(int port, uint32_t *payload) -{ - int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); - int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); - int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); - mux_state_t mux_mode = svdm_dp_mux_mode(port); - - if (!pin_mode) - return 0; - - CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode); - - /* - * Place the USB Type-C pins that are to be re-configured to DisplayPort - * Configuration into the Safe state. For USB_PD_MUX_DOCK, the - * superspeed signals can remain connected. For USB_PD_MUX_DP_ENABLED, - * disconnect the superspeed signals here, before the pins are - * re-configured to DisplayPort (in svdm_dp_post_config, when we receive - * the config ack). - */ - if (mux_mode == USB_PD_MUX_DP_ENABLED) - usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ - return 2; -}; - -#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD) -__override void svdm_dp_post_config(int port) -{ - /* Connect the SBU and USB lines to the connector. */ - ppc_set_sbu(port, 1); - usb_mux_set(port, svdm_dp_mux_mode(port), USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - - dp_flags[port] |= DP_FLAGS_DP_ON; - if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) - return; - - gpio_set_level(PORT_TO_HPD(port), 1); - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} - -#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h deleted file mode 100644 index 2eea7a158f..0000000000 --- a/baseboard/guybrush/base_fw_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _GUYBRUSH_BASE_FW_CONFIG__H_ -#define _GUYBRUSH_BASE_FW_CONFIG__H_ - -#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF - -#include <stdbool.h> -#include <stdint.h> - -/* - * Takes a bit offset and bit width and returns the fw_config field at that - * offset and width. Returns -1 if an error occurs. - */ -int get_fw_config_field(uint8_t offset, uint8_t width); - -/* - * Each Guybrush board variant will define a board specific fw_config schema. - * Below is the schema agnostic interface for fw_config fields. - * Fields that are not applicable outside a specific Guybrush variant do not - * need to be included here. - */ - -enum board_usb_a1_retimer { - USB_A1_RETIMER_UNKNOWN, - USB_A1_RETIMER_PS8811, - USB_A1_RETIMER_ANX7491 -}; - -enum board_usb_c1_mux { - USB_C1_MUX_UNKNOWN, - USB_C1_MUX_PS8818, - USB_C1_MUX_ANX7451 -}; - -enum board_form_factor { - FORM_FACTOR_UNKNOWN, - FORM_FACTOR_CLAMSHELL, - FORM_FACTOR_CONVERTIBLE -}; - -bool board_has_kblight(void); -enum board_usb_a1_retimer board_get_usb_a1_retimer(void); -enum board_usb_c1_mux board_get_usb_c1_mux(void); -enum board_form_factor board_get_form_factor(void); -bool board_is_convertible(void); - -#endif /* _GUYBRUSH_BASE_FW_CONFIG__H_ */ diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc deleted file mode 100644 index 259ccd9286..0000000000 --- a/baseboard/guybrush/base_gpio.inc +++ /dev/null @@ -1,150 +0,0 @@ -/* -*- mode:c -*- - * - * Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GSC Signals */ -GPIO_INT(EC_WP_L, PIN(5, 0), GPIO_INT_BOTH, switch_interrupt) /* Write Protect Enabled */ -GPIO(CCD_MODE_ODL, PIN(C, 6), GPIO_ODR_HIGH) /* Case Closed Debug Mode */ -GPIO(EC_GSC_PACKET_MODE, PIN(B, 1), GPIO_OUT_LOW) /* GSC Packet Mode */ -ALTERNATE( PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* UART_EC_TX_GSC_DBG_RX_R, UART_GSC_DBG_TX_EC_RX_R */ - -/* Power Signals */ -GPIO_INT(MECH_PWR_BTN_ODL, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) /* Mechanical Power Button */ -GPIO_INT(EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* Power Button */ -GPIO_INT(SLP_S3_L, PIN(6, 1), GPIO_INT_BOTH, baseboard_en_pwr_s0) /* Sleep S3 */ -GPIO_INT(SLP_S5_L, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) /* Sleep S5 */ -GPIO_INT(SLP_S3_S0I3_L, PIN(7, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Sleep S0ix */ -GPIO_INT(PG_PWR_S5, PIN(C, 0), GPIO_INT_BOTH, baseboard_en_pwr_s0) /* S5 Power OK */ -GPIO_INT(PG_PCORE_S0_R_OD, PIN(B, 6), GPIO_INT_BOTH, power_signal_interrupt) /* S0 Power OK */ -GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* AC Power Present */ -GPIO_INT(EC_PCORE_INT_ODL, PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* Power Core Interrupt */ -GPIO_INT(PG_GROUPC_S0_OD, PIN(A, 3), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0) /* Power Group C S0 */ -GPIO_INT(PG_LPDDR4X_S3_OD, PIN(9, 5), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0) /* Power Group LPDDR4 S3 */ -GPIO(EN_PWR_S5, PIN(B, 7), GPIO_OUT_LOW) /* Enable S5 Power */ -GPIO(EN_PWR_S0_R, PIN(F, 1), GPIO_OUT_LOW) -GPIO(EN_PWR_PCORE_S0_R, PIN(E, 1), GPIO_OUT_LOW) -ALTERNATE(/*MECH_PWR_BTN_ODL*/ PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0) /* PSL - Mechanical Power Button */ -ALTERNATE(/*LID_OPEN*/ PIN_MASK(0, BIT(2)), 0, MODULE_PMU, 0) /* PSL - Lid Open */ -ALTERNATE(/*ACOK_OD*/ PIN_MASK(0, BIT(0)), 0, MODULE_PMU, 0) /* PSL - AC Power Present */ - -/* SOC Signals */ -GPIO(EC_ENTERING_RW, PIN(6, 6), GPIO_OUT_LOW) /* Tell SOC we entered RW */ -GPIO(EC_SYS_RST_L, PIN(7, 6), GPIO_ODR_HIGH) /* Cold Reset SOC */ -GPIO(EC_SOC_RSMRST_L, PIN(C, 5), GPIO_OUT_LOW) /* Resume Reset SOC */ -GPIO(EC_CLR_CMOS, PIN(A, 1), GPIO_OUT_LOW) /* Clear SOC CMOS */ -GPIO(EC_MEM_EVENT, PIN(A, 5), GPIO_OUT_LOW) /* Memory Thermal Event to SOC*/ -GPIO(EC_SOC_PWR_BTN_L, PIN(6, 3), GPIO_OUT_HIGH) /* Power Button to SOC */ -GPIO(EC_SOC_PWR_GOOD, PIN(D, 3), GPIO_OUT_LOW) /* Power Good to SOC */ -GPIO(EC_SOC_WAKE_L, PIN(0, 3), GPIO_OUT_HIGH) /* Wake SOC */ -GPIO(EC_SOC_INT_L, PIN(8, 3), GPIO_OUT_HIGH) /* Matrix Keyboard Protocol Event to SOC */ -GPIO(PROCHOT_ODL, PIN(D, 5), GPIO_ODR_HIGH) /* Force SOC into HTC-active state */ -GPIO(SOC_ALERT_EC_L, PIN(E, 2), GPIO_INPUT) /* Sideband-Temperature Iterrupt */ -GPIO(SOC_THERMTRIP_ODL, PIN(E, 5), GPIO_INPUT) /* Temperature Trip Sensor */ - -/* USB Signals */ -GPIO_INT(USB_C0_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event) -GPIO_INT(USB_C1_TCPC_INT_ODL, PIN(C, 7), GPIO_INT_FALLING, tcpc_alert_event) -GPIO_INT(USB_C0_PPC_INT_ODL, PIN(7, 5), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C1_PPC_INT_ODL, PIN(D, 4), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C0_BC12_INT_ODL, PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP, bc12_interrupt) -GPIO_INT(USB_C1_BC12_INT_ODL, PIN(9, 6), GPIO_INT_FALLING | GPIO_PULL_UP, bc12_interrupt) -GPIO(USB_C0_C1_FAULT_ODL, PIN(7, 3), GPIO_ODR_HIGH) /* C0/C1 Fault to SOC */ -GPIO(USB_C0_TCPC_RST_L, PIN(3, 4), GPIO_OUT_HIGH) /* C0 TCPC Reset */ -GPIO(USB_C1_TCPC_RST_L, PIN(3, 7), GPIO_OUT_HIGH) /* C1 TCPC Reset */ -GPIO(USB_C0_HPD, PIN(F, 5), GPIO_OUT_LOW) /* C0 DP Hotplug Detect */ -GPIO(USB_C1_HPD, PIN(F, 4), GPIO_OUT_LOW) /* C1 DP Hotplug Detect */ - -/* Sensor Signals */ -GPIO(3AXIS_INT_L, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN) /* 3 Axis Accel */ -GPIO_INT(LID_OPEN, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) /* Lid Open */ -GPIO_INT(VOLDN_BTN_ODL, PIN(A, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* Volume Down */ -GPIO_INT(VOLUP_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* Volume Up */ -GPIO(EC_BATT_PRES_ODL, PIN(9, 4), GPIO_INPUT) /* Battery Present */ -ALTERNATE(/*TEMP_SOC|CHRG|MEM*/ PIN_MASK(4, BIT(3) | BIT(4) | BIT(5)), 0, MODULE_ADC, 0) /* SOC, Charger and Memory Temperature */ -ALTERNATE( PIN_MASK(4, BIT(1) | BIT(2)), 0, MODULE_ADC, 0) /* EC_ADC_CORE_IMON1, EC_ADC_SOC_IMON2 */ - -/* LED Signals */ -GPIO(EC_DISABLE_DISP_BL, PIN(A, 6), GPIO_OUT_HIGH) /* Disable Display Backlight */ - -/* Fan Signals */ -ALTERNATE( PIN_MASK(C, BIT(3)), 0, MODULE_PWM, 0) /* EC_FAN_PWM - Fan PWM */ -ALTERNATE( PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0) /* EC_FAN_SPEED - Fan Speed */ - -/* I2C Signals -- i2c pins need to be exposed as GPIO for bit banging, even though set to alternate mode below */ -GPIO(EC_I2C_USB_A0_C0_SCL, PIN(B, 5), GPIO_INPUT) -GPIO(EC_I2C_USB_A0_C0_SDA, PIN(B, 4), GPIO_INPUT) -GPIO(EC_I2C_USB_A1_C1_SCL, PIN(9, 0), GPIO_INPUT) -GPIO(EC_I2C_USB_A1_C1_SDA, PIN(8, 7), GPIO_INPUT) -GPIO(EC_I2C_BATT_SCL, PIN(9, 2), GPIO_INPUT) -GPIO(EC_I2C_BATT_SDA, PIN(9, 1), GPIO_INPUT) -GPIO(EC_I2C_USBC_MUX_SCL, PIN(D, 1), GPIO_INPUT) -GPIO(EC_I2C_USBC_MUX_SDA, PIN(D, 0), GPIO_INPUT) -GPIO(EC_I2C_POWER_SCL, PIN(F, 3), GPIO_INPUT) -GPIO(EC_I2C_POWER_SDA, PIN(F, 2), GPIO_INPUT) -GPIO(EC_I2C_CBI_SCL, PIN(3, 3), GPIO_INPUT) -GPIO(EC_I2C_CBI_SDA, PIN(3, 6), GPIO_INPUT) -GPIO(EC_I2C_SENSOR_SCL, PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V) -GPIO(EC_I2C_SENSOR_SDA, PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V) -GPIO(EC_I2C_SOC_SIC, PIN(B, 3), GPIO_INPUT) -GPIO(EC_I2C_SOC_SID, PIN(B, 2), GPIO_INPUT) - -ALTERNATE( PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0) /* I2C0 */ -ALTERNATE( PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */ -ALTERNATE( PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0) /* I2C1 SDA */ -ALTERNATE( PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0) /* I2C3 */ -ALTERNATE( PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0) /* I2C4 */ -ALTERNATE( PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0) /* I2C5 */ -ALTERNATE( PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0) /* I2C6 */ -ALTERNATE( PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0) /* I2C7 */ - -/* Keyboard Signals */ -GPIO(EN_KB_BL, PIN(9, 7), GPIO_OUT_HIGH) /* Enable Keyboard Backlight */ -ALTERNATE(/*PWM_KB_BL*/ PIN_MASK(C, BIT(2)), 0, MODULE_PWM, 0) /* Keyboard Backlight Level */ -ALTERNATE(/*KSI_00-01*/ PIN_MASK(3, BIT(0) | BIT(1)), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) -ALTERNATE(/*KSI_02-07*/ PIN_MASK(2, GENMASK(7, 2)), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) -ALTERNATE(/*KSO_00-01*/ PIN_MASK(2, BIT(0) | BIT(1)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) -GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */ -ALTERNATE(/*KSO_03-09*/ PIN_MASK(1, GENMASK(6, 0)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) -ALTERNATE(/*KSO_10-13*/ PIN_MASK(0, GENMASK(7, 4)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) -ALTERNATE(/*KSO_14*/ PIN_MASK(8, BIT(2)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) - -/* b/186135022: Pull eSPI RST# high to disable */ -GPIO(EC_ESPI_RST_L, PIN(5, 4), GPIO_PULL_UP) - -#if 0 -/* - * SOC eSPI Bus - * These signals do not need to be explicitly configured. - * Leaving here so all signals are documented. - */ -GPIO(ESPI_SOC_CLK, PIN(5, 5), GPIO_DEFAULT) -GPIO(ESPI_SOC_CS_EC_L, PIN(5, 3), GPIO_DEFAULT) -GPIO(ESPI_SOC_D0_EC, PIN(4, 6), GPIO_DEFAULT) -GPIO(ESPI_SOC_D1_EC, PIN(4, 7), GPIO_DEFAULT) -GPIO(ESPI_SOC_D2_EC, PIN(5, 1), GPIO_DEFAULT) -GPIO(ESPI_SOC_D3_EC, PIN(5, 2), GPIO_DEFAULT) -GPIO(ESPI_EC_ALERT_SOC_L, PIN(5, 7), GPIO_DEFAULT) -#endif - -/* TCPC C0 */ -IOEX(USB_C0_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW) -IOEX(USB_C0_PPC_EN_L, EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_LOW) -IOEX(USB_C0_PPC_ILIM_3A_EN, EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW) -IOEX_INT(USB_C0_SBU_FAULT_ODL, EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt) -IOEX(EN_PP5000_USB_A0_VBUS, EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW) -IOEX(USB_A0_LIMIT_SDP, EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_LOW) -IOEX(USB_C0_SBU_FLIP, EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW) - -/* TCPC C1 */ -IOEX(USB_A1_RETIMER_EN, EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW) -IOEX(USB_A1_RETIMER_RST, EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW) -IOEX(USB_C1_IN_HPD, EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW) -IOEX(USB_C1_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW) -IOEX(USB_C1_PPC_EN_L, EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_LOW) -IOEX(USB_C1_PPC_ILIM_3A_EN, EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW) -IOEX_INT(USB_C1_SBU_FAULT_ODL, EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING, sbu_fault_interrupt) -IOEX(EN_PP5000_USB_A1_VBUS_DB, EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_LOW) -IOEX(USB_A1_LIMIT_SDP_DB, EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW) diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c deleted file mode 100644 index 344ea459de..0000000000 --- a/baseboard/guybrush/baseboard.c +++ /dev/null @@ -1,894 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush family-specific configuration */ - -#include "cros_board_info.h" -#include "base_fw_config.h" -#include "battery_fuel_gauge.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state_v2.h" -#include "charge_state.h" -#include "charger.h" -#include "chip/npcx/ps2_chip.h" -#include "chip/npcx/pwm_chip.h" -#include "chipset.h" -#include "driver/ppc/aoz1380.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/retimer/anx7491.h" -#include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" -#include "driver/tcpm/nct38xx.h" -#include "driver/usb_mux/anx7451.h" -#include "driver/usb_mux/amd_fp6.h" -#include "fan.h" -#include "fan_chip.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "ioexpander.h" -#include "isl9241.h" -#include "keyboard_scan.h" -#include "nct38xx.h" -#include "pi3usb9201.h" -#include "power.h" -#include "pwm.h" -#include "usb_mux.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -static void reset_nct38xx_port(int port); - -/* Wake Sources */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* Power Signal Input List */ -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S0_N] = { - .gpio = GPIO_PCH_SLP_S0_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S0_DEASSERTED", - }, - [X86_SLP_S3_N] = { - .gpio = GPIO_PCH_SLP_S3_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S3_DEASSERTED", - }, - [X86_SLP_S5_N] = { - .gpio = GPIO_PCH_SLP_S5_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S5_DEASSERTED", - }, - [X86_S0_PGOOD] = { - .gpio = GPIO_S0_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S0_PGOOD", - }, - [X86_S5_PGOOD] = { - .gpio = GPIO_S5_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S5_PGOOD", - }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A0_C0_SCL, - .sda = GPIO_EC_I2C_USB_A0_C0_SDA, - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A1_C1_SCL, - .sda = GPIO_EC_I2C_USB_A1_C1_SDA, - }, - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATT_SCL, - .sda = GPIO_EC_I2C_BATT_SDA, - }, - { - .name = "usb_mux", - .port = I2C_PORT_USB_MUX, - .kbps = 400, - .scl = GPIO_EC_I2C_USBC_MUX_SCL, - .sda = GPIO_EC_I2C_USBC_MUX_SDA, - }, - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 400, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA, - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_CBI_SCL, - .sda = GPIO_EC_I2C_CBI_SDA, - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA, - }, - { - .name = "soc_thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_EC_I2C_SOC_SIC, - .sda = GPIO_EC_I2C_SOC_SID, - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - - - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL9241_ADDR_FLAGS, - .drv = &isl9241_drv, - }, -}; - -const struct tcpc_config_t tcpc_config[] = { - [USBC_PORT_C0] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, - [USBC_PORT_C1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC1, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); -BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); - -const int usb_port_enable[USBA_PORT_COUNT] = { - IOEX_EN_PP5000_USB_A0_VBUS, - IOEX_EN_PP5000_USB_A1_VBUS_DB, -}; - -static void baseboard_interrupt_init(void) -{ - /* Enable Power Group interrupts. */ - gpio_enable_interrupt(GPIO_PG_GROUPC_S0_OD); - gpio_enable_interrupt(GPIO_PG_LPDDR4X_S3_OD); - - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); - - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); - - /* Enable BC 1.2 interrupts */ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); - - /* Enable SBU fault interrupts */ - ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL); - ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_ODL); -} -DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1); - -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { - [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); - -/* - * .init is not necessary here because it has nothing - * to do. Primary mux will handle mux state so .get is - * not needed as well. usb_mux.c can handle the situation - * properly. - */ -static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *); -struct usb_mux_driver usbc0_sbu_mux_driver = { - .set = fsusb42umx_set_mux, -}; - -/* - * Since FSUSB42UMX is not a i2c device, .i2c_port and - * .i2c_addr_flags are not required here. - */ -struct usb_mux usbc0_sbu_mux = { - .usb_port = USBC_PORT_C0, - .driver = &usbc0_sbu_mux_driver, -}; - -__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: PS8818 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_c1_ps8818_mux_set, -}; - -__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: ANX7451 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_anx7451 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS, - .driver = &anx7451_usb_mux_driver, - .board_set = &board_c1_anx7451_mux_set, -}; - -struct usb_mux usb_muxes[] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .next_mux = &usbc0_sbu_mux, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ - } -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); - -struct ioexpander_config_t ioex_config[] = { - [USBC_PORT_C0] = { - .i2c_host_port = I2C_PORT_TCPC0, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - }, - [USBC_PORT_C1] = { - .i2c_host_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT); -BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT); - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80us - */ - .output_settle_us = 80, - .debounce_down_us = 6 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 1500, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = SECOND, - .actual_key_mask = { - 0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { - .channel = 0, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000, - }, - [PWM_CH_KBLIGHT] = { - .channel = 1, - .flags = PWM_CONFIG_DSLEEP, - .freq = 100, - }, - [PWM_CH_LED_CHRG] = { - .channel = 2, - .flags = PWM_CONFIG_DSLEEP, - .freq = 100, - }, - [PWM_CH_LED_FULL] = { - .channel = 3, - .flags = PWM_CONFIG_DSLEEP, - .freq = 100, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -const struct mft_t mft_channels[] = { - [MFT_CH_0] = { - .module = NPCX_MFT_MODULE_1, - .clk_src = TCKC_LFCLK, - .pwm_id = PWM_CH_FAN, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); - -const struct fan_conf fan_conf_0 = { - .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ - .pgood_gpio = GPIO_S0_PGOOD, - .enable_gpio = -1, -}; -const struct fan_rpm fan_rpm_0 = { - .rpm_min = 1000, - .rpm_start = 1000, - .rpm_max = 6500, -}; -const struct fan_t fans[] = { - [FAN_CH_0] = { - .conf = &fan_conf_0, - .rpm = &fan_rpm_0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); - -/* - * USB C0 port SBU mux use standalone FSUSB42UMX - * chip and it needs a board specific driver. - * Overall, it will use chained mux framework. - */ -static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state, - bool *ack_required) -{ - /* This driver does not use host command ACKs */ - *ack_required = false; - - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); - - return EC_SUCCESS; -} - -static void setup_mux(void) -{ - switch (board_get_usb_c1_mux()) { - case USB_C1_MUX_PS8818: - CPRINTSUSB("C1: Setting PS8818 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818; - break; - case USB_C1_MUX_ANX7451: - CPRINTSUSB("C1: Setting ANX7451 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; - break; - default: - CPRINTSUSB("C1: Mux is unknown"); - } -} -DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int cur_port = charge_manager_get_active_charge_port(); - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * If this port had booted in dead battery mode, go - * ahead and reset it so EN_SNK responds properly. - */ - if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(cur_port); - pd_set_error_recovery(i); - } - - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - - /* Check if the port is sourcing VBUS. */ - if (tcpm_get_src_ctrl(port)) { - CPRINTSUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - /* - * Disallow changing ports if we booted in dead battery mode and don't - * have sufficient power to withstand Vbus loss. The NCT3807 may - * continue to keep EN_SNK low on the original port and allow a - * dangerous level of voltage to pass through to the initial charge - * port (see b/183660105) - * - * If we do have sufficient power, then reset the dead battery port and - * set up Type-C error recovery on its connection. - */ - if (cur_port != CHARGE_PORT_NONE && - port != cur_port && - nct38xx_get_boot_type(cur_port) == - NCT38XX_BOOT_DEAD_BATTERY) { - if (pd_is_battery_capable()) { - reset_nct38xx_port(cur_port); - pd_set_error_recovery(cur_port); - } else { - CPRINTSUSB("Battery too low for charge port change"); - return EC_ERROR_INVAL; - } - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -int board_is_i2c_port_powered(int port) -{ - switch (port) { - case I2C_PORT_USB_MUX: - case I2C_PORT_SENSOR: - /* USB mux and sensor i2c bus is unpowered in Z1 */ - return chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 0 : 1; - case I2C_PORT_THERMAL_AP: - /* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1; - default: - return 1; - } -} - -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) -{ - int rv; - - /* Use the TCPC to set the current limit */ - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); - - return rv; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -void sbu_fault_interrupt(enum ioex_signal signal) -{ - int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1; - - pd_handle_overcurrent(port); -} - -static void set_ac_prochot(void) -{ - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); -} -DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -static void reset_nct38xx_port(int port) -{ - enum gpio_signal reset_gpio_l; - - if (port == USBC_PORT_C0) - reset_gpio_l = GPIO_USB_C0_TCPC_RST_L; - else if (port == USBC_PORT_C1) - reset_gpio_l = GPIO_USB_C1_TCPC_RST_L; - else - /* Invalid port: do nothing */ - return; - - gpio_set_level(reset_gpio_l, 0); - msleep(NCT38XX_RESET_HOLD_DELAY_MS); - gpio_set_level(reset_gpio_l, 1); - nct38xx_reset_notify(port); - if (NCT3807_RESET_POST_DELAY_MS != 0) - msleep(NCT3807_RESET_POST_DELAY_MS); -} - - -void board_reset_pd_mcu(void) -{ - /* Reset TCPC0 */ - reset_nct38xx_port(USBC_PORT_C0); - - /* Reset TCPC1 */ - reset_nct38xx_port(USBC_PORT_C1); -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0) - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_INT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/** - * Return if VBUS is sagging too low - */ -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage = 0; - int rv; - - rv = charger_get_vbus_voltage(port, &voltage); - - if (rv) { - CPRINTSUSB("%s rv=%d", __func__, rv); - return 0; - } - - /* - * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown - * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. - * This partly defeats the point of ramping, but will still catch - * VBUS below 4.5V and above 0V. - */ - if (voltage == 0) { - CPRINTSUSB("%s vbus=0", __func__); - return 0; - } - - if (voltage < BC12_MIN_VOLTAGE) - CPRINTSUSB("%s vbus=%d", __func__, voltage); - - return voltage < BC12_MIN_VOLTAGE; -} - -/** - * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting - * PCH_PWRBTN_L. - */ -void board_pwrbtn_to_pch(int level) -{ - timestamp_t start; - const uint32_t timeout_rsmrst_rise_us = 30 * MSEC; - - /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ - if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) { - start = get_time(); - do { - usleep(200); - if (gpio_get_level(GPIO_PCH_RSMRST_L)) - break; - } while (time_since32(start) < timeout_rsmrst_rise_us); - - if (!gpio_get_level(GPIO_PCH_RSMRST_L)) - ccprints("Error pwrbtn: RSMRST_L still low"); - - msleep(G3_TO_PWRBTN_DELAY_MS); - } - gpio_set_level(GPIO_PCH_PWRBTN_L, level); -} - -void board_hibernate(void) -{ - int port; - - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851, b/143778351, b/147007265) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) { - pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); - - /* Give PD task and PPC chip time to get to 5V */ - msleep(SAFE_RESET_VBUS_DELAY_MS); - } - - /* Try to put our battery fuel gauge into sleep mode */ - if (battery_sleep_fuel_gauge() != EC_SUCCESS) - cprints(CC_SYSTEM, "Failed to send battery sleep command"); -} - -__overridable enum ec_error_list -board_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); - } while (rv && --tries); - - if (rv) { - CPRINTSUSB("A1: PS8811 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: PS8811 retimer detected"); - rv = board_a1_ps8811_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv); - return rv; -} - -/* PS8811 is just a type-A USB retimer, reusing mux structure for convience. */ -const struct usb_mux usba1_ps8811 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3, - .board_init = &baseboard_a1_ps8811_retimer_init, -}; - -__overridable enum ec_error_list -board_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val); - } while (rv && --tries); - if (rv) { - CPRINTSUSB("A1: ANX7491 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: ANX7491 retimer detected"); - rv = board_a1_anx7491_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv); - return rv; -} - -/* ANX7491 is just a type-A USB retimer, reusing mux structure for convience. */ -const struct usb_mux usba1_anx7491 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS, - .board_init = &baseboard_a1_anx7491_retimer_init, -}; - -void baseboard_a1_retimer_setup(void) -{ - struct usb_mux a1_retimer; - switch (board_get_usb_a1_retimer()) { - case USB_A1_RETIMER_ANX7491: - a1_retimer = usba1_anx7491; - break; - case USB_A1_RETIMER_PS8811: - a1_retimer = usba1_ps8811; - break; - default: - CPRINTSUSB("A1: Unknown retimer!"); - return; - } - a1_retimer.board_init(&a1_retimer); -} -DECLARE_DEFERRED(baseboard_a1_retimer_setup); - -static void baseboard_chipset_suspend(void) -{ - /* Disable display and keyboard backlights. */ - gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 1); - ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -static void baseboard_chipset_resume(void) -{ - /* Enable display and keyboard backlights. */ - gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 0); - ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1); - /* Some retimers take several ms to be ready, so defer setup call */ - hook_call_deferred(&baseboard_a1_retimer_setup_data, 20 * MSEC); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -void board_overcurrent_event(int port, int is_overcurrented) -{ - switch (port) { - case USBC_PORT_C0: - case USBC_PORT_C1: - gpio_set_level(GPIO_USB_C0_C1_FAULT_ODL, !is_overcurrented); - break; - - default: - break; - } -} - -void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) -{ - - /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ - gpio_set_level(GPIO_EN_PWR_PCORE_S0_R, - gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) && - gpio_get_level(GPIO_PG_GROUPC_S0_OD)); -} - -void baseboard_en_pwr_s0(enum gpio_signal signal) -{ - - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_set_level(GPIO_EN_PWR_S0_R, - gpio_get_level(GPIO_SLP_S3_L) && - gpio_get_level(GPIO_PG_PWR_S5)); - - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h deleted file mode 100644 index ef1338c5d5..0000000000 --- a/baseboard/guybrush/baseboard.h +++ /dev/null @@ -1,373 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* NPCX9 config */ -#define CONFIG_PORT80_4_BYTE -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - -/* Optional features */ -#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT -#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */ -#define CONFIG_I2C_DEBUG /* Print i2c traces */ -#define CONFIG_CMD_S5_TIMEOUT /* Allow a user-specified timeout to exit S5 */ - -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Vboot Config */ -#define CONFIG_CRC8 -#define CONFIG_VBOOT_EFS2 -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE - -/* CBI Config */ -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI - -/* Power Config */ -#define CONFIG_CHIPSET_X86_RSMRST_DELAY -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_HIBERNATE_PSL -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define G3_TO_PWRBTN_DELAY_MS 16 -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 -#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD -#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD -#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define SAFE_RESET_VBUS_DELAY_MS 900 -#define SAFE_RESET_VBUS_MV 5000 -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Thermal Config */ -#define CONFIG_ADC -#define CONFIG_AMD_SB_RMI -#define CONFIG_AMD_STT -#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_THROTTLE_AP -#define CONFIG_TEMP_SENSOR_SB_TSI -#define CONFIG_TEMP_SENSOR_TMP112 -#define CONFIG_THERMISTOR -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL - -/* Flash Config */ -/* See config_chip-npcx9.h for SPI flash configuration */ -#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */ -#define GPIO_WP_L GPIO_EC_WP_L - -/* Host communication */ -#define CONFIG_CMD_CHARGEN -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT -#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L - -/* Chipset config */ -#define CONFIG_CHIPSET_CEZANNE -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CHIPSET_RESET_HOOK - -/* Keyboard Config */ -#define CONFIG_KEYBOARD_BACKLIGHT - -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_VIVALDI -#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV - -/* Sensors */ -#ifdef HAS_TASK_MOTIONSENSE - -#define CONFIG_TABLET_MODE -#define CONFIG_GMR_TABLET_MODE -#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_LID_ANGLE -#define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL - -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is a power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs. */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - -/* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) -#endif /* HAS_TASK_MOTIONSENSE */ - -/* Backlight config */ -#define CONFIG_BACKLIGHT_LID -#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL - -/* Battery Config */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART -#define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 -#define CONFIG_HOSTCMD_BATTERY_V2 -#define CONFIG_BC12_DETECT_PI3USB9201 - -/* Charger Config */ -#define CONFIG_CHARGER -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9241 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - -/* - * EC will boot AP to depthcharge if: (BAT >= 2%) || (AC >= 50W) - * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on - * Depthcharge to boot OS. - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 - -/* - * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging - * but that feature of ISL9241 is broken (b/160287056) so we have to use - * CONFIG_CHARGE_RAMP_SW instead. - */ -#define CONFIG_CHARGE_RAMP_SW - -/* USB Type C and USB PD config */ -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_DRP_ACC_TRYSRC -/* TODO: Enable TCPMv2 Fast Role Swap (FRS) */ -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_CMD_TCPC_DUMP -#define CONFIG_USB_CHARGER -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_5V_EN_CUSTOM -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DISCHARGE_TCPC -#define CONFIG_USB_PD_DP_HPD_GPIO -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_NCT38XX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_VBUS_DETECT_TCPC -#define CONFIG_USBC_PPC -#define CONFIG_USBC_PPC_SBU -#define CONFIG_USBC_PPC_AOZ1380 -#define CONFIG_USBC_RETIMER_PI3HDX1204 -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USBC_PPC_NX20P3483 -#define CONFIG_USBC_RETIMER_PS8811 -#define CONFIG_USBC_RETIMER_PS8818 -#define CONFIG_USB_MUX_RUNTIME_CONFIG -#define CONFIG_USB_MUX_AMD_FP6 - -#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD -#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD - -#define CONFIG_IO_EXPANDER -#define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT - -/* TODO(b/176988382): Tune values for guybrush */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ - -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 -/* Max Power = 100 W */ -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) - -/* USB-A config */ -#define USB_PORT_COUNT USBA_PORT_COUNT -#define CONFIG_USB_PORT_POWER_SMART -#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY -#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP -#define CONFIG_USB_PORT_POWER_SMART_INVERTED - -#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP -#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB - -/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 - -/* - * USB ID - This is allocated specifically for Guybrush - */ -#define CONFIG_USB_PID 0x504D - -/* BC 1.2 */ -/* - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current - * until voltage drops to 4.5V. Don't go lower than this to be kind to the - * charger (see b/67964166). - */ -#define BC12_MIN_VOLTAGE 4500 - -/* I2C Bus Configuration */ -#define CONFIG_I2C -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_UPDATE_IF_CHANGED -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT4_1 -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -/* Volume Button Config */ -#define CONFIG_VOLUME_BUTTONS -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL - -/* Fan Config */ -#define CONFIG_FANS FAN_CH_COUNT -/* TODO: Set CONFIG_FAN_INIT_SPEED, defaults to 100 */ - -/* LED Config */ -#define CONFIG_PWM -#define CONFIG_PWM_KBLIGHT - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "registers.h" - -/* Power input signals */ -enum power_signal { - X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT, -}; - -/* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; - -/* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; - -/* TMP112 sensors */ -enum tmp112_sensor { - TMP112_SOC, - TMP112_AMB, - TMP112_COUNT, -}; - -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; - -/* PWM Channels */ -enum pwm_channel { - PWM_CH_FAN = 0, - PWM_CH_KBLIGHT, - PWM_CH_LED_CHRG, - PWM_CH_LED_FULL, - PWM_CH_COUNT -}; - -/* Fan Channels */ -enum fan_channel { - FAN_CH_0 = 0, - /* Number of FAN channels */ - FAN_CH_COUNT, -}; -enum mft_channel { - MFT_CH_0 = 0, - /* Number of MFT channels */ - MFT_CH_COUNT, -}; - -/* Common definition for the USB PD interrupt handlers. */ -void tcpc_alert_event(enum gpio_signal signal); -void bc12_interrupt(enum gpio_signal signal); -void ppc_interrupt(enum gpio_signal signal); -void sbu_fault_interrupt(enum ioex_signal signal); - -void baseboard_en_pwr_pcore_s0(enum gpio_signal signal); -void baseboard_en_pwr_s0(enum gpio_signal signal); - -int board_get_soc_temp_k(int idx, int *temp_k); - -/* CBI utility functions */ -uint32_t get_sku_id(void); -uint32_t get_board_version(void); -uint32_t get_fw_config(void); -/* Board callback after CBI has been initialized */ -__overridable void board_cbi_init(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk deleted file mode 100644 index 976ff2c931..0000000000 --- a/baseboard/guybrush/build.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Guybrush baseboard specific files build -# - -CHIP:=npcx -CHIP_FAMILY:=npcx9 -CHIP_VARIANT:=npcx9m3f - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o
\ No newline at end of file diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c deleted file mode 100644 index 6d66b826dc..0000000000 --- a/baseboard/guybrush/cbi.c +++ /dev/null @@ -1,96 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush CrOS Board Info(CBI) utilities */ - -#include "base_fw_config.h" -#include "console.h" -#include "common.h" -#include "cros_board_info.h" -#include "hooks.h" - -uint32_t get_sku_id(void) -{ - static uint32_t sku_id; - - if (sku_id == 0) { - uint32_t val; - - if (cbi_get_sku_id(&val) != EC_SUCCESS) - return 0; - sku_id = val; - } - return sku_id; -} - -uint32_t get_board_version(void) -{ - static uint32_t board_version; - - if (board_version == 0) { - uint32_t val; - - if (cbi_get_board_version(&val) != EC_SUCCESS) - return -1; - board_version = val; - } - return board_version; -} - -uint32_t get_fw_config(void) -{ - static uint32_t fw_config = UNINITIALIZED_FW_CONFIG; - - if (fw_config == UNINITIALIZED_FW_CONFIG) { - uint32_t val; - - if (cbi_get_fw_config(&val) != EC_SUCCESS) - return UNINITIALIZED_FW_CONFIG; - fw_config = val; - } - return fw_config; -} - - -int get_fw_config_field(uint8_t offset, uint8_t width) -{ - uint32_t fw_config = get_fw_config(); - - if (fw_config == UNINITIALIZED_FW_CONFIG) - return -1; - - return (fw_config >> offset) & ((1 << width) - 1); -} - - -__overridable void board_cbi_init(void) -{ -} - -static void cbi_init(void) -{ - uint32_t board_ver = get_board_version(); - uint32_t sku_id = get_sku_id(); - uint32_t fw_config = get_fw_config(); - - if (board_ver != 0) - ccprints("Board Version: %d (0x%x)", board_ver, board_ver); - else - ccprints("Board Version: not set in cbi"); - - if (sku_id != 0) - ccprints("SKU ID: %d (0x%x)", sku_id, sku_id); - else - ccprints("SKU ID: not set in cbi"); - - if (fw_config != UNINITIALIZED_FW_CONFIG) - ccprints("FW Config: %d (0x%x)", fw_config, fw_config); - else - ccprints("FW Config: not set in cbi"); - - /* Allow the board project to make runtime changes based on CBI data */ - board_cbi_init(); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c deleted file mode 100644 index 79725e827a..0000000000 --- a/baseboard/guybrush/usb_pd_policy.c +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Zork boards */ - -#include "charge_manager.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "ioexpander.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -int pd_check_vconn_swap(int port) -{ - /* - * Do not allow vconn swap 5V rail is off - * S5_PGOOD depends on PG_PP5000_S5 being asserted, - * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5 - */ - return gpio_get_level(GPIO_S5_PGOOD); -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -__override int board_pd_set_frs_enable(int port, int enable) -{ - /* - * Both PPCs require the FRS GPIO to be set as soon as FRS capability - * is established. - */ - if (port == 0) - ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable); - else if (port == 1) - ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable); - - return EC_SUCCESS; -} - -/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */ -int board_vbus_source_enabled(int port) -{ - return tcpm_get_src_ctrl(port); -} - -/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */ -int board_is_sourcing_vbus(int port) -{ - return board_vbus_source_enabled(port); -} diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c deleted file mode 100644 index dd93e581cf..0000000000 --- a/baseboard/hatch/baseboard.c +++ /dev/null @@ -1,397 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hatch family-specific configuration */ -#include "atomic.h" -#include "battery_fuel_gauge.h" -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "chipset.h" -#include "console.h" -#include "cros_board_info.h" -#include "driver/charger/bq25710.h" -#include "driver/ppc/sn5s330.h" -#include "driver/tcpm/anx7447.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "ec_commands.h" -#include "espi.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "power.h" -#include "stdbool.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "timer.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_ACOK_OD, - GPIO_POWER_BUTTON_L, - /* EC_RST_ODL needs to wake device while in PSL hibernate. */ - GPIO_SYS_RESET_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { -#ifdef CONFIG_ACCEL_FIFO - {"sensor", I2C_PORT_SENSOR, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, -#endif - {"ppc0", I2C_PORT_PPC0, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - {"tcpc1", I2C_PORT_TCPC1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, -#endif - {"tcpc0", I2C_PORT_TCPC0, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, -#ifdef BOARD_AKEMI - {"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, -#endif -#ifdef BOARD_JINLON - {"thermal", I2C_PORT_THERMAL, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, -#endif -#ifdef BOARD_MUSHU - {"f75303_temp", I2C_PORT_THERMAL, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, - {"gpu_temp", I2C_PORT_GPU, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, -#endif - {"power", I2C_PORT_POWER, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}, - {"eeprom", I2C_PORT_EEPROM, 100, GPIO_I2C7_SCL, GPIO_I2C7_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/******************************************************************************/ -/* Charger Chip Configuration */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, - .drv = &bq25710_drv, - }, -}; - -/******************************************************************************/ -/* Chipset callbacks/hooks */ - -__attribute__((weak)) bool board_has_kb_backlight(void) -{ - /* Default enable keyboard backlight */ - return true; -} - -/* Called on AP S0iX -> S0 transition */ -static void baseboard_chipset_resume(void) -{ - if (board_has_kb_backlight()) - gpio_set_level(GPIO_EC_KB_BL_EN, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S0iX transition */ -static void baseboard_chipset_suspend(void) -{ - if (board_has_kb_backlight()) - gpio_set_level(GPIO_EC_KB_BL_EN, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -void board_hibernate(void) -{ - int port; - - /* - * To support hibernate from ectool, keyboard, and console, - * ensure that the AP is fully shutdown before hibernating. - */ -#ifdef HAS_TASK_CHIPSET - chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); -#endif - - /* - * If VBUS is not being provided by any of the PD ports, - * then enable the SNK FET to allow AC to pass through - * if it is later connected to ensure that AC_PRESENT - * will wake up the EC from this state - */ - for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) - ppc_vbus_sink_enable(port, 1); - - /* - * This seems like a hack, but the AP chipset state machine - * needs time to work through the transitions. Also, it - * works. - */ - msleep(300); -} - -/******************************************************************************/ -/* USB-C PPC Configuration */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, -#endif -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* Power Delivery and charging functions */ -void baseboard_tcpc_init(void) -{ - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL); - /* Enable BC 1.2 interrupts */ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); - -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); - /* Enable BC 1.2 interrupts */ - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); -#endif -} -DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int level; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) { - level = !!(tcpc_config[USB_PD_PORT_TCPC_0].flags & - TCPC_FLAGS_RESET_ACTIVE_HIGH); - if (gpio_get_level(GPIO_USB_C0_TCPC_RST) != level) - status |= PD_STATUS_TCPC_ALERT_0; - } - -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) { - level = !!(tcpc_config[USB_PD_PORT_TCPC_1].flags & - TCPC_FLAGS_RESET_ACTIVE_HIGH); - if (gpio_get_level(GPIO_USB_C1_TCPC_RST) != level) - status |= PD_STATUS_TCPC_ALERT_1; - } -#endif - - return status; -} - -static void reset_pd_port(int port, enum gpio_signal reset_gpio, - int hold_delay, int finish_delay) -{ - int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH); - - gpio_set_level(reset_gpio, level); - msleep(hold_delay); - gpio_set_level(reset_gpio, !level); - if (finish_delay) - msleep(finish_delay); -} - -void board_reset_pd_mcu(void) -{ - /* - * TODO(b/130194590): This should be replaced with a common function - * once the gpio signal and delays are added to tcpc_config struct. - */ - - /* Assert reset to TCPC for required delay only if we have a battery. */ - if (battery_is_present() != BP_YES) - return; - - /* Reset TCPC0 */ - reset_pd_port(USB_PD_PORT_TCPC_0, GPIO_USB_C0_TCPC_RST, - BOARD_TCPC_C0_RESET_HOLD_DELAY, - BOARD_TCPC_C0_RESET_POST_DELAY); - -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - /* Reset TCPC1 */ - reset_pd_port(USB_PD_PORT_TCPC_1, GPIO_USB_C1_TCPC_RST, - BOARD_TCPC_C1_RESET_HOLD_DELAY, - BOARD_TCPC_C1_RESET_POST_DELAY); -#endif -} - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -int ppc_get_alert_status(int port) -{ - if (port == USB_PD_PORT_TCPC_0) - return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; - return port == USB_PD_PORT_TCPC_0 ? - gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 : -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; -#else - EC_SUCCESS; -#endif -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -#ifdef USB_PD_PORT_TCPC_MST -void baseboard_mst_enable_control(enum mst_source src, int level) -{ - static uint32_t mst_input_levels; - - if (level) - atomic_or(&mst_input_levels, 1 << src); - else - atomic_clear_bits(&mst_input_levels, 1 << src); - - gpio_set_level(GPIO_EN_MST, mst_input_levels ? 1 : 0); -} -#endif - -/* Enable or disable input devices, based on chipset state */ -__override void lid_angle_peripheral_enable(int enable) -{ - if (board_is_convertible()) { - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - enable = 0; - keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE); - } -} - -static uint8_t sku_id; -static uint8_t board_id; - -uint8_t get_board_sku(void) -{ - return sku_id; -} - -uint8_t get_board_id(void) -{ - return board_id; -} - -/* Read CBI from i2c eeprom and initialize variables for board variants */ -static void cbi_init(void) -{ - uint32_t val; - - /* SKU ID */ - if (cbi_get_sku_id(&val) != EC_SUCCESS || val > UINT8_MAX) { - CPRINTS("Read SKU Error value :%d", val); - return; - } - - sku_id = val; - - CPRINTS("SKU: %d", sku_id); - - /* Board ID */ - if (cbi_get_board_version(&val) != EC_SUCCESS || val > UINT8_MAX) { - CPRINTS("Read Board ID Error (%d)", val); - } - - board_id = val; - - CPRINTS("Board ID: %d", board_id); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); - -__override enum ec_pd_port_location board_get_pd_port_location(int port) -{ - switch (port) { - case 0: - return EC_PD_PORT_LOCATION_LEFT_BACK; - case 1: - return EC_PD_PORT_LOCATION_RIGHT_BACK; - default: - return EC_PD_PORT_LOCATION_UNKNOWN; - } -} diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h deleted file mode 100644 index bf9140b33f..0000000000 --- a/baseboard/hatch/baseboard.h +++ /dev/null @@ -1,222 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hatch baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#include "compiler.h" -#include "stdbool.h" - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) -#undef CONFIG_HOSTCMD_DEBUG_MODE -#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF - -/* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -/* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#define CONFIG_I2C - -/* Optional console commands */ -#define CONFIG_CMD_CHARGER_DUMP - -/* EC Defines */ -#define CONFIG_ADC -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CRC8 -#define CONFIG_CBI_EEPROM -#define CONFIG_DPTF -#define CONFIG_HIBERNATE_PSL -#define CONFIG_LED_ONOFF_STATES -#define CONFIG_LTO -#define CONFIG_PWM -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -/* Chipset config */ -#define CONFIG_CHIPSET_COMETLAKE -#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE - -/* Common Keyboard Defines */ -#define CONFIG_CMD_KEYBOARD -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_KEYPAD -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 - -/* Sensors */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT - -/* Don't wake up from suspend on any MKBP event */ -#define CONFIG_MKBP_EVENT_WAKEUP_MASK 0 - -/* I2C_PORT_ACCEL needs to be defined for i2c transactions */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR - -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#if !defined(BOARD_PALKIA) -#define CONFIG_ACCEL_FIFO -/* FIFO size is in power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - -/* Sensor console commands */ -#define CONFIG_CMD_ACCELS -#define CONFIG_CMD_ACCEL_INFO -#endif /* !BOARD_PALKIA */ - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT -#define CONFIG_CHARGER -#define CONFIG_CHARGER_BQ25710 -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */ -#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -/* - * Don't allow the system to boot to S0 when the battery is low and unable to - * communicate on locked systems (which haven't PD negotiated) - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 - -/* Common battery defines */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_HW_PRESENT_CUSTOM -#define CONFIG_BATTERY_PRESENT_CUSTOM -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART -#undef CONFIG_BATT_HOST_FULL_FACTOR -#define CONFIG_BATT_HOST_FULL_FACTOR 100 - -/* USB Type C and USB PD defines */ -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV1 -#if defined(BOARD_PALKIA) -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -#else -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#endif -#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USBC_PPC_SN5S330 -#define CONFIG_USBC_PPC_VCONN -#define CONFIG_USBC_SS_MUX -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USBC_PPC_DEDICATED_INT - -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_CMD_PPC_DUMP - -/* Include CLI command needed to support CCD testing. */ -#define CONFIG_CMD_CHARGEN - -#define USB_PD_PORT_TCPC_0 0 -#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 -#define USB_PD_PORT_TCPC_1 1 -#endif - -/* BC 1.2 */ -#define CONFIG_USB_CHARGER - -#if !defined(BOARD_PALKIA) -/* Common Sensor Defines */ -#define CONFIG_TABLET_MODE -#endif - -/* TODO(b/122273953): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* TODO(b/122273953): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/* I2C Bus Configuration */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER - -/* Other common defines */ -#define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD - -#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) - -#ifndef __ASSEMBLER__ - -enum mst_source { - MST_TYPE_C0, - MST_TYPE_C1, - MST_HDMI, -}; - -/* Forward declare common (within Hatch) board-specific functions */ -bool board_has_kb_backlight(void); -unsigned char get_board_sku(void); -unsigned char get_board_id(void); -void board_reset_pd_mcu(void); -void baseboard_mst_enable_control(enum mst_source, int level); -bool board_is_convertible(void); - -FORWARD_DECLARE_ENUM(battery_present); - -/* Check with variant about battery presence. */ -enum battery_present variant_battery_present(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c deleted file mode 100644 index 063aa3721d..0000000000 --- a/baseboard/hatch/battery.c +++ /dev/null @@ -1,80 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery.h" -#include "battery_fuel_gauge.h" -#include "battery_smart.h" -#include "gpio.h" -#include "system.h" - -static enum battery_present batt_pres_prev = BP_NOT_SURE; - -enum battery_present __attribute__((weak)) variant_battery_present(void) -{ - return BP_NOT_SURE; -} - -enum battery_present battery_hw_present(void) -{ - enum battery_present bp = variant_battery_present(); - - if (bp != BP_NOT_SURE) - return bp; - - return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES; -} - -static int battery_init(void) -{ - int batt_status; - - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); -} - -/* - * Physical detection of battery. - */ -static enum battery_present battery_check_present_status(void) -{ - enum battery_present batt_pres; - - /* Get the physical hardware status */ - batt_pres = battery_hw_present(); - - /* - * If the battery is not physically connected, then no need to perform - * any more checks. - */ - if (batt_pres != BP_YES) - return batt_pres; - - /* - * If the battery is present now and was present last time we checked, - * return early. - */ - if (batt_pres == batt_pres_prev) - return batt_pres; - - /* - * Ensure that battery is: - * 1. Not in cutoff - * 2. Initialized - */ - if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL || - battery_init() == 0) { - batt_pres = BP_NO; - } - - return batt_pres; -} - -enum battery_present battery_is_present(void) -{ - batt_pres_prev = battery_check_present_status(); - return batt_pres_prev; -} diff --git a/baseboard/hatch/build.mk b/baseboard/hatch/build.mk deleted file mode 100644 index 864225f605..0000000000 --- a/baseboard/hatch/build.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Hatch baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-$(CONFIG_BATTERY_SMART)+=battery.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c deleted file mode 100644 index a66bfefe87..0000000000 --- a/baseboard/hatch/usb_pd_policy.c +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Hatch boards */ - -#include "charge_manager.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "tcpm/tcpm.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if pp5000_A rail is enabled */ - return gpio_get_level(GPIO_EN_PP5000_A); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Give back the current quota we are no longer using */ - charge_manager_source_port(port, 0); -#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */ - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Ensure we advertise the proper available current quota */ - charge_manager_source_port(port, 1); -#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */ - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} -#endif - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c deleted file mode 100644 index 3103aaf4c5..0000000000 --- a/baseboard/herobrine/baseboard.c +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Herobrine baseboard-specific configuration */ - -#include "i2c.h" - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY); -} diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h deleted file mode 100644 index 108f7f8cf5..0000000000 --- a/baseboard/herobrine/baseboard.h +++ /dev/null @@ -1,218 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Herobrine baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted event and HC: - * The sensor stack is generating a lot of activity. - * They can be enabled through the console command 'chan'. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) - -/* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - -/* Internal SPI flash on NPCX7 */ -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - -/* EC Modules */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_VIRTUAL_BATTERY -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_LED_COMMON -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_ADC -#define CONFIG_BACKLIGHT_LID -#define CONFIG_FPU -#define CONFIG_PWM -#define CONFIG_PWM_DISPLIGHT -#define CONFIG_HIBERNATE_PSL - -#define CONFIG_VBOOT_HASH - -#undef CONFIG_PECI - -#define CONFIG_HOSTCMD_SHI -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_HOSTCMD_SECTION_SORTED -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_MKBP_USE_GPIO - -#define CONFIG_BOARD_VERSION_GPIO -#define CONFIG_CBI_GPIO -#define CONFIG_CRC8 -#define CONFIG_POWER_BUTTON -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_EMULATED_SYSRQ -#define CONFIG_CMD_BUTTON -#define CONFIG_SWITCH -#define CONFIG_LID_SWITCH -#define CONFIG_EXTPOWER_GPIO - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Increase console output buffer since we have the RAM available. */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL -#define CONFIG_BATTERY_SMART - -/* Charger */ -#define CONFIG_CHARGER -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER_ISL9238 -#define CONFIG_CHARGER_PROFILE_OVERRIDE -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_USB_CHARGER -#define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_PSYS -#define CONFIG_CHARGER_PSYS_READ -#define CONFIG_CHARGER_DISCHARGE_ON_AC - -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - -/* - * USB ID - * - * This is allocated specifically for Herobrine - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x5055 - -/* USB */ -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_CMD_TCPC_DUMP -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC -#define CONFIG_USB_PD_5V_EN_CUSTOM -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* RTC */ -#define CONFIG_CMD_RTC -#define CONFIG_HOSTCMD_RTC - -/* Sensors */ -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is a power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs. */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#define CONFIG_CMD_ACCELS -#define CONFIG_CMD_ACCEL_INFO - -/* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/* Chipset */ -#define CONFIG_CHIPSET_SC7280 -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CHIPSET_RESUME_INIT_HOOK -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_CMD_AP_RESET_LOG - -/* - * Macros for GPIO signals used in common code that don't match the - * schematic names. Signal names in gpio.inc match the schematic and are - * then redefined here to so it's more clear which signal is being used for - * which purpose. - */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV - -/* I2C Ports */ -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_RTC NPCX_I2C_PORT4_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - -/* UART */ -#define CONFIG_CMD_CHARGEN - -/* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) - -/* And the MKBP events */ -#ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) -#else -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) -#endif - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk deleted file mode 100644 index f007fd7118..0000000000 --- a/baseboard/herobrine/build.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y+=baseboard.o -baseboard-y+=usbc_config.o -baseboard-y+=usb_pd_policy.o diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c deleted file mode 100644 index 7ca2688aef..0000000000 --- a/baseboard/herobrine/usb_pd_policy.c +++ /dev/null @@ -1,262 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "chipset.h" -#include "console.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* In G3, do not allow vconn swap since PP5000 rail is off */ - return gpio_get_level(GPIO_EN_PP5000); -} - -static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -#if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; -#else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; -#endif - -static void board_vbus_update_source_current(int port) -{ - /* Both port are controlled by PPC SN5S330. */ - ppc_set_vbus_source_current_limit(port, vbus_rp[port]); - ppc_vbus_source_enable(port, vbus_en[port]); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = vbus_en[port]; - - /* Disable VBUS */ - vbus_en[port] = 0; - board_vbus_update_source_current(port); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - /* Disable charging */ - board_vbus_sink_enable(port, 0); - - pd_set_vbus_discharge(port, 0); - - /* Provide VBUS */ - vbus_en[port] = 1; - board_vbus_update_source_current(port); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; /* we are ready */ -} - -int board_vbus_source_enabled(int port) -{ - return vbus_en[port]; -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - vbus_rp[port] = rp; - board_vbus_update_source_current(port); -} - -int pd_snk_is_vbus_provided(int port) -{ - return tcpm_check_vbus_level(port, VBUS_PRESENT); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -#ifdef CONFIG_USB_PD_ALT_MODE_DFP -__override int svdm_dp_config(int port, uint32_t *payload) -{ - int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); - uint8_t pin_mode = get_dp_pin_mode(port); - - if (!pin_mode) - return 0; - - /* - * Defer setting the usb_mux until HPD goes high, svdm_dp_attention(). - * The AP only supports one DP phy. An external DP mux switches between - * the two ports. Should switch those muxes when it is really used, - * i.e. HPD high; otherwise, the real use case is preempted, like: - * (1) plug a dongle without monitor connected to port-0, - * (2) plug a dongle without monitor connected to port-1, - * (3) plug a monitor to the port-1 dongle. - */ - - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ - return 2; -}; - -__override void svdm_dp_post_config(int port) -{ - dp_flags[port] |= DP_FLAGS_DP_ON; -} - -/** - * Is the port fine to be muxed its DisplayPort lines? - * - * Only one port can be muxed to DisplayPort at a time. - * - * @param port Port number of TCPC. - * @return 1 is fine; 0 is bad as other port is already muxed; - */ -static int is_dp_muxable(int port) -{ - int i; - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) - if (i != port) { - if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) - return 0; - } - - return 1; -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET; - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); - int cur_lvl = gpio_get_level(hpd); - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - if (!is_dp_muxable(port)) { - /* TODO(waihong): Info user? */ - CPRINTS("p%d: The other port is already muxed.", port); - return 0; - } - - /* - * Initial implementation to handle HPD. Only the first-plugged port - * works, i.e. sending HPD signal to AP. The second-plugged port - * will be ignored. - * - * TODO(waihong): Continue the above case, if the first-plugged port - * is then unplugged, switch to the second-plugged port and signal AP? - */ - if (lvl) { - /* - * Enable and switch the DP port selection mux to the - * correct port. - * - * TODO(waihong): Better to move switching DP mux to - * the usb_mux abstraction. - */ - gpio_set_level(GPIO_DP_MUX_SEL, port == 1); - gpio_set_level(GPIO_DP_MUX_OE_L, 0); - - /* Connect the SBU lines in PPC chip. */ - if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) - ppc_set_sbu(port, 1); - - /* - * Connect the USB SS/DP lines in TCPC chip. - * - * When mf_pref not true, still use the dock muxing - * because of the board USB-C topology (limited to 2 - * lanes DP). - */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - } else { - /* Disconnect the DP port selection mux. */ - gpio_set_level(GPIO_DP_MUX_OE_L, 1); - gpio_set_level(GPIO_DP_MUX_SEL, 0); - - /* Disconnect the SBU lines in PPC chip. */ - if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) - ppc_set_sbu(port, 0); - - /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - } - - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) - /* - * Wake up the AP. IRQ or level high indicates a DP sink is now - * present. - */ - pd_notify_dp_alt_mode_entry(port); - - /* Configure TCPC for the HPD event, for proper muxing */ - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - - /* Signal AP for the HPD event, through GPIO to AP */ - if (irq & cur_lvl) { - uint64_t now = get_time().val; - /* Wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* Generate IRQ_HPD pulse */ - gpio_set_level(hpd, 0); - usleep(HPD_DSTREAM_DEBOUNCE_IRQ); - gpio_set_level(hpd, 1); - - /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } else if (irq & !lvl) { - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; - } else { - gpio_set_level(hpd, lvl); - /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } - - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ - if (is_dp_muxable(port)) { - /* Disconnect the DP port selection mux. */ - gpio_set_level(GPIO_DP_MUX_OE_L, 1); - gpio_set_level(GPIO_DP_MUX_SEL, 0); - - /* Signal AP for the HPD low event */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); - } -} -#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c deleted file mode 100644 index 5e613c40a5..0000000000 --- a/baseboard/herobrine/usbc_config.c +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Herobrine family-specific USB-C configuration */ - -#include "charger.h" -#include "charger/isl923x_public.h" -#include "charge_state.h" -#include "usb_pd.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - -int charger_profile_override(struct charge_state_data *curr) -{ - int usb_mv; - int port; - - if (curr->state != ST_CHARGE) - return 0; - - /* Lower the max requested voltage to 5V when battery is full. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && - !(curr->batt.flags & BATT_FLAG_BAD_STATUS) && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) - usb_mv = 5000; - else - usb_mv = PD_MAX_VOLTAGE_MV; - - if (pd_get_max_voltage() != usb_mv) { - CPRINTS("VBUS limited to %dmV", usb_mv); - for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) - pd_set_external_voltage_limit(port, usb_mv); - } - - return 0; -} - -enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) -{ - return EC_RES_INVALID_PARAM; -} - -enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) -{ - return EC_RES_INVALID_PARAM; -} diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c deleted file mode 100644 index df56697fbf..0000000000 --- a/baseboard/honeybuns/baseboard.c +++ /dev/null @@ -1,489 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Honeybuns family-specific configuration */ -#include "console.h" -#include "cros_board_info.h" -#include "driver/mp4245.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "usb_pd.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "usbc_ppc.h" -#include "driver/tcpm/tcpm.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -#define POWER_BUTTON_SHORT_USEC (300 * MSEC) -#define POWER_BUTTON_LONG_USEC (5000 * MSEC) -#define POWER_BUTTON_DEBOUNCE_USEC (30) - -#define BUTTON_EVT_CHANGE BIT(0) -#define BUTTON_EVT_INFO BIT(1) - -enum power { - POWER_OFF, - POWER_ON -}; - -enum button { - BUTTON_RELEASE, - BUTTON_PRESS, - BUTTON_PRESS_POWER_ON, - BUTTON_PRESS_SHORT, - BUTTON_PRESS_LONG, -}; - -#define LED_ON_OFF_BIT BIT(0) -#define LED_COLOR_BIT BIT(2) -#define LED_FLASH_SEQ_LENGTH 8 - -enum led_color { - GREEN, - YELLOW, - OFF, -}; - -static enum power dock_state; -#ifdef SECTION_IS_RW -static int button_level; -static int button_level_pending; -static int dock_mf; -static int led_count; -#endif - -/******************************************************************************/ - -__maybe_unused static void board_power_sequence(int enable) -{ - int i; - - if (enable) { - for(i = 0; i < board_power_seq_count; i++) { - gpio_set_level(board_power_seq[i].signal, - board_power_seq[i].level); - CPRINTS("power seq: rail = %d", i); - if (board_power_seq[i].delay_ms) - msleep(board_power_seq[i].delay_ms); - } - } else { - for(i = board_power_seq_count - 1; i >= 0; i--) { - gpio_set_level(board_power_seq[i].signal, - !board_power_seq[i].level); - CPRINTS("sequence[%d]: level = %d", i, - !board_power_seq[i].level); - } - } - - dock_state = enable; - CPRINTS("board: Power rails %s", dock_state ? "on" : "off"); -} - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { - {"i2c1", I2C_PORT_I2C1, 400, GPIO_EC_I2C1_SCL, GPIO_EC_I2C1_SDA}, - {"i2c3", I2C_PORT_I2C3, 400, GPIO_EC_I2C3_SCL, GPIO_EC_I2C3_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -#ifdef SECTION_IS_RW -static void baseboard_set_led(enum led_color color) -{ - /* - * TODO(b/164157329): The power button feature should be connected to a - * 2 color LED which is part of the button. Currently, the power button - * LED is a single color LED which is controlled by on the of the power - * rails. Using the status LED now to demonstrate the LED behavior - * associated with a power button press. - */ - CPRINTS("led: color = %d", color); - - /* Not all boards may have LEDs under EC control */ -#if defined(GPIO_PWR_BUTTON_RED) && defined(GPIO_PWR_BUTTON_GREEN) - if (color == OFF) { - gpio_set_level(GPIO_PWR_BUTTON_RED, 1); - gpio_set_level(GPIO_PWR_BUTTON_GREEN, 1); - } else if (color == GREEN) { - gpio_set_level(GPIO_PWR_BUTTON_RED, 1); - gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0); - } else if (color == YELLOW) { - gpio_set_level(GPIO_PWR_BUTTON_RED, 0); - gpio_set_level(GPIO_PWR_BUTTON_GREEN, 0); - } -#endif -} - -static void baseboard_led_callback(void); -DECLARE_DEFERRED(baseboard_led_callback); - -static void baseboard_led_callback(void) -{ - /* - * Flash LED on transition using a simple 3 bit counter. Bit 0 controls - * LED on/off and bit 2 controls which color to set during the on phase. - */ - int color = led_count & LED_COLOR_BIT ? dock_mf : dock_mf ^ 1; - - /* - * TODO(b/164157329): This function implements a simple flashing - * transition when the MF preference bit is changed via a long power - * button press sequence. This might need to move to the board function - * if not required/desired on all variants. - */ - - if (led_count & LED_ON_OFF_BIT) - baseboard_set_led(color); - else - baseboard_set_led(OFF); - - /* Flash sequence is 8 steps */ - if (++led_count < LED_FLASH_SEQ_LENGTH) - hook_call_deferred(&baseboard_led_callback_data, 150 * MSEC); -} - -static void baseboard_change_mf_led(void) -{ - led_count = 0; - baseboard_led_callback(); -} - -void baseboard_set_mst_lane_control(int mf) -{ - /* - * The parameter mf reflects the desired lane control value. If the - * current value does not match the desired, then the MST hub must first - * be put into reset, so the MST hub will latch in the correct value - * when it's taken out of reset. - */ - if (mf != gpio_get_level(GPIO_MST_HUB_LANE_SWITCH)) { - /* put MST into reset */ - gpio_set_level(GPIO_MST_RST_L, 0); - msleep(1); - gpio_set_level(GPIO_MST_HUB_LANE_SWITCH, mf); - CPRINTS("MST: lane control = %s", mf ? "high" : "low"); - msleep(1); - /* lane control is set, take MST out of reset */ - gpio_set_level(GPIO_MST_RST_L, 1); - } -} - -static void baseboard_enable_mp4245(void) -{ - int mv; - int ma; - - mp4245_set_voltage_out(5000); - mp4245_votlage_out_enable(1); - msleep(MP4245_VOUT_5V_DELAY_MS); - mp3245_get_vbus(&mv, &ma); - CPRINTS("mp4245: vout @ %d mV enabled", mv); -} - -#endif /* SECTION_IS_RW */ - -static void baseboard_init(void) -{ -#ifdef SECTION_IS_RW - uint32_t fw_config; -#endif - - /* Turn on power rails */ - board_power_sequence(1); - CPRINTS("board: Power rails enabled"); - -#ifdef SECTION_IS_RW - /* Force TC state machine to start in TC_ERROR_RECOVERY */ - system_clear_reset_flags(EC_RESET_FLAG_POWER_ON); - /* Make certain SN5S330 PPC does full initialization */ - system_set_reset_flags(EC_RESET_FLAG_EFS); - - /* - * Dock multi function (mf) preference is stored in bit 0 of fw_config - * field of the CBI. If this value is programmed, then make sure the - * MST_LANE_CONTROL gpio matches the mf bit. - */ - if (!cbi_get_fw_config(&fw_config)) { - dock_mf = CBI_FW_MF_PREFERENCE(fw_config); - baseboard_set_mst_lane_control(dock_mf); - } else { - dock_mf = dock_get_mf_preference(); - cbi_set_fw_config(dock_mf); - CPRINTS("cbi: setting default result = %s", - cbi_get_fw_config(&fw_config) ? "pass" : "fail"); - } - -#ifdef GPIO_USBC_UF_ATTACHED_SRC - /* Configure UF usbc ppc and check usbc state */ - baseboard_config_usbc_usb3_ppc(); -#endif /* GPIO_USBC_UF_ATTACHED_SRC */ - - /* Enable power button interrupt */ - gpio_enable_interrupt(GPIO_PWR_BTN); - /* Set dock mf preference LED */ - baseboard_set_led(dock_mf); - /* Setup VBUS to default value */ - baseboard_enable_mp4245(); - -#else - /* Set up host port usbc to present Rd on CC lines */ - if(baseboard_usbc_init(USB_PD_PORT_HOST)) - CPRINTS("usbc: Failed to set up sink path"); - else - CPRINTS("usbc: sink path configure success!"); -#endif /* SECTION_IS_RW */ -} -/* - * Power sequencing must run before any other chip init is attempted, so run - * power sequencing as soon as I2C bus is initialized. - */ -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_INIT_I2C + 1); - -#ifdef SECTION_IS_RW -static void baseboard_power_on(void) -{ - int port_max = board_get_usb_pd_port_count(); - int port; - - CPRINTS("pwrbtn: power on: mf = %d", dock_mf); - /* Adjust system flags to full PPC init occurs */ - system_clear_reset_flags(EC_RESET_FLAG_POWER_ON); - system_set_reset_flags(EC_RESET_FLAG_EFS); - /* Enable power rails and release reset signals */ - board_power_sequence(1); - /* Set VBUS to 5V and enable output from mp4245 */ - baseboard_enable_mp4245(); - /* Set dock mf preference LED */ - baseboard_set_led(dock_mf); - /* - * Lane control (realtek MST) must be set prior to releasing MST - * reset. - */ - baseboard_set_mst_lane_control(dock_mf); - /* - * When the power to the PPC is turned off, then back on, the PPC will - * default into dead battery mode. Dead battery resistors are disabled - * as part of the full PPC intializaiton sequence. This is required to - * force a detach event with port parter which can be attached as usbc - * source when honeybuns power rails are off. - */ - for (port = 0; port < port_max; port++) { - ppc_init(port); - msleep(1000); - /* Inform TC state machine that it can resume */ - pd_set_suspend(port, 0); - } - /* Enable usbc interrupts */ - board_enable_usbc_interrupts(); - -#ifdef GPIO_USBC_UF_ATTACHED_SRC - baseboard_config_usbc_usb3_ppc(); -#endif -} - -static void baseboard_power_off(void) -{ - int port_max = board_get_usb_pd_port_count(); - int port; - - CPRINTS("pwrbtn: power off"); - /* Put ports in TC suspend state */ - for (port = 0; port < port_max; port++) - pd_set_suspend(port, 1); - - /* Disable ucpd peripheral (prevents interrupts) */ - tcpm_release(USB_PD_PORT_HOST); - /* Disable PPC/TCPC interrupts */ - board_disable_usbc_interrupts(); - -#ifdef GPIO_USBC_UF_ATTACHED_SRC - /* Disable PPC interrupts for PS8803 managed port */ - baseboard_usbc_usb3_enable_interrupts(0); -#endif - /* Set dock power button/MF preference LED */ - baseboard_set_led(OFF); - /* Go into power off state */ - board_power_sequence(0); -} - -static void baseboard_toggle_mf(void) -{ - uint32_t fw_config; - - if (!cbi_get_fw_config(&fw_config)) { - /* Update the user MF preference stored in CBI */ - fw_config ^= CBI_FW_MF_MASK; - cbi_set_fw_config(fw_config); - /* Update variable used to track user MF preference */ - dock_mf = CBI_FW_MF_PREFERENCE(fw_config); - /* Flash led for visual indication of user MF change */ - baseboard_change_mf_led(); - - /* - * Suspend, then release host port to force new MF setting to - * take effect. - */ - pd_set_suspend(USB_PD_PORT_HOST, 1); - msleep(250); - pd_set_suspend(USB_PD_PORT_HOST, 0); - } -} - -/* - * Main task entry point for UCPD task - */ -void power_button_task(void *u) -{ - int timer_us = POWER_BUTTON_DEBOUNCE_USEC * 4; - enum button state = BUTTON_RELEASE; - uint32_t evt; - - /* - * Capture current button level in case it's being pressed when the dock - * is powered on. Note timer_us is initialized for debounce time to - * double check. - */ - button_level = gpio_get_level(GPIO_PWR_BTN); - - while (1) { - evt = task_wait_event(timer_us); - timer_us = -1; - - if (evt == BUTTON_EVT_INFO) { - /* Only used for console command for debug */ - CPRINTS("pwrbtn: pwr = %d, state = %d, level = %d", - dock_state, state, button_level); - continue; - } - - switch (state) { - case BUTTON_RELEASE: - /* - * Default wait state: Only need to check if the button - * is pressed and start the short press timer. - */ - if (evt & BUTTON_EVT_CHANGE && button_level == - BUTTON_PRESSED_LEVEL) { - state = BUTTON_PRESS; - timer_us = (POWER_BUTTON_SHORT_USEC - - POWER_BUTTON_DEBOUNCE_USEC); - } - break; - case BUTTON_PRESS: - /* - * Validate short press by ensuring that button is still - * pressed after short press timer expires. - */ - if (evt & BUTTON_EVT_CHANGE && - button_level == BUTTON_RELEASED_LEVEL) { - state = BUTTON_RELEASE; - } else { - /* Start long press timer */ - timer_us = POWER_BUTTON_LONG_USEC - - POWER_BUTTON_SHORT_USEC; - /* - * If dock is currently off, then change to the - * power on state. If dock is already on, then - * advance to short press state. - */ - if (dock_state == POWER_OFF) { - baseboard_power_on(); - state = BUTTON_PRESS_POWER_ON; - } else { - state = BUTTON_PRESS_SHORT; - } - } - break; - case BUTTON_PRESS_POWER_ON: - /* - * Short press recognized and dock was just powered - * on. If button is no longer pressed, then just return - * to the default state. Else, button is still pressed - * after long press timer has expired. - */ - if (evt & BUTTON_EVT_CHANGE && - button_level == BUTTON_RELEASED_LEVEL) { - state = BUTTON_RELEASE; - } else { - state = BUTTON_PRESS_LONG; - baseboard_toggle_mf(); - } - break; - case BUTTON_PRESS_SHORT: - /* - * Short press was recognized and dock power state was - * already on. If button is now released, then turn dock - * off. - */ - if (evt & BUTTON_EVT_CHANGE && - button_level == BUTTON_RELEASED_LEVEL) { - state = BUTTON_RELEASE; - baseboard_power_off(); - } else { - state = BUTTON_PRESS_LONG; - baseboard_toggle_mf(); - } - break; - case BUTTON_PRESS_LONG: - if (evt & BUTTON_EVT_CHANGE && - button_level == BUTTON_RELEASED_LEVEL) { - state = BUTTON_RELEASE; - } - break; - } - } -} - -static void baseboard_power_button_debounce(void) -{ - int level = gpio_get_level(GPIO_PWR_BTN); - - /* Sanity check, level should be same after debounce interval */ - if (level != button_level_pending) - return; - - button_level = level; - task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_CHANGE); -} -DECLARE_DEFERRED(baseboard_power_button_debounce); - -void baseboard_power_button_evt(int level) -{ - button_level_pending = level; - - hook_call_deferred(&baseboard_power_button_debounce_data, - POWER_BUTTON_DEBOUNCE_USEC); -} - -static int command_pwr_btn(int argc, char **argv) -{ - - if (argc == 1) { - task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO); - return EC_SUCCESS; - } - - if (!strcasecmp(argv[1], "on")) { - baseboard_power_on(); - } else if (!strcasecmp(argv[1], "off")) { - baseboard_power_off(); - } else if (!strcasecmp(argv[1], "mf")) { - baseboard_toggle_mf(); - } else { - return EC_ERROR_PARAM1; - } - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, - "<on|off|mf>", - "Simulate Power Button Press"); - -#endif diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h deleted file mode 100644 index 1b56b07f8c..0000000000 --- a/baseboard/honeybuns/baseboard.h +++ /dev/null @@ -1,330 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Honeybuns baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* EC Defines */ -#define CONFIG_CRC8 - -/* Flash Lyaout */ -/* - * Flash layout: we redefine the sections offsets and sizes as we will use - * RO/RW regions of different sizes. - */ -#undef _IMAGE_SIZE -#undef CONFIG_ROLLBACK_OFF -#undef CONFIG_ROLLBACK_SIZE -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FW_PSTATE_SIZE -#undef CONFIG_FW_PSTATE_OFF -#undef CONFIG_SHAREDLIB_SIZE -#undef CONFIG_RO_MEM_OFF -#undef CONFIG_RO_STORAGE_OFF -#undef CONFIG_RO_SIZE -#undef CONFIG_RW_MEM_OFF -#undef CONFIG_RW_STORAGE_OFF -#undef CONFIG_RW_SIZE -#undef CONFIG_EC_PROTECTED_STORAGE_OFF -#undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#undef CONFIG_EC_WRITABLE_STORAGE_OFF -#undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#undef CONFIG_WP_STORAGE_OFF -#undef CONFIG_WP_STORAGE_SIZE - -#define CONFIG_FLASH_PSTATE -/* Do not use a dedicated PSTATE bank */ -#undef CONFIG_FLASH_PSTATE_BANK - -#define CONFIG_SHAREDLIB_SIZE 0 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (64*1024) - -#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) - -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* 48 MHz SYSCLK clock frequency */ -#define CPU_CLOCK 48000000 -#define CONFIG_STM_HWTIMER32 -#define TIM_CLOCK32 2 -#define TIM_CLOCK_MSB 3 -#define TIM_CLOCK_LSB 15 -#define TIM_WATCHDOG 7 - -/* Honeybuns platform does not have a lid switch */ -#undef CONFIG_LID_SWITCH - -/* USART and EC console configs */ -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 3 -#define CONFIG_UART_TX_DMA -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 -#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART3_TX -#define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX - -/* CBI Configs */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CMD_CBI -#define CONFIG_EEPROM_CBI_WP -#define CONFIG_BYPASS_CBI_EEPROM_WP_CHECK -#define GPIO_EC_CBI_WP GPIO_EC_FLASH_WP_ODL -#define CBI_FW_MF_MASK BIT(0) -#define CBI_FW_MF_PREFERENCE(val) (val & (CBI_FW_MF_MASK)) - -/* USB Configuration */ -#define CONFIG_USB -#define CONFIG_STREAM_USB -#define CONFIG_USB_UPDATE -#define CONFIG_USB_SERIALNO -#define DEFAULT_SERIALNO "Uninitialized" -#define CONFIG_MAC_ADDR -#define DEFAULT_MAC_ADDR "Uninitialized" - -/* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_UPDATE 1 -#define USB_EP_COUNT 2 - -#define USB_IFACE_UPDATE 0 -#define USB_IFACE_COUNT 1 - -#ifndef __ASSEMBLER__ -/* USB string indexes */ -enum usb_strings { - USB_STR_DESC = 0, - USB_STR_VENDOR, - USB_STR_PRODUCT, - USB_STR_SERIALNO, - USB_STR_VERSION, - USB_STR_UPDATE_NAME, - USB_STR_COUNT -}; -#endif - -/* RW Specific Config Options */ -#ifdef SECTION_IS_RW -/* No AP on any honeybuns variants */ -#undef CONFIG_USB_PD_HOST_CMD - -/* USB Type C and USB PD defines */ -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_CUSTOM_PDO -#define CONFIG_USB_PD_ALT_MODE_UFP_DP -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_REV30 -/* - * Source current limit pull options. Honeybuns always wants TYPEC_RP_3A0 - * current limits for the usbc host port (C0). For port C1, some variants are - * designed with a 1.5A current limit. This variation is handled via - * BOARD_C1_1A5_LIMIT which would be set in a variant's board.h file. - * - * CONFIG_USB_PD_3A_PORTS should be left at 0 as this will disable DPM from - * doing any dynamic current limit management. - */ -#undef CONFIG_USB_PD_PULLUP -#define CONFIG_USB_PD_PULLUP TYPEC_RP_3A0 -#define CONFIG_USB_PD_3A_PORTS 0 -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_PS8805 -#define CONFIG_USB_PD_TCPM_STM32GX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USBC_PPC_SN5S330 -#define CONFIG_USBC_PPC_VCONN -#define CONFIG_USBC_PPC_DEDICATED_INT -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USBC_SS_MUX - -#define CONFIG_HAS_TASK_PD_INT -#define CONFIG_STM32G4_UCPD_DEBUG -#define CONFIG_CMD_PPC_DUMP -#define CONFIG_CMD_TCPC_DUMP - -#define CONFIG_MP4245 -#define USB_HUB_OCP_RESET_MSEC (10 * MSEC) - -#else /* RO Specific Config Options */ - -/* RWSIG Config Options */ -/* Sign and switch to RW partition on boot. */ -#define CONFIG_RWSIG -#define CONFIG_RSA -#define CONFIG_SHA256_UNROLLED -#undef CONFIG_RWSIG_JUMP_TIMEOUT -#define CONFIG_RWSIG_JUMP_TIMEOUT (7000 * MSEC) - -/* Don't build PD console command for RO */ -#undef CONFIG_CMD_PD -#undef CONFIG_USB_PD_CONSOLE_CMD -#undef CONFIG_USB_PD_HOST_CMD -/* Make sure these files aren't built in RO */ -#undef CONFIG_USB_PRL_SM -#undef CONFIG_USB_TYPEC_SM -#undef CONFIG_USB_PE_SM - -#endif /* SECTION_IS_RW */ - -#define CONFIG_RWSIG_TYPE_RWSIG -#define CONFIG_RSA_KEY_SIZE 3072 -#define CONFIG_RSA_EXPONENT_3 -#define CONFIG_SHA256 - -/* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 5000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 15000 -#define PD_OPERATING_POWER_MW 15000 - -/* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* I2C Bus Configuration */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER - -/* - * Macros for GPIO signals used in common code that don't match the - * schematic names. Signal names in gpio.inc match the schematic and are - * then redefined here to so it's more clear which signal is being used for - * which purpose. - */ -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_WP_L GPIO_EC_WP_L - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "stddef.h" - -struct power_seq { - enum gpio_signal signal; /* power/reset gpio_signal to control */ - int level; /* level to set in power sequence */ - unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */ -}; - -enum mf_preference { - MF_OFF = 0, - MF_ON, -}; - -/* - * This is required as adc_channel is included in adc.h which ends up being - * included when TCPMv2 functions are included - */ -enum adc_channel { - ADC_CH_COUNT -}; - -extern const struct power_seq board_power_seq[]; -extern const size_t board_power_seq_count; - -void baseboard_power_button_evt(int level); - -/* - * Configure the host port to present Rd on both CC lines. This function is - * called in RO which does not otherwise have usbc/usb-pd support. - * - * @return true - initialized. false - not. - */ -int baseboard_usbc_init(int port); - -/* - * Get a board's desired multi-function (MF) prefernce. This allows for board - * specific policy. - * - * @return 1 if multi function (DP + USB3) is preferred, 0 otherwise - */ -int dock_get_mf_preference(void); - -/* - * Initialize and configure PPC used for USB3 only port - * - * @return EC success if PPC initialization is successful - */ -int baseboard_config_usbc_usb3_ppc(void); - -/* - * Called from interrupt handler for PS8803 attached.src gpio. This gpio signal - * will be set high by the PS8803 when it's in the attached.src state and low - * otherwise. For boards wich have a PPC on this port, this signal is used to - * enable/disable VBUS in the PPC. - */ -void baseboard_usb3_check_state(void); - - -/* - * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected - * by the host in the DP Configure SVDM message. - * - * @param dock_mf 1 -> 2 lanes DP, 0 -> 4 lanes DP - */ -void baseboard_set_mst_lane_control(int dock_mf); - -/* - * Control enable/disable for interrupts used for usb3 only usbc port. - * - * @param enable -> 1 for enable, 0 for disable - */ -void baseboard_usbc_usb3_enable_interrupts(int enable); - -/* - * Called from interrupt handler for PPC used on usb3 only port. - * - */ -void baseboard_usbc_usb3_irq(void); - -/** - * Determine if VBUS is present or not. - * - * @param port: The Type-C port number. - * @return 1 if VBUS is present, 0 if not. - */ -int c1_ps8805_is_vbus_present(int port); - -/** - * Is the port sourcing Vbus? - * - * @param port: The Type-C port number. - * @return 1 if sourcing Vbus, 0 if not. - */ -int c1_ps8805_is_sourcing_vbus(int port); - -/** - * Turn on/off VBUS for port C1 - * - * @param port: The Type-C port number. - * @param enable: 1: Turn on VBUS, 0: turn off VBUS. - * @return EC_SUCCESS on success, error otherwise. - */ -int c1_ps8805_vbus_source_enable(int port, int enable); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk deleted file mode 100644 index 2868911925..0000000000 --- a/baseboard/honeybuns/build.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Honeybuns baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-y+=usbc_support.o diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c deleted file mode 100644 index ef2350a03d..0000000000 --- a/baseboard/honeybuns/usb_pd_policy.c +++ /dev/null @@ -1,638 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "chip/stm32/ucpd-stm32gx.h" -#include "cros_board_info.h" -#include "driver/mp4245.h" -#include "driver/tcpm/tcpci.h" -#include "driver/mp4245.h" -#include "hooks.h" -#include "task.h" -#include "timer.h" -#include "usb_common.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_dp_ufp.h" -#include "usb_tc_sm.h" -#include "usbc_ppc.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -#define MP4245_VOLTAGE_WINDOW BIT(2) -#define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1) - -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED) - -/* Voltage indexes for the PDOs */ -enum volt_idx { - PDO_IDX_5V = 0, - PDO_IDX_9V = 1, - PDO_IDX_15V = 2, - PDO_IDX_20V = 3, - PDO_IDX_COUNT -}; - -/* PDOs */ -const uint32_t pd_src_host_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), - [PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0), - [PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0), - [PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0), -}; -BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT); - -#ifdef BOARD_C1_1A5_LIMIT -const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), -}; -#else -const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), -}; -#endif - -const uint32_t pd_snk_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS), -}; -const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); - -static int src_host_pdo_cnt_override; - -#define PD_DR_SWAP_ATTEMPT_MAX 3 -static int pd_dr_swap_attempt_count[CONFIG_USB_PD_PORT_MAX_COUNT]; - -static int command_hostpdo(int argc, char **argv) -{ - char *e; - int limit; - - if (argc >= 2) { - - limit = strtoi(argv[1], &e, 10); - if ((limit < 0) || (limit > PDO_IDX_COUNT)) - return EC_ERROR_PARAM1; - - src_host_pdo_cnt_override = limit; - } - ccprintf("src host pdo override = %d\n", src_host_pdo_cnt_override); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, - "<0|1|2|3|4>", - "Limit number of PDOs for C0"); - -int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) -{ - int pdo_cnt = 0; - - if (port == USB_PD_PORT_HOST) { - *src_pdo = pd_src_host_pdo; - pdo_cnt = ARRAY_SIZE(pd_src_host_pdo); - /* - * This override is only active via a console command. Only used - * for debug to limit the level of VBUS offered to port partner - * if desired. The console command only allows 0 -> - * PDO_IDX_COUNT for this value. - */ - if (src_host_pdo_cnt_override) - pdo_cnt = src_host_pdo_cnt_override; - } else { - *src_pdo = pd_src_display_pdo; - pdo_cnt = ARRAY_SIZE(pd_src_display_pdo); - } - - return pdo_cnt; -} - -/* - * Default Port Discovery DR Swap Policy. - * - * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap - * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap - */ -__override bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag) -{ - /* - * Port0: test if role is DFP - * Port1: test if role is UFP - */ - enum pd_data_role role_test = - (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : PD_ROLE_UFP; - - /* - * Request data role swap if not in the port's desired data role and if - * the attempt count is less than the max allowed. This function is - * called for each PE run once in a PD contract. If the port partner - * rejects data role swap requests (eg compliance tester), want to limit - * how many DR swap requests are attempted. - */ - if (dr == role_test && (pd_dr_swap_attempt_count[port]++ < - PD_DR_SWAP_ATTEMPT_MAX)) - return true; - - /* Do not perform a DR swap */ - return false; -} - -/* - * Default Port Discovery VCONN Swap Policy. - * - * 1) No need to Vconn swap. This board does not require any cable information. - */ -__override bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag) -{ - return false; -} - -int pd_check_vconn_swap(int port) -{ - /*TODO: Dock is the Vconn source */ - return 1; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) - return; - - if (IS_ENABLED(BOARD_C1_NO_PPC) && port) { - prev_en = c1_ps8805_is_sourcing_vbus(port); - /* Disable VBUS via PPC. */ - c1_ps8805_vbus_source_enable(port, 0); - } else { - prev_en = ppc_is_sourcing_vbus(port); - /* Disable VBUS via PPC. */ - ppc_vbus_source_enable(port, 0); - } - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - if (port == USB_PD_PORT_HOST) { - int mv; - int ma; - int unused_mv; - - /* - * Because VBUS on C0 is turned on/off via the PPC, the - * voltage from the mp4245 does not need to be turned off, or - * set to 0V. Instead, reset VBUS voltage to default value - * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next - * attached.src condition. - */ - pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, - &unused_mv); - mp4245_set_voltage_out(mv); - /* Ensure voltage is back to 5V */ - pd_transition_voltage(1); - } -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* - * Note: For host port, the mp4245 output voltage is set for 5V by - * default and each time VBUS is turned off. VOUT from the mp4245 is - * left enabled as there is a switch (either PPC or discrete) to turn - * VBUS on/off on the wire. - */ - if (IS_ENABLED(BOARD_C1_NO_PPC) && port) - rv = c1_ps8805_vbus_source_enable(port, 1); - else - rv = ppc_vbus_source_enable(port, 1); - - if (rv) - return rv; - - return EC_SUCCESS; -} - -void pd_transition_voltage(int idx) -{ - int port = TASK_ID_TO_PD_PORT(task_get_current()); - int mv; - int target_mv; - int mv_average = 0; - int ma; - int vbus_hi; - int vbus_lo; - int i; - int mv_buffer[MP4245_VOLTAGE_WINDOW]; - - /* Only C0 can provide more than 5V */ - if (port != USB_PD_PORT_HOST) - return; - - /* - * Set the VBUS output voltage and current limit to the values specified - * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st - * PDO of SRC_CAP which must always be 5V fixed supply. - */ - pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, - &mv); - - /* Initialize sample delay buffer */ - for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++) - mv_buffer[i] = 0; - - /* Set VBUS level to value specified in the requested PDO */ - mp4245_set_voltage_out(target_mv); - /* Wait for vbus to be within ~5% of its target value */ - vbus_hi = target_mv + (target_mv >> 4); - vbus_lo = target_mv - (target_mv >> 4); - - for (i = 0; i < 20; i++) { - /* Read current sample */ - mv = 0; - mp3245_get_vbus(&mv, &ma); - /* Add new sample to cicrcular delay buffer */ - mv_buffer[i & MP4245_VOLTAGE_WINDOW_MASK] = mv; - /* - * Don't compute average until sample delay buffer is - * full. - */ - if (i >= (MP4245_VOLTAGE_WINDOW_MASK)) { - int sum = 0; - int j; - - /* Sum the voltage samples */ - for (j = 0; j < MP4245_VOLTAGE_WINDOW; j++) - sum += mv_buffer[j]; - /* Add rounding */ - sum += MP4245_VOLTAGE_WINDOW / 2; - mv_average = sum / MP4245_VOLTAGE_WINDOW; - /* - * Check if average is within the target - * voltage range. - */ - if ((mv_average >= vbus_lo) && - (mv_average <= vbus_hi)) { - CPRINTS("usbc[%d]: VBUS to %d mV in %d steps", - port, target_mv, i); - return; - } - } - - /* - * The voltage ramp from 5V to 20V requires ~30 - * msec. The max loop count and this sleep time gives plenty - * of time for this change. - */ - msleep(2); - } - - CPRINTS("usbc[%d]: Vbus transition timeout: target = %d, measure = %d", - port, target_mv, mv_average); -} - -int pd_snk_is_vbus_provided(int port) -{ - if (IS_ENABLED(BOARD_C1_NO_PPC) && port) - return c1_ps8805_is_vbus_present(port); - else - return ppc_is_vbus_present(port); -} - -__override bool pd_check_vbus_level(int port, enum vbus_level level) -{ - if (level == VBUS_PRESENT) - return pd_snk_is_vbus_provided(port); - else - return !pd_snk_is_vbus_provided(port); -} - -int board_vbus_source_enabled(int port) -{ - if (IS_ENABLED(BOARD_C1_NO_PPC) && port) - return c1_ps8805_is_sourcing_vbus(port); - else - return ppc_is_sourcing_vbus(port); -} - -void pd_set_input_current_limit(int port, uint32_t max_ma, - uint32_t supply_voltage) -{ - -} - -int pd_check_data_swap(int port, - enum pd_data_role data_role) -{ - int swap = 0; - - if (port == 0) - swap = (data_role == PD_ROLE_DFP); - else if (port == 1) - swap = (data_role == PD_ROLE_UFP); - - return swap; -} - -int pd_check_power_swap(int port) -{ - - if (pd_get_power_role(port) == PD_ROLE_SINK) - return 1; - - return 0; -} - -#ifdef BOARD_C1_1A5_LIMIT -__override int typec_get_default_current_limit_rp(int port) -{ - int rp = TYPEC_RP_USB; - - if (port == USB_PD_PORT_HOST) - rp = TYPEC_RP_3A0; - else if (port == USB_PD_PORT_DP) - rp = TYPEC_RP_1A5; - - return rp; -} -#endif - -static void usb_tc_connect(void) -{ - int port = TASK_ID_TO_PD_PORT(task_get_current()); - - /* - * The EC needs to indicate to the USB hub when the host port is - * attached so that the USB-EP can be properly enumerated. GPIO_BPWR_DET - * is used for this purpose. - */ - if (port == USB_PD_PORT_HOST) { - gpio_set_level(GPIO_BPWR_DET, 1); -#ifdef GPIO_UFP_PLUG_DET - gpio_set_level(GPIO_UFP_PLUG_DET, 0); -#endif - } - - /* Clear data role swap attempt counter at each usbc attach */ - pd_dr_swap_attempt_count[port] = 0; -} -DECLARE_HOOK(HOOK_USB_PD_CONNECT, usb_tc_connect, HOOK_PRIO_DEFAULT); - -static void usb_tc_disconnect(void) -{ - int port = TASK_ID_TO_PD_PORT(task_get_current()); - - /* Only the host port disconnect is relevant */ - if (port == USB_PD_PORT_HOST) { - gpio_set_level(GPIO_BPWR_DET, 0); -#ifdef GPIO_UFP_PLUG_DET - gpio_set_level(GPIO_UFP_PLUG_DET, 1); -#endif - } -} -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT); - -__override bool pd_can_charge_from_device(int port, const int pdo_cnt, - const uint32_t *pdos) -{ - /* - * This function is called to determine if this port can be charged by - * the port partner. We always want to be a power role source, so always - * return false. - */ - - return false; -} - -static int vdm_is_dp_enabled(int port) -{ - mux_state_t mux_state = usb_mux_get(port); - - return !!(mux_state & USB_PD_MUX_DP_ENABLED); -} - -/* ----------------- Vendor Defined Messages ------------------ */ - -const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ - 1, /* data caps as USB device */ - IDH_PTYPE_HUB, /* UFP product type usbpd hub */ - 1, /* supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 0, /* Data caps as USB host */ - 1, /* Data caps as USB device */ - IDH_PTYPE_HUB, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_UNDEFINED, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); - -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_RECONFIGURE, - USB_R30_SS_U32_U40_GEN2); - -static int svdm_response_identity(int port, uint32_t *payload) -{ - int vdo_count; - - /* Verify that SVID is PD SID */ - if (PD_VDO_VID(payload[0]) != USB_SID_PD) { - return 0; - } - - /* Cstat and Product VDOs don't depend on spec revision */ - payload[VDO_INDEX_CSTAT] = VDO_CSTAT(0); - payload[VDO_INDEX_PRODUCT] = vdo_product; - - if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { - /* PD Revision 3.0 */ - payload[VDO_INDEX_IDH] = vdo_idh_rev30; - payload[VDO_INDEX_PTYPE_UFP1_VDO] = vdo_ufp1; - vdo_count = VDO_INDEX_PTYPE_UFP1_VDO; - } else { - payload[VDO_INDEX_IDH] = vdo_idh; - vdo_count = VDO_INDEX_PRODUCT; - } - - /* Adjust VDO count for VDM header */ - return vdo_count + 1; -} - -static int svdm_response_svids(int port, uint32_t *payload) -{ - /* Verify that SVID is PD SID */ - if (PD_VDO_VID(payload[0]) != USB_SID_PD) { - return 0; - } - - payload[1] = USB_SID_DISPLAYPORT << 16; - /* number of data objects VDO header + 1 SVID for DP */ - return 2; -} - -#define OPOS_DP 1 - -const uint32_t vdo_dp_modes[1] = { - VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */ - MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, - 0, /* DFP pin cfg supported */ - 0, /* usb2.0 signalling in AMode may be req */ - CABLE_RECEPTACLE, /* its a receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ -}; - -static int svdm_response_modes(int port, uint32_t *payload) -{ - if (PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) { - memcpy(payload + 1, vdo_dp_modes, sizeof(vdo_dp_modes)); - return ARRAY_SIZE(vdo_dp_modes) + 1; - } else { - return 0; /* nak */ - } -} - -static int amode_dp_status(int port, uint32_t *payload) -{ - int opos = PD_VDO_OPOS(payload[0]); - int hpd = gpio_get_level(GPIO_DP_HPD); - int mf = dock_get_mf_preference(); - - if (opos != OPOS_DP) - return 0; /* nak */ - - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - mf, /* MF pref */ - vdm_is_dp_enabled(port), - 0, /* power low */ - 0x2); - return 2; -} - -static void svdm_configure_demux(int port, int enable, int mf) -{ - mux_state_t demux = usb_mux_get(port); - - if (enable) { - demux |= USB_PD_MUX_DP_ENABLED; - /* 4 lane mode if MF is not preferred */ - if (!mf) - demux &= ~USB_PD_MUX_USB_ENABLED; - /* - * Make sure the MST_LANE_CONTROL gpio is set to match the DP - * pin configuration selected by the host. Note that the mf - * passed into this function reflects the pin configuration - * selected by the host and not the user mf preference which is - * stored in bit 0 of CBI fw_config. - */ - baseboard_set_mst_lane_control(mf); - CPRINTS("DP[%d]: DFP-D selected pin config %s", - port, mf ? "D" : "C"); - } else { - demux &= ~USB_PD_MUX_DP_ENABLED; - demux |= USB_PD_MUX_USB_ENABLED; - } - - /* Configure demux for 2/4 lane DP and USB3 configuration */ - usb_mux_set(port, demux, USB_SWITCH_CONNECT, pd_get_polarity(port)); -} - -static int amode_dp_config(int port, uint32_t *payload) -{ - uint32_t dp_config = payload[1]; - int mf; - - /* - * Check pin assignment selected by DFP_D to determine if 2 lane or 4 - * lane DP ALT-MODe is required. (note PIN_C is for 4 lane and PIN_D is - * for 2 lane mode). - */ - mf = ((dp_config >> 8) & 0xff) == MODE_DP_PIN_D ? 1 : 0; - /* Configure demux for DP mode */ - svdm_configure_demux(port, 1, mf); - /* Notify hpd->pd conv that a DP_CONFIG message has been received */ - pd_ufp_enable_hpd_send(port); - - return 1; -} - -static int svdm_enter_mode(int port, uint32_t *payload) -{ - int rv = 0; /* will generate a NAK */ - - /* SID & mode request is valid */ - if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) && - (PD_VDO_OPOS(payload[0]) == OPOS_DP)) { - - /* Store valid object position to indicate mode is active */ - pd_ufp_set_dp_opos(port, OPOS_DP); - - /* Entering ALT-DP mode, enable DP connection in demux */ - usb_pd_hpd_converter_enable(1); - - /* ACK response has 1 VDO */ - rv = 1; - } - - CPRINTS("svdm_enter[%d]: svid = %x, ret = %d", port, - PD_VDO_VID(payload[0]), rv); - - return rv; -} - -static int svdm_exit_mode(int port, uint32_t *payload) -{ - int opos = pd_ufp_get_dp_opos(port); - - if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) && - (opos == OPOS_DP)) { - /* Clear mode active object position */ - pd_ufp_set_dp_opos(port, 0); - /* Configure demux to disable DP mode */ - svdm_configure_demux(port, 0, 0); - usb_pd_hpd_converter_enable(0); - - return 1; - } else { - CPRINTF("Unknown exit mode req:0x%08x\n", payload[0]); - return 0; - } -} - -static struct amode_fx dp_fx = { - .status = &amode_dp_status, - .config = &amode_dp_config, -}; - -const struct svdm_response svdm_rsp = { - .identity = &svdm_response_identity, - .svids = &svdm_response_svids, - .modes = &svdm_response_modes, - .enter_mode = &svdm_enter_mode, - .amode = &dp_fx, - .exit_mode = &svdm_exit_mode, -}; - -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) -{ - /* We don't support, so ignore this message */ - return 0; -} diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c deleted file mode 100644 index 4d7049ad37..0000000000 --- a/baseboard/honeybuns/usbc_support.c +++ /dev/null @@ -1,480 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USBC functions for RO */ - -#include "common.h" -#include "console.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/ps8xxx.h" -#include "sn5s330.h" -#include "hooks.h" -#include "i2c.h" -#include "system.h" -#include "timer.h" -#include "usb_charge.h" -#include "usb_pd_tcpm.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" -#include "registers.h" -#include "ucpd-stm32gx.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) - -enum usbc_states { - UNATTACHED_SNK, - ATTACH_WAIT_SNK, - ATTACHED_SNK, -}; - -/* Variables used to manage the simple usbc state machine */ -static int usbc_port; -static int usbc_state; -static int usbc_vbus; -static enum tcpc_cc_voltage_status cc1_v; -static enum tcpc_cc_voltage_status cc2_v; - -__maybe_unused static __const_data const char * const usbc_state_names[] = { - [UNATTACHED_SNK] = "Unattached.SNK", - [ATTACH_WAIT_SNK] = "AttachWait.SNK", - [ATTACHED_SNK] = "Attached.SNK", -}; - -static int read_reg(uint8_t port, int reg, int *regval) -{ - return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); -} - -static int write_reg(uint8_t port, int reg, int regval) -{ - return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); -} - -static int baseboard_ppc_enable_sink_path(int port) -{ - int regval; - int status; - int retries; - - /* - * It seems that sometimes setting the FUNC_SET1 register fails - * initially. Therefore, we'll retry a couple of times. - */ - retries = 0; - do { - status = write_reg(port, SN5S330_FUNC_SET1, SN5S330_ILIM_3_06); - if (status) { - retries++; - msleep(1); - } else { - break; - } - } while (retries < 10); - - /* Turn off dead battery resistors, turn on CC FETs */ - status = read_reg(port, SN5S330_FUNC_SET4, ®val); - if (!status) { - regval |= SN5S330_CC_EN; - status = write_reg(port, SN5S330_FUNC_SET4, regval); - } - if (status) { - return status; - } - - /* Enable sink path via PP2 */ - status = read_reg(port, SN5S330_FUNC_SET3, ®val); - if (!status) { - regval &= ~SN5S330_PP1_EN; - regval |= SN5S330_PP2_EN; - status = write_reg(port, SN5S330_FUNC_SET3, regval); - } - if (status) { - return status; - } - - return EC_SUCCESS; -} - -static void baseboard_ucpd_apply_rd(int port) -{ - uint32_t cfgr1_reg; - uint32_t moder_reg; - uint32_t cr; - - /* Ensure that clock to UCPD is enabled */ - STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN; - - /* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */ - moder_reg = STM32_GPIO_MODER(GPIO_B); - moder_reg |= 0x3300; - STM32_GPIO_MODER(GPIO_B) = moder_reg; - /* - * CFGR1 must be written when UCPD peripheral is disabled. Note that - * disabling ucpd causes the peripheral to quit any ongoing activity and - * sets all ucpd registers back their default values. - */ - - cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); - STM32_UCPD_CFGR1(port) = cfgr1_reg; - - /* Enable ucpd */ - STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN; - - /* Apply Rd to both CC lines */ - cr = STM32_UCPD_CR(port); - cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK; - STM32_UCPD_CR(port) = cr; - - /* - * After exiting reset, stm32gx will have dead battery mode enabled by - * default which connects Rd to CC1/CC2. This should be disabled when EC - * is powered up. - */ - STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; -} - - -static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) -{ - int vstate_cc1; - int vstate_cc2; - int anamode; - uint32_t sr; - - /* - * cc_voltage_status is determined from vstate_cc bit field in the - * status register. The meaning of the value vstate_cc depends on - * current value of ANAMODE (src/snk). - * - * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, - * but needs to be modified slightly for case ANAMODE = 0. - * - * If presenting Rp (source), then need to to a circular shift of - * vstate_ccx value: - * vstate_cc | cc_state - * ------------------ - * 0 -> 1 - * 1 -> 2 - * 2 -> 0 - */ - - /* Get vstate_ccx values and power role */ - sr = STM32_UCPD_SR(port); - /* Get Rp or Rd active */ - anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); - vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; - vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; - - /* Do circular shift if port == source */ - if (anamode) { - if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA) - vstate_cc1 += 4; - if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA) - vstate_cc2 += 4; - } else { - if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN) - vstate_cc1 = (vstate_cc1 + 1) % 3; - if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN) - vstate_cc2 = (vstate_cc2 + 1) % 3; - } - - *cc1 = vstate_cc1; - *cc2 = vstate_cc2; -} - -static int baseboard_rp_is_present(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) -{ - return (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF); -} - -static void baseboard_usbc_check_connect(void); -DECLARE_DEFERRED(baseboard_usbc_check_connect); - -static void baseboard_usbc_check_connect(void) -{ - enum tcpc_cc_voltage_status cc1; - enum tcpc_cc_voltage_status cc2; - int ppc_reg; - enum usbc_states enter_state = usbc_state; - - /* - * In RO, the only usbc related requirement is to enable the stm32g4 - * USB-EP to be enumerated by the host attached to C0. To prevent D+ - * being pulled high prior to VBUS presence, the EC uses GPIO_BPWR_DET - * to signal the USB hub that VBUS is present. Therefore, we need a - * simple usbc state machine to detect an attach (Rp and VBUS) event so - * this GPIO signal is properly controlled in RO. - * - * Note that RO only runs until the RWSIG timer expires and jumps to RW, - * and in RW, the full usb-pd stack is initialized and run. - */ - - /* Get current CC voltage levels */ - baseboard_ucpd_get_cc(usbc_port, &cc1, &cc2); - /* Update VBUS state */ - if (!read_reg(usbc_port, SN5S330_INT_STATUS_REG3, &ppc_reg)) - usbc_vbus = ppc_reg & SN5S330_VBUS_GOOD; - - switch (usbc_state) { - case UNATTACHED_SNK: - /* - * Require either CC1 or CC2 to have a valid Rp CC voltage level - * to advance to ATTACH_WAIT_SNK. - */ - if (baseboard_rp_is_present(cc1, cc2)) - usbc_state = ATTACH_WAIT_SNK; - break; - case ATTACH_WAIT_SNK: - /* - * This state handles debounce by ensuring the CC voltages are - * the same between two state machine iterations. If this - * condition is met, and VBUS is present, then advance to - * ATTACHED_SNK and set GPIO_BPWR_DET. - * - * If Rp voltage is no longer detected, then return to - * UNATTACHED_SNK. - */ - if (usbc_vbus && cc1 == cc1_v && cc2 == cc2_v) { - usbc_state = ATTACHED_SNK; - gpio_set_level(GPIO_BPWR_DET, 1); - } else if (!baseboard_rp_is_present(cc1, cc2)) { - usbc_state = UNATTACHED_SNK; - } - break; - case ATTACHED_SNK: - /* - * In this state, only checking for VBUS going away to indicate - * a detach event and inform the USB hub via GPIO_BPWR_DET. - */ - if (!usbc_vbus) { - usbc_state = UNATTACHED_SNK; - gpio_set_level(GPIO_BPWR_DET, 0); - } - break; - } - - /* Save CC voltage for debounce check */ - cc1_v = cc1; - cc2_v = cc2; - - if (enter_state != usbc_state) - CPRINTS("%s: cc1 = %d, cc2 = %d vbus = %d", - usbc_state_names[usbc_state], cc1, cc2, usbc_vbus); - - hook_call_deferred(&baseboard_usbc_check_connect_data, - PD_T_TRY_CC_DEBOUNCE); -} - -int baseboard_usbc_init(int port) -{ - int rv; - - /* Initialize ucpd and apply Rd to CC lines */ - baseboard_ucpd_apply_rd(port); - /* Initialize ppc to enable sink path */ - rv = baseboard_ppc_enable_sink_path(port); - if (rv) - CPRINTS("ppc init failed!"); - /* Save host port value */ - usbc_port = port; - /* Start RO usbc attach state machine */ - gpio_set_level(GPIO_BPWR_DET, 0); - /* Start simple usbc state machine */ - baseboard_usbc_check_connect(); - - return rv; -} - -#ifdef SECTION_IS_RW -int c1_ps8805_is_vbus_present(int port) -{ - int vbus; - - vbus = tcpm_check_vbus_level(port, VBUS_PRESENT); - - return vbus; -} - -int c1_ps8805_is_sourcing_vbus(int port) -{ - int rv; - int level; - - rv = ps8805_gpio_get_level(port, PS8805_GPIO_1, &level); - if (rv) - return 0; - - return level; -} - - -int c1_ps8805_vbus_source_enable(int port, int enable) -{ - - return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable); -} - -__override bool usb_ufp_check_usb3_enable(int port) -{ - /* USB3.1 mux should be enabled based on UFP data role */ - return port == USB_PD_PORT_HOST; -} - -#ifdef GPIO_USBC_UF_ATTACHED_SRC -static int ppc_ocp_count; - -static void baseboard_usb3_manage_vbus(void) -{ - int level = gpio_get_level(GPIO_USBC_UF_ATTACHED_SRC); - - /* - * GPIO_USBC_UF_MUX_VBUS_EN is an output from the PS8803 which tracks if - * C2 is attached. When it's attached, this signal will be high. Use - * this level to control PPC VBUS on/off. - */ - ppc_vbus_source_enable(USB_PD_PORT_USB3, level); - CPRINTS("C2: State = %s", level ? "Attached.SRC " : "Unattached.SRC"); - - /* Reset OCP event counter for detach */ - if (!level) { - ppc_ocp_count = 0; - -#ifdef GPIO_USB_HUB_OCP_NOTIFY - /* - * In the case of an OCP event on this port, the usb hub should be - * notified via a GPIO signal. Following, an OCP, the attached.src state - * for the usb3 only port is checked again. If it's attached, then make - * sure the OCP notify signal is reset. - */ - gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1); -#endif - } -} -DECLARE_DEFERRED(baseboard_usb3_manage_vbus); - -void baseboard_usb3_check_state(void) -{ - hook_call_deferred(&baseboard_usb3_manage_vbus_data, 0); -} - -void baseboard_usbc_usb3_enable_interrupts(int enable) -{ - if (enable) { - /* Enable VBUS control interrupt for C2 */ - gpio_enable_interrupt(GPIO_USBC_UF_ATTACHED_SRC); - /* Enable PPC interrupt */ - gpio_enable_interrupt(GPIO_USBC_UF_PPC_INT_ODL); - } else { - /* Disable VBUS control interrupt for C2 */ - gpio_disable_interrupt(GPIO_USBC_UF_ATTACHED_SRC); - /* Disable PPC interrupt */ - gpio_disable_interrupt(GPIO_USBC_UF_PPC_INT_ODL); - } -} - -int baseboard_config_usbc_usb3_ppc(void) -{ - int rv; - - /* - * This port is not usb-pd capable, but there is a ppc which must be - * initialized, and keep the VBUS switch enabled. - */ - rv = ppc_init(USB_PD_PORT_USB3); - if (rv) - return rv; - - /* Need to set current limit to 3A to match advertised value */ - ppc_set_vbus_source_current_limit(USB_PD_PORT_USB3, TYPEC_RP_3A0); - /* Reset OCP event counter */ - ppc_ocp_count = 0; - - /* Check state at init time */ - baseboard_usb3_manage_vbus(); - - /* Enable attached.src and PPC interrupts */ - baseboard_usbc_usb3_enable_interrupts(1); - - return EC_SUCCESS; -} - -static void baseboard_usbc_usb3_handle_interrupt(void) -{ - int port = USB_PD_PORT_USB3; - - /* - * SN5S330's /INT pin is level, so process interrupts until it - * deasserts if the chip has a dedicated interrupt pin. - */ - while (gpio_get_level(GPIO_USBC_UF_PPC_INT_ODL) == 0) { - int rise = 0; - int fall = 0; - - read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise); - read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall); - - /* Notify the system about the overcurrent event. */ - if (rise & SN5S330_ILIM_PP1_MASK) { - CPRINTS("usb3_ppc: VBUS OC!"); - gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0); - if (++ppc_ocp_count < 5) - hook_call_deferred(&baseboard_usb3_manage_vbus_data, - USB_HUB_OCP_RESET_MSEC); - else - CPRINTS("usb3_ppc: VBUS OC limit reached!"); - } - - /* Clear the interrupt sources. */ - write_reg(port, SN5S330_INT_TRIP_RISE_REG1, rise); - write_reg(port, SN5S330_INT_TRIP_FALL_REG1, fall); - - read_reg(port, SN5S330_INT_TRIP_RISE_REG2, &rise); - read_reg(port, SN5S330_INT_TRIP_FALL_REG2, &fall); - - /* - * VCONN may be latched off due to an overcurrent. Indicate - * when the VCONN overcurrent happens. - */ - if (rise & SN5S330_VCONN_ILIM) - CPRINTS("usb3_ppc: VCONN OC!"); - - /* - * CC overvoltage event. There is not action to take here, but - * log the event. - */ - if (rise & SN5S330_CC1_CON || rise & SN5S330_CC2_CON) - CPRINTS("usb3_ppc: CC OV!"); - - /* Clear the interrupt sources. */ - write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise); - write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall); - - } -} -DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt); - -void baseboard_usbc_usb3_irq(void) -{ - hook_call_deferred(&baseboard_usbc_usb3_handle_interrupt_data, 0); -} - -#endif /* defined(GPIO_USBC_UF_ATTACHED_SRC) */ -#endif /* defined(SECTION_IS_RW) */ - diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md deleted file mode 100644 index 39286e130d..0000000000 --- a/baseboard/intelrvp/README.md +++ /dev/null @@ -1,53 +0,0 @@ -This folder is for the baseboard for the board specific files which use Intel -Reference Validation Platform (RVP) for developing the EC and other peripherals -which can be hooked on EC or RVP. - -This baseboard follows the Intel Modular Embedded Controller Card (MECC) -specification for pinout and these pin definitions remain same on all the RVPs. -Chrome MECC spec is standardized for Icelake and successor RVPs hence this -baseboard code is applicable to Icelake and its successors only. - -Following hardware features are supported on MECC header by RVP and can be -validated by software by MECC. - -## MECC version 0.9 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header need to be added by MECC -4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) -6. 6 Temperature sensors -7. 4 ADC -8. 4 I2C Channels -9. 1 Fan control - -## MECC version 1.0 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header need to be added by MECC -4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on - RVP -6. Optional 2 Type-C port routed to MECC for integrated TCPC support -7. 6 I2C Channels -8. 2 SMLINK Channels -9. 2 I3C channels - -## MECC version 1.1 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header is added on RVP as an AIC -4. Google H1 chip is added on RVP as an AIC -5. 4 Type-C port support (SRC/SNK/MUX/Rerimer) as an (AIC) -6. Optional 2 Type-C port routed to MECC for integrated TCPC support -7. 6 I2C Channels -8. 2 SMLINK Channels -9. 2 I3C channels -10. 1 Fan control -11. 4 ADC based temperature sensors -12. PECI control -13. I2C based Keyboard is added on RVP as an AIC -14. Both Google & Intel CCD support is added on RVP on Type-C port 0 diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c deleted file mode 100644 index 78f4b3613a..0000000000 --- a/baseboard/intelrvp/adlrvp.c +++ /dev/null @@ -1,450 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel ADLRVP board-specific common configuration */ - -#include "charger.h" -#include "common.h" -#include "driver/retimer/bb_retimer_public.h" -#include "hooks.h" -#include "ioexpander.h" -#include "isl9241.h" -#include "pca9675.h" -#include "power/icelake.h" -#include "sn5s330.h" -#include "system.h" -#include "task.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) - -/* TCPC AIC GPIO Configuration */ -const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { - [TYPE_C_PORT_0] = { - .tcpc_alert = GPIO_USBC_TCPC_ALRT_P0, - .ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0, - .ppc_intr_handler = sn5s330_interrupt, - }, -#if defined(HAS_TASK_PD_C1) - [TYPE_C_PORT_1] = { - .tcpc_alert = GPIO_USBC_TCPC_ALRT_P1, - .ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1, - .ppc_intr_handler = sn5s330_interrupt, - }, -#endif -#if defined(HAS_TASK_PD_C2) - [TYPE_C_PORT_2] = { - .tcpc_alert = GPIO_USBC_TCPC_ALRT_P2, - .ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2, - .ppc_intr_handler = sn5s330_interrupt, - }, -#endif -#if defined(HAS_TASK_PD_C3) - [TYPE_C_PORT_3] = { - .tcpc_alert = GPIO_USBC_TCPC_ALRT_P3, - .ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3, - .ppc_intr_handler = sn5s330_interrupt, - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* USB-C PPC configuration */ -struct ppc_config_t ppc_chips[] = { - [TYPE_C_PORT_0] = { - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, - .drv = &sn5s330_drv, - }, -#if defined(HAS_TASK_PD_C1) - [TYPE_C_PORT_1] = { - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, - .drv = &sn5s330_drv - }, -#endif -#if defined(HAS_TASK_PD_C2) - [TYPE_C_PORT_2] = { - .i2c_port = I2C_PORT_TYPEC_2, - .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, - .drv = &sn5s330_drv, - }, -#endif -#if defined(HAS_TASK_PD_C3) - [TYPE_C_PORT_3] = { - .i2c_port = I2C_PORT_TYPEC_3, - .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, - .drv = &sn5s330_drv, - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* USB-C retimer Configuration */ -struct usb_mux usbc0_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; -#if defined(HAS_TASK_PD_C1) -struct usb_mux usbc1_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; -#endif -#if defined(HAS_TASK_PD_C2) -struct usb_mux usbc2_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_2, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; -#endif -#if defined(HAS_TASK_PD_C3) -struct usb_mux usbc3_tcss_usb_mux = { - .usb_port = TYPE_C_PORT_3, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; -#endif - -/* USB muxes Configuration */ -struct usb_mux usb_muxes[] = { - [TYPE_C_PORT_0] = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR, - }, -#if defined(HAS_TASK_PD_C1) - [TYPE_C_PORT_1] = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR, - }, -#endif -#if defined(HAS_TASK_PD_C2) - [TYPE_C_PORT_2] = { - .usb_port = TYPE_C_PORT_2, - .next_mux = &usbc2_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_2, - .i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR, - }, -#endif -#if defined(HAS_TASK_PD_C3) - [TYPE_C_PORT_3] = { - .usb_port = TYPE_C_PORT_3, - .next_mux = &usbc3_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_3, - .i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR, - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */ -struct usb_mux soc_side_bb_retimer0_usb_mux = { - .usb_port = TYPE_C_PORT_0, - .next_mux = &usbc0_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR, -}; - -#if defined(HAS_TASK_PD_C1) -struct usb_mux soc_side_bb_retimer1_usb_mux = { - .usb_port = TYPE_C_PORT_1, - .next_mux = &usbc1_tcss_usb_mux, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR, -}; -#endif - -const struct bb_usb_control bb_controls[] = { - [TYPE_C_PORT_0] = { - .retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST, - .usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN, - }, -#if defined(HAS_TASK_PD_C1) - [TYPE_C_PORT_1] = { - .retimer_rst_gpio = IOEX_USB_C1_BB_RETIMER_RST, - .usb_ls_en_gpio = IOEX_USB_C1_BB_RETIMER_LS_EN, - }, -#endif -#if defined(HAS_TASK_PD_C2) - [TYPE_C_PORT_2] = { - .retimer_rst_gpio = IOEX_USB_C2_BB_RETIMER_RST, - .usb_ls_en_gpio = IOEX_USB_C2_BB_RETIMER_LS_EN, - }, -#endif -#if defined(HAS_TASK_PD_C3) - [TYPE_C_PORT_3] = { - .retimer_rst_gpio = IOEX_USB_C3_BB_RETIMER_RST, - .usb_ls_en_gpio = IOEX_USB_C3_BB_RETIMER_LS_EN, - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(bb_controls) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* Cache BB retimer power state */ -static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT]; - -/* Each TCPC have corresponding IO expander and are available in pair */ -struct ioexpander_config_t ioex_config[] = { - [IOEX_C0_PCA9675] = { - .i2c_host_port = I2C_PORT_TYPEC_0, - .i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX, - .drv = &pca9675_ioexpander_drv, - }, - [IOEX_C1_PCA9675] = { - .i2c_host_port = I2C_PORT_TYPEC_1, - .i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX, - .drv = &pca9675_ioexpander_drv, - }, -#if defined(HAS_TASK_PD_C2) - [IOEX_C2_PCA9675] = { - .i2c_host_port = I2C_PORT_TYPEC_2, - .i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX, - .drv = &pca9675_ioexpander_drv, - }, - [IOEX_C3_PCA9675] = { - .i2c_host_port = I2C_PORT_TYPEC_3, - .i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX, - .drv = &pca9675_ioexpander_drv, - }, -#endif -}; -BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); - -/* Charger Chips */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL9241_ADDR_FLAGS, - .drv = &isl9241_drv, - }, -}; - -void board_overcurrent_event(int port, int is_overcurrented) -{ - /* Port 0 & 1 and 2 & 3 share same line for over current indication */ -#if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; -#else - enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; -#endif - - /* Overcurrent indication is active low signal */ - ioex_set_level(oc_signal, is_overcurrented ? 0 : 1); -} - -__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) -{ - /* - * ADL-P-DDR5 RVP SKU has cascaded retimer topology. - * Ports with cascaded retimers share common load switch and reset pin - * hence no need to set the power state again if the 1st retimer's power - * status has already changed. - */ - if (cache_bb_enable[me->usb_port] == enable) - return EC_SUCCESS; - - cache_bb_enable[me->usb_port] = enable; - - /* Handle retimer's power domain.*/ - if (enable) { - ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 1); - - /* - * minimum time from VCC to RESET_N de-assertion is 100us - * For boards that don't provide a load switch control, the - * retimer_init() function ensures power is up before calling - * this function. - */ - msleep(1); - ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 1); - - /* - * Allow 1ms time for the retimer to power up lc_domain - * which powers I2C controller within retimer - */ - msleep(1); - - } else { - ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 0); - msleep(1); - ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 0); - } - return EC_SUCCESS; -} - -static void board_connect_c0_sbu_deferred(void) -{ - int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL); - - if (ccd_intr_level) { - /* Default set the SBU lines to AUX mode on TCPC-AIC */ - ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0); - ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0); - } else { - /* Set the SBU lines to CCD mode on TCPC-AIC */ - ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1); - ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0); - } -} -DECLARE_DEFERRED(board_connect_c0_sbu_deferred); -/* Make sure SBU are routed to CCD or AUX based on CCD status at init */ -DECLARE_HOOK(HOOK_INIT, board_connect_c0_sbu_deferred, HOOK_PRIO_INIT_I2C + 2); - -void board_connect_c0_sbu(enum gpio_signal s) -{ - hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); -} - -static void enable_h1_irq(void) -{ - gpio_enable_interrupt(GPIO_CCD_MODE_ODL); -} -DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST); - -static void configure_retimer_usbmux(void) -{ - switch (ADL_RVP_BOARD_ID(board_get_version())) { - case ADLN_LP5_ERB_SKU_BOARD_ID: - case ADLN_LP5_RVP_SKU_BOARD_ID: - /* No retimer on Port0 & Port1 */ - usb_muxes[TYPE_C_PORT_0].driver = NULL; -#if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].driver = NULL; -#endif - break; - - case ADLP_LP5_T4_RVP_SKU_BOARD_ID: - /* No retimer on Port-2 */ -#if defined(HAS_TASK_PD_C2) - usb_muxes[TYPE_C_PORT_2].driver = NULL; -#endif - break; - - case ADLP_DDR5_RVP_SKU_BOARD_ID: - /* - * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1. - * Change the default usb mux config on runtime to support - * dual retimer topology. - */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; -#if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; -#endif - break; - - /* Add additional board SKUs */ - - default: - break; - } -} -DECLARE_HOOK(HOOK_INIT, configure_retimer_usbmux, HOOK_PRIO_INIT_I2C + 1); - -/******************************************************************************/ -/* PWROK signal configuration */ -/* - * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD - * as input. - */ -const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { - { - .gpio = GPIO_SYS_PWROK_EC, - .delay_ms = 3, - }, -}; -const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); - -const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { - { - .gpio = GPIO_SYS_PWROK_EC, - }, -}; -const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list); - -/* - * Returns board information (board id[7:0] and Fab id[15:8]) on success - * -1 on error. - */ -__override int board_get_version(void) -{ - /* Cache the ADLRVP board ID */ - static int adlrvp_board_id; - - int port0, port1; - int fab_id, board_id, bom_id; - - /* Board ID is already read */ - if (adlrvp_board_id) - return adlrvp_board_id; - - if (ioexpander_read_intelrvp_version(&port0, &port1)) - return -1; - /* - * Port0: bit 0 - BOM ID(2) - * bit 2:1 - FAB ID(1:0) + 1 - * Port1: bit 7:6 - BOM ID(1:0) - * bit 5:0 - BOARD ID(5:0) - */ - bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2); - fab_id = ((port0 & 0x06) >> 1) + 1; - board_id = port1 & 0x3F; - - CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); - - adlrvp_board_id = board_id | (fab_id << 8); - return adlrvp_board_id; -} - -__override bool board_is_tbt_usb4_port(int port) -{ - bool tbt_usb4 = true; - - switch (ADL_RVP_BOARD_ID(board_get_version())) { - case ADLN_LP5_ERB_SKU_BOARD_ID: - case ADLN_LP5_RVP_SKU_BOARD_ID: - /* No retimer on both ports */ - tbt_usb4 = false; - break; - - case ADLP_LP5_T4_RVP_SKU_BOARD_ID: - /* No retimer on Port-2 hence no platform level AUX & LSx mux */ -#if defined(HAS_TASK_PD_C2) - if (port == TYPE_C_PORT_2) - tbt_usb4 = false; -#endif - break; - - /* Add additional board SKUs */ - default: - break; - } - - return tbt_usb4; -} diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h deleted file mode 100644 index 31bfc5aded..0000000000 --- a/baseboard/intelrvp/adlrvp.h +++ /dev/null @@ -1,193 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel ADL-RVP specific configuration */ - -#ifndef __ADLRVP_BOARD_H -#define __ADLRVP_BOARD_H - -/* Temperature sensor */ -#define CONFIG_TEMP_SENSOR - -#include "baseboard.h" - -/* RVP Board ids */ -#define CONFIG_BOARD_VERSION_GPIO -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) - -/* MECC config */ -#define CONFIG_INTEL_RVP_MECC_VERSION_1_0 - -/* Support early firmware selection */ -#define CONFIG_VBOOT_EFS2 - -/* Chipset */ -#define CONFIG_CHIPSET_ALDERLAKE - -/* USB PD config */ -#if defined(HAS_TASK_PD_C3) -#define CONFIG_USB_PD_PORT_MAX_COUNT 4 -#elif defined(HAS_TASK_PD_C2) -#define CONFIG_USB_PD_PORT_MAX_COUNT 3 -#elif defined(HAS_TASK_PD_C1) -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#else -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -#endif -#define CONFIG_USB_MUX_VIRTUAL -#define PD_MAX_POWER_MW 100000 - -#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY - -/* TCPC AIC config */ -/* Support NXP PCA9675 I/O expander. */ -#define CONFIG_IO_EXPANDER -#define CONFIG_IO_EXPANDER_PCA9675 -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 - -/* DC Jack charge ports */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT -#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 -#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT - -/* PPC */ -#define CONFIG_USBC_PPC_SN5S330 -#define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PD_DISCHARGE_PPC -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 - -/* TCPC */ -#define CONFIG_USB_PD_DISCHARGE -#define CONFIG_USB_PD_TCPM_FUSB302 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 - -/* Config BB retimer */ -#define CONFIG_USBC_RETIMER_INTEL_BB -#define CONFIG_USBC_RETIMER_FW_UPDATE - -/* Connector side BB retimers */ -#define I2C_PORT0_BB_RETIMER_ADDR 0x56 -#if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_ADDR 0x57 -#endif -#if defined(HAS_TASK_PD_C2) -#define I2C_PORT2_BB_RETIMER_ADDR 0x58 -#endif -#if defined(HAS_TASK_PD_C3) -#define I2C_PORT3_BB_RETIMER_ADDR 0x59 -#endif - -/* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 -#if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 -#endif - -/* I2C EEPROM */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO - -/* Enable CBI */ -#define CONFIG_CBI_EEPROM - -/* Configure mux at runtime */ -#define CONFIG_USB_MUX_RUNTIME_CONFIG - -/* Enable VCONN */ -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Enabling Thunderbolt-compatible mode */ -#define CONFIG_USB_PD_TBT_COMPAT_MODE - -/* Enabling USB4 mode */ -#define CONFIG_USB_PD_USB4 - -/* Enable low power mode */ -#define CONFIG_USB_PD_TCPC_LOW_POWER - -/* Config Fan */ -#define CONFIG_FANS 1 -#define BOARD_FAN_MIN_RPM 3000 -#define BOARD_FAN_MAX_RPM 10000 - -/* Charger */ -#define CONFIG_CHARGER_ISL9241 - -/* Port 80 */ -#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS - -/* Board Id */ -#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 - -/* - * Frequent watchdog timer resets are seen, with the - * increase in number of type-c ports. So increase - * the timer value to support more type-c ports. - */ -#ifdef VARIANT_INTELRVP_EC_IT8320 -#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3) -#undef CONFIG_WATCHDOG_PERIOD_MS -#define CONFIG_WATCHDOG_PERIOD_MS 4000 -#endif -#endif - -/* - * Enable support for battery hostcmd, supporting longer strings. - * Support for EC_CMD_BATTERY_GET_STATIC version 1. - */ -#define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 -#define CONFIG_HOSTCMD_BATTERY_V2 - -#ifndef __ASSEMBLER__ - -enum adlrvp_charge_ports { - TYPE_C_PORT_0, -#if defined(HAS_TASK_PD_C1) - TYPE_C_PORT_1, -#endif -#if defined(HAS_TASK_PD_C2) - TYPE_C_PORT_2, -#endif -#if defined(HAS_TASK_PD_C3) - TYPE_C_PORT_3, -#endif -}; - -/* - * Each Type-C add in card has two I/O expanders hence even if one Type-C port - * is enabled other I/O expander is available for usage. - */ -enum ioex_port { - IOEX_C0_PCA9675, - IOEX_C1_PCA9675, -#if defined(HAS_TASK_PD_C2) - IOEX_C2_PCA9675, - IOEX_C3_PCA9675, -#endif - IOEX_PORT_COUNT -}; -#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT - -enum battery_type { - BATTERY_GETAC_SMP_HHP_408, - BATTERY_TYPE_COUNT, -}; - -void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); -void extpower_interrupt(enum gpio_signal signal); -void ppc_interrupt(enum gpio_signal signal); -void tcpc_alert_event(enum gpio_signal signal); -void board_connect_c0_sbu(enum gpio_signal s); -int board_get_version(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __ADLRVP_BOARD_H */ diff --git a/baseboard/intelrvp/adlrvp_battery2s.c b/baseboard/intelrvp/adlrvp_battery2s.c deleted file mode 100644 index bc61b407a0..0000000000 --- a/baseboard/intelrvp/adlrvp_battery2s.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery_fuel_gauge.h" -#include "battery_smart.h" -#include "common.h" -#include "util.h" - -const struct board_batt_params board_battery_info[] = { - /* - * Getac Battery (Getac SMP-HHP-408) Information - * Fuel gauge: BQ40Z50-R3 - */ - [BATTERY_GETAC_SMP_HHP_408] = { - .fuel_gauge = { - .manuf_name = "Getac", - .ship_mode = { - .reg_addr = 0x00, - .reg_data = { 0x0010, 0x0010 }, - }, - .fet = { - .reg_addr = 0x0, - .reg_mask = 0x6000, - .disconnect_val = 0x6000, - } - }, - .batt_info = { - .voltage_max = 8800, /* mV */ - .voltage_normal = 7700, - .voltage_min = 6000, - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 45, - .discharging_min_c = 0, - .discharging_max_c = 60, - }, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); - -const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408; - diff --git a/baseboard/intelrvp/adlrvp_battery3s.c b/baseboard/intelrvp/adlrvp_battery3s.c deleted file mode 100644 index 315d5c247e..0000000000 --- a/baseboard/intelrvp/adlrvp_battery3s.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery_fuel_gauge.h" -#include "battery_smart.h" -#include "common.h" -#include "util.h" - -const struct board_batt_params board_battery_info[] = { - /* - * Getac Battery (Getac SMP-HHP-408) Information - * Fuel gauge: BQ40Z50-R3 - */ - [BATTERY_GETAC_SMP_HHP_408] = { - .fuel_gauge = { - .manuf_name = "Getac", - .ship_mode = { - .reg_addr = 0x00, - .reg_data = { 0x0010, 0x0010 }, - }, - .fet = { - .reg_addr = 0x0, - .reg_mask = 0x6000, - .disconnect_val = 0x6000, - } - }, - .batt_info = { - .voltage_max = 13050, /* mV */ - .voltage_normal = 11400, - .voltage_min = 9000, - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 45, - .discharging_min_c = 0, - .discharging_max_c = 60, - }, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); - -const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408; - diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc deleted file mode 100644 index e5522b02b3..0000000000 --- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc +++ /dev/null @@ -1,31 +0,0 @@ -/* -*- mode:c -*- - * - * Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -IOEX(USB_C0_BB_RETIMER_RST, EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW) -IOEX(USB_C0_BB_RETIMER_LS_EN, EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW) -IOEX(USB_C0_USB_MUX_CNTRL_1, EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW) -IOEX(USB_C0_USB_MUX_CNTRL_0, EXPIN(IOEX_C0_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW) - -IOEX(USB_C1_BB_RETIMER_RST, EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW) -IOEX(USB_C1_BB_RETIMER_LS_EN, EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW) -IOEX(USB_C0_C1_OC, EXPIN(IOEX_C1_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH) - -#if defined(HAS_TASK_PD_C2) -IOEX(USB_C2_BB_RETIMER_RST, EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW) -IOEX(USB_C2_BB_RETIMER_LS_EN, EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW) -IOEX(USB_C2_USB_MUX_CNTRL_1, EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P04), GPIO_OUT_LOW) -IOEX(USB_C2_USB_MUX_CNTRL_0, EXPIN(IOEX_C2_PCA9675, 0, PCA9675_IO_P05), GPIO_OUT_LOW) - -IOEX(USB_C3_BB_RETIMER_RST, EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P00), GPIO_OUT_LOW) -IOEX(USB_C3_BB_RETIMER_LS_EN, EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P01), GPIO_OUT_LOW) -IOEX(USB_C2_C3_OC, EXPIN(IOEX_C3_PCA9675, 0, PCA9675_IO_P10), GPIO_OUT_HIGH) -#endif - -/* ADL-RVP has custom GPIO implementation for reading board ID */ -UNIMPLEMENTED(BOARD_VERSION1) -UNIMPLEMENTED(BOARD_VERSION2) -UNIMPLEMENTED(BOARD_VERSION3) diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c deleted file mode 100644 index 1e7b778c12..0000000000 --- a/baseboard/intelrvp/baseboard.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel-RVP family-specific configuration */ - -#include "adc_chip.h" -#include "charge_state.h" -#include "espi.h" -#include "fan.h" -#include "hooks.h" -#include "pca9555.h" -#include "peci.h" -#include "power.h" -#include "temp_sensor.h" -#include "temp_sensor/thermistor.h" -#include "timer.h" - -/* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_AC_PRESENT, - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -#ifdef CONFIG_TEMP_SENSOR -/* Temperature sensors */ -const struct temp_sensor_t temp_sensors[] = { - [TEMP_SNS_AMBIENT] = { - .name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v0_22k6_47k_4050b, - .idx = ADC_TEMP_SNS_AMBIENT, - }, - [TEMP_SNS_BATTERY] = { - .name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0, - }, - [TEMP_SNS_DDR] = { - .name = "DDR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v0_22k6_47k_4050b, - .idx = ADC_TEMP_SNS_DDR, - }, -#ifdef CONFIG_PECI - [TEMP_SNS_PECI] = { - .name = "PECI", - .type = TEMP_SENSOR_TYPE_CPU, - .read = peci_temp_sensor_get_val, - .idx = 0, - }, -#endif /* CONFIG_PECI */ - [TEMP_SNS_SKIN] = { - .name = "Skin", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v0_22k6_47k_4050b, - .idx = ADC_TEMP_SNS_SKIN, - }, - [TEMP_SNS_VR] = { - .name = "VR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v0_22k6_47k_4050b, - .idx = ADC_TEMP_SNS_VR, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - -const static struct ec_thermal_config thermal_a = { - .temp_host = { - [EC_TEMP_THRESH_WARN] = 0, - [EC_TEMP_THRESH_HIGH] = C_TO_K(75), - [EC_TEMP_THRESH_HALT] = C_TO_K(80), - }, - .temp_host_release = { - [EC_TEMP_THRESH_WARN] = 0, - [EC_TEMP_THRESH_HIGH] = C_TO_K(65), - [EC_TEMP_THRESH_HALT] = 0, - }, - .temp_fan_off = C_TO_K(15), - .temp_fan_max = C_TO_K(50), -}; - -struct ec_thermal_config thermal_params[] = { - [TEMP_SNS_AMBIENT] = thermal_a, - [TEMP_SNS_BATTERY] = thermal_a, - [TEMP_SNS_DDR] = thermal_a, -#ifdef CONFIG_PECI - [TEMP_SNS_PECI] = thermal_a, -#endif - [TEMP_SNS_SKIN] = thermal_a, - [TEMP_SNS_VR] = thermal_a, -}; -BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -#endif /* CONFIG_TEMP_SENSOR */ - -#ifdef CONFIG_FANS -/* Physical fan config */ -const struct fan_conf fan_conf_0 = { - .flags = FAN_USE_RPM_MODE, - .ch = 0, - .pgood_gpio = GPIO_ALL_SYS_PWRGD, - .enable_gpio = GPIO_FAN_POWER_EN, -}; - -/* Physical fan rpm config */ -const struct fan_rpm fan_rpm_0 = { - .rpm_min = BOARD_FAN_MIN_RPM, - .rpm_start = BOARD_FAN_MIN_RPM, - .rpm_max = BOARD_FAN_MAX_RPM, -}; - -/* FAN channels */ -const struct fan_t fans[] = { - [FAN_CH_0] = { - .conf = &fan_conf_0, - .rpm = &fan_rpm_0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); -#endif /* CONFIG_FANS */ - -static void board_init(void) -{ - /* Enable SOC SPI */ - gpio_set_level(GPIO_EC_SPI_OE_N, 1); -} -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST); - -static void board_interrupts_init(void) -{ - /* DC Jack interrupt */ - gpio_enable_interrupt(GPIO_DC_JACK_PRESENT); -} -DECLARE_HOOK(HOOK_INIT, board_interrupts_init, HOOK_PRIO_FIRST); - -int ioexpander_read_intelrvp_version(int *port0, int *port1) -{ - if (pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_0, port0)) - return -1; - - return pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_1, port1); -} - -__override void intel_x86_sys_reset_delay(void) -{ - /* - * From MAX6818 Data sheet, Range of 'Debounce Duaration' is - * Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms. - */ - udelay(60 * MSEC); -} diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h deleted file mode 100644 index de4cb671ac..0000000000 --- a/baseboard/intelrvp/baseboard.h +++ /dev/null @@ -1,274 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP board-specific configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#include "compiler.h" -#include "stdbool.h" - -#ifdef VARIANT_INTELRVP_EC_IT8320 - #include "ite_ec.h" -#elif defined(VARIANT_INTELRVP_EC_MCHP) - #include "mchp_ec.h" -#elif defined(VARIANT_INTELRVP_EC_NPCX) - #include "npcx_ec.h" -#else - #error "Define EC chip variant" -#endif - -/* - * Allow dangerous commands. - * TODO: Remove this config before production. - */ -#define CONFIG_SYSTEM_UNLOCKED - -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) -#undef CONFIG_HOSTCMD_DEBUG_MODE - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF - -/* EC console commands */ -#define CONFIG_CMD_CHARGER_DUMP -#define CONFIG_CMD_KEYBOARD -#define CONFIG_CMD_USB_PD_CABLE -#define CONFIG_CMD_USB_PD_PE - -/* Host commands */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET -#define CONFIG_HOSTCMD_PD_CONTROL - -/* Port80 display */ -#define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -/* Charger */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_SENSE_RESISTOR 5 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_TRICKLE_CHARGING - -/* - * Don't allow the system to boot to S0 when the battery is low and unable to - * communicate on locked systems (which haven't PD negotiated) - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 - -/* Keyboard */ - -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 - -/* UART */ -#define CONFIG_LOW_POWER_IDLE - -/* USB-A config */ - -/* BC1.2 config */ -#ifdef HAS_TASK_USB_CHG_P0 - #define CONFIG_CHARGE_RAMP_HW -#endif - -/* Enable USB-PD REV 3.0 */ -#define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PID 0x8086 - -/* USB PD config */ -#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1) - #define CONFIG_USB_PD_TCPMV1 - #define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 -#else - #define CONFIG_USB_DRP_ACC_TRYSRC - #define CONFIG_USB_PD_DECODE_SOP - #define CONFIG_USB_PD_TCPMV2 - #define CONFIG_USB_PD_TCPM_MUX -#endif -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_POWER_DELIVERY - -/* USB MUX */ -#ifdef CONFIG_USB_MUX_VIRTUAL - #define CONFIG_HOSTCMD_LOCATE_CHIP -#endif -#define CONFIG_USBC_SS_MUX - -/* SoC / PCH */ -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_HOST_EVENT -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE - -/* EC */ -#define CONFIG_LED_COMMON -#define CONFIG_LID_SWITCH -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_WP_ALWAYS - -/* Tablet mode */ -#define CONFIG_TABLET_MODE -#define CONFIG_GMR_TABLET_MODE - -/* Verified boot */ -#define CONFIG_CRC8 -#define CONFIG_SHA256_UNROLLED -#define CONFIG_VBOOT_HASH - -/* - * Enable 1 slot of secure temporary storage to support - * suspend/resume with read/write memory training. - */ -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -/* Temperature sensor */ -#ifdef CONFIG_TEMP_SENSOR - #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B - #define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A - #define CONFIG_THERMISTOR - #define CONFIG_THROTTLE_AP -#ifdef CONFIG_PECI - #define CONFIG_PECI_COMMON -#endif /* CONFIG_PECI */ -#endif /* CONFIG_TEMP_SENSOR */ - -/* I2C ports */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER - -/* EC exclude modules */ - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "module_id.h" -#include "registers.h" - -FORWARD_DECLARE_ENUM(tcpc_rp_value); - -/* PWM channels */ -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_COUNT -}; - -/* FAN channels */ -enum fan_channel { - FAN_CH_0, - FAN_CH_COUNT, -}; - -/* ADC channels */ -enum adc_channel { - ADC_TEMP_SNS_AMBIENT, - ADC_TEMP_SNS_DDR, - ADC_TEMP_SNS_SKIN, - ADC_TEMP_SNS_VR, - ADC_CH_COUNT, -}; - -/* Temperature sensors */ -enum temp_sensor_id { - TEMP_SNS_AMBIENT, - TEMP_SNS_BATTERY, - TEMP_SNS_DDR, -#ifdef CONFIG_PECI - TEMP_SNS_PECI, -#endif - TEMP_SNS_SKIN, - TEMP_SNS_VR, - TEMP_SENSOR_COUNT, -}; - -/* TODO(b:132652892): Verify the below numbers. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* Define typical operating power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) -#define DC_JACK_MAX_VOLTAGE_MV 19000 - -/* TCPC gpios */ -struct tcpc_gpio_t { - enum gpio_signal pin; - uint8_t pin_pol; -}; - -/* VCONN gpios */ -struct vconn_gpio_t { - enum gpio_signal cc1_pin; - enum gpio_signal cc2_pin; - uint8_t pin_pol; -}; - -struct tcpc_gpio_config_t { - /* VBUS interrput */ - struct tcpc_gpio_t vbus; - /* Source enable */ - struct tcpc_gpio_t src; - /* Sink enable */ - struct tcpc_gpio_t snk; -#if defined(CONFIG_USBC_VCONN) && defined(CHIP_FAMILY_IT83XX) - /* Enable VCONN */ - struct vconn_gpio_t vconn; -#endif - /* Enable source ILIM */ - struct tcpc_gpio_t src_ilim; -}; -extern const struct tcpc_gpio_config_t tcpc_gpios[]; - -struct tcpc_aic_gpio_config_t { - /* TCPC interrupt */ - enum gpio_signal tcpc_alert; - /* PPC interrupt */ - enum gpio_signal ppc_alert; - /* PPC interrupt handler */ - void (*ppc_intr_handler)(int port); -}; -extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[]; - -void board_charging_enable(int port, int enable); -void board_vbus_enable(int port, int enable); -void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp); -int ioexpander_read_intelrvp_version(int *port0, int *port1); -void board_dc_jack_interrupt(enum gpio_signal signal); -void tcpc_alert_event(enum gpio_signal signal); -bool is_typec_port(int port); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c deleted file mode 100644 index 9f212fba4e..0000000000 --- a/baseboard/intelrvp/bc12.c +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP BC1.2 specific configuration */ - -#include "common.h" -#include "max14637.h" - -/* BC1.2 chip Configuration */ -#ifdef CONFIG_BC12_DETECT_MAX14637 -const struct max14637_config_t max14637_config[] = { - [TYPE_C_PORT_0] = { - .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL, - .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, -#ifdef HAS_TASK_PD_C1 - [TYPE_C_PORT_1] = { - .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL, - .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, -#endif /* HAS_TASK_PD_C1 */ -}; -BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT); -#endif /* CONFIG_BC12_DETECT_MAX14637 */ diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk deleted file mode 100644 index 6abf8bbe0c..0000000000 --- a/baseboard/intelrvp/build.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -#Intel RVP common files -baseboard-y=baseboard.o -baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o - -ifneq ($(CONFIG_USB_POWER_DELIVERY),) -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o -baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o -baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o -baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o -baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o -endif - -#EC specific files -baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o -baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o -baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o - -#BC1.2 specific files -baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o - -#Common board specific files -ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \ - $(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \ - $(BOARD_ADLRVPP_MCHP1727)),) -baseboard-y+=adlrvp.o -ifneq ($(BOARD_ADLRVPM_ITE),) -baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery2s.o -else -baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery3s.o -endif -endif diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c deleted file mode 100644 index 9f64cdd4e7..0000000000 --- a/baseboard/intelrvp/chg_usb_pd.c +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common USB PD charge configuration */ - -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "hooks.h" -#include "tcpm/tcpci.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -bool is_typec_port(int port) -{ -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE); -#else - return !(port == CHARGE_PORT_NONE); -#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ -} - -static inline int board_dc_jack_present(void) -{ -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - return gpio_get_level(GPIO_DC_JACK_PRESENT); -#else - return 0; -#endif -} - -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 -static void board_dc_jack_handle(void) -{ - struct charge_port_info charge_dc_jack; - - /* System is booted from DC Jack */ - if (board_dc_jack_present()) { - charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) / - DC_JACK_MAX_VOLTAGE_MV; - charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; - } else { - charge_dc_jack.current = 0; - charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV; - } - - charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, &charge_dc_jack); -} -#endif - -void board_dc_jack_interrupt(enum gpio_signal signal) -{ -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - board_dc_jack_handle(); -#endif -} - -static void board_charge_init(void) -{ - int port, supplier; - struct charge_port_info charge_init = { - .current = 0, - .voltage = USB_CHARGER_VOLTAGE_MV, - }; - - /* Initialize all charge suppliers to seed the charge manager */ - for (port = 0; port < CHARGE_PORT_COUNT; port++) { - for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++) - charge_manager_update_charge(supplier, port, - &charge_init); - } - -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - board_dc_jack_handle(); -#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ -} -DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT); - -int board_set_active_charge_port(int port) -{ - int i; - /* charge port is a realy physical port */ - int is_real_port = (port >= 0 && - port < CHARGE_PORT_COUNT); - /* check if we are source vbus on that port */ - int source = board_vbus_source_enabled(port); - - if (is_real_port && source) { - CPRINTS("Skip enable p%d", port); - return EC_ERROR_INVAL; - } - -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - /* - * Do not enable Type-C port if the DC Jack is present. - * When the Type-C is active port, hardware circuit will - * block DC jack from enabling +VADP_OUT. - */ - if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) { - CPRINTS("DC Jack present, Skip enable p%d", port); - return EC_ERROR_INVAL; - } -#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */ - - /* Make sure non-charging ports are disabled */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (i == port) - continue; - - board_charging_enable(i, 0); - } - - /* Enable charging port */ - if (is_typec_port(port)) - board_charging_enable(port, 1); - - CPRINTS("New chg p%d", port); - - return EC_SUCCESS; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c deleted file mode 100644 index fa9f1e147f..0000000000 --- a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel-RVP family-specific configuration */ - -#include "console.h" -#include "hooks.h" -#include "tcpm/tcpci.h" -#include "system.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -/* Reset PD MCU */ -void board_reset_pd_mcu(void) -{ - /* Add code if TCPC chips need a reset */ -} - -int board_vbus_source_enabled(int port) -{ - int src_en = 0; - - /* Only Type-C ports can source VBUS */ - if (is_typec_port(port)) { - src_en = gpio_get_level(tcpc_gpios[port].src.pin); - - src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en; - } - - return src_en; -} - -void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) -{ - int ilim_en; - - /* Only Type-C ports can source VBUS */ - if (is_typec_port(port)) { - /* Enable SRC ILIM if rp is MAX single source current */ - ilim_en = (rp == TYPEC_RP_3A0 && - board_vbus_source_enabled(port)); - - gpio_set_level(tcpc_gpios[port].src_ilim.pin, - tcpc_gpios[port].src_ilim.pin_pol ? - ilim_en : !ilim_en); - } -} - -void board_charging_enable(int port, int enable) -{ - gpio_set_level(tcpc_gpios[port].snk.pin, - tcpc_gpios[port].snk.pin_pol ? enable : !enable); - -} - -void board_vbus_enable(int port, int enable) -{ - gpio_set_level(tcpc_gpios[port].src.pin, - tcpc_gpios[port].src.pin_pol ? enable : !enable); -} - -int pd_snk_is_vbus_provided(int port) -{ - int vbus_intr; - -#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - if (port == DEDICATED_CHARGE_PORT) - return 1; -#endif - - vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin); - - return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr; -} - -void tcpc_alert_event(enum gpio_signal signal) -{ - int i; - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (tcpc_gpios[i].vbus.pin == signal) { - schedule_deferred_pd_interrupt(i); - break; - } - } -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int i; - - /* Check which port has the ALERT line set */ - for (i = 0; i < CHARGE_PORT_COUNT; i++) { - /* No alerts for embdeded TCPC */ - if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) - continue; - - /* Add TCPC alerts if present */ - } - - return status; -} - -void board_tcpc_init(void) -{ - int i; - - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - /* Enable TCPCx interrupt */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) - gpio_enable_interrupt(tcpc_gpios[i].vbus.pin); -} -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c deleted file mode 100644 index 0c091efead..0000000000 --- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel-RVP family-specific configuration */ - -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "console.h" -#include "driver/ppc/sn5s330.h" -#include "hooks.h" -#include "tcpm/tcpci.h" -#include "system.h" -#include "usbc_ppc.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -/* Reset PD MCU */ -void board_reset_pd_mcu(void) -{ - /* Add code if TCPC chips need a reset */ -} - -static void baseboard_tcpc_init(void) -{ - int i; - - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - /* Enable PPC interrupts. */ - if (tcpc_aic_gpios[i].ppc_intr_handler) - gpio_enable_interrupt(tcpc_aic_gpios[i].ppc_alert); - - /* Enable TCPC interrupts. */ - if (tcpc_config[i].bus_type != EC_BUS_TYPE_EMBEDDED) - gpio_enable_interrupt(tcpc_aic_gpios[i].tcpc_alert); - } -} -DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_CHIPSET); - -void tcpc_alert_event(enum gpio_signal signal) -{ - int i; - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - /* No alerts for embdeded TCPC */ - if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) - continue; - - if (signal == tcpc_aic_gpios[i].tcpc_alert) { - schedule_deferred_pd_interrupt(i); - break; - } - } -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - int i; - - /* Check which port has the ALERT line set */ - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - /* No alerts for embdeded TCPC */ - if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) - continue; - - if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) - status |= PD_STATUS_TCPC_ALERT_0 << i; - } - - return status; -} - -int ppc_get_alert_status(int port) -{ - if (!tcpc_aic_gpios[port].ppc_intr_handler) - return 0; - - return !gpio_get_level(tcpc_aic_gpios[port].ppc_alert); -} - -/* PPC support routines */ -void ppc_interrupt(enum gpio_signal signal) -{ - int i; - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if (tcpc_aic_gpios[i].ppc_intr_handler && - signal == tcpc_aic_gpios[i].ppc_alert) { - tcpc_aic_gpios[i].ppc_intr_handler(i); - break; - } - } -} - -void board_charging_enable(int port, int enable) -{ - if (ppc_vbus_sink_enable(port, enable)) - CPRINTS("C%d: sink path %s failed", - port, enable ? "en" : "dis"); -} diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c deleted file mode 100644 index bafddc5f9e..0000000000 --- a/baseboard/intelrvp/ite_ec.c +++ /dev/null @@ -1,153 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP ITE EC specific configuration */ - -#include "adc_chip.h" -#include "common.h" -#include "it83xx_pd.h" -#include "keyboard_scan.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "timer.h" -#include "usb_pd_tcpm.h" - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - .output_settle_us = 35, - .debounce_down_us = 5 * MSEC, - .debounce_up_us = 40 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -/* ADC channels */ -const struct adc_t adc_channels[] = { - [ADC_TEMP_SNS_AMBIENT] = { - .name = "ADC_TEMP_SNS_AMBIENT", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_AMBIENT_CHANNEL, - }, - [ADC_TEMP_SNS_DDR] = { - .name = "ADC_TEMP_SNS_DDR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_DDR_CHANNEL, - }, - [ADC_TEMP_SNS_SKIN] = { - .name = "ADC_TEMP_SNS_SKIN", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_SKIN_CHANNEL, - }, - [ADC_TEMP_SNS_VR] = { - .name = "ADC_TEMP_SNS_VR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_VR_CHANNEL, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/* - * PWM HW channelx binding tachometer channelx for fan control. - * Four tachometer input pins but two tachometer modules only, - * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or - * [TACH_CH_TACH1A | TACH_CH_TACH1B] - */ -const struct fan_tach_t fan_tach[] = { - [PWM_HW_CH_DCR0] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR1] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR2] = { - .ch_tach = TACH_CH_TACH1A, - .fan_p = 2, - .rpm_re = 1, - .s_duty = 1, - }, - [PWM_HW_CH_DCR3] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR4] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR5] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR6] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR7] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL); - -/* PWM channels */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { - .channel = PWM_HW_CH_DCR2, - .flags = PWM_CONFIG_HAS_RPM_MODE, - .freq_hz = 30000, - .pcfsr_sel = PWM_PRESCALER_C7, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -#if defined(CONFIG_USBC_VCONN) && defined(CONFIG_USB_PD_TCPM_ITE_ON_CHIP) -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ -#ifndef CONFIG_USBC_PPC_VCONN - /* - * Setting VCONN low by disabling the power switch before - * enabling the VCONN on respective CC line - */ - gpio_set_level(tcpc_gpios[port].vconn.cc1_pin, - !tcpc_gpios[port].vconn.pin_pol); - gpio_set_level(tcpc_gpios[port].vconn.cc2_pin, - !tcpc_gpios[port].vconn.pin_pol); - - if (enabled) - gpio_set_level((cc_pin != USBPD_CC_PIN_1) ? - tcpc_gpios[port].vconn.cc2_pin : - tcpc_gpios[port].vconn.cc1_pin, - tcpc_gpios[port].vconn.pin_pol); -#endif -} -#endif diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h deleted file mode 100644 index c773a48b21..0000000000 --- a/baseboard/intelrvp/ite_ec.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP ITE EC specific configuration */ - -#ifndef __CROS_EC_ITE_EC_H -#define __CROS_EC_ITE_EC_H - -/* Optional feature - used by ITE */ -#define CONFIG_IT83XX_FLASH_CLOCK_48MHZ -#define CONFIG_IT83XX_VCC_1P8V - -/* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 - -#ifdef CONFIG_USBC_VCONN - #define CONFIG_USBC_VCONN_SWAP - /* delay to turn on/off vconn */ -#endif -#endif /* __CROS_EC_ITE_EC_H */ diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c deleted file mode 100644 index 47dad8994f..0000000000 --- a/baseboard/intelrvp/led.c +++ /dev/null @@ -1,106 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Power and battery LED control for Phaser - */ - -#include "chipset.h" -#include "ec_commands.h" -#include "gpio.h" -#include "led_common.h" -#include "led_states.h" - -#define LED_ON_LVL 0 -#define LED_OFF_LVL 1 - -const int led_charge_lvl_1 = 5; - -const int led_charge_lvl_2 = 97; - -struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; - -const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; - -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -void led_set_color_power(enum ec_led_colors color) -{ - if (color == EC_LED_COLOR_WHITE) - gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL); - else - /* LED_OFF and unsupported colors */ - gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL); -} - -void led_set_color_battery(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_RED: - gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); - break; - case EC_LED_COLOR_AMBER: - gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); - break; - case EC_LED_COLOR_GREEN: - gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); - break; - default: /* LED_OFF and other unsupported colors */ - gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); - break; - } -} - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - brightness_range[EC_LED_COLOR_RED] = 1; - brightness_range[EC_LED_COLOR_AMBER] = 1; - brightness_range[EC_LED_COLOR_GREEN] = 1; - } else if (led_id == EC_LED_ID_POWER_LED) { - brightness_range[EC_LED_COLOR_WHITE] = 1; - } -} - -int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - if (brightness[EC_LED_COLOR_RED] != 0) - led_set_color_battery(EC_LED_COLOR_RED); - else if (brightness[EC_LED_COLOR_AMBER] != 0) - led_set_color_battery(EC_LED_COLOR_AMBER); - else if (brightness[EC_LED_COLOR_GREEN] != 0) - led_set_color_battery(EC_LED_COLOR_GREEN); - else - led_set_color_battery(LED_OFF); - } else if (led_id == EC_LED_ID_POWER_LED) { - if (brightness[EC_LED_COLOR_WHITE] != 0) - led_set_color_power(EC_LED_COLOR_WHITE); - else - led_set_color_power(LED_OFF); - } - - return EC_SUCCESS; -} diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c deleted file mode 100644 index 5f8768bdd9..0000000000 --- a/baseboard/intelrvp/led_states.c +++ /dev/null @@ -1,188 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Power and battery LED state control for octopus boards - */ - -#include "battery.h" -#include "charge_state.h" -#include "chipset.h" -#include "console.h" -#include "ec_commands.h" -#include "extpower.h" -#include "hooks.h" -#include "led_common.h" -#include "led_states.h" - -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) - -static enum led_states led_get_state(void) -{ - int charge_lvl; - enum led_states new_state = LED_NUM_STATES; - - switch (charge_get_state()) { - case PWR_STATE_CHARGE: - /* Get percent charge */ - charge_lvl = charge_get_percent(); - /* Determine which charge state to use */ - if (charge_lvl < led_charge_lvl_1) - new_state = STATE_CHARGING_LVL_1; - else if (charge_lvl < led_charge_lvl_2) - new_state = STATE_CHARGING_LVL_2; - else - new_state = STATE_CHARGING_FULL_CHARGE; - break; - case PWR_STATE_DISCHARGE_FULL: - if (extpower_is_present()) { - new_state = STATE_CHARGING_FULL_CHARGE; - break; - } - /* Intentional fall-through */ - case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */: - if (chipset_in_state(CHIPSET_STATE_ON)) - new_state = STATE_DISCHARGE_S0; - else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - new_state = STATE_DISCHARGE_S3; - else - new_state = STATE_DISCHARGE_S5; - break; - case PWR_STATE_ERROR: - new_state = STATE_BATTERY_ERROR; - break; - case PWR_STATE_CHARGE_NEAR_FULL: - new_state = STATE_CHARGING_FULL_CHARGE; - break; - case PWR_STATE_IDLE: /* External power connected in IDLE */ - if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) - new_state = STATE_FACTORY_TEST; - else - new_state = STATE_DISCHARGE_S0; - break; - default: - /* Other states don't alter LED behavior */ - break; - } - - return new_state; -} - -static void led_update_battery(void) -{ - static uint8_t ticks, period; - static int led_state = LED_NUM_STATES; - int phase; - enum led_states desired_state = led_get_state(); - - /* - * We always need to check the current state since the value could - * have been manually overwritten. If we're in a new valid state, - * update our ticks and period info. If our new state isn't defined, - * continue using the previous one. - */ - if (desired_state != led_state && desired_state < LED_NUM_STATES) { - /* State is changing */ - led_state = desired_state; - /* Reset ticks and period when state changes */ - ticks = 0; - - period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - - } - - /* If this state is undefined, turn the LED off */ - if (period == 0) { - CPRINTS("Undefined LED behavior for battery state %d," - "turning off LED", led_state); - led_set_color_battery(LED_OFF); - return; - } - - /* - * Determine which phase of the state table to use. The phase is - * determined if it falls within first phase time duration. - */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; - ticks = (ticks + 1) % period; - - /* Set the color for the given state and phase */ - led_set_color_battery(led_bat_state_table[led_state][phase].color); -} - -static enum pwr_led_states pwr_led_get_state(void) -{ - if (extpower_is_present()) { - if (charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL) - return PWR_LED_STATE_OFF; - else - return PWR_LED_STATE_ON; - } else - return PWR_LED_STATE_SUSPEND_AC; -} - -static void led_update_power(void) -{ - static uint8_t ticks, period; - static enum pwr_led_states led_state = PWR_LED_NUM_STATES; - int phase; - enum pwr_led_states desired_state = pwr_led_get_state(); - - /* - * If we're in a new valid state, update our ticks and period info. - * Otherwise, continue to use old state - */ - if (desired_state != led_state && desired_state < PWR_LED_NUM_STATES) { - /* State is changing */ - led_state = desired_state; - /* Reset ticks and period when state changes */ - ticks = 0; - - period = led_pwr_state_table[led_state][LED_PHASE_0].time + - led_pwr_state_table[led_state][LED_PHASE_1].time; - - } - - /* If this state is undefined, turn the LED off */ - if (period == 0) { - CPRINTS("Undefined LED behavior for power state %d," - "turning off LED", led_state); - led_set_color_power(LED_OFF); - return; - } - - /* - * Determine which phase of the state table to use. The phase is - * determined if it falls within first phase time duration. - */ - phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; - ticks = (ticks + 1) % period; - - /* Set the color for the given state and phase */ - led_set_color_power(led_pwr_state_table[led_state][phase].color); -} - -static void led_init(void) -{ - /* If battery LED is enabled, set it to "off" to start with */ - if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) - led_set_color_battery(LED_OFF); -} -DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT); - -/* Called by hook task every hook tick (200 msec) */ -static void led_update(void) -{ - /* - * If battery LED is enabled, set its state based on our power and - * charge - */ - if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) - led_update_battery(); - if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) - led_update_power(); -} -DECLARE_HOOK(HOOK_TICK, led_update, HOOK_PRIO_DEFAULT); diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h deleted file mode 100644 index 907ff5c8b8..0000000000 --- a/baseboard/intelrvp/led_states.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Common functions for stateful LEDs (charger and power) - */ - -#ifndef __CROS_EC_BASEBOARD_LED_H -#define __CROS_EC_BASEBOARD_LED_H - -#include "ec_commands.h" - -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT - -/* - * All LED states should have one phase defined, - * and an additional phase can be defined for blinking - */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; - -/* - * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 - * - * STATE_CHARGING_LVL_2 is when led_charge_level_1 <= - * charge_percentage < led_charge_level_2 - * - * STATE_CHARGING_FULL_CHARGE is when led_charge_level_2 <= - * charge_percentage < 100 - */ -enum led_states { - STATE_CHARGING_LVL_1, - STATE_CHARGING_LVL_2, - STATE_CHARGING_FULL_CHARGE, - STATE_DISCHARGE_S0, - STATE_DISCHARGE_S0_BAT_LOW, - STATE_DISCHARGE_S3, - STATE_DISCHARGE_S5, - STATE_BATTERY_ERROR, - STATE_FACTORY_TEST, - LED_NUM_STATES -}; - -struct led_descriptor { - enum ec_led_colors color; - uint8_t time; -}; - - -/* Charging LED state table - defined in board's led.c */ -extern struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; - -/* Charging LED state level 1 - defined in board's led.c */ -extern const int led_charge_lvl_1; - -/* Charging LED state level 2 - defined in board's led.c */ -extern const int led_charge_lvl_2; - -enum pwr_led_states { - PWR_LED_STATE_ON, - PWR_LED_STATE_SUSPEND_AC, - PWR_LED_STATE_SUSPEND_NO_AC, - PWR_LED_STATE_OFF, - PWR_LED_NUM_STATES -}; - -/* Power LED state table - defined in board's led.c */ -extern const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; - -/** - * Set battery LED color - defined in board's led.c - * - * @param color Color to set on battery LED - * - */ -void led_set_color_battery(enum ec_led_colors color); - -/** - * Set power LED color - defined in board's led.c - */ -void led_set_color_power(enum ec_led_colors color); - -#endif /* __CROS_EC_BASEBOARD_LED_H */ diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c deleted file mode 100644 index f1eb4678c1..0000000000 --- a/baseboard/intelrvp/mchp_ec.c +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP MCHP EC specific configuration */ - -#include "adc_chip.h" -#include "common.h" -#include "keyboard_scan.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "timer.h" -#include "usb_pd_tcpm.h" - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80 us from 50 us. - */ - .output_settle_us = 80, - .debounce_down_us = 9 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -/* ADC channels */ -const struct adc_t adc_channels[] = { - [ADC_TEMP_SNS_AMBIENT] = { - .name = "ADC_TEMP_SNS_AMBIENT", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_AMBIENT_CHANNEL, - }, - [ADC_TEMP_SNS_DDR] = { - .name = "ADC_TEMP_SNS_DDR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_DDR_CHANNEL, - }, - [ADC_TEMP_SNS_SKIN] = { - .name = "ADC_TEMP_SNS_SKIN", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_SKIN_CHANNEL, - }, - [ADC_TEMP_SNS_VR] = { - .name = "ADC_TEMP_SNS_VR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = ADC_TEMP_SNS_VR_CHANNEL, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/* - * TODO - Fan and tach table. - * MCHP MEC1322 and MEC170x have fan speed controller(s) - * whereas MEC152x only has multiple TACH and PWM modules. - * MEC152x fan control will require a firmware layer that uses - * specified TACH and PWM modules. - */ - -/* PWM channels */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { -#ifdef CHIP_FAMILY_MEC172X - .channel = PWM_HW_CH_0, -#else - .channel = PWM_HW_CH_4, -#endif - .flags = PWM_CONFIG_HAS_RPM_MODE, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h deleted file mode 100644 index 227ccaef6d..0000000000 --- a/baseboard/intelrvp/mchp_ec.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP MCHP EC specific configuration */ - -#ifndef __CROS_EC_MCHP_EC_H -#define __CROS_EC_MCHP_EC_H - -/* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 - -/* - * ADC maximum voltage is a board level configuration. - * MEC152x ADC can use an external 3.0 or 3.3V reference with - * maximum values up to the reference voltage. - * The ADC maximum voltage depends upon the external reference - * voltage connected to MEC152x. - */ -#define ADC_MAX_MVOLT 3000 - -#endif /* __CROS_EC_MCHP_EC_H */ diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c deleted file mode 100644 index d6eca2e55b..0000000000 --- a/baseboard/intelrvp/npcx_ec.c +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP NPCX EC specific configuration */ - -#include "adc_chip.h" -#include "fan_chip.h" -#include "keyboard_scan.h" -#include "pwm_chip.h" -#include "time.h" - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - .output_settle_us = 35, - .debounce_down_us = 5 * MSEC, - .debounce_up_us = 40 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -/* ADC channels */ -const struct adc_t adc_channels[] = { - [ADC_TEMP_SNS_AMBIENT] = { - .name = "ADC_TEMP_SNS_AMBIENT", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .input_ch = ADC_TEMP_SNS_AMBIENT_CHANNEL, - }, - [ADC_TEMP_SNS_DDR] = { - .name = "ADC_TEMP_SNS_DDR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .input_ch = ADC_TEMP_SNS_DDR_CHANNEL, - }, - [ADC_TEMP_SNS_SKIN] = { - .name = "ADC_TEMP_SNS_SKIN", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .input_ch = ADC_TEMP_SNS_SKIN_CHANNEL, - }, - [ADC_TEMP_SNS_VR] = { - .name = "ADC_TEMP_SNS_VR", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .input_ch = ADC_TEMP_SNS_VR_CHANNEL, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/* PWM configuration */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { - .channel = PWN_FAN_CHANNEL, - .flags = 0, - .freq = 30000, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -const struct mft_t mft_channels[] = { - [MFT_CH_0] = { - .module = NPCX_MFT_MODULE_2, - .clk_src = TCKC_LFCLK, - .pwm_id = PWM_CH_FAN, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h deleted file mode 100644 index 52bcb2dae6..0000000000 --- a/baseboard/intelrvp/npcx_ec.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Intel BASEBOARD-RVP NPCX EC specific configuration */ - -#ifndef __CROS_EC_NPCX_EC_H -#define __CROS_EC_NPCX_EC_H - -#if !defined(__ASSEMBLER__) - -enum mft_channel { - MFT_CH_0 = 0, - /* Number of MFT channels */ - MFT_CH_COUNT, -}; - -#endif /* __ASSEMBLER__ */ - -/* ADC channels */ -#define ADC_MAX_MVOLT ADC_MAX_VOLT -#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 -#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 -#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 - -/* KSO2 is inverted */ -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV - -/* Fan */ -#define CONFIG_PWM -#define PWN_FAN_CHANNEL 3 - -/* GPIO64/65 are used as UART pins. */ -#define NPCX_UART_MODULE2 1 - -#endif /* __CROS_EC_NPCX_EC_H */ diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c deleted file mode 100644 index 6d173fd032..0000000000 --- a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "console.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_set_power_supply_ready(int port) -{ - /* Disable charging */ - board_charging_enable(port, 0); - - /* Provide VBUS */ - board_vbus_enable(port, 1); - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Ensure we advertise the proper available current quota */ - charge_manager_source_port(port, 1); -#endif - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; /* we are ready */ -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS */ - board_vbus_enable(port, 0); - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Give back the current quota we are no longer using */ - charge_manager_source_port(port, 0); -#endif - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if PP5000 rail is enabled */ - return gpio_get_level(GPIO_EN_PP5000); -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - board_set_vbus_source_current_limit(port, rp); -} diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c deleted file mode 100644 index 29a538231f..0000000000 --- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "console.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = board_vbus_source_enabled(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if PP3300 rail is enabled */ - return gpio_get_level(GPIO_EN_PP3300_A); -} - -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} - -int board_vbus_source_enabled(int port) -{ - if (is_typec_port(port)) - return ppc_is_sourcing_vbus(port); - return 0; -} diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c deleted file mode 100644 index 00459b12bc..0000000000 --- a/baseboard/ite_evb/baseboard.c +++ /dev/null @@ -1,195 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* ite_evb baseboard configuration */ -#include "clock.h" -#include "common.h" -#include "console.h" -#include "fan.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "intc.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "lpc.h" -#include "power_button.h" -#include "pwm_chip.h" -#include "registers.h" -#include "spi.h" -#include "switch.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" -#include "gpio_list.h" - -#if defined(CONFIG_FANS) || defined(CONFIG_PWM) -const struct fan_conf fan_conf_0 = { - .flags = FAN_USE_RPM_MODE, - .ch = 0, /* Use MFT id to control fan */ - .pgood_gpio = -1, - .enable_gpio = -1, -}; - -const struct fan_rpm fan_rpm_0 = { - .rpm_min = 1500, - .rpm_start = 1500, - .rpm_max = 6500, -}; - -const struct fan_t fans[] = { - { .conf = &fan_conf_0, - .rpm = &fan_rpm_0, }, -}; -BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS); - -/* - * PWM HW channelx binding tachometer channelx for fan control. - * Four tachometer input pins but two tachometer modules only, - * so always binding [TACH_CH_TACH0A | TACH_CH_TACH0B] and/or - * [TACH_CH_TACH1A | TACH_CH_TACH1B] - */ -const struct fan_tach_t fan_tach[] = { - [PWM_HW_CH_DCR0] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR1] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR2] = { - .ch_tach = TACH_CH_TACH1A, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR3] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR4] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR5] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR6] = { - .ch_tach = TACH_CH_NULL, - .fan_p = -1, - .rpm_re = -1, - .s_duty = -1, - }, - [PWM_HW_CH_DCR7] = { - .ch_tach = TACH_CH_TACH0A, - .fan_p = 2, - .rpm_re = 50, - .s_duty = 30, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(fan_tach) == PWM_HW_CH_TOTAL); -#endif /* defined(CONFIG_FANS) || defined(CONFIG_PWM) */ - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - .output_settle_us = 35, - .debounce_down_us = 5 * MSEC, - .debounce_up_us = 40 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -#if defined(CONFIG_SPI_FLASH_PORT) -/* SPI devices */ -const struct spi_device_t spi_devices[] = { - [CONFIG_SPI_FLASH_PORT] = { - .port = CONFIG_SPI_FLASH_PORT, - .div = 0, - .gpio_cs = -1 - }, -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -#endif - -/* Initialize board. */ -static void board_init(void) -{ -} -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - -/* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_POWER_BUTTON_L, GPIO_LID_OPEN -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* - * I2C channels (A, B, and C) are using the same timing registers (00h~07h) - * at default. - * In order to set frequency independently for each channels, - * We use timing registers 09h~0Bh, and the supported frequency will be: - * 50KHz, 100KHz, 400KHz, or 1MHz. - * I2C channels (D, E and F) can be set different frequency on different ports. - * The I2C(D/E/F) frequency depend on the frequency of SMBus Module and - * the individual prescale register. - * The frequency of SMBus module is 24MHz on default. - * The allowed range of I2C(D/E/F) frequency is as following setting. - * SMBus Module Freq = PLL_CLOCK / ((IT83XX_ECPM_SCDCR2 & 0x0F) + 1) - * (SMBus Module Freq / 510) <= I2C Freq <= (SMBus Module Freq / 8) - * Channel D has multi-function and can be used as UART interface. - * Channel F is reserved for EC debug. - */ - -/* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA, - }, - { - .name = "evb-1", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA, - }, - { - .name = "evb-2", - .port = IT83XX_I2C_CH_B, - .kbps = 100, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA, - }, - { - .name = "opt-4", - .port = IT83XX_I2C_CH_E, - .kbps = 100, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA, - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/ite_evb/baseboard.h b/baseboard/ite_evb/baseboard.h deleted file mode 100644 index 7fe309491c..0000000000 --- a/baseboard/ite_evb/baseboard.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* ite_evb baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* Optional features */ -#define CONFIG_BATTERY_SMART -#define CONFIG_BOARD_VERSION_GPIO -#define CONFIG_FANS 1 -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_IT83XX_ENABLE_MOUSE_DEVICE -#define CONFIG_IT83XX_SMCLK2_ON_GPC7 -#define CONFIG_IT83XX_VCC_3P3V - -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LOW_POWER_S0 -#define CONFIG_PECI -#define CONFIG_PECI_COMMON -#define CONFIG_PECI_TJMAX 100 -#define CONFIG_POWER_BUTTON -#define CONFIG_PWM -/* Use CS0 of SSPI */ -#define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FLASH_PORT 0 -#define CONFIG_UART_HOST -#define CONFIG_HOSTCMD_LPC - -/* Optional console commands */ -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SCRATCHPAD -#define CONFIG_CMD_STACKOVERFLOW - -/* Debug */ -#undef CONFIG_CMD_FORCETIME -#undef CONFIG_HOOK_DEBUG -#undef CONFIG_KEYBOARD_DEBUG -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* I2C Bus Configuration */ -#define I2C_PORT_CHARGER IT83XX_I2C_CH_C -#define I2C_PORT_BATTERY IT83XX_I2C_CH_C - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/ite_evb/build.mk b/baseboard/ite_evb/build.mk deleted file mode 100644 index 77352145ee..0000000000 --- a/baseboard/ite_evb/build.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c deleted file mode 100644 index 59f3da13f5..0000000000 --- a/baseboard/ite_evb/usb_pd_policy.c +++ /dev/null @@ -1,140 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for ite_evb baseboard */ - -#include "adc.h" -#include "config.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "it83xx_pd.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_mux.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -/* ---------------- Power Data Objects (PDOs) ----------------- */ -#ifdef CONFIG_USB_PD_CUSTOM_PDO -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP) - -/* Threshold voltage of VBUS provided (mV) */ -#define PD_VBUS_PROVIDED_THRESHOLD 3900 - -const uint32_t pd_src_pdo[] = { - PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), -}; -const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); - -const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), - PDO_BATT(4500, 14000, 10000), - PDO_VAR(4500, 14000, 3000), -}; -const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); -#endif - -int pd_is_max_request_allowed(void) -{ - /* Max voltage request allowed */ - return 1; -} - -int pd_snk_is_vbus_provided(int port) -{ - int mv = ADC_READ_ERROR; - - switch (port) { - case USBPD_PORT_A: - mv = adc_read_channel(ADC_VBUSSA); - break; - case USBPD_PORT_B: - mv = adc_read_channel(ADC_VBUSSB); - break; - case USBPD_PORT_C: - mv = adc_read_channel(ADC_VBUSSC); - break; - } - - return mv > PD_VBUS_PROVIDED_THRESHOLD; -} - -int pd_set_power_supply_ready(int port) -{ - /* Provide VBUS */ - board_pd_vbus_ctrl(port, 1); - /* Vbus provided or not */ - return !pd_snk_is_vbus_provided(port); -} - -void pd_power_supply_reset(int port) -{ - /* Kill VBUS */ - board_pd_vbus_ctrl(port, 0); -} - - -__override int pd_check_data_swap(int port, enum pd_data_role data_role) -{ - /* Always allow data swap: we can be DFP or UFP for USB */ - return 1; -} - -int pd_check_vconn_swap(int port) -{ - /* - * VCONN is provided directly by the battery(PPVAR_SYS) - * but use the same rules as power swap - */ - return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0; -} - -/* ----------------- Vendor Defined Messages ------------------ */ -/* - * We don't have mux on pd evb and not define CONFIG_USBC_SS_MUX, - * so mux related functions do nothing then return. - */ -__override int svdm_enter_dp_mode(int port, uint32_t mode_caps) -{ - /* - * Do not enter dp mode, we let VDM enumeration stop after discover - * modes have done. - */ - return -1; -} - -__override void svdm_dp_post_config(int port) -{ -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - /* Ack */ - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ -} - -__override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) -{ - /* Return length 0, means nothing needn't tx */ - return 0; -} - -__override int svdm_dp_config(int port, uint32_t *payload) -{ - /* Return length 0, means nothing needn't tx */ - return 0; -}; diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c deleted file mode 100644 index f6a6b23110..0000000000 --- a/baseboard/kalista/baseboard.c +++ /dev/null @@ -1,516 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Kalista baseboard configuration */ - -#include "adc.h" -#include "baseboard.h" -#include "battery.h" -#include "bd99992gw.h" -#include "board_config.h" -#include "button.h" -#include "chipset.h" -#include "console.h" -#include "cros_board_info.h" -#include "driver/pmic_tps650x30.h" -#include "driver/temp_sensor/tmp432.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "espi.h" -#include "extpower.h" -#include "espi.h" -#include "fan.h" -#include "fan_chip.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "i2c.h" -#include "math_util.h" -#include "oz554.h" -#include "pi3usb9281.h" -#include "power.h" -#include "power_button.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "spi.h" -#include "switch.h" -#include "system.h" -#include "task.h" -#include "temp_sensor.h" -#include "timer.h" -#include "uart.h" -#include "usb_charge.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -static uint8_t board_version; -static uint32_t oem; -static uint32_t sku; - -enum bj_adapter { - BJ_90W_19V, - BJ_135W_19V, -}; - -/* - * Bit masks to map SKU ID to BJ adapter wattage. 1:135W 0:90W - * KBL-R i7 8550U 4 135 - * KBL-R i5 8250U 5 135 - * KBL-R i3 8130U 6 135 - * KBL-U i7 7600 3 135 - * KBL-U i5 7500 2 135 - * KBL-U i3 7100 1 90 - * KBL-U Celeron 3965 7 90 - * KBL-U Celeron 3865 0 90 - */ -#define BJ_ADAPTER_135W_MASK (1 << 4 | 1 << 5 | 1 << 6 | 1 << 3 | 1 << 2) - -static void tcpc_alert_event(enum gpio_signal signal) -{ - if (!gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) - return; -#ifdef HAS_TASK_PDCMD - /* Exchange status with TCPCs */ - host_command_pd_send_status(PD_CHARGE_NO_CHANGE); -#endif -} - -void vbus0_evt(enum gpio_signal signal) -{ - task_wake(TASK_ID_PD_C0); -} - -#include "gpio_list.h" - -/* Hibernate wake configuration */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* ADC channels */ -const struct adc_t adc_channels[] = { - /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/* TODO: Verify fan control and mft */ -const struct fan_conf fan_conf_0 = { - .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ - .pgood_gpio = -1, - .enable_gpio = GPIO_FAN_PWR_EN, -}; - -const struct fan_rpm fan_rpm_0 = { - .rpm_min = 2180, - .rpm_start = 2180, - .rpm_max = 4900, -}; - -const struct fan_t fans[] = { - [FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, }, -}; -BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); - -const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, -}; -BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); - -const struct i2c_port_t i2c_ports[] = { - {"tcpc", I2C_PORT_TCPC0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA}, - {"eeprom", I2C_PORT_EEPROM, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA}, - {"backlight", I2C_PORT_BACKLIGHT, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, - {"pmic", I2C_PORT_PMIC, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, - {"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/* TCPC mux configuration */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - /* Alert is active-low, push-pull */ - { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = I2C_ADDR_TCPC0_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - }, -}; - -static int ps8751_tune_mux(const struct usb_mux *me) -{ - /* 0x98 sets lower EQ of DP port (4.5db) */ - mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98); - return EC_SUCCESS; -} - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, - }, -}; - -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_USB1_ENABLE, - GPIO_USB2_ENABLE, - GPIO_USB3_ENABLE, - GPIO_USB4_ENABLE, -}; - -void board_reset_pd_mcu(void) -{ - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); - msleep(1); - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); -} - -void board_tcpc_init(void) -{ - int reg; - - /* This needs to be executed only once per boot. It could be run by RO - * if we boot in recovery mode. It could be run by RW if we boot in - * normal or dev mode. Note EFS makes RO jump to RW before HOOK_INIT. */ - board_reset_pd_mcu(); - - /* - * Wake up PS8751. If PS8751 remains in low power mode after sysjump, - * TCPM_INIT will fail due to not able to access PS8751. - * Note PS8751 A3 will wake on any I2C access. - */ - i2c_read8(I2C_PORT_TCPC0, I2C_ADDR_TCPC0_FLAGS, 0xA0, ®); - - /* Enable TCPC interrupts */ - gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); - - /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ - for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); - -uint16_t tcpc_get_alert_status(void) -{ - if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) && - gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) - return PD_STATUS_TCPC_ALERT_0; - return 0; -} - -/* - * TMP431 has one local and one remote sensor. - * - * Temperature sensors data; must be in same order as enum temp_sensor_id. - * Sensor index and name must match those present in coreboot: - * src/mainboard/google/${board}/acpi/dptf.asl - */ -const struct temp_sensor_t temp_sensors[] = { - {"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, -}; -BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - -/* - * Thermal limits for each temp sensor. All temps are in degrees K. Must be in - * same order as enum temp_sensor_id. To always ignore any temp, use 0. - */ -struct ec_thermal_config thermal_params[] = { - /* {Twarn, Thigh, Thalt}, <on> - * {Twarn, Thigh, X }, <off> - * fan_off, fan_max - */ - {{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0}, - C_TO_K(4), C_TO_K(76)}, /* TMP431_Internal */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* TMP431_Sensor_1 */ -}; -BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); - -/* Initialize PMIC */ -#define I2C_PMIC_READ(reg, data) \ - i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data)) - -#define I2C_PMIC_WRITE(reg, data) \ - i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data)) - -static void board_pmic_init(void) -{ - int err; - int error_count = 0; - static uint8_t pmic_initialized = 0; - - if (pmic_initialized) - return; - - /* Read vendor ID */ - while (1) { - int data; - err = I2C_PMIC_READ(TPS650X30_REG_VENDORID, &data); - if (!err && data == TPS650X30_VENDOR_ID) - break; - else if (error_count > 5) - goto pmic_error; - error_count++; - } - - /* - * VCCIOCNT register setting - * [6] : CSDECAYEN - * otherbits: default - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_VCCIOCNT, 0x4A); - if (err) - goto pmic_error; - - /* - * VRMODECTRL: - * [4] : VCCIOLPM clear - * otherbits: default - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_VRMODECTRL, 0x2F); - if (err) - goto pmic_error; - - /* - * PGMASK1 : Exclude VCCIO from Power Good Tree - * [7] : MVCCIOPG clear - * otherbits: default - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_PGMASK1, 0x80); - if (err) - goto pmic_error; - - /* - * PWFAULT_MASK1 Register settings - * [7] : 1b V4 Power Fault Masked - * [4] : 1b V7 Power Fault Masked - * [2] : 1b V9 Power Fault Masked - * [0] : 1b V13 Power Fault Masked - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_PWFAULT_MASK1, 0x95); - if (err) - goto pmic_error; - - /* - * Discharge control 4 register configuration - * [7:6] : 00b Reserved - * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm - * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm - * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT4, 0x15); - if (err) - goto pmic_error; - - /* - * Discharge control 3 register configuration - * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm - * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm - * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm - * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT3, 0x55); - if (err) - goto pmic_error; - - /* - * Discharge control 2 register configuration - * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm - * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm - * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm - * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT2, 0x55); - if (err) - goto pmic_error; - - /* - * Discharge control 1 register configuration - * [7:2] : 00b Reserved - * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_DISCHCNT1, 0x01); - if (err) - goto pmic_error; - - /* - * Increase Voltage - * [7:0] : 0x2a default - * [5:4] : 10b default - * [5:4] : 01b 5.1V (0x1a) - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_V5ADS3CNT, 0x1a); - if (err) - goto pmic_error; - - /* - * PBCONFIG Register configuration - * [7] : 1b Power button debounce, 0ms (no debounce) - * [6] : 0b Power button reset timer logic, no action (default) - * [5:0] : 011111b Force an Emergency reset time, 31s (default) - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_PBCONFIG, 0x9F); - if (err) - goto pmic_error; - - /* - * V3.3A_DSW (VR3) control. Default: 0x2A. - * [7:6] : 00b Disabled - * [5:4] : 00b Vnom + 3%. (default: 10b 0%) - */ - err = I2C_PMIC_WRITE(TPS650X30_REG_V33ADSWCNT, 0x0A); - if (err) - goto pmic_error; - - CPRINTS("PMIC init done"); - pmic_initialized = 1; - return; - -pmic_error: - CPRINTS("PMIC init failed"); -} - -void chipset_pre_init_callback(void) -{ - board_pmic_init(); -} - -/** - * Notify PCH of the AC presence. - */ -static void board_extpower(void) -{ - gpio_set_level(GPIO_PCH_ACPRESENT, extpower_is_present()); -} -DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT); - -int64_t get_time_dsw_pwrok(void) -{ - /* DSW_PWROK is turned on before EC was powered. */ - return -20 * MSEC; -} - -const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -struct fan_step { - int on; - int off; - int rpm; -}; - -/* Note: Do not make the fan on/off point equal to 0 or 100 */ -static const struct fan_step fan_table0[] = { - {.on = 0, .off = 5, .rpm = 0}, - {.on = 30, .off = 5, .rpm = 2180}, - {.on = 49, .off = 46, .rpm = 2680}, - {.on = 53, .off = 50, .rpm = 3300}, - {.on = 58, .off = 54, .rpm = 3760}, - {.on = 63, .off = 59, .rpm = 4220}, - {.on = 68, .off = 64, .rpm = 4660}, - {.on = 75, .off = 70, .rpm = 4900}, -}; -/* All fan tables must have the same number of levels */ -#define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) - -static const struct fan_step *fan_table = fan_table0; - - -static void cbi_init(void) -{ - uint32_t val; - if (cbi_get_board_version(&val) == EC_SUCCESS && val <= UINT8_MAX) - board_version = val; - CPRINTS("Board Version: 0x%02x", board_version); - - if (cbi_get_oem_id(&val) == EC_SUCCESS && val < OEM_COUNT) - oem = val; - CPRINTS("OEM: %d", oem); - - if (cbi_get_sku_id(&val) == EC_SUCCESS) - sku = val; - CPRINTS("SKU: 0x%08x", sku); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); - -static void setup_bj(void) -{ - enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? - BJ_135W_19V : BJ_90W_19V; - gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V); -} - -static void board_init(void) -{ - setup_bj(); - - board_extpower(); - - gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L); -} -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - -int fan_percent_to_rpm(int fan, int pct) -{ - static int current_level; - static int previous_pct; - int i; - - /* - * Compare the pct and previous pct, we have the three paths : - * 1. decreasing path. (check the off point) - * 2. increasing path. (check the on point) - * 3. invariant path. (return the current RPM) - */ - if (pct < previous_pct) { - for (i = current_level; i >= 0; i--) { - if (pct <= fan_table[i].off) - current_level = i - 1; - else - break; - } - } else if (pct > previous_pct) { - for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) { - if (pct >= fan_table[i].on) - current_level = i; - else - break; - } - } - - if (current_level < 0) - current_level = 0; - - previous_pct = pct; - - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) - cprints(CC_THERMAL, "Setting fan RPM to %d", - fan_table[current_level].rpm); - - return fan_table[current_level].rpm; -} diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h deleted file mode 100644 index 230b815a48..0000000000 --- a/baseboard/kalista/baseboard.h +++ /dev/null @@ -1,238 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Kalista baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * Allow dangerous commands. - * TODO: Remove this config before production. - */ -#undef CONFIG_SYSTEM_UNLOCKED -#define CONFIG_USB_PD_COMM_LOCKED - -/* EC */ -#define CONFIG_ADC -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_BOARD_HAS_RTC_RESET -#define CONFIG_CRC8 -#define CONFIG_CEC -#define CONFIG_CBI_EEPROM -#define CONFIG_DEDICATED_RECOVERY_BUTTON -#define CONFIG_EMULATED_SYSRQ -#define CONFIG_LED_COMMON -#define CONFIG_MKBP_INPUT_DEVICES -#define CONFIG_MKBP_USE_HOST_EVENT -#define CONFIG_DPTF -#define CONFIG_FLASH_SIZE_BYTES 0x80000 -#define CONFIG_FPU -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#undef CONFIG_LID_SWITCH -#define CONFIG_POWER_BUTTON_IGNORE_LID -#define CONFIG_PWM -#define CONFIG_LTO -#define CONFIG_CHIP_PANIC_BACKUP -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25X40 -#define CONFIG_WATCHDOG_HELP -#define CONFIG_WIRELESS -#define CONFIG_WIRELESS_SUSPEND \ - (EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER) -#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L -#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN -#define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE -#define CEC_GPIO_OUT GPIO_CEC_OUT -#define CEC_GPIO_IN GPIO_CEC_IN -#define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP -#define CONFIG_FANS 1 -#define CONFIG_FAN_RPM_CUSTOM -#define CONFIG_THROTTLE_AP -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_PWM - -/* EC console commands */ -#define CONFIG_CMD_BUTTON - -/* SOC */ -#define CONFIG_CHIPSET_SKYLAKE -#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET -#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 - -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_BUTTON_INIT_IDLE -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30 -#define CONFIG_DELAY_DSW_PWROK_TO_PWRBTN - -/* Sensor */ -#define CONFIG_TEMP_SENSOR -#define CONFIG_TEMP_SENSOR_TMP432 - -/* USB */ -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_CUSTOM_PDO -#define CONFIG_USB_PD_DISCHARGE_TCPC -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -#define CONFIG_USB_PD_VBUS_DETECT_GPIO -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPM_PS8751 -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV1 -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN - -/* USB-A config */ -#define CONFIG_USB_PORT_POWER_DUMB -#define USB_PORT_COUNT 4 - -/* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ - -/* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 -#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 - -/* I2C addresses */ -#define I2C_ADDR_TCPC0_FLAGS 0x0b -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -/* Verify and jump to RW image on boot */ -#define CONFIG_VBOOT_EFS -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -/* - * LED backlight controller - */ -#define CONFIG_LED_DRIVER_OZ554 - -/* - * Flash layout. Since config_flash_layout.h is included before board.h, - * we can only overwrite (=undef/define) these parameters here. - * - * Flash stores 3 images: RO, RW_A, RW_B. We divide the flash by 4. - * A public key is stored at the end of RO. Signatures are stored at the - * end of RW_A and RW_B, respectively. - */ -#define CONFIG_RW_B -#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF -#undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) -#undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE) -#define CONFIG_RW_A_SIGN_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define CONFIG_RW_B_SIGN_STORAGE_OFF (CONFIG_RW_B_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) - -#undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE - -#define CONFIG_RWSIG -#define CONFIG_RWSIG_TYPE_RWSIG -#define CONFIG_RSA -#ifdef SECTION_IS_RO -#define CONFIG_RSA_OPTIMIZED -#endif -#define CONFIG_SHA256 -#ifdef SECTION_IS_RO -#define CONFIG_SHA256_UNROLLED -#endif -#define CONFIG_RSA_KEY_SIZE 3072 -#define CONFIG_RSA_EXPONENT_3 - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "registers.h" - -enum charge_port { - CHARGE_PORT_TYPEC0, - CHARGE_PORT_BARRELJACK, -}; - -enum temp_sensor_id { - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ - TEMP_SENSOR_COUNT -}; - -enum adc_channel { - ADC_VBUS, - ADC_CH_COUNT -}; - -enum pwm_channel { - PWM_CH_LED_RED, - PWM_CH_LED_BLUE, - PWM_CH_FAN, - /* Number of PWM channels */ - PWM_CH_COUNT -}; - -enum fan_channel { - FAN_CH_0, - /* Number of FAN channels */ - FAN_CH_COUNT -}; - -enum mft_channel { - MFT_CH_0, - /* Number of MFT channels */ - MFT_CH_COUNT -}; - -enum OEM_ID { - OEM_KARMA = 7, - /* Number of OEM IDs */ - OEM_COUNT -}; - -/* TODO(crosbug.com/p/61098): Verify the numbers below. */ -/* - * delay to turn on the power supply max is ~16ms. - * delay to turn off the power supply max is about ~180ms. - */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* delay to turn on/off vconn */ - -/* Board specific handlers */ -void board_reset_pd_mcu(void); -void board_set_tcpc_power_mode(int port, int mode); -void led_alert(int enable); -void led_critical(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk deleted file mode 100644 index e64b6a2d71..0000000000 --- a/baseboard/kalista/build.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-y+=led.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
\ No newline at end of file diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c deleted file mode 100644 index e04eecf5e3..0000000000 --- a/baseboard/kalista/led.c +++ /dev/null @@ -1,232 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Power and battery LED control for Kalista - */ - -#include "chipset.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "hooks.h" -#include "led_common.h" -#include "pwm.h" -#include "timer.h" -#include "util.h" - -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -enum led_color { - LED_OFF = 0, - LED_RED, - LED_BLUE, - LED_AMBER, - - /* Number of colors, not a color itself */ - LED_COLOR_COUNT -}; - -static int set_color_power(enum led_color color, int duty) -{ - int blue = 0; - int red = 0; - - if (duty < 0 || 100 < duty) - return EC_ERROR_UNKNOWN; - - switch (color) { - case LED_OFF: - break; - case LED_BLUE: - blue = 1; - break; - case LED_RED: - red = 1; - break; - case LED_AMBER: - blue = 1; - red = 1; - break; - default: - return EC_ERROR_UNKNOWN; - } - - if (red) - pwm_set_duty(PWM_CH_LED_RED, duty); - else - pwm_set_duty(PWM_CH_LED_RED, 0); - - if (blue) - pwm_set_duty(PWM_CH_LED_BLUE, duty); - else - pwm_set_duty(PWM_CH_LED_BLUE, 0); - - return EC_SUCCESS; -} - -static int set_color(enum ec_led_id id, enum led_color color, int duty) -{ - switch (id) { - case EC_LED_ID_POWER_LED: - return set_color_power(color, duty); - default: - return EC_ERROR_UNKNOWN; - } -} - -#define LED_PULSE_US (2 * SECOND) -/* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) - -/* When pulsing is enabled, brightness is incremented by <duty_inc> every - * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented - * likewise in LED_PULSE_US usec. */ -static struct { - uint32_t interval; - int duty_inc; - enum led_color color; - int duty; -} led_pulse; - -#define LED_PULSE_TICK(interval, color) \ - config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color)) - -static void config_tick(uint32_t interval, int duty_inc, enum led_color color) -{ - led_pulse.interval = interval; - led_pulse.duty_inc = duty_inc; - led_pulse.color = color; - led_pulse.duty = 0; -} - -static void pulse_power_led(enum led_color color) -{ - set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty); - if (led_pulse.duty + led_pulse.duty_inc > 100) - led_pulse.duty_inc = led_pulse.duty_inc * -1; - else if (led_pulse.duty + led_pulse.duty_inc < 0) - led_pulse.duty_inc = led_pulse.duty_inc * -1; - led_pulse.duty += led_pulse.duty_inc; -} - -static void led_tick(void); -DECLARE_DEFERRED(led_tick); -static void led_tick(void) -{ - uint32_t elapsed; - uint32_t next = 0; - uint32_t start = get_time().le.lo; - static uint8_t pwm_enabled = 0; - - if (!pwm_enabled) { - pwm_enable(PWM_CH_LED_RED, 1); - pwm_enable(PWM_CH_LED_BLUE, 1); - pwm_enabled = 1; - } - if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) - pulse_power_led(led_pulse.color); - elapsed = get_time().le.lo - start; - next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0; - hook_call_deferred(&led_tick_data, next); -} - -static void led_suspend(void) -{ - LED_PULSE_TICK(LED_PULSE_TICK_US, LED_BLUE); - led_tick(); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend, HOOK_PRIO_DEFAULT); - -static void led_shutdown(void) -{ - hook_call_deferred(&led_tick_data, -1); - if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) - set_color(EC_LED_ID_POWER_LED, LED_OFF, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown, HOOK_PRIO_DEFAULT); - -static void led_resume(void) -{ - /* Assume there is no race condition with led_tick, which also - * runs in hook_task. */ - hook_call_deferred(&led_tick_data, -1); - if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) - set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT); - -void led_alert(int enable) -{ - if (enable) { - /* Overwrite the current signal */ - config_tick(1 * SECOND, 100, LED_RED); - led_tick(); - } else { - /* Restore the previous signal */ - if (chipset_in_state(CHIPSET_STATE_ON)) - led_resume(); - else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) - led_suspend(); - else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - led_shutdown(); - } -} - -void led_critical(void) -{ - hook_call_deferred(&led_tick_data, -1); - if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) - set_color(EC_LED_ID_POWER_LED, LED_RED, 100); -} - -static int command_led(int argc, char **argv) -{ - enum ec_led_id id = EC_LED_ID_POWER_LED; - - if (argc < 2) - return EC_ERROR_PARAM_COUNT; - - if (!strcasecmp(argv[1], "debug")) { - led_auto_control(id, !led_auto_control_is_enabled(id)); - ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n"); - } else if (!strcasecmp(argv[1], "off")) { - set_color(id, LED_OFF, 0); - } else if (!strcasecmp(argv[1], "red")) { - set_color(id, LED_RED, 100); - } else if (!strcasecmp(argv[1], "blue")) { - set_color(id, LED_BLUE, 100); - } else if (!strcasecmp(argv[1], "amber")) { - set_color(id, LED_AMBER, 100); - } else if (!strcasecmp(argv[1], "alert")) { - led_alert(1); - } else if (!strcasecmp(argv[1], "crit")) { - led_critical(); - } else { - return EC_ERROR_PARAM1; - } - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|blue|amber|off|alert|crit]", - "Turn on/off LED."); - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ - brightness_range[EC_LED_COLOR_RED] = 100; - brightness_range[EC_LED_COLOR_BLUE] = 100; - brightness_range[EC_LED_COLOR_AMBER] = 100; -} - -int led_set_brightness(enum ec_led_id id, const uint8_t *brightness) -{ - if (brightness[EC_LED_COLOR_RED]) - return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]); - else if (brightness[EC_LED_COLOR_BLUE]) - return set_color(id, LED_BLUE, brightness[EC_LED_COLOR_BLUE]); - else if (brightness[EC_LED_COLOR_AMBER]) - return set_color(id, LED_AMBER, brightness[EC_LED_COLOR_AMBER]); - else - return set_color(id, LED_OFF, 0); -} diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c deleted file mode 100644 index 89af4b50fb..0000000000 --- a/baseboard/kalista/usb_pd_policy.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "extpower.h" -#include "charge_manager.h" -#include "common.h" -#include "console.h" -#include "driver/tcpm/anx74xx.h" -#include "driver/tcpm/ps8xxx.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \ - PDO_FIXED_DATA_SWAP | \ - PDO_FIXED_COMM_CAP) - -const uint32_t pd_src_pdo[] = { - PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), -}; -const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); - -int board_vbus_source_enabled(int port) -{ - if (port != 0) - return 0; - return gpio_get_level(GPIO_USB_C0_5V_EN); -} - -int pd_set_power_supply_ready(int port) -{ - /* Enable VBUS source */ - gpio_set_level(GPIO_USB_C0_5V_EN, 1); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; /* we are ready */ -} - -void pd_power_supply_reset(int port) -{ - /* Disable VBUS source */ - gpio_set_level(GPIO_USB_C0_5V_EN, 0); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_snk_is_vbus_provided(int port) -{ - return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L); -} - -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags) -{ -} diff --git a/baseboard/keeby b/baseboard/keeby deleted file mode 120000 index 14558486f6..0000000000 --- a/baseboard/keeby +++ /dev/null @@ -1 +0,0 @@ -dedede
\ No newline at end of file diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c deleted file mode 100644 index 68542b4fb6..0000000000 --- a/baseboard/kukui/base_detect_kukui.c +++ /dev/null @@ -1,231 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "base_state.h" -#include "board.h" -#include "charge_manager.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "timer.h" -#include "usb_pd.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -/* Krane base detection code */ - -/* Base detection and debouncing */ -#define BASE_DETECT_DEBOUNCE_US (20 * MSEC) - -/* - * If the base status is unclear (i.e. not within expected ranges, read - * the ADC value again every 500ms. - */ -#define BASE_DETECT_RETRY_US (500 * MSEC) - -enum kukui_pogo_device_type { - DEVICE_TYPE_ERROR = -2, - DEVICE_TYPE_UNKNOWN = -1, - DEVICE_TYPE_DETACHED = 0, -#ifdef VARIANT_KUKUI_POGO_DOCK - DEVICE_TYPE_DOCK, -#endif - DEVICE_TYPE_KEYBOARD, - DEVICE_TYPE_COUNT, -}; - -struct { - int mv_low, mv_high; -} static const pogo_detect_table[] = { - [DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */ -#ifdef VARIANT_KUKUI_POGO_DOCK - [DEVICE_TYPE_DOCK] = {141, 173}, /* 10K, 0.5K ohm */ -#endif - [DEVICE_TYPE_KEYBOARD] = {270, 400}, /* 10K, 1K ohm */ -}; -BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT); - -static uint64_t base_detect_debounce_time; -static enum kukui_pogo_device_type pogo_type; - -int kukui_pogo_extpower_present(void) -{ -#ifdef VARIANT_KUKUI_POGO_DOCK - return pogo_type == DEVICE_TYPE_DOCK && - gpio_get_level(GPIO_POGO_VBUS_PRESENT); -#else - return 0; -#endif -} - -static enum kukui_pogo_device_type get_device_type(int mv) -{ - int i; - - if (mv == ADC_READ_ERROR) - return DEVICE_TYPE_ERROR; - - for (i = 0; i < DEVICE_TYPE_COUNT; i++) { - if (pogo_detect_table[i].mv_low <= mv && - mv <= pogo_detect_table[i].mv_high) - return i; - } - - return DEVICE_TYPE_UNKNOWN; -} - -static void enable_charge(int enable) -{ -#ifdef VARIANT_KUKUI_POGO_DOCK - if (enable) { - struct charge_port_info info = { - .voltage = 5000, .current = 1500}; - /* - * Set supplier type to PD to have same priority as type c - * port. - */ - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info); - } else { - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL); - } - pd_send_host_event(PD_EVENT_POWER_CHANGE); -#endif -} - -static void enable_power_supply(int enable) -{ - gpio_set_level(GPIO_EN_PP3300_POGO, enable); -} - -static void base_detect_deferred(void); -DECLARE_DEFERRED(base_detect_deferred); - -static void base_set_device_type(enum kukui_pogo_device_type device_type) -{ - switch (device_type) { - case DEVICE_TYPE_ERROR: - case DEVICE_TYPE_UNKNOWN: - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_RETRY_US); - break; - - case DEVICE_TYPE_DETACHED: - enable_power_supply(0); - enable_charge(0); - base_set_state(0); - break; - -#ifdef VARIANT_KUKUI_POGO_DOCK - case DEVICE_TYPE_DOCK: - enable_power_supply(0); - enable_charge(1); - base_set_state(1); - break; -#endif - - case DEVICE_TYPE_KEYBOARD: - enable_charge(0); - enable_power_supply(1); - base_set_state(1); - break; - - case DEVICE_TYPE_COUNT: - /* should not happen */ - break; - } -} - -static void base_detect_deferred(void) -{ - uint64_t time_now = get_time().val; - int mv; - - if (base_detect_debounce_time > time_now) { - hook_call_deferred(&base_detect_deferred_data, - base_detect_debounce_time - time_now); - return; - } - - /* - * Disable interrupt first to prevent it triggered by value - * changed from 1 to disabled state(=0). - */ - gpio_disable_interrupt(GPIO_POGO_ADC_INT_L); - gpio_set_flags(GPIO_POGO_ADC_INT_L, GPIO_ANALOG); - mv = adc_read_channel(ADC_POGO_ADC_INT_L); - /* restore the pin function */ - gpio_set_flags(GPIO_POGO_ADC_INT_L, GPIO_INT_BOTH); - gpio_enable_interrupt(GPIO_POGO_ADC_INT_L); - - pogo_type = get_device_type(mv); - CPRINTS("POGO: adc=%d, type=%d", mv, pogo_type); - - base_set_device_type(pogo_type); -} - -void pogo_adc_interrupt(enum gpio_signal signal) -{ - uint64_t time_now = get_time().val; - - if (base_detect_debounce_time <= time_now) { - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_DEBOUNCE_US); - } - - base_detect_debounce_time = time_now + BASE_DETECT_DEBOUNCE_US; -} - -static void pogo_chipset_init(void) -{ - /* Enable pogo interrupt */ - gpio_enable_interrupt(GPIO_POGO_ADC_INT_L); - - hook_call_deferred(&base_detect_deferred_data, 0); -} -DECLARE_HOOK(HOOK_INIT, pogo_chipset_init, HOOK_PRIO_DEFAULT); - -/* Called on AP S3 -> S5 transition */ -static void pogo_chipset_shutdown(void) -{ - /* Disable pogo interrupt */ - gpio_disable_interrupt(GPIO_POGO_ADC_INT_L); - - enable_power_supply(0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pogo_chipset_shutdown, HOOK_PRIO_DEFAULT); - -void base_force_state(enum ec_set_base_state_cmd state) -{ - if (state >= EC_SET_BASE_STATE_RESET) { - CPRINTS("BD forced reset"); - pogo_chipset_init(); - return; - } - - gpio_disable_interrupt(GPIO_POGO_ADC_INT_L); - pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED); - base_set_device_type(state == EC_SET_BASE_STATE_ATTACH - ? DEVICE_TYPE_KEYBOARD - : DEVICE_TYPE_DETACHED); - CPRINTS("BD forced %sconnected", state == EC_SET_BASE_STATE_ATTACH ? - "" : "dis"); -} - -#ifdef VARIANT_KUKUI_POGO_DOCK -static void board_pogo_charge_init(void) -{ - int i; - - /* Initialize all charge suppliers to 0 */ - for (i = 0; i < CHARGE_SUPPLIER_COUNT; i++) - charge_manager_update_charge(i, CHARGE_PORT_POGO, NULL); -} -DECLARE_HOOK(HOOK_INIT, board_pogo_charge_init, - HOOK_PRIO_CHARGE_MANAGER_INIT + 1); -#endif diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c deleted file mode 100644 index 3f9a1c36c6..0000000000 --- a/baseboard/kukui/baseboard.c +++ /dev/null @@ -1,222 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "charger.h" -#include "chipset.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "timer.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -#ifndef CONFIG_CHARGER_RUNTIME_CONFIG -#if defined(VARIANT_KUKUI_CHARGER_MT6370) -#include "driver/charger/rt946x.h" -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = RT946X_ADDR_FLAGS, - .drv = &rt946x_drv, - }, -}; -#elif defined(VARIANT_KUKUI_CHARGER_ISL9238) -#include "driver/charger/isl923x.h" -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; -#endif /* VARIANT_KUKUI_CHARGER_* */ - -#endif /* CONFIG_CHARGER_RUNTIME_CONFIG */ - -void board_reset_pd_mcu(void) -{ -} - -void board_config_pre_init(void) -{ -#ifdef VARIANT_KUKUI_EC_STM32F098 - STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1; - /* - * Remap USART1 and SPI2 DMA: - * - * Ch4: USART1_TX / Ch5: USART1_RX (1000) - * Ch6: SPI2_RX / Ch7: SPI2_TX (0011) - */ - STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | - (3 << 20) | (3 << 24); - -#elif defined(VARIANT_KUKUI_EC_STM32L431) -#ifdef CONFIG_DMA - dma_init(); -#endif - /* - * Remap USART1 and SPI2 DMA: - * - * DMA2_CH=DMA1_CH+8 - * - * Ch6 (DMA2): USART1_TX / Ch7: USART1_RX (0010) - * Ch4 (DMA1): SPI2_RX / Ch5: SPI2_TX (0010) - * - * (*((volatile unsigned long *)(0x400200A8UL))) = 0x00011000; - * (*((volatile unsigned long *)(0x400204A8UL))) = 0x00200000; - */ - - STM32_DMA_CSELR(STM32_DMAC_CH4) = (1 << 12) | (1 << 16); - STM32_DMA_CSELR(STM32_DMAC_CH14) = (2 << 20) | (2 << 24); -#endif -} - -enum kukui_board_version { - BOARD_VERSION_UNKNOWN = -1, - BOARD_VERSION_REV0 = 0, - BOARD_VERSION_REV1 = 1, - BOARD_VERSION_REV2 = 2, - BOARD_VERSION_REV3 = 3, - BOARD_VERSION_REV4 = 4, - BOARD_VERSION_REV5 = 5, - BOARD_VERSION_REV6 = 6, - BOARD_VERSION_REV7 = 7, - BOARD_VERSION_REV8 = 8, - BOARD_VERSION_REV9 = 9, - BOARD_VERSION_REV10 = 10, - BOARD_VERSION_REV11 = 11, - BOARD_VERSION_REV12 = 12, - BOARD_VERSION_REV13 = 13, - BOARD_VERSION_REV14 = 14, - BOARD_VERSION_REV15 = 15, - BOARD_VERSION_COUNT, -}; - -/* map from kukui_board_version to board id voltage in mv */ -#ifdef VARIANT_KUKUI_EC_IT81202 -const int16_t kukui_board_id_map[] = { - 136, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 388, /* 51.1k , 6.8K ohm */ - 584, /* 51.1K , 11K ohm */ - 785, /* 56K , 17.4K ohm */ - 993, /* 51.1K , 22K ohm */ - 1221, /* 51.1K , 30K ohm */ - 1433, /* 51.1K , 39.2K ohm */ - 1650, /* 56K , 56K ohm */ - 1876, /* 47K , 61.9K ohm */ - 2084, /* 47K , 80.6K ohm */ - 2273, /* 56K , 124K ohm */ - 2461, /* 51.1K , 150K ohm */ - 2672, /* 47K , 200K ohm */ - 2889, /* 47K , 330K ohm */ - 3086, /* 47K , 680K ohm */ - 3300, /* 56K , NC */ -}; - -#define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */ -#else -const int16_t kukui_board_id_map[] = { - 109, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 211, /* 51.1k , 6.8K ohm */ - 319, /* 51.1K , 11K ohm */ - 427, /* 56K , 17.4K ohm */ - 542, /* 51.1K , 22K ohm */ - 666, /* 51.1K , 30K ohm */ - 781, /* 51.1K , 39.2K ohm */ - 900, /* 56K , 56K ohm */ - 1023, /* 47K , 61.9K ohm */ - 1137, /* 47K , 80.6K ohm */ - 1240, /* 56K , 124K ohm */ - 1343, /* 51.1K , 150K ohm */ - 1457, /* 47K , 200K ohm */ - 1576, /* 47K , 330K ohm */ - 1684, /* 47K , 680K ohm */ - 1800, /* 56K , NC */ -}; - -#define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */ -#endif /* VARIANT_KUKUI_EC_IT81202 */ -BUILD_ASSERT(ARRAY_SIZE(kukui_board_id_map) == BOARD_VERSION_COUNT); - -int board_get_version(void) -{ - static int version = BOARD_VERSION_UNKNOWN; - int mv; - int i; - - if (version != BOARD_VERSION_UNKNOWN) - return version; - - gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 0); - /* Wait to allow cap charge */ - msleep(20); - mv = adc_read_channel(ADC_BOARD_ID); - - if (mv == ADC_READ_ERROR) - mv = adc_read_channel(ADC_BOARD_ID); - - gpio_set_level(GPIO_EC_BOARD_ID_EN_L, 1); - - for (i = 0; i < BOARD_VERSION_COUNT; ++i) { - if (mv < kukui_board_id_map[i] + THRESHOLD_MV) { - version = i; - break; - } - } - -#ifdef VARIANT_KUKUI_EC_STM32F098 - /* - * For devices without pogo, Disable ADC module after we detect the - * board version, since this is the only thing ADC module needs to do - * for this board. - */ - if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 && - version != BOARD_VERSION_UNKNOWN) - adc_disable(); -#endif - - return version; -} - -static void baseboard_spi_init(void) -{ -#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431) - /* Set SPI PA15,PB3/4/5/13/14/15 pins to high speed */ - STM32_GPIO_OSPEEDR(GPIO_A) |= 0xc0000000; - STM32_GPIO_OSPEEDR(GPIO_B) |= 0xfc000fc0; -#endif -} -DECLARE_HOOK(HOOK_INIT, baseboard_spi_init, HOOK_PRIO_INIT_SPI + 1); - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY); -} - -/* Enable or disable input devices, based on chipset state and tablet mode */ -#ifdef VARIANT_KUKUI_JACUZZI -__override void lid_angle_peripheral_enable(int enable) -{ - int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON); - - if (enable) { - keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE); - } else { - /* - * Ensure that the chipset is off before disabling the - * keyboard. When the chipset is on, the EC keeps the - * keyboard enabled and the AP decides whether to - * ignore input devices or not. - */ - if (!chipset_in_s0) - keyboard_scan_enable(0, - KB_SCAN_DISABLE_LID_ANGLE); - } -} -#endif diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h deleted file mode 100644 index 87ebeb40e1..0000000000 --- a/baseboard/kukui/baseboard.h +++ /dev/null @@ -1,357 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Kukui board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * Variant battery defines, pick one: - * VARIANT_KUKUI_BATTERY_MAX17055 - * VARIANT_KUKUI_BATTERY_MM8013 - * VARIANT_KUKUI_BATTERY_BQ27541 - * VARIANT_KUKUI_BATTERY_SMART - */ -#if defined(VARIANT_KUKUI_BATTERY_MAX17055) -#define CONFIG_BATTERY_MAX17055 -#define CONFIG_BATTERY_MAX17055_ALERT -#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ -#elif defined(VARIANT_KUKUI_BATTERY_MM8013) -#define CONFIG_BATTERY_MM8013 -#elif defined(VARIANT_KUKUI_BATTERY_BQ27541) -#define CONFIG_BATTERY_BQ27541 -#elif defined(VARIANT_KUKUI_BATTERY_SMART) -#define CONFIG_BATTERY_SMART -#define CONFIG_BATTERY_FUEL_GAUGE -#else -#error Must define a VARIANT_KUKUI_BATTERY -#endif /* VARIANT_KUKUI_BATTERY */ - -/* - * Variant charger defines, pick one: - * VARIANT_KUKUI_CHARGER_MT6370 - * VARIANT_KUKUI_CHARGER_ISL9238 - */ -#if defined(VARIANT_KUKUI_CHARGER_MT6370) -#define CONFIG_CHARGER_MT6370 -#define CONFIG_CHARGER_MT6370_BC12_GPIO -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_OTG -#define CONFIG_CHARGER_PROFILE_OVERRIDE -#define CONFIG_USB_PD_TCPM_MT6370 -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_DISCHARGE_TCPC -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - -/* TCPC MT6370 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* - * The Maximum input voltage is 13.5V, need another 5% tolerance. - * 12.85V * 1.05 = 13.5V - */ -#define PD_MAX_VOLTAGE_MV 12850 -#define CONFIG_USB_PD_PREFER_MV -#elif defined(VARIANT_KUKUI_CHARGER_ISL9238) -#define CONFIG_CHARGER_ISL9238C -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ -#define CONFIG_CHARGER_OTG -#define CONFIG_CHARGE_RAMP_HW - -/* TCPC FUSB302 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* b/2230219: 15V has better charging performance than 20V */ -#define PD_MAX_VOLTAGE_MV 15000 -#else -#error Must define a VARIANT_KUKUI_CHARGER -#endif /* VARIANT_KUKUI_CHARGER */ - -/* - * Variant pogo defines, if pick, VARIANT_KUKUI_POGO_KEYBOARD is mandatory - * VARIANT_KUKUI_POGO_KEYBOARD - * VARIANT_KUKUI_POGO_DOCK - */ -#ifdef VARIANT_KUKUI_POGO_DOCK -#ifndef VARIANT_KUKUI_POGO_KEYBOARD -#error VARIANT_KUKUI_POGO_KEYBOARD is mandatory if use dock -#endif /* !VARIANT_KUKUI_POGO_KEYBOARD */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT -#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 -#define DEDICATED_CHARGE_PORT 1 -#endif /* VARIANT_KUKUI_POGO_DOCK */ - -#ifdef VARIANT_KUKUI_POGO_KEYBOARD -#define CONFIG_DETACHABLE_BASE -#define CONFIG_BASE_ATTACHED_SWITCH -#endif - -/* define this if the board is jacuzzi family */ -#ifdef VARIANT_KUKUI_JACUZZI -#define CONFIG_HOSTCMD_AP_SET_SKUID -/* - * IT81202 based boards are variant of jacuzzi and I/O expander isn't required - * on them. - */ -#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431) -#define CONFIG_IO_EXPANDER -#define CONFIG_IO_EXPANDER_IT8801 -#define CONFIG_IO_EXPANDER_PORT_COUNT 1 -#define CONFIG_KEYBOARD_NOT_RAW - -#endif - -#define CONFIG_KEYBOARD_COL2_INVERTED - -#define CONFIG_GMR_TABLET_MODE -#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L -#define CONFIG_TABLET_MODE -#define CONFIG_TABLET_MODE_SWITCH - -#define PD_OPERATING_POWER_MW 30000 - -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -#else /* !VARIANT_KUKUI_JACUZZI */ - -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -#endif /* VARIANT_KUKUI_JACUZZI */ - -#if defined(SECTION_IS_RW) || defined(VARIANT_KUKUI_EC_IT81202) -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#endif - -/* - * Define this flag if board controls dp mux via gpio pins USB_C0_DP_OE_L and - * USB_C0_DP_POLARITY. - * - * board must provide function board_set_dp_mux_control(output_enable, polarity) - * - * #define VARIANT_KUKUI_DP_MUX_GPIO - */ - -/* Optional modules */ -#define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG -#define CONFIG_CHIPSET_MT8183 -#define CONFIG_CMD_ACCELS -#define CONFIG_EMULATED_SYSRQ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_VIRTUAL_BATTERY -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_LED_COMMON -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_POWER_COMMON -#define CONFIG_SPI -#define CONFIG_SWITCH - -#ifdef SECTION_IS_RO -#undef CONFIG_SYSTEM_UNLOCKED /* Disabled in RO to save space */ -#else -#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ -#endif - -/* Bootblock */ -#ifdef SECTION_IS_RO -#define CONFIG_BOOTBLOCK - -#define EMMC_SPI_PORT 2 -#endif - -/* Optional features */ -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BUTTON_TRIGGERED_RECOVERY -#define CONFIG_CHARGER_ILIM_PIN_DISABLED -#define CONFIG_FORCE_CONSOLE_RESUME -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_PRESERVE_LOGS - -/* Required for FAFT */ -#define CONFIG_CMD_BUTTON -#define CONFIG_CMD_CHARGEN - -/* By default, set hcdebug to off */ -#undef CONFIG_HOSTCMD_DEBUG_MODE -#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF - -#define CONFIG_LTO -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_IGNORE_LID -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_SOFTWARE_PANIC -#define CONFIG_VBOOT_HASH - -#define CONFIG_CHARGER -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2 -#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000 -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM -#define CONFIG_USB_CHARGER - -/* Increase tx buffer size, as we'd like to stream EC log to AP. */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -#define GPIO_LID_OPEN GPIO_HALL_INT_L - -#ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_FIFO -/* FIFO size is in power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#endif /* VARIANT_KUKUI_NO_SENSORS */ - -#ifndef VARIANT_KUKUI_TABLET_PWRBTN -#define POWERBTN_BOOT_DELAY 0 -#endif - -/* USB PD config */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_5V_EN_CUSTOM -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_PD_COMM_LOCKED - -#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_CUSTOM -#define CONFIG_BATTERY_REVIVE_DISCONNECT - -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#ifdef BOARD_KODAMA -#define PD_MAX_CURRENT_MA 2000 -#else -#define PD_MAX_CURRENT_MA 3000 -#endif - -/* Optional for testing */ -#undef CONFIG_PECI -#undef CONFIG_PSTORE - -#define CONFIG_TASK_PROFILING -#define CONFIG_MKBP_USE_GPIO - -/* - * Variant EC defines. Pick one: - * VARIANT_KUKUI_EC_STM32F098 - * VARIANT_KUKUI_EC_IT81202 - * VARIANT_KUKUI_EC_STM32L431 - */ -#if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431) -/* Timer selection */ -#define TIM_CLOCK32 2 -#define TIM_WATCHDOG 7 - -/* 48 MHz SYSCLK clock frequency */ -#ifdef VARIANT_KUKUI_EC_STM32L431 -#define CPU_CLOCK 80000000 -#else -#define CPU_CLOCK 48000000 -#endif - -#undef CONFIG_HIBERNATE -#define CONFIG_SPI_CONTROLLER -#define CONFIG_STM_HWTIMER32 -#define CONFIG_WATCHDOG_HELP -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 1 -#define CONFIG_UART_RX_DMA - -/* This option is limited to TCPMv1 */ -#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 -/* STM32F098 based boards use TCPMv1 */ -#define CONFIG_USB_PD_TCPMV1 -#define CONFIG_USB_PD_VBUS_DETECT_TCPC - -/* Modules we want to exclude */ -#undef CONFIG_CMD_BATTFAKE -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_HASH -#undef CONFIG_CMD_MD -#undef CONFIG_CMD_POWERINDEBUG -#undef CONFIG_CMD_TIMERINFO - -/* save space at RO image */ -#ifdef SECTION_IS_RO -#undef CONFIG_CMD_ADC -#undef CONFIG_CMD_APTHROTTLE -#undef CONFIG_CMD_CRASH -#undef CONFIG_CMD_HCDEBUG -#undef CONFIG_CMD_IDLE_STATS -#undef CONFIG_CMD_MFALLOW -#undef CONFIG_CMD_MMAPINFO -#undef CONFIG_CMD_PWR_AVG -#undef CONFIG_CMD_REGULATOR -#undef CONFIG_CMD_RW -#undef CONFIG_CMD_SHMEM -#undef CONFIG_CMD_SLEEPMASK -#undef CONFIG_CMD_SLEEPMASK_SET -#undef CONFIG_CMD_SYSLOCK -#undef CONFIG_CMD_TYPEC -#undef CONFIG_HOSTCMD_FLASHPD -#undef CONFIG_HOSTCMD_RWHASHPD -#undef CONFIG_CONSOLE_CMDHELP - -#undef CONFIG_HOSTCMD_GET_UPTIME_INFO -#undef CONFIG_CMD_AP_RESET_LOG -#undef CONFIG_CMD_I2C_SCAN -#undef CONFIG_CMD_I2C_XFER - -/* free flash space */ -#undef CONFIG_USB_PD_DEBUG_LEVEL -#define CONFIG_USB_PD_DEBUG_LEVEL 0 -#undef CONFIG_USB_PD_LOGGING -#define CONFIG_COMMON_GPIO_SHORTNAMES -#define CONFIG_DEBUG_ASSERT_BRIEF -/* Exclude PD state names from RO image to save space */ -#undef CONFIG_USB_PD_TCPMV1_DEBUG -#endif -#elif defined(VARIANT_KUKUI_EC_IT81202) -#define CONFIG_IT83XX_HARD_RESET_BY_GPG1 -#define CONFIG_IT83XX_VCC_1P8V - -/* IT81202 based boards use TCPMv2 */ -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 -#define CONFIG_USB_PD_TCPMV2 -#else -#error "Must define a VARIANT_KUKUI_EC_XXX!" -#endif - -#ifndef __ASSEMBLER__ -#ifdef VARIANT_KUKUI_DP_MUX_GPIO -void board_set_dp_mux_control(int output_enable, int polarity); -#endif /* VARIANT_KUKUI_DP_MUX_GPIO */ - -/* If POGO pin is providing power. */ -int kukui_pogo_extpower_present(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c deleted file mode 100644 index 94f46b3326..0000000000 --- a/baseboard/kukui/battery_bq27541.c +++ /dev/null @@ -1,225 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery.h" -#include "charge_state.h" -#include "charger_mt6370.h" -#include "console.h" -#include "driver/tcpm/mt6370.h" -#include "ec_commands.h" -#include "util.h" - -#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT - -#define BATT_ID 0 - -#define BATTERY_CPT_CHARGE_MIN_TEMP 0 -#define BATTERY_CPT_CHARGE_MAX_TEMP 50 - -#define CHARGER_LIMIT_TIMEOUT_HOURS 48 -#define CHARGER_LIMIT_TIMEOUT_HOURS_TEMP 2 - -#define BAT_LEVEL_PD_LIMIT 85 - -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) - -enum battery_type { - BATTERY_CPT = 0, - BATTERY_COUNT -}; - -static const struct battery_info info[] = { - [BATTERY_CPT] = { - .voltage_max = 4400, - .voltage_normal = 3850, - .voltage_min = 3000, - .precharge_voltage = 3400, - .precharge_current = 256, - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 50, - .discharging_min_c = -20, - .discharging_max_c = 60, - }, -}; - -const struct battery_info *battery_get_info(void) -{ - return &info[BATT_ID]; -} - -int charger_profile_override(struct charge_state_data *curr) -{ - static timestamp_t deadline_48; - static timestamp_t deadline_2; - int cycle_count = 0, rv, val; - unsigned char rcv = 0, rcv_cycle = 0, rcv_soh = 0; - /* (FullCharge Capacity / Design Capacity) * 100 = SOH */ - int full_cap = 0, design_cap = 0, soh = 0; - /* battery temp in 0.1 deg C */ - int bat_temp_c = curr->batt.temperature - 2731; - /* - * Keep track of battery temperature range: - * - * ZONE_0 ZONE_1 ZONE_2 - * -----+--------+--------+------------+----- Temperature (C) - * t0 t1 t2 t3 - */ - enum { - TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */ - TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */ - TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */ - TEMP_ZONE_3, /* t3 < bat_temp_c <= t4 */ - TEMP_ZONE_COUNT - } temp_zone; - - static struct { - int temp_min; /* 0.1 deg C */ - int temp_max; /* 0.1 deg C */ - int desired_current; /* mA */ - int desired_voltage; /* mV */ - } temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = { - [BATTERY_CPT] = { - /* TEMP_ZONE_0 */ - {BATTERY_CPT_CHARGE_MIN_TEMP * 10, 150, 1408, 4370}, - /* TEMP_ZONE_1 */ - {150, 430, 3520, 4370}, - /* TEMP_ZONE_2 */ - {430, 450, 2112, 4320}, - /* TEMP_ZONE_3 */ - {450, BATTERY_CPT_CHARGE_MAX_TEMP * 10, 1760, 4170}, - }, - }; - BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT); - BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT); - - if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) || - (bat_temp_c < temp_zones[BATT_ID][0].temp_min) || - (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max)) - temp_zone = TEMP_OUT_OF_RANGE; - else { - for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { - if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) - break; - } - } - - switch (temp_zone) { - case TEMP_ZONE_0: - case TEMP_ZONE_1: - case TEMP_ZONE_2: - case TEMP_ZONE_3: - curr->requested_current = - temp_zones[BATT_ID][temp_zone].desired_current; - curr->requested_voltage = - temp_zones[BATT_ID][temp_zone].desired_voltage; - break; - case TEMP_OUT_OF_RANGE: - curr->requested_current = curr->requested_voltage = 0; - curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE; - curr->state = ST_IDLE; - break; - } - - /* Check cycle count to decrease charging voltage. */ - rv = battery_cycle_count(&val); - if (!rv) - cycle_count = val; - if (cycle_count > 20 && cycle_count <= 50) - rcv_cycle = 50; - else if (cycle_count > 50 && cycle_count <= 300) - rcv_cycle = 65; - else if (cycle_count > 300 && cycle_count <= 600) - rcv_cycle = 80; - else if (cycle_count > 600 && cycle_count <= 1000) - rcv_cycle = 100; - else if (cycle_count > 1000) - rcv_cycle = 150; - /* Check SOH to decrease charging voltage. */ - if (!battery_full_charge_capacity(&full_cap) && - !battery_design_capacity(&design_cap)) - soh = ((full_cap * 100) / design_cap); - if (soh > 70 && soh <= 75) - rcv_soh = 50; - else if (soh > 60 && soh <= 70) - rcv_soh = 65; - else if (soh > 55 && soh <= 60) - rcv_soh = 80; - else if (soh > 50 && soh <= 55) - rcv_soh = 100; - else if (soh <= 50) - rcv_soh = 150; - rcv = MAX(rcv_cycle, rcv_soh); - curr->requested_voltage -= rcv; - - /* Should not keep charging voltage > 4250mV for 48hrs. */ - if ((curr->state == ST_DISCHARGE) || - curr->chg.voltage < 4250) { - deadline_48.val = 0; - /* Starting count 48hours */ - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { - if (deadline_48.val == 0) - deadline_48.val = get_time().val + - CHARGER_LIMIT_TIMEOUT_HOURS * HOUR; - /* If charging voltage keep > 4250 for 48hrs, - * set charging voltage = 4250 - */ - else if (timestamp_expired(deadline_48, NULL)) - curr->requested_voltage = 4250; - } - /* Should not keeep battery voltage > 4100mV and - * battery temperature > 45C for two hour - */ - if (curr->state == ST_DISCHARGE || - curr->batt.voltage < 4100 || - bat_temp_c < 450) { - deadline_2.val = 0; - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { - if (deadline_2.val == 0) - deadline_2.val = get_time().val + - CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR; - else if (timestamp_expired(deadline_2, NULL)) { - /* Set discharge and charging voltage = 4100mV */ - if (curr->batt.voltage >= 4100) { - curr->requested_current = 0; - curr->requested_voltage = 4100; - } - } - } - -#ifdef VARIANT_KUKUI_CHARGER_MT6370 - mt6370_charger_profile_override(curr); -#endif /* CONFIG_CHARGER_MT6370 */ - - return 0; -} - -enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) -{ - return EC_RES_INVALID_PARAM; -} - -enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) -{ - return EC_RES_INVALID_PARAM; -} - -int get_battery_manufacturer_name(char *dest, int size) -{ - static const char * const name[] = { - [BATTERY_CPT] = "AS1XXXD3Ka", - }; - ASSERT(dest); - strzcpy(dest, name[BATT_ID], size); - return EC_SUCCESS; -} diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c deleted file mode 100644 index 6247f665aa..0000000000 --- a/baseboard/kukui/battery_max17055.c +++ /dev/null @@ -1,188 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery.h" -#include "charge_state.h" -#include "charger_mt6370.h" -#include "console.h" -#include "driver/battery/max17055.h" -#include "ec_commands.h" -#include "util.h" - -#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT - -#define BATT_ID 0 - -#define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0 -#define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60 - -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) - -enum battery_type { - BATTERY_SIMPLO = 0, - BATTERY_COUNT -}; - -static const struct battery_info info[] = { - [BATTERY_SIMPLO] = { - .voltage_max = 4400, - .voltage_normal = 3860, - .voltage_min = 3000, - .precharge_current = 256, - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 60, - .discharging_min_c = -20, - .discharging_max_c = 60, - }, -}; - -static const struct max17055_batt_profile batt_profile[] = { - [BATTERY_SIMPLO] = { - .is_ez_config = 1, - .design_cap = MAX17055_DESIGNCAP_REG(6910), - .ichg_term = MAX17055_ICHGTERM_REG(235), - .v_empty_detect = MAX17055_VEMPTY_REG(3000, 3600), - }, -}; - -static const struct max17055_alert_profile alert_profile[] = { - [BATTERY_SIMPLO] = { - .v_alert_mxmn = VALRT_DISABLE, - .t_alert_mxmn = MAX17055_TALRTTH_REG( - BATTERY_SIMPLO_CHARGE_MAX_TEMP, - BATTERY_SIMPLO_CHARGE_MIN_TEMP), - .s_alert_mxmn = SALRT_DISABLE, - .i_alert_mxmn = IALRT_DISABLE, - }, -}; - -const struct max17055_batt_profile *max17055_get_batt_profile(void) -{ - return &batt_profile[BATT_ID]; -} - -const struct max17055_alert_profile *max17055_get_alert_profile(void) -{ - return &alert_profile[BATT_ID]; -} - -const struct battery_info *battery_get_info(void) -{ - return &info[BATT_ID]; -} - -enum battery_disconnect_state battery_get_disconnect_state(void) -{ - if (battery_is_present() == BP_YES) - return BATTERY_NOT_DISCONNECTED; - return BATTERY_DISCONNECTED; -} - -int charger_profile_override(struct charge_state_data *curr) -{ - /* battery temp in 0.1 deg C */ - int bat_temp_c = curr->batt.temperature - 2731; - - /* - * Keep track of battery temperature range: - * - * ZONE_0 ZONE_1 ZONE_2 - * -----+--------+--------+------------+----- Temperature (C) - * t0 t1 t2 t3 - */ - enum { - TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */ - TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */ - TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */ - TEMP_ZONE_3, /* t3 < bat_temp_c <= t4 */ - TEMP_ZONE_COUNT - } temp_zone; - static struct { - int temp_min; /* 0.1 deg C */ - int temp_max; /* 0.1 deg C */ - int desired_current; /* mA */ - int desired_voltage; /* mV */ - } temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = { - [BATTERY_SIMPLO] = { - /* Add a empty range here to avoid TEMP_ZONE_COUNT mismatch. */ - /* TEMP_ZONE_0 */ - {BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10, - BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10, 1772, 4376}, - /* TEMP_ZONE_1 */ - {BATTERY_SIMPLO_CHARGE_MIN_TEMP * 10, 150, 1772, 4376}, - /* TEMP_ZONE_2 */ - {150, 450, 4020, 4376}, - /* TEMP_ZONE_3 */ - {450, BATTERY_SIMPLO_CHARGE_MAX_TEMP * 10, 3350, 4300}, - }, - }; - BUILD_ASSERT(ARRAY_SIZE(temp_zones[BATT_ID]) == TEMP_ZONE_COUNT); - BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT); - - if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) || - (bat_temp_c < temp_zones[BATT_ID][0].temp_min) || - (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max)) - temp_zone = TEMP_OUT_OF_RANGE; - else { - for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { - if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) - break; - } - } - - if (curr->state != ST_CHARGE) - return 0; - - switch (temp_zone) { - case TEMP_ZONE_0: - case TEMP_ZONE_1: - case TEMP_ZONE_2: - case TEMP_ZONE_3: - curr->requested_current = - temp_zones[BATT_ID][temp_zone].desired_current; - curr->requested_voltage = - temp_zones[BATT_ID][temp_zone].desired_voltage; - break; - case TEMP_OUT_OF_RANGE: - curr->requested_current = curr->requested_voltage = 0; - curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE; - curr->state = ST_IDLE; - break; - } - -#ifdef VARIANT_KUKUI_CHARGER_MT6370 - mt6370_charger_profile_override(curr); -#endif /* CONFIG_CHARGER_MT6370 */ - - return 0; -} - -enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) -{ - return EC_RES_INVALID_PARAM; -} - -enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) -{ - return EC_RES_INVALID_PARAM; -} - -int get_battery_manufacturer_name(char *dest, int size) -{ - static const char * const name[] = { - [BATTERY_SIMPLO] = "SIMPLO", - }; - ASSERT(dest); - strzcpy(dest, name[BATT_ID], size); - return EC_SUCCESS; -} - diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c deleted file mode 100644 index e7f422e561..0000000000 --- a/baseboard/kukui/battery_mm8013.c +++ /dev/null @@ -1,141 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery.h" -#include "charge_state.h" -#include "charger_mt6370.h" -#include "console.h" -#include "driver/tcpm/mt6370.h" -#include "ec_commands.h" -#include "util.h" - -#define TEMP_OUT_OF_RANGE TEMP_ZONE_COUNT - -#define BATT_ID 0 - -#define BATTERY_SCUD_CHARGE_MIN_TEMP 0 -#define BATTERY_SCUD_CHARGE_MAX_TEMP 50 - -#define BAT_LEVEL_PD_LIMIT 85 - -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) - -enum battery_type { - BATTERY_SCUD = 0, - BATTERY_COUNT -}; - -static const struct battery_info info[] = { - [BATTERY_SCUD] = { - .voltage_max = 4400, - .voltage_normal = 3850, - .voltage_min = 3000, - .precharge_voltage = 3400, - .precharge_current = 256, - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 50, - .discharging_min_c = -20, - .discharging_max_c = 59, - }, -}; - -const struct battery_info *battery_get_info(void) -{ - return &info[BATT_ID]; -} - -enum battery_disconnect_state battery_get_disconnect_state(void) -{ - if (battery_is_present() == BP_YES) - return BATTERY_NOT_DISCONNECTED; - return BATTERY_DISCONNECTED; -} - -int charger_profile_override(struct charge_state_data *curr) -{ - /* battery temp in 0.1 deg C */ - int bat_temp_c = curr->batt.temperature - 2731; - /* - * Keep track of battery temperature range: - * - * ZONE_0 ZONE_1 ZONE_2 - * -----+--------+--------+------------+----- Temperature (C) - * t0 t1 t2 t3 - */ - enum { - TEMP_ZONE_0, /* t0 < bat_temp_c <= t1 */ - TEMP_ZONE_1, /* t1 < bat_temp_c <= t2 */ - TEMP_ZONE_2, /* t2 < bat_temp_c <= t3 */ - TEMP_ZONE_COUNT - } temp_zone; - - static struct { - int temp_min; /* 0.1 deg C */ - int temp_max; /* 0.1 deg C */ - int desired_current; /* mA */ - int desired_voltage; /* mV */ - } temp_zones[BATTERY_COUNT][TEMP_ZONE_COUNT] = { - [BATTERY_SCUD] = { - /* TEMP_ZONE_0 */ - {BATTERY_SCUD_CHARGE_MIN_TEMP * 10, 150, 1400, 4400}, - /* TEMP_ZONE_1 */ - {150, 450, 3500, 4400}, - /* TEMP_ZONE_2 */ - {450, BATTERY_SCUD_CHARGE_MAX_TEMP * 10, 3500, 4200}, - }, - }; - BUILD_ASSERT(ARRAY_SIZE(temp_zones[0]) == TEMP_ZONE_COUNT); - BUILD_ASSERT(ARRAY_SIZE(temp_zones) == BATTERY_COUNT); - - if ((curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE) || - (bat_temp_c < temp_zones[BATT_ID][0].temp_min) || - (bat_temp_c >= temp_zones[BATT_ID][TEMP_ZONE_COUNT - 1].temp_max)) - temp_zone = TEMP_OUT_OF_RANGE; - else { - for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { - if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) - break; - } - } - - switch (temp_zone) { - case TEMP_ZONE_0: - case TEMP_ZONE_1: - case TEMP_ZONE_2: - curr->requested_current = - temp_zones[BATT_ID][temp_zone].desired_current; - curr->requested_voltage = - temp_zones[BATT_ID][temp_zone].desired_voltage; - break; - case TEMP_OUT_OF_RANGE: - curr->requested_current = curr->requested_voltage = 0; - curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE; - curr->state = ST_IDLE; - break; - } - -#ifdef VARIANT_KUKUI_CHARGER_MT6370 - mt6370_charger_profile_override(curr); -#endif /* CONFIG_CHARGER_MT6370 */ - - return 0; -} - -enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) -{ - return EC_RES_INVALID_PARAM; -} - -enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) -{ - return EC_RES_INVALID_PARAM; -} diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c deleted file mode 100644 index ba2af17443..0000000000 --- a/baseboard/kukui/battery_smart.c +++ /dev/null @@ -1,138 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery pack vendor provided charging profile - */ - -#include "battery.h" -#include "battery_fuel_gauge.h" -#include "battery_smart.h" -#include "timer.h" -#include "util.h" - -enum battery_present batt_pres_prev = BP_NOT_SURE; - -/* - * Physical detection of battery. - */ -static enum battery_present battery_check_present_status(void) -{ - enum battery_present batt_pres = BP_NOT_SURE; - -#ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM - /* Get the physical hardware status */ - batt_pres = battery_hw_present(); -#endif - - /* - * If the battery is not physically connected, then no need to perform - * any more checks. - */ - if (batt_pres == BP_NO) - return batt_pres; - - /* - * If the battery is present now and was present last time we checked, - * return early. - */ - if (batt_pres == batt_pres_prev) - return batt_pres; - - /* - * Check battery disconnect status. If we are unable to read battery - * disconnect status, then return BP_NOT_SURE. Battery could be in ship - * mode and might require pre-charge current to wake it up. BP_NO is not - * returned here because charger state machine will not provide - * pre-charge current assuming that battery is not present. - */ - if (battery_get_disconnect_state() == BATTERY_DISCONNECT_ERROR) - return BP_NOT_SURE; - - /* Ensure the battery is not in cutoff state */ - if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL) - return BP_NO; - - return batt_pres; -} - -enum battery_present battery_is_present(void) -{ - batt_pres_prev = battery_check_present_status(); - return batt_pres_prev; -} - -#ifdef CONFIG_I2C_BITBANG -static void fix_single_param(int flag, int *cached, int *curr) -{ - if (flag) - *curr = *cached; - else - *cached = *curr; -} - -#define CACHE_INVALIDATION_TIME_US (5 * SECOND) - -/* - * b:144195782: bitbang fails randomly, and there's no way to - * notify kernel side that bitbang read failed. - * Thus, if any value in batt_params is bad, replace it with a cached - * good value, to make sure we never send random numbers to kernel - * side. - */ -__override void board_battery_compensate_params(struct batt_params *batt) -{ - static struct batt_params batt_cache = { 0 }; - static timestamp_t deadline; - - /* - * If battery keeps failing for 5 seconds, stop hiding the error and - * report back to host. - */ - if (batt->flags & BATT_FLAG_BAD_ANY) { - if (timestamp_expired(deadline, NULL)) - return; - } else { - deadline.val = get_time().val + CACHE_INVALIDATION_TIME_US; - } - - /* return cached values for at most CACHE_INVALIDATION_TIME_US */ - fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE, - &batt_cache.state_of_charge, - &batt->state_of_charge); - fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE, - &batt_cache.voltage, - &batt->voltage); - fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT, - &batt_cache.current, - &batt->current); - fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE, - &batt_cache.desired_voltage, - &batt->desired_voltage); - fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT, - &batt_cache.desired_current, - &batt->desired_current); - fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY, - &batt_cache.remaining_capacity, - &batt->remaining_capacity); - fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY, - &batt_cache.full_capacity, - &batt->full_capacity); - fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, - &batt_cache.status, - &batt->status); - fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE, - &batt_cache.temperature, - &batt->temperature); - /* - * If battery_compensate_params() didn't calculate display_charge - * for us, also update it with last good value. - */ - fix_single_param(batt->display_charge == 0, - &batt_cache.display_charge, - &batt->display_charge); - - /* remove bad flags after applying cached values */ - batt->flags &= ~BATT_FLAG_BAD_ANY; -} -#endif /* CONFIG_I2C_BITBANG */ diff --git a/baseboard/kukui/build.mk b/baseboard/kukui/build.mk deleted file mode 100644 index c64f6978c8..0000000000 --- a/baseboard/kukui/build.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -# Select eMMC CMD0 driver. -EMMC_CMD0_DRIVER=$(if $(CHIP_IT83XX),emmc_ite.o,emmc.o) - -baseboard-y=baseboard.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(CONFIG_BOOTBLOCK)+=$(EMMC_CMD0_DRIVER) - -baseboard-$(VARIANT_KUKUI_BATTERY_MAX17055)+=battery_max17055.o -baseboard-$(VARIANT_KUKUI_BATTERY_MM8013)+=battery_mm8013.o -baseboard-$(VARIANT_KUKUI_BATTERY_BQ27541)+=battery_bq27541.o -baseboard-$(VARIANT_KUKUI_BATTERY_SMART)+=battery_smart.o - -baseboard-$(VARIANT_KUKUI_CHARGER_MT6370)+=charger_mt6370.o - -baseboard-$(VARIANT_KUKUI_POGO_KEYBOARD)+=base_detect_kukui.o - -$(out)/RO/baseboard/$(BASEBOARD)/$(EMMC_CMD0_DRIVER): $(out)/bootblock_data.h - -# bootblock size from 12769.0 -DEFAULT_BOOTBLOCK_SIZE:=21504 diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c deleted file mode 100644 index 327b567db6..0000000000 --- a/baseboard/kukui/charger_mt6370.c +++ /dev/null @@ -1,366 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "charger_mt6370.h" -#include "console.h" -#include "driver/charger/rt946x.h" -#include "driver/tcpm/mt6370.h" -#include "hooks.h" -#include "power.h" -#include "timer.h" -#include "usb_common.h" -#include "usb_pd.h" -#include "util.h" - -#define BAT_LEVEL_PD_LIMIT 85 -#define SYSTEM_PLT_MW 3500 -/* - * b/143318064: Prefer a voltage above 5V to force it picks a voltage - * above 5V at first. If PREFER_MV is 5V, when desired power is around - * 15W ~ 11W, it would pick 5V/3A initially, and mt6370 can only sink - * around 10W, and cause a low charging efficiency. - */ -#define PREVENT_CURRENT_DROP_MV 6000 -#define DEFAULT_PREFER_MV 5000 -/* - * We empirically chose 300mA as the limit for when buck inefficiency is - * noticeable. - */ -#define STABLE_CURRENT_DELTA 300 - -struct pd_pref_config_t pd_pref_config = { - .mv = PREVENT_CURRENT_DROP_MV, - .cv = 70, - .plt_mw = SYSTEM_PLT_MW, - .type = PD_PREFER_BUCK, -}; - -static void update_plt_suspend(void) -{ - pd_pref_config.plt_mw = 0; -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, update_plt_suspend, HOOK_PRIO_DEFAULT); - -static void update_plt_resume(void) -{ - pd_pref_config.plt_mw = SYSTEM_PLT_MW; -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT); - -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) - -/* wait time to evaluate charger thermal status */ -static timestamp_t thermal_wait_until; -/* input current bound when charger throttled */ -static int throttled_ma = PD_MAX_CURRENT_MA; -/* charge_ma in last board_set_charge_limit call */ -static int prev_charge_limit; -/* charge_mv in last board_set_charge_limit call */ -static int prev_charge_mv; - -#ifndef CONFIG_BATTERY_SMART -int board_cut_off_battery(void) -{ - /* The cut-off procedure is recommended by Richtek. b/116682788 */ - rt946x_por_reset(); - mt6370_vconn_discharge(0); - rt946x_cutoff_battery(); - - return EC_SUCCESS; -} -#endif - -static void board_set_charge_limit_throttle(int charge_ma, int charge_mv) -{ - charge_set_input_current_limit( - MIN(throttled_ma, MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT)), - charge_mv); -} - -static void battery_thermal_control(struct charge_state_data *curr) -{ - int input_current, jc_temp; - static int skip_reset; - /* - * mt6370's input current setting is 50mA step, use 50 as well for - * easy value mapping. - */ - const int k_p = 50; - - if (charge_manager_get_charger_voltage() == 5000 || - curr->state != ST_CHARGE) { - /* We already set the charge limit, do not reset it again. */ - if (skip_reset) - return; - skip_reset = 1; - thermal_wait_until.val = 0; - throttled_ma = PD_MAX_CURRENT_MA; - board_set_charge_limit_throttle(prev_charge_limit, - prev_charge_mv); - return; - } - - skip_reset = 0; - - if (thermal_wait_until.val == 0) - goto thermal_exit; - - if (get_time().val < thermal_wait_until.val) - return; - - /* If we fail to read adc, skip for this cycle. */ - if (rt946x_get_adc(MT6370_ADC_TEMP_JC, &jc_temp)) - return; - - /* If we fail to read input curr limit, skip for this cycle. */ - if (charger_get_input_current_limit(CHARGER_SOLO, &input_current)) - return; - - /* - * If input current limit is maximum, and we are under thermal budget, - * just skip. - */ - if (input_current == PD_MAX_CURRENT_MA && - jc_temp < thermal_bound.target + thermal_bound.err) - return; - - /* If the temp is within +- err, thermal is under control */ - if (jc_temp < thermal_bound.target + thermal_bound.err && - jc_temp > thermal_bound.target - thermal_bound.err) - return; - - /* - * PID algorithm (https://en.wikipedia.org/wiki/PID_controller), - * and operates on only P value. - */ - throttled_ma = MIN( - PD_MAX_CURRENT_MA, - /* - * Should not pass the previously set input current by - * charger manager. This value might be related the charger's - * capability. - */ - MIN(prev_charge_limit, - input_current + k_p * (thermal_bound.target - jc_temp))); - - /* If the input current doesn't change, just skip. */ - if (throttled_ma != input_current) - board_set_charge_limit_throttle(throttled_ma, prev_charge_mv); - -thermal_exit: - thermal_wait_until.val = get_time().val + (3 * SECOND); -} - -int command_jc(int argc, char **argv) -{ - static int prev_jc_temp; - int jc_temp; - - if (rt946x_get_adc(MT6370_ADC_TEMP_JC, &jc_temp)) - jc_temp = prev_jc_temp; - - ccprintf("JC Temp: %d\n", jc_temp); - prev_jc_temp = jc_temp; - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(jc, command_jc, "", "mt6370 junction temp"); - -/* - * b/143318064: A workwround for mt6370 bad buck efficiency. - * If the delta of VBUS and VBAT(on krane, desired voltage 4.4V) is too small - * (i.e. < 500mV), the buck throughput will be bounded, and causing that we - * can't drain 5V/3A when battery SoC above around 40%. - * This function watches battery current. If we see battery current drops after - * switching from high voltage to 5V (This will happen if we enable - * CONFIG_USB_PD_PREFER_MV and set prefer votage to 5V), the charger will lost - * power due to the inefficiency (e.g. switch from 9V/1.67A = 15W to 5V/3A, - * but mt6370 would only sink less than 5V/2.4A = 12W), and we will request a - * higher voltage PDO to prevent a slow charging time. - */ -static void battery_desired_curr_dynamic(struct charge_state_data *curr) -{ - static int prev_stable_current = CHARGE_CURRENT_UNINITIALIZED; - static int prev_supply_voltage; - int supply_voltage; - int stable_current; - int delta_current; - - if (curr->state != ST_CHARGE) { - prev_supply_voltage = 0; - prev_stable_current = CHARGE_CURRENT_UNINITIALIZED; - /* - * Always force higher voltage on first PD negotiation. - * When desired power is around 15W ~ 11W, PD would pick - * 5V/3A initially, but mt6370 can't drain that much, and - * causes a low charging efficiency. - */ - pd_pref_config.mv = PREVENT_CURRENT_DROP_MV; - return; - } - - supply_voltage = charge_manager_get_charger_voltage(); - stable_current = charge_get_stable_current(); - - if (!charge_is_current_stable()) - return; - - if (!prev_supply_voltage) - goto update_charge; - - delta_current = prev_stable_current - stable_current; - if (curr->batt.state_of_charge >= pd_pref_config.cv && - supply_voltage == DEFAULT_PREFER_MV && - prev_supply_voltage > supply_voltage && - delta_current > STABLE_CURRENT_DELTA) { - /* Raise perfer voltage above 5000mV */ - pd_pref_config.mv = PREVENT_CURRENT_DROP_MV; - /* - * Delay stable current evaluation for 5 mins if we see a - * current drop. It's a reasonable waiting time since that - * the battery desired current can't catch the gap that fast - * in the period. - */ - charge_reset_stable_current_us(5 * MINUTE); - /* Rewrite the stable current to re-evalute desired watt */ - charge_set_stable_current(prev_stable_current); - - /* - * do not alter current by thermal if we just raising PD - * voltage - */ - thermal_wait_until.val = get_time().val + (10 * SECOND); - } else { - pd_pref_config.mv = DEFAULT_PREFER_MV; - /* - * If the power supply is plugged while battery full, - * the stable_current will always be 0 such that we are unable - * to switch to 5V. We force evaluating PDO to switch to 5V. - */ - if (prev_supply_voltage == supply_voltage && !stable_current && - !prev_stable_current && - supply_voltage != DEFAULT_PREFER_MV && - charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) - pd_set_new_power_request( - charge_manager_get_active_charge_port()); - } - -update_charge: - prev_supply_voltage = supply_voltage; - prev_stable_current = stable_current; -} - -#ifdef CONFIG_BATTERY_SMART -static void charge_enable_eoc_and_te(void) -{ - rt946x_enable_charge_eoc(1); - rt946x_enable_charge_termination(1); -} -DECLARE_DEFERRED(charge_enable_eoc_and_te); -#endif - -void mt6370_charger_profile_override(struct charge_state_data *curr) -{ - static int previous_chg_limit_mv; - int chg_limit_mv = pd_get_max_voltage(); - - battery_desired_curr_dynamic(curr); - - battery_thermal_control(curr); - -#ifdef CONFIG_BATTERY_SMART - /* - * SMP battery uses HW pre-charge circuit and pre-charge current is - * limited to ~50mA. Once the charge current is lower than IEOC level - * within CHG_TEDG_EOC, and TE is enabled, the charging power path will - * be turned off. Disable EOC and TE when battery stays over discharge - * state, otherwise enable EOC and TE. - */ - if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) { - const struct battery_info *batt_info = battery_get_info(); - static int normal_charge_lock, over_discharge_lock; - - if (curr->batt.voltage < batt_info->voltage_min) { - normal_charge_lock = 0; - - if (!over_discharge_lock && curr->state == ST_CHARGE) { - over_discharge_lock = 1; - rt946x_enable_charge_eoc(0); - rt946x_enable_charge_termination(0); - } - } else { - over_discharge_lock = 0; - - if (!normal_charge_lock) { - normal_charge_lock = 1; - /* - * b/148045048: When the battery is activated - * in shutdown mode, the adapter cannot boot - * DUT automatically. It's a workaround to - * delay 4.5 second to enable charger EOC - * and TE function. - */ - hook_call_deferred( - &charge_enable_eoc_and_te_data, - (4.5 * SECOND)); - } - } - } -#endif - - /* Limit input (=VBUS) to 5V when soc > 85% and charge current < 1A. */ - if (!(curr->batt.flags & BATT_FLAG_BAD_CURRENT) && - charge_get_percent() > BAT_LEVEL_PD_LIMIT && - curr->batt.current < 1000 && power_get_state() != POWER_S0) - chg_limit_mv = 5500; - else - chg_limit_mv = PD_MAX_VOLTAGE_MV; - - if (chg_limit_mv != previous_chg_limit_mv) - CPRINTS("VBUS limited to %dmV", chg_limit_mv); - previous_chg_limit_mv = chg_limit_mv; - - /* Pull down VBUS */ - if (pd_get_max_voltage() != chg_limit_mv) - pd_set_external_voltage_limit(0, chg_limit_mv); - - /* - * When the charger says it's done charging, even if fuel gauge says - * SOC < BATTERY_LEVEL_NEAR_FULL, we'll overwrite SOC with - * BATTERY_LEVEL_NEAR_FULL. So we can ensure both Chrome OS UI - * and battery LED indicate full charge. - * - * Enable this hack on on-board gauge only (b/142097561) - */ - if (IS_ENABLED(CONFIG_BATTERY_MAX17055) && rt946x_is_charge_done()) { - curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL, - curr->batt.state_of_charge); - } - -} - -#ifndef CONFIG_BATTERY_SMART -static void board_charge_termination(void) -{ - static uint8_t te; - /* Enable charge termination when we are sure battery is present. */ - if (!te && battery_is_present() == BP_YES) { - if (!rt946x_enable_charge_termination(1)) - te = 1; - } -} -DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, - board_charge_termination, - HOOK_PRIO_DEFAULT); -#endif - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - prev_charge_limit = charge_ma; - prev_charge_mv = charge_mv; - board_set_charge_limit_throttle(charge_ma, charge_mv); -} diff --git a/baseboard/kukui/charger_mt6370.h b/baseboard/kukui/charger_mt6370.h deleted file mode 100644 index 880b00a1a8..0000000000 --- a/baseboard/kukui/charger_mt6370.h +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_BASEBOARD_CHARGER_MT6370_H -#define __CROS_EC_BASEBOARD_CHARGER_MT6370_H - -#include "charge_state.h" - -void mt6370_charger_profile_override(struct charge_state_data *curr); - -struct mt6370_thermal_bound { - /* mt6370 junction's thermal target in Celsius degree */ - int target; - /* mt6370 junction's thermal evaluation error in Celsius degree */ - int err; -}; - -extern struct mt6370_thermal_bound thermal_bound; -#endif diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c deleted file mode 100644 index 68953d8923..0000000000 --- a/baseboard/kukui/emmc.c +++ /dev/null @@ -1,400 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Transfer bootblock over SPI by emulating eMMC "Alternative Boot operation" - * (section 6.3.4 of eMMC 5.0 specification, JESD84-B50). - * - * eMMC boot operation looks a lot like SPI: CMD is unidirectional MOSI, DAT is - * unidirectional MISO. CLK is driven by the master. However, there is no - * chip-select, and the clock is active for a long time before any command is - * sent on the CMD line. From SPI perspective, this looks like a lot of '1' - * are being sent from the master. - * - * To catch the commands, we setup DMA to write the data into a circular buffer - * (in_msg), and monitor for a falling edge on CMD (emmc_cmd_interrupt). Once - * an interrupt is received, we scan the circular buffer, in reverse, to - * be as fast as possible and minimize chances of missing the command. - * - * We then figure out the bit-wise command alignment, decode it, and, upon - * receiving BOOT_INITIATION command, setup DMA to respond with the data on the - * DAT line. The data in bootblock_data.h is preprocessed to include necessary - * eMMC headers: acknowledge boot mode, start of block, CRC, end of block, etc. - * The host can only slow down transfer by stopping the clock, which is - * compatible with SPI. - * - * In some cases (e.g. if the BootROM expects data over 8 lanes instead of 1), - * the BootROM will quickly interrupt the transfer with an IDLE command. In this - * case we interrupt the transfer, and the BootROM will try again. - */ - -#include "chipset.h" -#include "clock.h" -#include "console.h" -#include "dma.h" -#include "endian.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#include "bootblock_data.h" - -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) - -#if EMMC_SPI_PORT == 1 -#define STM32_SPI_EMMC_REGS STM32_SPI1_REGS -#define STM32_DMAC_SPI_EMMC_TX STM32_DMAC_SPI1_TX -#define STM32_DMAC_SPI_EMMC_RX STM32_DMAC_SPI1_RX -#elif EMMC_SPI_PORT == 2 -#define STM32_SPI_EMMC_REGS STM32_SPI2_REGS -#define STM32_DMAC_SPI_EMMC_TX STM32_DMAC_SPI2_TX -#define STM32_DMAC_SPI_EMMC_RX STM32_DMAC_SPI2_RX -#else -#error "Please define EMMC_SPI_PORT in board.h." -#endif - -/* Is eMMC emulation enabled? */ -static int emmc_enabled; - -/* Maximum amount of time to wait for AP to boot. */ -static timestamp_t boot_deadline; -#define BOOT_TIMEOUT (5 * SECOND) -#define EMMC_STATUS_CHECK_PERIOD (10 * MSEC) - -/* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */ -#define SPI_RX_BUF_BYTES 1024 -#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4) -static uint32_t in_msg[SPI_RX_BUF_WORDS]; - -/* Macros to advance in the circular buffer. */ -#define RX_BUF_NEXT_32(i) (((i) + 1) & (SPI_RX_BUF_WORDS - 1)) -#define RX_BUF_DEC_32(i, j) (((i) - (j)) & (SPI_RX_BUF_WORDS - 1)) -#define RX_BUF_PREV_32(i) RX_BUF_DEC_32((i), 1) - -enum emmc_cmd { - EMMC_ERROR = -1, - EMMC_IDLE = 0, - EMMC_PRE_IDLE, - EMMC_BOOT, -}; - -static const struct dma_option dma_tx_option = { - STM32_DMAC_SPI_EMMC_TX, (void *)&STM32_SPI_EMMC_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -}; - -/* Circular RX buffer */ -static const struct dma_option dma_rx_option = { - STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC -}; - -/* Setup DMA to transfer bootblock. */ -static void bootblock_transfer(void) -{ - static int transfer_try; - - dma_chan_t *txdma = dma_get_channel(STM32_DMAC_SPI_EMMC_TX); - - dma_prepare_tx(&dma_tx_option, sizeof(bootblock_raw_data), - bootblock_raw_data); - dma_go(txdma); - - CPRINTS("transfer %d", ++transfer_try); -} - -/* Abort an ongoing transfer. */ -static void bootblock_stop(void) -{ - const uint32_t timeout = 1 * MSEC; - uint32_t start; - - dma_disable(STM32_DMAC_SPI_EMMC_TX); - - /* - * Wait for SPI FIFO to become empty. - * We timeout after 1 ms in case the bus is not clocked anymore. - */ - start = __hw_clock_source_read(); - while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL && - __hw_clock_source_read() - start < timeout) - ; - - /* Then flush SPI FIFO, and make sure DAT line stays idle (high). */ - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; -} - -static enum emmc_cmd emmc_parse_command(int index) -{ - int32_t shift0; - uint32_t data[3]; - - if (in_msg[index] == 0xffffffff) - return EMMC_ERROR; - - data[0] = htobe32(in_msg[index]); - index = RX_BUF_NEXT_32(index); - data[1] = htobe32(in_msg[index]); - index = RX_BUF_NEXT_32(index); - data[2] = htobe32(in_msg[index]); - - /* Figure out alignment (cmd starts with 01) */ - - /* Number of leading ones. */ - shift0 = __builtin_clz(~data[0]); - - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); - - if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { - /* 400000000095 GO_IDLE_STATE */ - CPRINTS("goIdle"); - return EMMC_IDLE; - } - - if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) { - /* 40f0f0f0f0fd GO_PRE_IDLE_STATE */ - CPRINTS("goPreIdle"); - return EMMC_PRE_IDLE; - } - - if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) { - /* 40fffffffae5 BOOT_INITIATION */ - CPRINTS("bootInit"); - return EMMC_BOOT; - } - - CPRINTS("eMMC error"); - return EMMC_ERROR; -} - - -/* - * Wake the EMMC task when there is a falling edge on the CMD line, so that we - * can capture the command. - */ -void emmc_cmd_interrupt(enum gpio_signal signal) -{ - task_wake(TASK_ID_EMMC); - CPRINTF("i"); -} - -static void emmc_init_spi(void) -{ -#if EMMC_SPI_PORT == 1 - /* Reset SPI */ - STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1; - STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1; - - /* Enable clocks to SPI module */ - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; -#elif EMMC_SPI_PORT == 2 -#ifdef CHIP_FAMILY_STM32L4 - /* Reset SPI */ - STM32_RCC_APB1RSTR1 |= STM32_RCC_PB1_SPI2; - STM32_RCC_APB1RSTR1 &= ~STM32_RCC_PB1_SPI2; - - /* Enable clocks to SPI module */ - STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; -#else - /* Reset SPI */ - STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2; - STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2; - - /* Enable clocks to SPI module */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; -#endif -#else -#error "Please define EMMC_SPI_PORT in board.h." -#endif - clock_wait_bus_cycles(BUS_APB, 1); - gpio_config_module(MODULE_SPI_FLASH, 1); - - STM32_SPI_EMMC_REGS->cr2 = - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8) | - STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN; - - /* Manual CS, disable. */ - STM32_SPI_EMMC_REGS->cr1 = STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI; - - /* Flush SPI TX FIFO, and make sure DAT line stays idle (high). */ - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; - STM32_SPI_EMMC_REGS->dr = 0xff; - - /* Enable the SPI peripheral */ - STM32_SPI_EMMC_REGS->cr1 |= STM32_SPI_CR1_SPE; -} -DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI); - -static void emmc_check_status(void); -DECLARE_DEFERRED(emmc_check_status); - -static void emmc_enable_spi(void) -{ - if (emmc_enabled) - return; - - disable_sleep(SLEEP_MASK_EMMC); - - /* Start receiving in circular buffer in_msg. */ - dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg); - /* Enable internal chip select. */ - STM32_SPI_EMMC_REGS->cr1 &= ~STM32_SPI_CR1_SSI; - /* - * EMMC_CMD and SPI1_NSS share EXTI15, make sure GPIO_EMMC_CMD is - * selected. - */ - gpio_disable_interrupt(GPIO_SPI1_NSS); - gpio_enable_interrupt(GPIO_EMMC_CMD); - - emmc_enabled = 1; - CPRINTS("emmc enabled"); - - boot_deadline.val = get_time().val + BOOT_TIMEOUT; - - /* Check if AP has booted periodically. */ - hook_call_deferred(&emmc_check_status_data, EMMC_STATUS_CHECK_PERIOD); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST); - -static void emmc_disable_spi(void) -{ - if (!emmc_enabled) - return; - - /* Cancel check hook. */ - hook_call_deferred(&emmc_check_status_data, -1); - - gpio_disable_interrupt(GPIO_EMMC_CMD); - /* - * EMMC_CMD and SPI1_NSS share EXTI15, so re-enable interrupt on - * SPI1_NSS to reconfigure the interrupt selection. - */ - gpio_enable_interrupt(GPIO_SPI1_NSS); - /* Disable TX DMA. */ - dma_disable(STM32_DMAC_SPI_EMMC_TX); - /* Disable internal chip select. */ - STM32_SPI_EMMC_REGS->cr1 |= STM32_SPI_CR1_SSI; - /* Disable RX DMA. */ - dma_disable(STM32_DMAC_SPI_EMMC_RX); - - /* Blank out buffer to make sure we do not look at old data. */ - memset(in_msg, 0xff, sizeof(in_msg)); - - enable_sleep(SLEEP_MASK_EMMC); - - emmc_enabled = 0; - CPRINTS("emmc disabled"); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, emmc_disable_spi, HOOK_PRIO_FIRST); - -static void emmc_check_status(void) -{ - /* Bootblock switch disabled, switch off emulation */ - if (gpio_get_level(GPIO_BOOTBLOCK_EN_L) == 1) { - emmc_disable_spi(); - return; - } - - if (timestamp_expired(boot_deadline, NULL)) { - CPRINTS("emmc: AP failed to boot."); - chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); - return; - } - - /* Check if AP has booted again, next time. */ - hook_call_deferred(&emmc_check_status_data, EMMC_STATUS_CHECK_PERIOD); -} - -void emmc_task(void *u) -{ - int dma_pos, i; - dma_chan_t *rxdma; - enum emmc_cmd cmd; - /* Are we currently transmitting data? */ - int tx = 0; - - rxdma = dma_get_channel(STM32_DMAC_SPI_EMMC_RX); - - while (1) { - /* Wait for a command */ - task_wait_event(-1); - - dma_pos = dma_bytes_done(rxdma, sizeof(in_msg)) / 4; - i = RX_BUF_PREV_32(dma_pos); - - /* - * By now, bus should be idle again (it takes <10us to transmit - * a command, less than is needed to process interrupt and wake - * this task). - */ - if (in_msg[i] != 0xffffffff) { - CPRINTF("?"); - /* TODO(b:110907438): We should probably just retry. */ - continue; - } - - /* - * Find a command, looking from the end of the buffer to make - * it faster. - */ - while (i != dma_pos && in_msg[i] == 0xffffffff) - i = RX_BUF_PREV_32(i); - - /* - * We missed the command? That should not happen if we process - * the buffer quickly enough (and the interrupt was real). - */ - if (i == dma_pos) { - CPRINTF("!"); - continue; - } - - /* - * We found the end of the command, now find the beginning - * (commands are 6-byte long so the starting point is either 2 - * or 1 word before the end of the command). - */ - i = RX_BUF_DEC_32(i, 2); - if (in_msg[i] == 0xffffffff) - i = RX_BUF_NEXT_32(i); - - cmd = emmc_parse_command(i); - - if (!tx) { - /* - * When not transferring, host will send GO_IDLE_STATE, - * GO_PRE_IDLE_STATE, then BOOT_INITIATION commands. But - * all we really care about is the BOOT_INITIATION - * command: start the transfer. - */ - if (cmd == EMMC_BOOT) { - tx = 1; - bootblock_transfer(); - } - } else { - /* - * Host sends GO_IDLE_STATE to abort the transfer (e.g. - * when an incorrect number of lanes is used) and when - * the transfer is complete. - * Also react to GO_PRE_IDLE_STATE in case we missed - * GO_IDLE_STATE command. - */ - if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) { - bootblock_stop(); - tx = 0; - } - } - } -} diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c deleted file mode 100644 index 8c3e63064c..0000000000 --- a/baseboard/kukui/emmc_ite.c +++ /dev/null @@ -1,205 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "console.h" -#include "endian.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "intc.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#include "bootblock_data.h" - -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -enum emmc_cmd { - EMMC_ERROR = -1, - EMMC_IDLE = 0, - EMMC_PRE_IDLE, - EMMC_BOOT, -}; - -static void emmc_reset_spi_tx(void) -{ - /* Reset TX FIFO and count monitor */ - IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR; - /* Send idle state (high/0xff) if master clocks in data. */ - IT83XX_SPI_FCR = 0; -} - -static void emmc_reset_spi_rx(void) -{ - /* End Rx FIFO access */ - IT83XX_SPI_TXRXFAR = 0; - /* Reset RX FIFO and count monitor */ - IT83XX_SPI_FCR = IT83XX_SPI_RXFR | IT83XX_SPI_RXFCMR; -} - -/* - * Set SPI module work as eMMC Alternative Boot Mode. - * (CS# pin isn't required, and dropping data until CMD goes low) - */ -static void emmc_enable_spi(void) -{ - /* Set SPI pin mux to eMMC (GPM2:CLK, GPM3:CMD, GPM6:DATA0) */ - IT83XX_GCTRL_PIN_MUX0 |= BIT(7); - /* Enable eMMC Alternative Boot Mode */ - IT83XX_SPI_EMMCBMR |= IT83XX_SPI_EMMCABM; - /* Reset TX and RX FIFO */ - emmc_reset_spi_tx(); - emmc_reset_spi_rx(); - /* Response idle state (high) */ - IT83XX_SPI_SPISRDR = 0xff; - /* FIFO will be overwritten once it's full */ - IT83XX_SPI_GCR2 = 0; - /* Write to clear pending interrupt bits */ - IT83XX_SPI_ISR = 0xff; - IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI; - /* Enable RX fifo full interrupt */ - IT83XX_SPI_IMR = 0xff; - IT83XX_SPI_RX_VLISMR |= IT83XX_SPI_RVLIM; - IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_FIFO_FULL; - /* - * Enable interrupt to detect AP's BOOTBLOCK_EN_L. So EC is able to - * switch SPI module back to communication mode once BOOTBLOCK_EN_L - * goes high (AP Jumped to bootloader). - */ - gpio_clear_pending_interrupt(GPIO_BOOTBLOCK_EN_L); - gpio_enable_interrupt(GPIO_BOOTBLOCK_EN_L); - - disable_sleep(SLEEP_MASK_EMMC); - CPRINTS("eMMC emulation enabled"); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, emmc_enable_spi, HOOK_PRIO_FIRST); - -static void emmc_init_spi(void) -{ - /* Enable alternate function */ - gpio_config_module(MODULE_SPI_FLASH, 1); -} -DECLARE_HOOK(HOOK_INIT, emmc_init_spi, HOOK_PRIO_INIT_SPI + 1); - -static void emmc_send_data_over_spi(uint8_t *tx, int tx_size, int rst_tx) -{ - int i; - - /* Reset TX FIFO and count monitor */ - if (rst_tx) - IT83XX_SPI_TXFCR = IT83XX_SPI_TXFR | IT83XX_SPI_TXFCMR; - /* CPU access TX FIFO1 and FIFO2 */ - IT83XX_SPI_TXRXFAR = IT83XX_SPI_CPUTFA; - - /* Write response data to TX FIFO */ - for (i = 0; i < tx_size; i += 4) - IT83XX_SPI_CPUWTFDB0 = *(uint32_t *)(tx + i); - /* - * After writing data to TX FIFO is finished, this bit will - * be to indicate the SPI slave controller. - */ - IT83XX_SPI_TXFCR = IT83XX_SPI_TXFS; - /* End CPU access TX FIFO */ - IT83XX_SPI_TXRXFAR = 0; - /* SPI module access TX FIFO */ - IT83XX_SPI_FCR = IT83XX_SPI_SPISRTXF; -} - -static void emmc_bootblock_transfer(void) -{ - int tx_size, sent = 0, remaining = sizeof(bootblock_raw_data); - uint8_t *raw = (uint8_t *)bootblock_raw_data; - const uint32_t timeout_us = 200; - uint32_t start; - - /* - * HW will transmit the data of FIFO1 or FIFO2 in turn. - * So when a FIFO is empty, we need to fill the FIFO out - * immediately. - */ - emmc_send_data_over_spi(&raw[sent], 256, 1); - sent += 256; - - while (sent < remaining) { - /* Wait for FIFO1 or FIFO2 have been transmitted */ - start = __hw_clock_source_read(); - while (!(IT83XX_SPI_TXFSR & BIT(0)) && - (__hw_clock_source_read() - start < timeout_us)) - ; - /* Abort an ongoing transfer due to a command is received. */ - if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) - break; - /* fill out next 128 bytes to FIFO1 or FIFO2 */ - tx_size = (remaining - sent) < 128 ? (remaining - sent) : 128; - emmc_send_data_over_spi(&raw[sent], tx_size, 0); - sent += tx_size; - } -} - -static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0) -{ - int32_t shift0; - uint32_t data[3]; - - data[0] = htobe32(cmd0[index]); - data[1] = htobe32(cmd0[index+1]); - data[2] = htobe32(cmd0[index+2]); - - if ((data[0] & 0xff000000) != 0x40000000) { - /* Figure out alignment (cmd starts with 01) */ - /* Number of leading ones. */ - shift0 = __builtin_clz(~data[0]); - - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); - } - - if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { - /* 400000000095 GO_IDLE_STATE */ - CPRINTS("goIdle"); - return EMMC_IDLE; - } - - if (data[0] == 0x40f0f0f0 && data[1] == 0xf0fdffff) { - /* 40f0f0f0f0fd GO_PRE_IDLE_STATE */ - CPRINTS("goPreIdle"); - return EMMC_PRE_IDLE; - } - - if (data[0] == 0x40ffffff && data[1] == 0xfae5ffff) { - /* 40fffffffae5 BOOT_INITIATION */ - CPRINTS("bootInit"); - return EMMC_BOOT; - } - - CPRINTS("eMMC error"); - return EMMC_ERROR; -} - -void spi_emmc_cmd0_isr(uint32_t *cmd0_payload) -{ - enum emmc_cmd cmd; - - for (int i = 0; i < 8; i++) { - if (cmd0_payload[i] == 0xffffffff) - continue; - - cmd = emmc_parse_command(i, &cmd0_payload[i]); - - if (cmd == EMMC_IDLE || cmd == EMMC_PRE_IDLE) { - /* Abort an ongoing transfer. */ - emmc_reset_spi_tx(); - break; - } - - if (cmd == EMMC_BOOT) { - emmc_bootblock_transfer(); - break; - } - } -} diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c deleted file mode 100644 index 28ef005ee8..0000000000 --- a/baseboard/kukui/usb_pd_policy.c +++ /dev/null @@ -1,298 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "charge_state_v2.h" -#include "charger.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "timer.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usb_pd_policy.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -static int board_get_polarity(int port) -{ - /* Krane's aux mux polarity is reversed. Workaround to flip it back. */ - if (IS_ENABLED(BOARD_KRANE) && board_get_version() == 3) - return !polarity_rm_dts(pd_get_polarity(port)); - - return polarity_rm_dts(pd_get_polarity(port)); -} - -static uint8_t vbus_en; - -#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */ -#define VBUS_EN_HOOK_VERSION 1 - -static void vbus_en_preserve_state(void) -{ - system_add_jump_tag(VBUS_EN_SYSJUMP_TAG, VBUS_EN_HOOK_VERSION, - sizeof(vbus_en), &vbus_en); -} -DECLARE_HOOK(HOOK_SYSJUMP, vbus_en_preserve_state, HOOK_PRIO_DEFAULT); - -static void vbus_en_restore_state(void) -{ - const uint8_t *prev_vbus_en; - int size, version; - - prev_vbus_en = (const uint8_t *)system_get_jump_tag( - VBUS_EN_SYSJUMP_TAG, &version, &size); - - if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION && - size == sizeof(*prev_vbus_en)) { - memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en)); - } -} -DECLARE_HOOK(HOOK_INIT, vbus_en_restore_state, HOOK_PRIO_DEFAULT); - -int board_vbus_source_enabled(int port) -{ - return vbus_en; -} - -int board_is_sourcing_vbus(int port) -{ - if (IS_ENABLED(BOARD_KUKUI) && board_get_version() <= 1) - return charger_is_sourcing_otg_power(port); - else - return board_vbus_source_enabled(port); -} - -int pd_set_power_supply_ready(int port) -{ - if (port != CHARGE_PORT_USB_C) - return EC_ERROR_INVAL; - - pd_set_vbus_discharge(port, 0); - /* Provide VBUS */ - vbus_en = 1; - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Ensure we advertise the proper available current quota */ - charge_manager_source_port(port, 1); -#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */ - - if (IS_ENABLED(VARIANT_KUKUI_CHARGER_ISL9238)) - charge_set_output_current_limit(CHARGER_SOLO, 3300, 5000); - else - charger_enable_otg_power(CHARGER_SOLO, 1); - - gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1); - gpio_set_level(GPIO_EN_PP5000_USBC, 1); - if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C)) - charger_set_current(CHARGER_SOLO, 0); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; /* we are ready */ -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - if (port != CHARGE_PORT_USB_C) - return; - - prev_en = vbus_en; - /* Disable VBUS */ - vbus_en = 0; - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - -#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT - /* Give back the current quota we are no longer using */ - charge_manager_source_port(port, 0); -#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */ - - if (IS_ENABLED(VARIANT_KUKUI_CHARGER_ISL9238)) - charge_set_output_current_limit(CHARGER_SOLO, 0, 0); - else - charger_enable_otg_power(CHARGER_SOLO, 0); - - gpio_set_level(GPIO_EN_PP5000_USBC, 0); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_check_vconn_swap(int port) -{ - /* always allow vconn swap, since PSYS sources VCONN */ - return 1; -} - -/* ----------------- Vendor Defined Messages ------------------ */ -#ifdef CONFIG_USB_PD_ALT_MODE_DFP -__overridable int board_has_virtual_mux(void) -{ - return IS_ENABLED(CONFIG_USB_MUX_VIRTUAL); -} - -static void board_usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_mode, int polarity) -{ - usb_mux_set(port, mux_mode, usb_mode, polarity); - - if (!board_has_virtual_mux()) - /* b:149181702: Inform AP of DP status */ - host_set_single_event(EC_HOST_EVENT_USB_MUX); -} - -__override void svdm_safe_dp_mode(int port) -{ - /* make DP interface safe until configure */ - dp_flags[port] = 0; - dp_status[port] = 0; - board_usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, - board_get_polarity(port)); -} - -__override int svdm_enter_dp_mode(int port, uint32_t mode_caps) -{ - /* Kukui/Krane doesn't support superspeed lanes. */ - const uint32_t support_pin_mode = board_has_virtual_mux() ? - (MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL; - - /** - * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane) - * capable - */ - if ((mode_caps & MODE_DP_SNK) && - (mode_caps & ((support_pin_mode << MODE_DP_DFP_PIN_SHIFT) | - (support_pin_mode << MODE_DP_UFP_PIN_SHIFT)))) { - svdm_safe_dp_mode(port); - return 0; - } - - CPRINTS("ERR:DP mode SNK or C&E missing! 0x%x", mode_caps); - return -1; -} - -__override int svdm_dp_config(int port, uint32_t *payload) -{ - int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); - int status = dp_status[port]; - int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); - int pin_mode; - - /* Kukui doesn't support multi-function mode, mask it out. */ - if (board_has_virtual_mux()) - status &= ~PD_VDO_DPSTS_MF_MASK; - - pin_mode = pd_dfp_dp_get_pin_mode(port, status); - - if (!pin_mode) - return 0; - - if (board_has_virtual_mux()) - board_usb_mux_set(port, USB_PD_MUX_DP_ENABLED, - USB_SWITCH_CONNECT, board_get_polarity(port)); - else - board_usb_mux_set( - port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED, - USB_SWITCH_CONNECT, board_get_polarity(port)); - - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ - return 2; -}; - -__override void svdm_dp_post_config(int port) -{ - dp_flags[port] |= DP_FLAGS_DP_ON; - if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) - return; - - gpio_set_level(GPIO_USB_C0_HPD_OD, 1); -#ifdef VARIANT_KUKUI_DP_MUX_GPIO - board_set_dp_mux_control(1, board_get_polarity(port)); -#endif - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - int cur_lvl = gpio_get_level(GPIO_USB_C0_HPD_OD); - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - /* Its initial DP status message prior to config */ - if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { - if (lvl) - dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; - return 1; - } - - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - - if (irq & cur_lvl) { - uint64_t now = get_time().val; - /* wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* generate IRQ_HPD pulse */ - gpio_set_level(GPIO_USB_C0_HPD_OD, 0); - usleep(HPD_DSTREAM_DEBOUNCE_IRQ); - gpio_set_level(GPIO_USB_C0_HPD_OD, 1); - -#ifdef VARIANT_KUKUI_DP_MUX_GPIO - board_set_dp_mux_control(1, board_get_polarity(port)); -#endif - - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } else if (irq & !lvl) { - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; /* nak */ - } else { - gpio_set_level(GPIO_USB_C0_HPD_OD, lvl); -#ifdef VARIANT_KUKUI_DP_MUX_GPIO - board_set_dp_mux_control(lvl, board_get_polarity(port)); -#endif - /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } - - /* ack */ - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ - gpio_set_level(GPIO_USB_C0_HPD_OD, 0); -#ifdef VARIANT_KUKUI_DP_MUX_GPIO - board_set_dp_mux_control(0, 0); -#endif - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} -#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/kukui/usb_pd_policy.h b/baseboard/kukui/usb_pd_policy.h deleted file mode 100644 index 78e0213f53..0000000000 --- a/baseboard/kukui/usb_pd_policy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_BASEBOARD_USB_PD_POLICY_H -#define __CROS_EC_BASEBOARD_USB_PD_POLICY_H - -#include "common.h" - -__override_proto int board_has_virtual_mux(void); - -#endif /* __CROS_EC_BASEBOARD_USB_PD_POLICY_H */ diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c deleted file mode 100644 index a34a08f1fe..0000000000 --- a/baseboard/mtscp-rv32i/baseboard.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* MT SCP RV32i configuration */ - -#include "cache.h" -#include "csr.h" -#include "registers.h" - -#define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - -struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { - /* SRAM (for most code, data) */ - {0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, - /* SRAM (for IPI shared buffer) */ - {SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R}, - /* For AP domain */ -#ifdef CHIP_VARIANT_MT8195 - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P}, -#else - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R}, -#endif - /* For SCP sys */ - {0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R}, -#ifdef CHIP_VARIANT_MT8195 - {0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, -#else - {0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R}, -#endif -}; - -#include "gpio_list.h" diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h deleted file mode 100644 index a8f3b522a0..0000000000 --- a/baseboard/mtscp-rv32i/baseboard.h +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MT SCP RV32i board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_IPI))) - -#define CONFIG_FLASH_SIZE_BYTES CONFIG_RAM_BASE -#define CONFIG_LTO -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_UART_CONSOLE 0 - -/* IPI configs */ -#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 -#define CONFIG_IPC_SHARED_OBJ_ADDR \ - (SCP_FW_END - \ - (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) -#define CONFIG_IPI -#define CONFIG_RPMSG_NAME_SERVICE - -#define SCP_IPI_INIT 0 -#define SCP_IPI_VDEC_H264 1 -#define SCP_IPI_VDEC_VP8 2 -#define SCP_IPI_VDEC_VP9 3 -#define SCP_IPI_VENC_H264 4 -#define SCP_IPI_VENC_VP8 5 -#define SCP_IPI_MDP_INIT 6 -#define SCP_IPI_MDP_DEINIT 7 -#define SCP_IPI_MDP_FRAME 8 -#define SCP_IPI_DIP 9 -#define SCP_IPI_ISP_CMD 10 -#define SCP_IPI_ISP_FRAME 11 -#define SCP_IPI_FD_CMD 12 -#define SCP_IPI_HOST_COMMAND 13 -#define SCP_IPI_VDEC_LAT 14 -#define SCP_IPI_VDEC_CORE 15 -#define SCP_IPI_COUNT 16 - -#define IPI_COUNT SCP_IPI_COUNT - -#define SCP_IPI_NS_SERVICE 0xFF - -/* Access DRAM through cached access */ -#define CONFIG_DRAM_BASE 0x10000000 -/* Shared memory address in AP physical address space. */ -#define CONFIG_DRAM_BASE_LOAD 0x50000000 -#define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */ - -/* MPU settings */ -#define NR_MPU_ENTRIES 16 - -#ifndef __ASSEMBLER__ -#include "gpio_signal.h" -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/mtscp-rv32i/build.mk b/baseboard/mtscp-rv32i/build.mk deleted file mode 100644 index 420a3a4e08..0000000000 --- a/baseboard/mtscp-rv32i/build.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -*- makefile -*- -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# -baseboard-y+=baseboard.o - -baseboard-$(HAS_TASK_VDEC_SERVICE)+=vdec.o -baseboard-$(HAS_TASK_VENC_SERVICE)+=venc.o -baseboard-$(HAS_TASK_MDP_SERVICE)+=mdp.o diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c deleted file mode 100644 index b0756a797a..0000000000 --- a/baseboard/mtscp-rv32i/mdp.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "console.h" -#include "ipi_chip.h" -#include "mdp.h" -#include "queue_policies.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -static void event_mdp_written(struct consumer const *consumer, size_t count) -{ - task_wake(TASK_ID_MDP_SERVICE); -} -static struct consumer const event_mdp_consumer; -static struct queue const event_mdp_queue = QUEUE_DIRECT(4, - struct mdp_msg_service, null_producer, event_mdp_consumer); -static struct consumer const event_mdp_consumer = { - .queue = &event_mdp_queue, - .ops = &((struct consumer_ops const) { - .written = event_mdp_written, - }), -}; - -/* Stub functions only provided by private overlays. */ -#ifndef HAVE_PRIVATE_MT_SCP -void mdp_common_init(void) {} -void mdp_ipi_task_handler(void *pvParameters) {} -#endif - -static void mdp_ipi_handler(int id, void *data, unsigned int len) -{ - struct mdp_msg_service rsv_msg; - - if (!len) { - CPRINTS("len is zero."); - return; - } - - rsv_msg.id = id; - memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg))); - - /* - * If there is no other IPI handler touch this queue, we don't need to - * interrupt_disable() or task_disable_irq(). - */ - if (!queue_add_unit(&event_mdp_queue, &rsv_msg)) - CPRINTS("Could not send mdp id: %d to the queue.", id); -} -DECLARE_IPI(SCP_IPI_MDP_INIT, mdp_ipi_handler, 0); -DECLARE_IPI(SCP_IPI_MDP_FRAME, mdp_ipi_handler, 0); -DECLARE_IPI(SCP_IPI_MDP_DEINIT, mdp_ipi_handler, 0); - -void mdp_service_task(void *u) -{ - struct mdp_msg_service rsv_msg; - size_t size; - - mdp_common_init(); - - while (1) { - /* - * Queue unit is added in IPI handler, which is in ISR context. - * Disable IRQ to prevent a clobbered queue. - */ - ipi_disable_irq(); - size = queue_remove_unit(&event_mdp_queue, &rsv_msg); - ipi_enable_irq(); - - if (!size) - task_wait_event(-1); - else - mdp_ipi_task_handler(&rsv_msg); - } -} diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h deleted file mode 100644 index eea3ffb289..0000000000 --- a/baseboard/mtscp-rv32i/mdp.h +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_SCP_MDP_H -#define __CROS_EC_SCP_MDP_H - -struct mdp_msg_service { - int id; - unsigned char msg[20]; -}; -BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -/* Functions provided by private overlay. */ -void mdp_common_init(void); -void mdp_ipi_task_handler(void *pvParameters); - -#endif /* __CROS_EC_SCP_MDP_H */ diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c deleted file mode 100644 index c3f5f5a9cf..0000000000 --- a/baseboard/mtscp-rv32i/vdec.c +++ /dev/null @@ -1,136 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "console.h" -#include "hooks.h" -#include "ipi_chip.h" -#include "queue.h" -#include "queue_policies.h" -#include "registers.h" -#include "task.h" -#include "util.h" -#include "vdec.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -static void event_vdec_written(struct consumer const *consumer, size_t count) -{ - task_wake(TASK_ID_VDEC_SERVICE); -} -static struct consumer const event_vdec_consumer; -static struct queue const event_vdec_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_consumer); -static struct consumer const event_vdec_consumer = { - .queue = &event_vdec_queue, - .ops = &((struct consumer_ops const) { - .written = event_vdec_written, - }), -}; - -static void event_vdec_core_written(struct consumer const *consumer, - size_t count) -{ - task_wake(TASK_ID_VDEC_CORE_SERVICE); -} -static struct consumer const event_vdec_core_consumer; -static struct queue const event_vdec_core_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_core_consumer); -static struct consumer const event_vdec_core_consumer = { - .queue = &event_vdec_core_queue, - .ops = &((struct consumer_ops const) { - .written = event_vdec_core_written, - }), -}; - -/* Stub functions only provided by private overlays. */ -#ifndef HAVE_PRIVATE_MT_SCP -void vdec_msg_handler(void *data) {} -void vdec_core_msg_handler(void *data) {} -#endif - -static void vdec_h264_ipi_handler(int id, void *data, uint32_t len) -{ - struct vdec_msg rsv_msg; - - if (!len) { - CPRINTS("len is zero."); - return; - } - - rsv_msg.type = VDEC_LAT; - memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg))); - - /* - * If there is no other IPI handler touch this queue, we don't need to - * interrupt_disable() or task_disable_irq(). - */ - if (!queue_add_unit(&event_vdec_queue, &rsv_msg)) - CPRINTS("Could not send vdec %d to the queue.", rsv_msg.type); -} -DECLARE_IPI(SCP_IPI_VDEC_LAT, vdec_h264_ipi_handler, 0); - -static void vdec_h264_ipi_core_handler(int id, void *data, uint32_t len) -{ - struct vdec_msg rsv_msg; - - if (!len) { - CPRINTS("len is zero."); - return; - } - - rsv_msg.type = VDEC_CORE; - memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg))); - - /* - * If there is no other IPI handler touch this queue, we don't need to - * interrupt_disable() or task_disable_irq(). - */ - if (!queue_add_unit(&event_vdec_core_queue, &rsv_msg)) - CPRINTS("Could not send vdec %d to core queue.", rsv_msg.type); -} -DECLARE_IPI(SCP_IPI_VDEC_CORE, vdec_h264_ipi_core_handler, 0); - -void vdec_service_task(void *u) -{ - struct vdec_msg rsv_msg; - size_t size; - - while (1) { - /* - * Queue unit is added in IPI handler, which is in ISR context. - * Disable IRQ to prevent a clobbered queue. - */ - ipi_disable_irq(); - size = queue_remove_unit(&event_vdec_queue, &rsv_msg); - ipi_enable_irq(); - - if (!size) - task_wait_event(-1); - else - vdec_msg_handler(rsv_msg.msg); - } -} - -void vdec_core_service_task(void *u) -{ - struct vdec_msg rsv_msg; - size_t size; - - while (1) { - /* - * Queue unit is added in IPI handler, which is in ISR context. - * Disable IRQ to prevent a clobbered queue. - */ - ipi_disable_irq(); - size = queue_remove_unit(&event_vdec_core_queue, &rsv_msg); - ipi_enable_irq(); - - if (!size) - task_wait_event(-1); - else - vdec_core_msg_handler(rsv_msg.msg); - } -} diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h deleted file mode 100644 index cdc16ba9e0..0000000000 --- a/baseboard/mtscp-rv32i/vdec.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_SCP_VDEC_H -#define __CROS_EC_SCP_VDEC_H - -#include "compile_time_macros.h" - -enum vdec_type { - VDEC_LAT, - VDEC_CORE, - VDEC_MAX, -}; - -struct vdec_msg { - enum vdec_type type; - unsigned char msg[48]; -}; -BUILD_ASSERT(member_size(struct vdec_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -/* Functions provided by private overlay. */ -void vdec_core_msg_handler(void *msg); -void vdec_msg_handler(void *msg); - -#endif /* __CROS_EC_SCP_VDEC_H */ diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c deleted file mode 100644 index 09bb0cbd39..0000000000 --- a/baseboard/mtscp-rv32i/venc.c +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "console.h" -#include "hooks.h" -#include "ipi_chip.h" -#include "queue.h" -#include "queue_policies.h" -#include "registers.h" -#include "task.h" -#include "util.h" -#include "venc.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -static void event_venc_written(struct consumer const *consumer, size_t count) -{ - task_wake(TASK_ID_VENC_SERVICE); -} -static struct consumer const event_venc_consumer; -static struct queue const event_venc_queue = QUEUE_DIRECT(8, - struct venc_msg, null_producer, event_venc_consumer); -static struct consumer const event_venc_consumer = { - .queue = &event_venc_queue, - .ops = &((struct consumer_ops const) { - .written = event_venc_written, - }), -}; - -/* Stub functions only provided by private overlays. */ -#ifndef HAVE_PRIVATE_MT_SCP -void venc_h264_msg_handler(void *data) {} -#endif - -static void venc_h264_ipi_handler(int id, void *data, uint32_t len) -{ - struct venc_msg rsv_msg; - - if (!len) { - CPRINTS("len is zero."); - return; - } - - rsv_msg.type = VENC_H264; - memcpy(rsv_msg.msg, data, MIN(len, sizeof(rsv_msg.msg))); - - /* - * If there is no other IPI handler touch this queue, we don't need to - * interrupt_disable() or task_disable_irq(). - */ - if (!queue_add_unit(&event_venc_queue, &rsv_msg)) - CPRINTS("Could not send venc %d to the queue.", rsv_msg.type); -} -DECLARE_IPI(SCP_IPI_VENC_H264, venc_h264_ipi_handler, 0); - -void venc_service_task(void *u) -{ - struct venc_msg rsv_msg; - size_t size; - - typedef void (*venc_msg_handler)(void *msg); - static venc_msg_handler mtk_venc_msg_handle[VENC_MAX] = { - [VENC_H264] = venc_h264_msg_handler, - }; - - while (1) { - /* - * Queue unit is added in IPI handler, which is in ISR context. - * Disable IRQ to prevent a clobbered queue. - */ - ipi_disable_irq(); - size = queue_remove_unit(&event_venc_queue, &rsv_msg); - ipi_enable_irq(); - - if (!size) - task_wait_event(-1); - else if (mtk_venc_msg_handle[rsv_msg.type]) - mtk_venc_msg_handle[rsv_msg.type](rsv_msg.msg); - else - CPRINTS("venc handler %d not exists.", rsv_msg.type); - } -} diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h deleted file mode 100644 index 47454c4507..0000000000 --- a/baseboard/mtscp-rv32i/venc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_SCP_VENC_H -#define __CROS_EC_SCP_VENC_H - -#include "compile_time_macros.h" - -enum venc_type { - VENC_H264, - VENC_MAX, -}; - -struct venc_msg { - enum venc_type type; - unsigned char msg[288]; -}; -BUILD_ASSERT(member_size(struct venc_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -/* Functions provided by private overlay. */ -void venc_h264_msg_handler(void *data); - -#endif /* __CROS_EC_SCP_VENC_H */ diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c deleted file mode 100644 index 15e46f006e..0000000000 --- a/baseboard/nucleo-f412zg/base-board.c +++ /dev/null @@ -1,11 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "gpio.h" - -__overridable void button_event(enum gpio_signal signal) -{ -} diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h deleted file mode 100644 index d41cdfd207..0000000000 --- a/baseboard/nucleo-f412zg/base-board.h +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Nucleo-F412ZG baseboard configuration */ - -#ifndef __CROS_EC_BASE_BOARD_H -#define __CROS_EC_BASE_BOARD_H - -/*-------------------------------------------------------------------------* - * Flash layout: - * - * +++++++++++++ - * | RO | - * | ......... | - * | Rollback | (two sectors) - * +-----------+ - * | RW | - * | | - * | | - * | | - * | | - * +++++++++++++ - * - * We adjust the following macros to accommodate a for a rollback, RO, - * and RW region of different sizes. - * - *-------------------------------------------------------------------------*/ - -#undef _IMAGE_SIZE -#undef CONFIG_ROLLBACK_OFF -#undef CONFIG_ROLLBACK_SIZE -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FW_PSTATE_SIZE -#undef CONFIG_FW_PSTATE_OFF -#undef CONFIG_SHAREDLIB_SIZE -#undef CONFIG_RO_MEM_OFF -#undef CONFIG_RO_STORAGE_OFF -#undef CONFIG_RO_SIZE -#undef CONFIG_RW_MEM_OFF -#undef CONFIG_RW_STORAGE_OFF -#undef CONFIG_RW_SIZE -#undef CONFIG_EC_PROTECTED_STORAGE_OFF -#undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#undef CONFIG_EC_WRITABLE_STORAGE_OFF -#undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#undef CONFIG_WP_STORAGE_OFF -#undef CONFIG_WP_STORAGE_SIZE - -#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 - -#define CONFIG_SHAREDLIB_SIZE 0 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) - -/* EC rollback protection block */ -#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) -#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */ - -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) - -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* - * We want to prevent flash readout, and use it as indicator of protection - * status. - */ -#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - -/*-------------------------------------------------------------------------* - * UART Console Setup - *-------------------------------------------------------------------------*/ - -/* The UART console is on USART3 */ -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 3 -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 -#define CONFIG_UART_TX_REQ_CH 4 -#define CONFIG_UART_RX_REQ_CH 4 -/* We don't currently use DMA. */ -#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX -#undef CONFIG_UART_TX_DMA -#undef CONFIG_UART_RX_DMA - -/*-------------------------------------------------------------------------* - * Console Commands - *-------------------------------------------------------------------------*/ - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IDLE_STATS - -/*-------------------------------------------------------------------------* - * Rollback Block - *-------------------------------------------------------------------------*/ - -#define CONFIG_ROLLBACK -#define CONFIG_MPU -#define CONFIG_ROLLBACK_MPU_PROTECT - -/* - * We do not use any "locally" generated entropy: this is normally used - * to add local entropy when the main source of entropy is remote. - */ -#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE -#ifdef SECTION_IS_RW - #undef CONFIG_ROLLBACK_UPDATE -#endif - -/*-------------------------------------------------------------------------* - * RW Signature Verification - *-------------------------------------------------------------------------*/ - -#ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ - #define CONFIG_RSA - #define CONFIG_RWSIG -#endif /* SECTION_IS_RO */ -#define CONFIG_RSA_KEY_SIZE 3072 -#define CONFIG_RSA_EXPONENT_3 -#define CONFIG_RWSIG_TYPE_RWSIG - -/*-------------------------------------------------------------------------* - * Watchdog - *-------------------------------------------------------------------------*/ - -/* - * RW does slow compute, RO does slow flash erase. - */ -#undef CONFIG_WATCHDOG_PERIOD_MS -#define CONFIG_WATCHDOG_PERIOD_MS 10000 -#define CONFIG_WATCHDOG_HELP - -/*-------------------------------------------------------------------------* - * Disable Features - *-------------------------------------------------------------------------*/ - -#undef CONFIG_ADC -#undef CONFIG_HIBERNATE -#undef CONFIG_I2C -#undef CONFIG_LID_SWITCH -#undef CONFIG_TASK_PROFILING - -/*-------------------------------------------------------------------------* - * Other - *-------------------------------------------------------------------------*/ - -#define CONFIG_AES -#define CONFIG_AES_GCM -#define CONFIG_DMA -#define CONFIG_FPU -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT -#define CONFIG_RNG -#define CONFIG_SHA256 -#define CONFIG_SHA256_UNROLLED -#define CONFIG_STM_HWTIMER32 -#define CONFIG_WP_ACTIVE_HIGH - -#ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ - #define CONFIG_SPI -#endif - -#ifndef __ASSEMBLER__ - /* Timer selection */ - #define TIM_CLOCK32 2 - #define TIM_WATCHDOG 16 - #include "gpio_signal.h" - void button_event(enum gpio_signal signal); -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASE_BOARD_H */ diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc deleted file mode 100644 index 4ebd99f91f..0000000000 --- a/baseboard/nucleo-f412zg/base-gpio.inc +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Note that these pins map to the Nucleo-F412ZG. - */ - -/* Inputs and Interrupts */ -GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event) -GPIO_INT(BTN1, PIN(C, 13), GPIO_INT_BOTH, button_event) -GPIO(WP, PIN(B, 8), GPIO_INPUT) /* Not same as bloonchipper */ - -/* Outputs */ -GPIO(EC_INT_L, PIN(A, 1), GPIO_OUT_HIGH) -GPIO(LED1, PIN(B, 0), GPIO_OUT_LOW) /* Green */ -GPIO(LED2, PIN(B, 7), GPIO_OUT_LOW) /* Blue */ -GPIO(LED3, PIN(B, 14), GPIO_OUT_LOW) /* Red */ - -UNIMPLEMENTED(ENTERING_RW) - -/* USART3: PD8/PD9 (TX/RX) */ -ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) -/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */ -ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI, 0) diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk deleted file mode 100644 index 1456331fec..0000000000 --- a/baseboard/nucleo-f412zg/build.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Nucleo-F412ZG baseboard specific files build -# - -# the IC is STmicro STM32F412 -CHIP:=stm32 -CHIP_FAMILY:=stm32f4 -CHIP_VARIANT:=stm32f412 - -baseboard-y=base-board.o diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg deleted file mode 100644 index 3333d1163a..0000000000 --- a/baseboard/nucleo-f412zg/openocd-flash.cfg +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -source [find board/st_nucleo_f4.cfg] - -gdb_port 0 -tcl_port 0 -telnet_port 0 -init -reset halt -flash write_image erase $BUILD_DIR/ec.bin 0x08000000 -reset -shutdown diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg deleted file mode 100644 index 589d4400f4..0000000000 --- a/baseboard/nucleo-f412zg/openocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -source [find board/st_nucleo_f4.cfg] - -# Enabled EC task context support -# This is supported by the upstream OpenOCD -$_TARGETNAME configure -rtos Chromium-EC diff --git a/baseboard/nucleo-h743zi/base-board.c b/baseboard/nucleo-h743zi/base-board.c deleted file mode 100644 index 15e46f006e..0000000000 --- a/baseboard/nucleo-h743zi/base-board.c +++ /dev/null @@ -1,11 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "gpio.h" - -__overridable void button_event(enum gpio_signal signal) -{ -} diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h deleted file mode 100644 index df5e4bfa8c..0000000000 --- a/baseboard/nucleo-h743zi/base-board.h +++ /dev/null @@ -1,179 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Nucleo-H743ZI baseboard configuration */ - -#ifndef __CROS_EC_BASE_BOARD_H -#define __CROS_EC_BASE_BOARD_H - -/* - * Flash layout: - * - * +++++++++++++ - * | RO | Bank 1 - * | | - * | | - * | ......... | - * | Rollback | (last two sectors) - * +-----------+ - * | RW | Bank 2 - * | | - * | | - * | | - * | | - * +++++++++++++ - * - * We adjust the following macros to accommodate a rollback region - * and RO/RW regions of different sizes. - */ - -#undef _IMAGE_SIZE -#undef CONFIG_ROLLBACK_OFF -#undef CONFIG_ROLLBACK_SIZE -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FW_PSTATE_SIZE -#undef CONFIG_FW_PSTATE_OFF -#undef CONFIG_RO_MEM_OFF -#undef CONFIG_RO_STORAGE_OFF -#undef CONFIG_RO_SIZE -#undef CONFIG_RW_MEM_OFF -#undef CONFIG_RW_STORAGE_OFF -#undef CONFIG_RW_SIZE -#undef CONFIG_EC_PROTECTED_STORAGE_OFF -#undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#undef CONFIG_EC_WRITABLE_STORAGE_OFF -#undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#undef CONFIG_WP_STORAGE_OFF -#undef CONFIG_WP_STORAGE_SIZE - -/* - * EC rollback protection block - * - * We need 2 independently erasable blocks, at a minimum. - */ -#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE_BYTES / 2) - \ - CONFIG_ROLLBACK_SIZE) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* Disabled features */ - -#undef CONFIG_ADC -#undef CONFIG_HIBERNATE -#undef CONFIG_I2C -#undef CONFIG_LID_SWITCH -#undef CONFIG_TASK_PROFILING - -/* Enabled features */ - -#define CONFIG_AES -#define CONFIG_AES_GCM -#define CONFIG_DMA -#define CONFIG_FORCE_CONSOLE_RESUME -#define CONFIG_FPU -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT -#define CONFIG_RNG -#define CONFIG_RWSIG_TYPE_RWSIG -#define CONFIG_SHA256 -#define CONFIG_SHA256_UNROLLED -#undef CONFIG_SHAREDLIB_SIZE -#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_STM_HWTIMER32 -#define CONFIG_WATCHDOG_HELP -#define CONFIG_WP_ACTIVE_HIGH - -#ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ -# define CONFIG_SPI -#endif - -/* - * We want to prevent flash readout, and use it as indicator of protection - * status. - */ -#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - -/* - * RW does slow compute, RO does slow flash erase. - */ -#undef CONFIG_WATCHDOG_PERIOD_MS -#define CONFIG_WATCHDOG_PERIOD_MS 10000 - -/* Setup UART console */ - -#undef CONFIG_UART_CONSOLE -#define CONFIG_UART_CONSOLE 3 /* The UART console is on USART3 */ -#define CONFIG_UART_TX_DMA -#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Console commands */ - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IDLE_STATS - -#ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ -# define CONFIG_RSA -# define CONFIG_RWSIG -#endif /* SECTION_IS_RO */ - -#define CONFIG_RSA_KEY_SIZE 3072 -#define CONFIG_RSA_EXPONENT_3 - -/* - * We do not use any "locally" generated entropy: this is normally used - * to add local entropy when the main source of entropy is remote. - */ -#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE -#ifdef SECTION_IS_RW -# undef CONFIG_ROLLBACK_UPDATE -#endif -/* - * Add rollback protection - */ -#define CONFIG_ROLLBACK -#define CONFIG_ROLLBACK_MPU_PROTECT - -#ifndef __ASSEMBLER__ - /* Timer selection */ -# define TIM_CLOCK32 2 -# define TIM_WATCHDOG 16 -# include "gpio_signal.h" - void button_event(enum gpio_signal signal); -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASE_BOARD_H */ diff --git a/baseboard/nucleo-h743zi/base-ec.tasklist b/baseboard/nucleo-h743zi/base-ec.tasklist deleted file mode 100644 index fae8952113..0000000000 --- a/baseboard/nucleo-h743zi/base-ec.tasklist +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * See CONFIG_TASK_LIST in config.h for details. - */ -#define BASEBOARD_CONFIG_TASK_LIST \ - TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \ - TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \ - TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) diff --git a/baseboard/nucleo-h743zi/base-gpio.inc b/baseboard/nucleo-h743zi/base-gpio.inc deleted file mode 100644 index ef224cbaf1..0000000000 --- a/baseboard/nucleo-h743zi/base-gpio.inc +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Note that these pins map to the Nucleo-H743ZI V2 and are only slightly - * compatible with the original version. - * - * The V2 is denoted by "Nucleo-H743ZI2" vs. "Nucleo-H743ZI". - */ - -/* Inputs ands Interrupts */ -GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event) -GPIO_INT(BTN1, PIN(C, 13), GPIO_INT_BOTH, button_event) -GPIO(WP, PIN(B, 7), GPIO_INPUT) - -/* Outputs */ -GPIO(EC_INT_L, PIN(A, 1), GPIO_OUT_HIGH) -GPIO(LED1, PIN(B, 0), GPIO_OUT_LOW) /* Green */ -GPIO(LED2, PIN(E, 1), GPIO_OUT_LOW) /* Yellow */ -GPIO(LED3, PIN(B, 14), GPIO_OUT_LOW) /* Red */ - -UNIMPLEMENTED(ENTERING_RW) - -/* USART3: PD8/PD9 */ -ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART, MODULE_UART, GPIO_PULL_UP) -/* SPI1 slave from the AP: PA4/5/6/7 */ -ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI, 0) diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk deleted file mode 100644 index e9f9ae3faa..0000000000 --- a/baseboard/nucleo-h743zi/build.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Nucleo-H743ZI baseboard specific files build -# - -# the IC is STmicro STM32H743 -CHIP:=stm32 -CHIP_FAMILY:=stm32h7 -CHIP_VARIANT:=stm32h7x3 - -baseboard-y=base-board.o
\ No newline at end of file diff --git a/baseboard/nucleo-h743zi/openocd-flash.cfg b/baseboard/nucleo-h743zi/openocd-flash.cfg deleted file mode 100644 index 4517266d7b..0000000000 --- a/baseboard/nucleo-h743zi/openocd-flash.cfg +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -source [find board/st_nucleo_h743zi.cfg] - -gdb_port 0 -tcl_port 0 -telnet_port 0 -init -reset halt -flash write_image erase $BUILD_DIR/ec.bin 0x08000000 -reset -shutdown diff --git a/baseboard/nucleo-h743zi/openocd.cfg b/baseboard/nucleo-h743zi/openocd.cfg deleted file mode 100644 index 528e8d6cab..0000000000 --- a/baseboard/nucleo-h743zi/openocd.cfg +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -source [find board/st_nucleo_h743zi.cfg] - -# Enabled EC task context support -# This is supported by the upstream OpenOCD -$_TARGETNAME configure -rtos Chromium-EC diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c deleted file mode 100644 index 4f338ab131..0000000000 --- a/baseboard/octopus/baseboard.c +++ /dev/null @@ -1,384 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Octopus family-specific configuration */ - -#include "charge_manager.h" -#include "charge_state.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/bc12/max14637.h" -#include "driver/charger/isl923x.h" -#include "driver/ppc/nx20p348x.h" -#include "gpio.h" -#include "hooks.h" -#ifdef VARIANT_OCTOPUS_EC_ITE8320 -#include "intc.h" -#endif -#include "keyboard_scan.h" -#include "power.h" -#include "system.h" -#include "task.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/******************************************************************************/ -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80us from 50us. - */ - .output_settle_us = 80, - .debounce_down_us = 9 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 3 * MSEC, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = 100 * MSEC, - .actual_key_mask = { -#ifndef CONFIG_KEYBOARD_KEYPAD - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ -#else - 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */ -#endif - }, -}; - -/******************************************************************************/ -/* USB-A Configuration */ -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_EN_USB_A0_5V, - GPIO_EN_USB_A1_5V, -}; - -/******************************************************************************/ -/* BC 1.2 chip Configuration */ -const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON, - .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, - { - .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON, - .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L, - .flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW, - }, -}; - -/******************************************************************************/ -/* Charger Chip Configuration */ -#ifdef VARIANT_OCTOPUS_CHARGER_ISL9238 -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; -#endif - -/******************************************************************************/ -/* Chipset callbacks/hooks */ - -/* Called by APL power state machine when transitioning from G3 to S5 */ -void chipset_pre_init_callback(void) -{ -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* - * Since we disable eSPI module for IT8320 part when system goes into G3 - * state, so we need to enable it at system startup. - */ - espi_enable_pad(1); -#endif - - /* Enable 5.0V and 3.3V rails, and wait for Power Good */ - power_5v_enable(task_get_current(), 1); - - gpio_set_level(GPIO_EN_PP3300, 1); - while (!gpio_get_level(GPIO_PP5000_PG) || - !gpio_get_level(GPIO_PP3300_PG)) - ; - - /* Enable PMIC */ - gpio_set_level(GPIO_PMIC_EN, 1); -} - -/* Called on AP S5 -> S3 transition */ -static void baseboard_chipset_startup(void) -{ - /* Enable Trackpad in S3+, so it can be an AP wake source. */ - gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, - HOOK_PRIO_DEFAULT); - -/* Called on AP S3 -> S0 transition */ -static void baseboard_chipset_resume(void) -{ - /* - * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and - * LID_OPEN connection in hardware. - */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1); - /* Enable the keyboard backlight */ - gpio_set_level(GPIO_KB_BL_PWR_EN, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -/* Called on AP S0 -> S3 transition */ -static void baseboard_chipset_suspend(void) -{ - /* - * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and - * LID_OPEN connection in hardware. - */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0); - /* Disable the keyboard backlight */ - gpio_set_level(GPIO_KB_BL_PWR_EN, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -/* Called on AP S3 -> S5 transition */ -static void baseboard_chipset_shutdown(void) -{ - /* Disable Trackpad in S5- to save power; not a low power wake source */ - gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, - HOOK_PRIO_DEFAULT); - -/* Called by APL power state machine when transitioning to G3. */ -void chipset_do_shutdown(void) -{ -#ifdef VARIANT_OCTOPUS_EC_ITE8320 - /* - * We want the processor to be reset before dropping the PP3300_A rail - * below, otherwise the PP3300_LDO and PP3300_EC rails can be overloaded - */ - if (gpio_get_level(GPIO_PCH_SLP_S4_L)) { - /* assert RSMRST to PCH */ - gpio_set_level(GPIO_PCH_RSMRST_L, 0); - /* Wait SLP_S4 goes low; would rather watchdog than continue */ - while (gpio_get_level(GPIO_PCH_SLP_S4_L)) - ; - } -#endif - - /* Disable PMIC */ - gpio_set_level(GPIO_PMIC_EN, 0); - - /* Disable 5.0V and 3.3V rails, and wait until they power down. */ - power_5v_enable(task_get_current(), 0); - - /* - * Shutdown the 3.3V rail and wait for it to go down. We cannot wait - * for the 5V rail since other tasks may be using it. - */ - gpio_set_level(GPIO_EN_PP3300, 0); - while (gpio_get_level(GPIO_PP3300_PG)) - ; - -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* - * The IT8320 part doesn't go into its lowest power state in idle task - * when the eSPI module is on and CS# is asserted, so we need to - * manually disable it. - */ - espi_enable_pad(0); -#endif -} - -int board_is_i2c_port_powered(int port) -{ - if (port != I2C_PORT_SENSOR) - return 1; - - /* Sensor rails are off in S5/G3 */ - return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; -} - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -enum adc_channel board_get_vbus_adc(int port) -{ - if (port == 0) - return ADC_VBUS_C0; - if (port == 1) - return ADC_VBUS_C1; - CPRINTSUSB("Unknown vbus adc port id: %d", port); - return ADC_VBUS_C0; -} -#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */ - -void baseboard_tcpc_init(void) -{ - /* Only reset TCPC if not sysjump */ - if (!system_jumped_late()) - board_reset_pd_mcu(); - - /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ - for (int port = 0; port < board_get_usb_pd_port_count(); ++port) - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); -} -/* Called after the cbi_init (via +2) */ -DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < board_get_usb_pd_port_count()); - int i; - - if (!is_valid_port && port != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - /* - * Empirically, the charger seems to draw a little more current that - * it is set to, so we reduce our limit by 5%. - */ -#if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238) - charge_ma = (charge_ma * 95) / 100; -#endif - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -void board_hibernate(void) -{ - int port; - - /* - * To support hibernate called from console commands, ectool commands - * and key sequence, shutdown the AP before hibernating. - * - * If board_hibernate() is called from within chipset task, then - * chipset_do_shutdown needs to be called directly since - * chipset_force_shutdown basically just sets wake event for chipset - * task. But that will not help since chipset task is in board_hibernate - * and never returns back to the power state machine to take down power - * rails. - */ -#ifdef HAS_TASK_CHIPSET - if (task_get_current() == TASK_ID_CHIPSET) - chipset_do_shutdown(); - else -#endif - chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); - -#ifdef CONFIG_USBC_PPC_NX20P3483 - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) - pd_request_source_voltage(port, NX20P348X_SAFE_RESET_VBUS_MV); -#endif - - /* - * If Vbus isn't already on this port, then we need to put the PPC into - * low power mode or open the SNK FET based on which signals wake up - * the EC from hibernate. - */ - for (port = 0; port < board_get_usb_pd_port_count(); port++) { - if (!pd_is_vbus_present(port)) { -#ifdef VARIANT_OCTOPUS_EC_ITE8320 - /* - * ITE variant uses the PPC interrupts instead of - * AC_PRESENT to wake up, so we do not need to enable - * the SNK FETS. - */ - ppc_enter_low_power_mode(port); -#else - /* - * Open the SNK path to allow AC to pass through to the - * charger when connected. This is need if the TCPC/PPC - * rails do not go away and AC_PRESENT wakes up the EC - * (b/79173959). - */ - ppc_vbus_sink_enable(port, 1); -#endif - } - } - - /* - * Delay allows AP power state machine to settle down along - * with any PD contract renegotiation, and tcpm to put TCPC into low - * power mode if required. - */ - msleep(1500); -} diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h deleted file mode 100644 index 8b05c30f4c..0000000000 --- a/baseboard/octopus/baseboard.h +++ /dev/null @@ -1,322 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Octopus board configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/******************************************************************************* - * EC Config - */ - -/* - * By default, enable all console messages excepted HC, ACPI and event: - * The sensor stack is generating a lot of activity. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) - -/* - * Variant EC defines. Pick one: - * VARIANT_OCTOPUS_EC_NPCX796FB - * VARIANT_OCTOPUS_EC_ITE8320 - */ -#if defined(VARIANT_OCTOPUS_EC_NPCX796FB) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ - #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - - /* Internal SPI flash on NPCX7 */ - /* Flash is 1MB but reserve half for future use. */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 - #define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 - #define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 - #define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 - #define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - /* Enable PSL hibernate mode. */ - #define CONFIG_HIBERNATE_PSL - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - - /* Allow the EC to enter deep sleep in S0 */ - #define CONFIG_LOW_POWER_S0 -#elif defined(VARIANT_OCTOPUS_EC_ITE8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_SENSOR IT83XX_I2C_CH_B - #define I2C_PORT_USBC0 IT83XX_I2C_CH_C - #define I2C_PORT_USBC1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_F - #define I2C_ADDR_EEPROM_FLAGS 0x50 - #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS -#else - #error Must define a VARIANT_OCTOPUS_EC -#endif /* VARIANT_OCTOPUS_EC */ - -/* Common EC defines */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#define CONFIG_CRC8 -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_DPTF -#define CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA -#define CONFIG_BOARD_HAS_RTC_RESET -#define CONFIG_LED_ONOFF_STATES -#define CONFIG_CMD_CHARGEN - -/* Port80 -- allow larger buffer for port80 messages */ -#undef CONFIG_PORT80_HISTORY_LEN -#define CONFIG_PORT80_HISTORY_LEN 256 - -/* - * We don't need CONFIG_BACKLIGHT_LID since hardware AND's LID_OPEN and AP - * signals with EC backlight enable signal. - */ - -/******************************************************************************* - * Battery/Charger/Power Config - */ - -/* - * Variant charger defines. Pick one: - * VARIANT_OCTOPUS_CHARGER_ISL9238 - * VARIANT_OCTOPUS_CHARGER_BQ25703 - */ -#if defined(VARIANT_OCTOPUS_CHARGER_ISL9238) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - /* - * ISL923x driver sets "Adapter insertion to Switching Debounce" - * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703) - #define CONFIG_CHARGER_BQ25703 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 - /* - * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 50 -#elif defined(CONFIG_CHARGER_RUNTIME_CONFIG) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_BQ25710 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_BQ25710 10 - - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#else - #error Must define a VARIANT_OCTOPUS_CHARGER -#endif /* VARIANT_OCTOPUS_CHARGER */ - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER -#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_USB_CHARGER - -/* Common battery defines */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART - -/******************************************************************************* - * USB-C Configs - * Automatically defined by VARIANT_OCTOPUS_EC_ variant. - */ - - /* - * Variant USBC defines. Pick one: - * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) - */ -#if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS) - #define CONFIG_USB_PD_TCPC_LOW_POWER - #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - #define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ -#endif - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ - #define CONFIG_USB_PD_VBUS_DETECT_TCPC - #define CONFIG_USBC_PPC_NX20P3483 -#elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS) - #undef CONFIG_USB_PD_TCPC_LOW_POWER - #undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - #define CONFIG_USB_PD_VBUS_DETECT_PPC - #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ - #define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ - #define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER - #define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ - #define CONFIG_USBC_PPC_VCONN - #define CONFIG_USBC_PPC_DEDICATED_INT -#else - #error Must define a VARIANT_OCTOPUS_USBC -#endif /* VARIANT_OCTOPUS_USBC */ - -/* Common USB-C defines */ -#define USB_PD_PORT_TCPC_0 0 -#define USB_PD_PORT_TCPC_1 1 -#define CONFIG_USB_PID 0x5046 - -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_PD_3A_PORTS 0 -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_COMM_LOCKED -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_BC12_DETECT_MAX14637 -#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS -#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100 -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_CMD_PPC_DUMP - -/* TODO(b/76218141): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -/* TODO(b/76218141): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/******************************************************************************* - * USB-A Configs - */ - -/* Common USB-A defines */ -#define USB_PORT_COUNT 2 -#define CONFIG_USB_PORT_POWER_SMART -#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY -#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP -#define CONFIG_USB_PORT_POWER_SMART_INVERTED -#define GPIO_USB1_ILIM_SEL GPIO_USB_A0_CHARGE_EN_L -#define GPIO_USB2_ILIM_SEL GPIO_USB_A1_CHARGE_EN_L - -/******************************************************************************* - * SoC / PCH Config - */ - - /* Common SoC / PCH defines */ -#define CONFIG_CHIPSET_GEMINILAKE -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_HOSTCMD_ESPI -/* TODO(b/74123961): Enable Virtual Wires after bringup */ -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_EXTPOWER_GPIO - -/******************************************************************************* - * Keyboard Config - */ - -/* Common Keyboard Defines */ -#define CONFIG_CMD_KEYBOARD - -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#undef CONFIG_KEYBOARD_VIVALDI - -/******************************************************************************* - * Sensor Config - */ - -/* Common Sensor Defines */ -#define CONFIG_TABLET_MODE -#define CONFIG_GMR_TABLET_MODE -#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L -/* - * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. - */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US -#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) - -#ifndef VARIANT_OCTOPUS_NO_SENSORS -/* - * Interrupt and fifo are only used for base accelerometer - * and the lid sensor is polled real-time (in forced mode). - */ -#define CONFIG_ACCEL_INTERRUPTS -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* Power of 2 - Too large of a fifo causes too much timestamp jitter */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#endif /* VARIANT_OCTOPUS_NO_SENSORS */ - -/* - * Sensor stack in EC/Kernel depends on a hardware interrupt pin from EC->AP, so - * do not define CONFIG_MKBP_USE_HOST_EVENT since all octopus boards use - * hardware pin to send interrupt from EC -> AP (except casta). - */ -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" - -/* Forward declare common (within octopus) board-specific functions */ -void board_reset_pd_mcu(void); - -#ifdef VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS -void tcpc_alert_event(enum gpio_signal signal); -#endif - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk deleted file mode 100644 index bb8a6f8267..0000000000 --- a/baseboard/octopus/build.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o cbi_ssfc.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(VARIANT_OCTOPUS_EC_NPCX796FB)+=variant_ec_npcx796fb.o -baseboard-$(VARIANT_OCTOPUS_EC_ITE8320)+=variant_ec_ite8320.o -baseboard-$(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)+= \ - variant_usbc_standalone_tcpcs.o -baseboard-$(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)+=variant_usbc_ec_tcpcs.o diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c deleted file mode 100644 index 80d8614eb5..0000000000 --- a/baseboard/octopus/cbi_ssfc.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_ssfc.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -/**************************************************************************** - * Octopus CBI Second Source Factory Cache - */ - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache SSFC on init since we don't expect it to change in runtime */ -static uint32_t cached_ssfc; - -static void cbi_ssfc_init(void) -{ - if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_ssfc = 0; - - CPRINTS("CBI SSFC: 0x%04X", cached_ssfc); -} -DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); - -enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void) -{ - return ((cached_ssfc & SSFC_TCPC_P1_MASK) >> SSFC_TCPC_P1_OFFSET); -} - -enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void) -{ - return ((cached_ssfc & SSFC_PPC_P1_MASK) >> SSFC_PPC_P1_OFFSET); -} - -enum ssfc_charger get_cbi_ssfc_charger(void) -{ - return ((cached_ssfc & SSFC_CHARGER_MASK) >> SSFC_CHARGER_OFFSET); -} - -enum ssfc_sensor get_cbi_ssfc_sensor(void) -{ - return ((cached_ssfc & SSFC_SENSOR_MASK) >> SSFC_SENSOR_OFFSET); -} diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h deleted file mode 100644 index b762336e59..0000000000 --- a/baseboard/octopus/cbi_ssfc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _OCTOPUS_CBI_SSFC__H_ -#define _OCTOPUS_CBI_SSFC__H_ - -/**************************************************************************** - * Octopus CBI Second Source Factory Cache - */ - -/* - * TCPC Port 1 (Bits 0-2) - */ -enum ssfc_tcpc_p1 { - SSFC_TCPC_P1_DEFAULT, - SSFC_TCPC_P1_PS8751, - SSFC_TCPC_P1_PS8755, -}; -#define SSFC_TCPC_P1_OFFSET 0 -#define SSFC_TCPC_P1_MASK GENMASK(2, 0) - -/* - * PPC Port 1 (Bits 3-5) - */ -enum ssfc_ppc_p1 { - SSFC_PPC_P1_DEFAULT, - SSFC_PPC_P1_NX20P348X, - SSFC_PPC_P1_SYV682X, -}; -#define SSFC_PPC_P1_OFFSET 3 -#define SSFC_PPC_P1_MASK GENMASK(5, 3) - -/* - * Charger (Bits 8-6) - */ -enum ssfc_charger { - SSFC_CHARGER_DEFAULT, - SSFC_CHARGER_ISL9238, - SSFC_CHARGER_BQ25710, -}; -#define SSFC_CHARGER_OFFSET 6 -#define SSFC_CHARGER_MASK GENMASK(8, 6) - -/* - * Audio (Bits 11-9) - */ - -/* - * Sensor (Bits 14-12) - */ -enum ssfc_sensor { - SSFC_SENSOR_DEFAULT, - SSFC_SENSOR_BMI160, - SSFC_SENSOR_ICM426XX, -}; -#define SSFC_SENSOR_OFFSET 12 -#define SSFC_SENSOR_MASK GENMASK(14, 12) - -enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void); -enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void); -enum ssfc_charger get_cbi_ssfc_charger(void); -enum ssfc_sensor get_cbi_ssfc_sensor(void); - -#endif /* _OCTOPUS_CBI_SSFC__H_ */ diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c deleted file mode 100644 index 3dd6ad29f5..0000000000 --- a/baseboard/octopus/usb_pd_policy.c +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for octopus boards */ - -#include "charge_manager.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if pp5000_A rail is enabled */ - return gpio_get_level(GPIO_EN_PP5000); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} -#endif - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c deleted file mode 100644 index 459ea113b3..0000000000 --- a/baseboard/octopus/variant_ec_ite8320.c +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_EC_ITE8320 configuration */ - -#include "gpio.h" -#include "i2c.h" -#include "util.h" - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_POWER_BUTTON_L, - /* - * The PPC interrupts (which fire when Vbus changes) is a proxy for - * AC_PRESENT. This allows us to turn off the PPC SNK FETS during - * hibernation which saves power. Once the EC wakes up, it will enable - * the SNK FETs and power will make it to the rest of the system. - */ - GPIO_USB_C0_PD_INT_ODL, - GPIO_USB_C1_PD_INT_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { - {"power", IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, - {"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, - {"usbc0", IT83XX_I2C_CH_C, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, - {"usbc1", IT83XX_I2C_CH_E, 400, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, - {"eeprom", IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c deleted file mode 100644 index bccb360563..0000000000 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_EC_NPCX796FB configuration */ - -#include "charge_manager.h" -#include "gpio.h" -#include "i2c.h" -#include "power.h" -#ifdef CONFIG_PWM -#include "pwm.h" -#include "pwm_chip.h" -#endif -#include "timer.h" -#include "usbc_ppc.h" -#include "util.h" - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, - /* EC_RST_ODL needs to wake device while in PSL hibernate. */ - GPIO_EC_RST_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* I2C port map configuration */ -const struct i2c_port_t i2c_ports[] = { - {"battery", I2C_PORT_BATTERY, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, - {"tcpc0", I2C_PORT_TCPC0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, - {"tcpc1", I2C_PORT_TCPC1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, - {"eeprom", I2C_PORT_EEPROM, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, - {"charger", I2C_PORT_CHARGER, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA}, -#ifndef VARIANT_OCTOPUS_NO_SENSORS - {"sensor", I2C_PORT_SENSOR, 100, GPIO_I2C7_SCL, GPIO_I2C7_SDA}, -#endif -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -#ifdef CONFIG_PWM -/******************************************************************************/ -/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP, - .freq = 100 }, -}; -BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -#endif diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c deleted file mode 100644 index 2e3248410f..0000000000 --- a/baseboard/octopus/variant_usbc_ec_tcpcs.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_USBC_EC_TCPCS configuration */ - -#include "charge_state.h" -#include "common.h" -#include "console.h" -#include "driver/ppc/sn5s330.h" -#include "driver/tcpm/it83xx_pd.h" -#include "driver/usb_mux/it5205.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 - -/******************************************************************************/ -/* USB-C TPCP Configuration */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it83xx_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, - [USB_PD_PORT_ITE_1] = { - .bus_type = EC_BUS_TYPE_EMBEDDED, - /* TCPC is embedded within EC so no i2c config needed */ - .drv = &it83xx_tcpm_drv, - /* Alert is active-low, push-pull */ - .flags = 0, - }, -}; - -/******************************************************************************/ -/* USB-C MUX Configuration */ - -/* TODO(crbug.com/826441): Consolidate this logic with other impls */ -static void board_it83xx_hpd_status(const struct usb_mux *me, - mux_state_t mux_state) -{ - int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; - int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0; - enum gpio_signal gpio = me->usb_port ? - GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL; - - /* Invert HPD level since GPIOs are active low. */ - hpd_lvl = !hpd_lvl; - - gpio_set_level(gpio, hpd_lvl); - if (hpd_irq) { - gpio_set_level(gpio, 1); - msleep(1); - gpio_set_level(gpio, hpd_lvl); - } -} - -/* This configuration might be override by each boards */ -struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .usb_port = USB_PD_PORT_ITE_0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - .hpd_update = &board_it83xx_hpd_status, - }, - [USB_PD_PORT_ITE_1] = { - .usb_port = USB_PD_PORT_ITE_1, - /* Use PS8751 as mux only */ - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = PS8751_I2C_ADDR1_FLAGS, - .flags = USB_MUX_FLAG_NOT_TCPC, - .driver = &ps8xxx_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - } -}; - -/******************************************************************************/ -/* USB-C PPC Configuration */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .i2c_port = I2C_PORT_USBC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_ITE_1] = { - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -void variant_tcpc_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL); -} -/* Called after the baseboard_tcpc_init (via +3) */ -DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3); - -uint16_t tcpc_get_alert_status(void) -{ - /* - * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD - * tasks.The (embedded) TCPC status since chip driver code will - * handles its own interrupts and forward the correct events to - * the PD_C0 task. See it83xx/intc.c - */ - return 0; -} - -/** - * Reset all system PD/TCPC MCUs -- currently called from both - * handle_pending_reboot() in common/system.c and baseboard_tcpc_init() in the - * octopus/baseboard.c - */ -void board_reset_pd_mcu(void) -{ - /* - * C0 & C1: The internal TCPC on ITE EC does not have a reset signal, - * but it will get reset when the EC gets reset. We will, however, - * reset the USB muxes here. - */ - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); - - msleep(PS8XXX_RESET_DELAY_MS); - - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); -} - -void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) -{ - /* - * We ignore the cc_pin because the polarity should already be set - * correctly in the PPC driver via the pd state machine. - */ - if (ppc_set_vconn(port, enabled) != EC_SUCCESS) - cprints(CC_USBPD, "C%d: Failed %sabling vconn", - port, enabled ? "en" : "dis"); -} diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c deleted file mode 100644 index fb5d466e65..0000000000 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ /dev/null @@ -1,216 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common code for VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS configuration */ - -#include "charge_state.h" -#include "common.h" -#include "console.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/tcpm/anx7447.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/tcpm/tcpci.h" -#include "driver/tcpm/tcpm.h" -#include "gpio.h" -#include "hooks.h" -#include "system.h" -#include "tcpm/tcpci.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) - -/******************************************************************************/ -/* USB-C TPCP Configuration */ -const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = PS8751_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, -#else - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, - }, - .drv = &anx7447_tcpm_drv, -#endif - }, - [USB_PD_PORT_TCPC_1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC1, - .addr_flags = PS8751_I2C_ADDR1_FLAGS, - }, - .drv = &ps8xxx_tcpm_drv, - }, -}; - -/******************************************************************************/ -/* USB-C MUX Configuration */ - -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) -static int ps8751_tune_mux(const struct usb_mux *me) -{ - /* Tune USB mux registers for casta's port 0 Rx measurement */ - mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40); - return EC_SUCCESS; -} -#endif - -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .usb_port = USB_PD_PORT_TCPC_0, -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, -#else - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, -#endif - }, - [USB_PD_PORT_TCPC_1] = { - .usb_port = USB_PD_PORT_TCPC_1, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - } -}; - -/******************************************************************************/ -/* USB-C PPC Configuration */ -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv, - }, - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv, - }, -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/******************************************************************************/ -/* Power Delivery and charing functions */ - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port = -1; - - switch (signal) { - case GPIO_USB_C0_MUX_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_MUX_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -void variant_tcpc_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_PD_C0_INT_ODL); - gpio_enable_interrupt(GPIO_USB_PD_C1_INT_ODL); - - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_MUX_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_MUX_INT_ODL); -} -/* Called after the baseboard_tcpc_init (via +3) */ -DECLARE_HOOK(HOOK_INIT, variant_tcpc_init, HOOK_PRIO_INIT_I2C + 3); - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - if (!gpio_get_level(GPIO_USB_C0_MUX_INT_ODL)) { -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - if (gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) -#else - if (!gpio_is_implemented(GPIO_USB_C0_PD_RST) || - !gpio_get_level(GPIO_USB_C0_PD_RST)) -#endif - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_get_level(GPIO_USB_C1_MUX_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C1_PD_RST_ODL)) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -/** - * Reset all system PD/TCPC MCUs -- currently only called from - * handle_pending_reboot() in common/power.c just before hard - * resetting the system. This logic is likely not needed as the - * PP3300_A rail should be dropped on EC reset. - */ -void board_reset_pd_mcu(void) -{ -#if defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - /* - * C0: Assert reset to TCPC0 (PS8751) for required delay if we have a - * battery - */ - if (battery_is_present() == BP_YES) { - /* - * TODO(crbug:846412): After refactor, ensure that battery has - * enough charge to last the reboot as well - */ - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); - msleep(PS8XXX_RESET_DELAY_MS); - gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); - } -#else - /* - * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if - * we have a battery - * - * Note: The TEST_R pin is not hooked up to a GPIO on all boards, so - * verify the name exists before setting it. After the name is - * introduced for later board firmware, this pin will still be wired - * to USB2_OTG_ID on the proto boards, which should be set to open - * drain so it can't be driven high. - */ - if (gpio_is_implemented(GPIO_USB_C0_PD_RST) && - battery_is_present() == BP_YES) { - gpio_set_level(GPIO_USB_C0_PD_RST, 1); - msleep(ANX74XX_RESET_HOLD_MS); - gpio_set_level(GPIO_USB_C0_PD_RST, 0); - msleep(ANX74XX_RESET_FINISH_MS); - } -#endif - /* - * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if - * we have a battery, otherwise we may brown out the system. - */ - if (battery_is_present() == BP_YES) { - /* - * TODO(crbug:846412): After refactor, ensure that battery has - * enough charge to last the reboot as well - */ - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); - msleep(PS8XXX_RESET_DELAY_MS); - gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); - } else { - CPRINTS("Skipping C1 TCPC reset because no battery"); - } -} diff --git a/baseboard/trogdor/baseboard.c b/baseboard/trogdor/baseboard.c deleted file mode 100644 index de01d58211..0000000000 --- a/baseboard/trogdor/baseboard.c +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Trogdor baseboard-specific configuration */ - -#include "i2c.h" - -/* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, - GPIO_EC_RST_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -int board_allow_i2c_passthru(int port) -{ - return (port == I2C_PORT_VIRTUAL_BATTERY || - port == I2C_PORT_TCPC0 || - port == I2C_PORT_TCPC1); -} diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h deleted file mode 100644 index 4eabeb0ca3..0000000000 --- a/baseboard/trogdor/baseboard.h +++ /dev/null @@ -1,216 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Trogdor baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -/* - * By default, enable all console messages excepted event and HC: - * The sensor stack is generating a lot of activity. - * They can be enabled through the console command 'chan'. - */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) - -/* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - -/* Internal SPI flash on NPCX7 */ -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - -/* EC Modules */ -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_VIRTUAL_BATTERY -#define CONFIG_I2C_PASSTHRU_RESTRICTED -#define CONFIG_LED_COMMON -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_ADC -#define CONFIG_BACKLIGHT_LID -#define CONFIG_FPU -#define CONFIG_PWM -#define CONFIG_PWM_DISPLIGHT - -#define CONFIG_VBOOT_HASH - -#undef CONFIG_PECI - -#define CONFIG_HOSTCMD_SHI -#define CONFIG_HOST_COMMAND_STATUS -#define CONFIG_HOSTCMD_SECTION_SORTED -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_MKBP_USE_GPIO - -#define CONFIG_BOARD_VERSION_GPIO -#define CONFIG_POWER_BUTTON -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_EMULATED_SYSRQ -#define CONFIG_CMD_BUTTON -#define CONFIG_SWITCH -#define CONFIG_LID_SWITCH -#define CONFIG_EXTPOWER_GPIO - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Increase console output buffer since we have the RAM available. */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -/* Battery */ -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL -#define CONFIG_BATTERY_SMART - -/* Charger */ -#define CONFIG_CHARGER -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER_ISL9238 -#define CONFIG_CHARGER_PROFILE_OVERRIDE -#define CONFIG_CHARGE_RAMP_HW -#define CONFIG_USB_CHARGER -#define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_PSYS -#define CONFIG_CHARGER_PSYS_READ -#define CONFIG_CHARGER_DISCHARGE_ON_AC - -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - -/* - * USB ID - * - * This is allocated specifically for Trogdor - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x5043 - -/* USB */ -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_DECODE_SOP -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_CMD_TCPC_DUMP -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC -#define CONFIG_USB_PD_5V_EN_CUSTOM -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* RTC */ -#define CONFIG_CMD_RTC -#define CONFIG_HOSTCMD_RTC - -/* Sensors */ -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is a power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs. */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#define CONFIG_CMD_ACCELS -#define CONFIG_CMD_ACCEL_INFO - -/* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ - -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -/* Chipset */ -#define CONFIG_CHIPSET_SC7180 -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CHIPSET_RESUME_INIT_HOOK -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_PP5000_CONTROL -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_CMD_AP_RESET_LOG - -/* - * Macros for GPIO signals used in common code that don't match the - * schematic names. Signal names in gpio.inc match the schematic and are - * then redefined here to so it's more clear which signal is being used for - * which purpose. - */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV - -/* I2C Ports */ -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - -/* UART */ -#define CONFIG_CMD_CHARGEN - -/* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) - -/* And the MKBP events */ -#ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) -#else -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) -#endif - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/trogdor/build.mk b/baseboard/trogdor/build.mk deleted file mode 100644 index 0f36051eee..0000000000 --- a/baseboard/trogdor/build.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y+=baseboard.o -baseboard-y+=hibernate.o -baseboard-y+=power.o -baseboard-y+=usbc_config.o -baseboard-y+=usb_pd_policy.o diff --git a/baseboard/trogdor/hibernate.c b/baseboard/trogdor/hibernate.c deleted file mode 100644 index c28082e75d..0000000000 --- a/baseboard/trogdor/hibernate.c +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "gpio.h" -#include "system.h" - -void board_hibernate_late(void) -{ - /* Set the hibernate GPIO to turn off the rails */ - gpio_set_level(GPIO_HIBERNATE_L, 0); -} diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c deleted file mode 100644 index b539539c98..0000000000 --- a/baseboard/trogdor/power.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "gpio.h" -#include "hooks.h" -#include "power.h" -#include "task.h" - -void board_chipset_pre_init(void) -{ - /* Turn on the 3.3V rail */ - gpio_set_level(GPIO_EN_PP3300_A, 1); - - /* Turn on the 5V rail. */ -#ifdef CONFIG_POWER_PP5000_CONTROL - power_5v_enable(task_get_current(), 1); -#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */ - gpio_set_level(GPIO_EN_PP5000, 1); -#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */ -} -DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT); - -void board_chipset_shutdown_complete(void) -{ - /* Turn off the 5V rail. */ -#ifdef CONFIG_POWER_PP5000_CONTROL - power_5v_enable(task_get_current(), 0); -#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */ - gpio_set_level(GPIO_EN_PP5000, 0); -#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */ - - /* Turn off the 3.3V and 5V rails. */ - gpio_set_level(GPIO_EN_PP3300_A, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete, - HOOK_PRIO_DEFAULT); diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c deleted file mode 100644 index d7ed03e941..0000000000 --- a/baseboard/trogdor/usb_pd_policy.c +++ /dev/null @@ -1,262 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charge_manager.h" -#include "chipset.h" -#include "console.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* In G3, do not allow vconn swap since PP5000 rail is off */ - return gpio_get_level(GPIO_EN_PP5000); -} - -static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -#if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; -#else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; -#endif - -static void board_vbus_update_source_current(int port) -{ - /* Both port are controlled by PPC SN5S330. */ - ppc_set_vbus_source_current_limit(port, vbus_rp[port]); - ppc_vbus_source_enable(port, vbus_en[port]); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = vbus_en[port]; - - /* Disable VBUS */ - vbus_en[port] = 0; - board_vbus_update_source_current(port); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - /* Disable charging */ - board_vbus_sink_enable(port, 0); - - pd_set_vbus_discharge(port, 0); - - /* Provide VBUS */ - vbus_en[port] = 1; - board_vbus_update_source_current(port); - - /* notify host of power info change */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; /* we are ready */ -} - -int board_vbus_source_enabled(int port) -{ - return vbus_en[port]; -} - -__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) -{ - vbus_rp[port] = rp; - board_vbus_update_source_current(port); -} - -int pd_snk_is_vbus_provided(int port) -{ - return tcpm_check_vbus_level(port, VBUS_PRESENT); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -#ifdef CONFIG_USB_PD_ALT_MODE_DFP -__override int svdm_dp_config(int port, uint32_t *payload) -{ - int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); - uint8_t pin_mode = get_dp_pin_mode(port); - - if (!pin_mode) - return 0; - - /* - * Defer setting the usb_mux until HPD goes high, svdm_dp_attention(). - * The AP only supports one DP phy. An external DP mux switches between - * the two ports. Should switch those muxes when it is really used, - * i.e. HPD high; otherwise, the real use case is preempted, like: - * (1) plug a dongle without monitor connected to port-0, - * (2) plug a dongle without monitor connected to port-1, - * (3) plug a monitor to the port-1 dongle. - */ - - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ - return 2; -}; - -__override void svdm_dp_post_config(int port) -{ - dp_flags[port] |= DP_FLAGS_DP_ON; -} - -/** - * Is the port fine to be muxed its DisplayPort lines? - * - * Only one port can be muxed to DisplayPort at a time. - * - * @param port Port number of TCPC. - * @return 1 is fine; 0 is bad as other port is already muxed; - */ -static int is_dp_muxable(int port) -{ - int i; - - for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) - if (i != port) { - if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) - return 0; - } - - return 1; -} - -__override int svdm_dp_attention(int port, uint32_t *payload) -{ - enum gpio_signal hpd = GPIO_DP_HOT_PLUG_DET; - int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); - int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); - int cur_lvl = gpio_get_level(hpd); - mux_state_t mux_state; - - dp_status[port] = payload[1]; - - if (!is_dp_muxable(port)) { - /* TODO(waihong): Info user? */ - CPRINTS("p%d: The other port is already muxed.", port); - return 0; - } - - /* - * Initial implementation to handle HPD. Only the first-plugged port - * works, i.e. sending HPD signal to AP. The second-plugged port - * will be ignored. - * - * TODO(waihong): Continue the above case, if the first-plugged port - * is then unplugged, switch to the second-plugged port and signal AP? - */ - if (lvl) { - /* - * Enable and switch the DP port selection mux to the - * correct port. - * - * TODO(waihong): Better to move switching DP mux to - * the usb_mux abstraction. - */ - gpio_set_level(GPIO_DP_MUX_SEL, port == 1); - gpio_set_level(GPIO_DP_MUX_OE_L, 0); - - /* Connect the SBU lines in PPC chip. */ - if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) - ppc_set_sbu(port, 1); - - /* - * Connect the USB SS/DP lines in TCPC chip. - * - * When mf_pref not true, still use the dock muxing - * because of the board USB-C topology (limited to 2 - * lanes DP). - */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - } else { - /* Disconnect the DP port selection mux. */ - gpio_set_level(GPIO_DP_MUX_OE_L, 1); - gpio_set_level(GPIO_DP_MUX_SEL, 0); - - /* Disconnect the SBU lines in PPC chip. */ - if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) - ppc_set_sbu(port, 0); - - /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); - } - - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) - /* - * Wake up the AP. IRQ or level high indicates a DP sink is now - * present. - */ - pd_notify_dp_alt_mode_entry(port); - - /* Configure TCPC for the HPD event, for proper muxing */ - mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); - usb_mux_hpd_update(port, mux_state); - - /* Signal AP for the HPD event, through GPIO to AP */ - if (irq & cur_lvl) { - uint64_t now = get_time().val; - /* Wait for the minimum spacing between IRQ_HPD if needed */ - if (now < svdm_hpd_deadline[port]) - usleep(svdm_hpd_deadline[port] - now); - - /* Generate IRQ_HPD pulse */ - gpio_set_level(hpd, 0); - usleep(HPD_DSTREAM_DEBOUNCE_IRQ); - gpio_set_level(hpd, 1); - - /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } else if (irq & !lvl) { - CPRINTF("ERR:HPD:IRQ&LOW\n"); - return 0; - } else { - gpio_set_level(hpd, lvl); - /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; - } - - return 1; -} - -__override void svdm_exit_dp_mode(int port) -{ - if (is_dp_muxable(port)) { - /* Disconnect the DP port selection mux. */ - gpio_set_level(GPIO_DP_MUX_OE_L, 1); - gpio_set_level(GPIO_DP_MUX_SEL, 0); - - /* Signal AP for the HPD low event */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); - } -} -#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/baseboard/trogdor/usbc_config.c b/baseboard/trogdor/usbc_config.c deleted file mode 100644 index 8f3fb02c30..0000000000 --- a/baseboard/trogdor/usbc_config.c +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Trogdor family-specific USB-C configuration */ - -#include "charger.h" -#include "charger/isl923x_public.h" -#include "charge_state.h" -#include "usb_pd.h" - -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - }, -}; - -int charger_profile_override(struct charge_state_data *curr) -{ - int usb_mv; - int port; - - if (curr->state != ST_CHARGE) - return 0; - - /* Lower the max requested voltage to 5V when battery is full. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && - !(curr->batt.flags & BATT_FLAG_BAD_STATUS) && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) - usb_mv = 5000; - else - usb_mv = PD_MAX_VOLTAGE_MV; - - if (pd_get_max_voltage() != usb_mv) { - CPRINTS("VBUS limited to %dmV", usb_mv); - for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) - pd_set_external_voltage_limit(port, usb_mv); - } - - return 0; -} - -enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) -{ - return EC_RES_INVALID_PARAM; -} - -enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) -{ - return EC_RES_INVALID_PARAM; -} diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c deleted file mode 100644 index 6b3ad33a35..0000000000 --- a/baseboard/volteer/baseboard.c +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer family-specific configuration */ -#include "adc.h" -#include "button.h" -#include "cbi_ec_fw_config.h" -#include "charger.h" -#include "charge_ramp.h" -#include "cros_board_info.h" -#include "driver/charger/isl9241.h" -#include "driver/tcpm/ps8xxx.h" -#include "driver/temp_sensor/thermistor.h" -#include "gpio.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "system.h" -#include "task.h" -#include "temp_sensor.h" -#ifdef CONFIG_ZEPHYR -#include "usbc_config.h" -#endif - -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) - -/******************************************************************************/ -/* ADC configuration */ -const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1_CHARGER] = { - .name = "TEMP_CHARGER", - .input_ch = NPCX_ADC_CH0, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, - [ADC_TEMP_SENSOR_2_PP3300_REGULATOR] = { - .name = "TEMP_PP3300_REGULATOR", - .input_ch = NPCX_ADC_CH1, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, - [ADC_TEMP_SENSOR_3_DDR_SOC] = { - .name = "TEMP_DDR_SOC", - .input_ch = NPCX_ADC_CH8, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, - [ADC_TEMP_SENSOR_4_FAN] = { - .name = "TEMP_FAN", - .input_ch = NPCX_ADC_CH3, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -/******************************************************************************/ -/* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_ACOK_OD, - GPIO_POWER_BUTTON_L, - GPIO_EC_RST_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/******************************************************************************/ -/* Temperature sensor configuration */ -const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CHARGER}, - [TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR}, - [TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_DDR_SOC}, - [TEMP_SENSOR_4_FAN] = {.name = "Fan", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_FAN}, -}; -BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h deleted file mode 100644 index 38a464813a..0000000000 --- a/baseboard/volteer/baseboard.h +++ /dev/null @@ -1,285 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#include <stdbool.h> - -/* - * By default, enable all console messages excepted HC - */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) - -/* NPCX7 config */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -/* Internal SPI flash on NPCX796FC is 512 kB */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - -/* Allow objects to be linked into a flash resident section */ -#define CONFIG_CHIP_INIT_ROM_REGION - -/* EC Defines */ -#define CONFIG_LTO -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CRC8 -#define CONFIG_CBI_EEPROM -#define CONFIG_DPTF -#define CONFIG_FPU -#define CONFIG_HIBERNATE_PSL -#define CONFIG_PWM -#define CONFIG_VBOOT_HASH -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 -#define CONFIG_VOLUME_BUTTONS -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -/* Host communication */ -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 - -/* Chipset config */ -#define CONFIG_CHIPSET_TIGERLAKE -#define CONFIG_CHIPSET_PP3300_RAIL_FIRST -#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE -#define CONFIG_CHIPSET_X86_RSMRST_DELAY -#define CONFIG_CHIPSET_RESET_HOOK -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_S0IX -#define CONFIG_POWER_SLEEP_FAILURE_DETECTION -#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_BOARD_HAS_RTC_RESET - -/* Common Keyboard Defines */ -#define CONFIG_CMD_KEYBOARD - -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_KEYPAD -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#define CONFIG_PWM_KBLIGHT - -/* Sensors */ -#define CONFIG_TABLET_MODE -#define CONFIG_GMR_TABLET_MODE - -#define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_USE_GPIO -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_INTERRUPTS - -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is in power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - -/* Sensor console commands */ -#define CONFIG_CMD_ACCELS -#define CONFIG_CMD_ACCEL_INFO - -/* Thermal features */ -#define CONFIG_FANS FAN_CH_COUNT -#define CONFIG_TEMP_SENSOR -#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PG_EC_DSW_PWROK -#define CONFIG_THERMISTOR -#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_THROTTLE_AP -#define CONFIG_CHIPSET_CAN_THROTTLE - -/* Common charger defines */ -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 - -/* - * Hardware based charge ramp is broken in the ISL9241 (b/169350714). - */ -#define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_ISL9241 -/* Setting ISL9241 Register Control1 switching frequency to 724kHz. */ -#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ - -#define CONFIG_USB_CHARGER -#define CONFIG_BC12_DETECT_PI3USB9201 - -/* - * Don't allow the system to boot to S0 when the battery is low and unable to - * communicate on locked systems (which haven't PD negotiated) - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 - -/* Common battery defines */ -#define CONFIG_BATTERY_SMART -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_PRESENT_CUSTOM -#define CONFIG_BATTERY_HW_PRESENT_CUSTOM -#define CONFIG_BATTERY_REVIVE_DISCONNECT - -/* Common LED defines */ -#define CONFIG_LED_COMMON - -/* EDP back-light control defines */ -#define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN - -/* USB Type C and USB PD defines */ -/* Enable the new USB-C PD stack */ -#define CONFIG_USB_PD_TCPMV2 -#define CONFIG_USB_DRP_ACC_TRYSRC -#define CONFIG_USB_PD_REV30 - -/* - * TODO(b/158572770): TCPMv2: Conserve flash space - * Add these console commands as flash space permits. - */ -#undef CONFIG_CMD_HCDEBUG -#undef CONFIG_CMD_ACCELS -#undef CONFIG_CMD_ACCEL_INFO -#undef CONFIG_CMD_ACCELSPOOF -#undef CONFIG_CMD_PPC_DUMP - -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_ALT_MODE_UFP -#define CONFIG_USB_PD_DISCHARGE_PPC -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TCPM_RT1715 -#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ -#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ -#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ -#define CONFIG_CMD_USB_PD_PE - -/* - * Because of the CSE Lite, an extra cold AP reset is needed, and older cr50 - * firmware will not be able to detect it because of updated cr50 pin straps. - * Therefore, the AP will require the EC to reset it so that the proper reset - * signal will be read and verstage can execute again. - */ -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_HOSTCMD_AP_RESET - -/* - * The PS8815 TCPC was found to require a 50ms delay to consistently work - * with non-PD chargers. Override the default low-power mode exit delay. - */ -#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) - -/* Enable USB3.2 DRD */ -#define CONFIG_USB_PD_USB32_DRD - -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC - -#define CONFIG_USB_MUX_RUNTIME_CONFIG - -#define CONFIG_USBC_PPC -/* Note - SN5S330 support automatically adds - * CONFIG_USBC_PPC_POLARITY - * CONFIG_USBC_PPC_SBU - * CONFIG_USBC_PPC_VCONN - */ -#define CONFIG_USBC_PPC_DEDICATED_INT - -#define CONFIG_USBC_SS_MUX -#define CONFIG_USB_MUX_VIRTUAL - -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP - -/* Enabling SOP* communication */ -#define CONFIG_CMD_USB_PD_CABLE -#define CONFIG_USB_PD_DECODE_SOP - -/* UART COMMAND */ -#define CONFIG_CMD_CHARGEN - -/* - * USB ID - * This is allocated specifically for Volteer - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x503E -/* Device version of product. */ -#define CONFIG_USB_BCD_DEV 0x0000 - -/* Retimer */ -#define CONFIG_USBC_RETIMER_INTEL_BB -#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG -#define CONFIG_USBC_RETIMER_FW_UPDATE - -/* Enable volume button command in EC console */ -#define CONFIG_CMD_BUTTON - -/* Enable volume button in ectool */ -#define CONFIG_HOSTCMD_BUTTON - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "common.h" -#include "baseboard_usbc_config.h" -#include "cbi.h" - -enum adc_channel { - ADC_TEMP_SENSOR_1_CHARGER, - ADC_TEMP_SENSOR_2_PP3300_REGULATOR, - ADC_TEMP_SENSOR_3_DDR_SOC, - ADC_TEMP_SENSOR_4_FAN, - ADC_CH_COUNT -}; - -enum fan_channel { - FAN_CH_0 = 0, - /* Number of FAN channels */ - FAN_CH_COUNT, -}; - -enum mft_channel { - MFT_CH_0 = 0, - /* Number of MFT channels */ - MFT_CH_COUNT, -}; - -enum temp_sensor_id { - TEMP_SENSOR_1_CHARGER, - TEMP_SENSOR_2_PP3300_REGULATOR, - TEMP_SENSOR_3_DDR_SOC, - TEMP_SENSOR_4_FAN, - TEMP_SENSOR_COUNT -}; - -/* - * Check battery disconnect state. - * This function will return if battery is initialized or not. - * @return true - initialized. false - not. - */ -__override_proto bool board_battery_is_initialized(void); - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/volteer/baseboard_usbc_config.h b/baseboard/volteer/baseboard_usbc_config.h deleted file mode 100644 index bf02b1cb34..0000000000 --- a/baseboard/volteer/baseboard_usbc_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* volteer family-specific USB-C configuration */ - -#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H -#define __CROS_EC_BASEBOARD_USBC_CONFIG_H - -#include "gpio_signal.h" - -/* Common definition for the USB PD interrupt handlers. */ -void ppc_interrupt(enum gpio_signal signal); -void tcpc_alert_event(enum gpio_signal signal); -void bc12_interrupt(enum gpio_signal signal); - -#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */ diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c deleted file mode 100644 index 4953d7a49e..0000000000 --- a/baseboard/volteer/battery_presence.c +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Common battery presence checking for Volteer family. - * Each board should implement board_battery_info[] to define the specific - * battery packs supported. - */ -#include <stdbool.h> - -#include "battery.h" -#include "battery_smart.h" -#include "gpio.h" - -static enum battery_present batt_pres_prev = BP_NOT_SURE; - -enum battery_present battery_hw_present(void) -{ - /* The GPIO is low when the battery is physically present */ - return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES; -} - -static bool battery_init(void) -{ - int batt_status; - - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); -} - -__overridable bool board_battery_is_initialized(void) -{ - /* - * Set default to return true - */ - return true; -} - -/* - * Physical detection of battery. - */ -static enum battery_present battery_check_present_status(void) -{ - enum battery_present batt_pres; - bool batt_initialization_state; - - /* Get the physical hardware status */ - batt_pres = battery_hw_present(); - - /* - * If the battery is not physically connected, then no need to perform - * any more checks. - */ - if (batt_pres != BP_YES) - return batt_pres; - - /* - * If the battery is present now and was present last time we checked, - * return early. - */ - if (batt_pres == batt_pres_prev) - return batt_pres; - - /* - * Check battery initialization. If the battery is not initialized, - * then return BP_NOT_SURE. Battery could be in ship - * mode and might require pre-charge current to wake it up. BP_NO is not - * returned here because charger state machine will not provide - * pre-charge current assuming that battery is not present. - */ - batt_initialization_state = board_battery_is_initialized(); - if (!batt_initialization_state) - return BP_NOT_SURE; - /* - * Ensure that battery is: - * 1. Not in cutoff - * 2. Initialized - */ - if (battery_is_cut_off() || !battery_init()) - batt_pres = BP_NO; - - return batt_pres; -} - -enum battery_present battery_is_present(void) -{ - batt_pres_prev = battery_check_present_status(); - return batt_pres_prev; -} diff --git a/baseboard/volteer/build.mk b/baseboard/volteer/build.mk deleted file mode 100644 index 08b68c5816..0000000000 --- a/baseboard/volteer/build.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Volteer baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-y+=battery_presence.o -baseboard-y+=charger.o -baseboard-y+=usb_pd_policy.o -baseboard-y+=cbi.o -baseboard-y+=cbi_ec_fw_config.o -baseboard-y+=cbi_ssfc.o -baseboard-y+=power.o -baseboard-y+=usbc_config.o diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c deleted file mode 100644 index ea446acc4e..0000000000 --- a/baseboard/volteer/cbi.c +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer family-specific functions, shared with Zephyr */ - -#include "cbi_ec_fw_config.h" -#include "common.h" -#include "cros_board_info.h" -#include "hooks.h" -#include "system.h" - -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) - -static uint8_t board_id; - -uint8_t get_board_id(void) -{ - return board_id; -} - -__overridable void board_cbi_init(void) -{ -} - -/* - * Read CBI from i2c eeprom and initialize variables for board variants - * - * Example for configuring for a USB3 DB: - * ectool cbi set 6 2 4 10 - */ -static void cbi_init(void) -{ - uint32_t cbi_val; - - /* Board ID */ - if (cbi_get_board_version(&cbi_val) != EC_SUCCESS || - cbi_val > UINT8_MAX) - CPRINTS("CBI: Read Board ID failed"); - else - board_id = cbi_val; - - CPRINTS("Board ID: %d", board_id); - - /* FW config */ - init_fw_config(); - - /* Allow the board project to make runtime changes based on CBI data */ - board_cbi_init(); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_FIRST); diff --git a/baseboard/volteer/cbi.h b/baseboard/volteer/cbi.h deleted file mode 100644 index 049c0f65e2..0000000000 --- a/baseboard/volteer/cbi.h +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer family-specific CBI functions, shared with Zephyr */ - -#ifndef __CROS_EC_BASEBOARD_CBI_H -#define __CROS_EC_BASEBOARD_CBI_H - -unsigned char get_board_id(void); - -/** - * Configure run-time data structures and operation based on CBI data. This - * typically includes customization for changes in the BOARD_VERSION and - * FW_CONFIG fields in CBI. This routine is called from the baseboard after - * the CBI data has been initialized. - */ -__override_proto void board_cbi_init(void); - -#endif /* __CROS_EC_BASEBOARD_CBI_H */ diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c deleted file mode 100644 index e602691aeb..0000000000 --- a/baseboard/volteer/cbi_ec_fw_config.c +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "cbi_ec_fw_config.h" -#include "cros_board_info.h" - -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) - -static union volteer_cbi_fw_config fw_config; -BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); - -/**************************************************************************** - * Volteer FW_CONFIG access - */ -void init_fw_config(void) -{ - if (cbi_get_fw_config(&fw_config.raw_value)) { - CPRINTS("CBI: Read FW_CONFIG failed, using board defaults"); - fw_config = fw_config_defaults; - } -} - -union volteer_cbi_fw_config get_fw_config(void) -{ - return fw_config; -} - -enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void) -{ - return fw_config.usb_db; -} - -bool ec_cfg_has_tabletmode(void) -{ - return (fw_config.tabletmode == TABLETMODE_ENABLED); -} - -bool ec_cfg_has_keyboard_backlight(void) -{ - return (fw_config.kb_bl == KEYBOARD_BACKLIGHT_ENABLED); -} - -bool ec_cfg_has_numeric_pad(void) -{ - return (fw_config.num_pad == NUMERIC_PAD_ENABLED); -} - -enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void) -{ - return fw_config.kb_layout; -} diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h deleted file mode 100644 index 0a44e1f9e4..0000000000 --- a/baseboard/volteer/cbi_ec_fw_config.h +++ /dev/null @@ -1,124 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __VOLTEER_CBI_EC_FW_CONFIG_H_ -#define __VOLTEER_CBI_EC_FW_CONFIG_H_ - -#include "stdbool.h" -#include "stdint.h" - -/**************************************************************************** - * CBI FW_CONFIG layout shared by all Volteer boards - * - * Source of truth is the program/volteer/program.star configuration file. - */ - -enum ec_cfg_usb_db_type { - DB_USB_ABSENT = 0, - DB_USB4_GEN2 = 1, - DB_USB3_ACTIVE = 2, - DB_USB4_GEN3 = 3, - DB_USB3_PASSIVE = 4, - DB_USB3_NO_A = 5, - DB_USB_COUNT -}; - -/* - * Tablet Mode (1 bit), shared by all Volteer boards - */ -enum ec_cfg_tabletmode_type { - TABLETMODE_DISABLED = 0, - TABLETMODE_ENABLED = 1, -}; - -enum ec_cfg_keyboard_backlight_type { - KEYBOARD_BACKLIGHT_DISABLED = 0, - KEYBOARD_BACKLIGHT_ENABLED = 1 -}; - -enum ec_cfg_numeric_pad_type { - NUMERIC_PAD_DISABLED = 0, - NUMERIC_PAD_ENABLED = 1 -}; - -enum ec_cfg_keyboard_layout { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1 -}; - -union volteer_cbi_fw_config { - struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t thermal : 4; - uint32_t audio : 3; - enum ec_cfg_tabletmode_type tabletmode : 1; - uint32_t lte_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - enum ec_cfg_numeric_pad_type num_pad : 1; - uint32_t sd_db : 4; - enum ec_cfg_keyboard_layout kb_layout : 2; - uint32_t reserved_2 : 10; - }; - uint32_t raw_value; -}; - -/* - * Each Volteer board must define the default FW_CONFIG options to use - * if the CBI data has not been initialized. - */ -extern union volteer_cbi_fw_config fw_config_defaults; - -/** - * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the - * FW_CONFIG to the board specific defaults. - */ -void init_fw_config(void); - -/** - * Read the cached FW_CONFIG. Guaranteed to have valid values. - * - * @return the FW_CONFIG for the board. - */ -union volteer_cbi_fw_config get_fw_config(void); - -/** - * Get the USB daughter board type from FW_CONFIG. - * - * @return the USB daughter board type. - */ -enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void); - -/** - * Check if the FW_CONFIG has enabled tablet mode operation. - * - * @return true if board supports tablet mode, false if the board supports - * clamshell operation only. - */ -bool ec_cfg_has_tabletmode(void); - -/** - * Check if the FW_CONFIG has enabled keyboard backlight. - * - * @return true if board supports keyboard backlight, false if the board - * doesn't support it. - */ -bool ec_cfg_has_keyboard_backlight(void); - -/** - * Check if the FW_CONFIG has enabled numeric pad. - * - * @return true if board supports numeric pad, false if the board - * doesn't support it. - */ -bool ec_cfg_has_numeric_pad(void); - -/** - * Get keyboard type from FW_CONFIG. - * - * @return the keyboard type. - */ -enum ec_cfg_keyboard_layout ec_cfg_keyboard_layout(void); - -#endif /* __VOLTEER_CBI_EC_FW_CONFIG_H_ */ diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c deleted file mode 100644 index 42b11c4a1c..0000000000 --- a/baseboard/volteer/cbi_ssfc.c +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_ssfc.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache SSFC on init since we don't expect it to change in runtime */ -static union volteer_cbi_ssfc cached_ssfc; -BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t)); - -static void cbi_ssfc_init(void) -{ - if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_ssfc.raw_value = 0; - - CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value); -} -DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); - -enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) -{ - return cached_ssfc.base_sensor; -} - -enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) -{ - return cached_ssfc.lid_sensor; -} - -enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void) -{ - return cached_ssfc.lightbar; -} diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h deleted file mode 100644 index 27db1d3809..0000000000 --- a/baseboard/volteer/cbi_ssfc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _VOLTEER_CBI_SSFC__H_ -#define _VOLTEER_CBI_SSFC__H_ - -#include "stdint.h" - -/**************************************************************************** - * Volteer CBI Second Source Factory Cache - */ - -/* - * Base Sensor (Bits 0-2) - */ -enum ec_ssfc_base_sensor { - SSFC_SENSOR_BASE_DEFAULT = 0, - SSFC_SENSOR_BASE_BMI160 = 1, - SSFC_SENSOR_BASE_ICM426XX = 2 -}; - -/* - * Lid Sensor (Bits 3-5) - */ -enum ec_ssfc_lid_sensor { - SSFC_SENSOR_LID_DEFAULT = 0, - SSFC_SENSOR_LID_BMA255 = 1, - SSFC_SENSOR_LID_KX022 = 2 -}; - -/* - * Lightbar (Bits 6-7) - */ -enum ec_ssfc_lightbar { - SSFC_LIGHTBAR_NONE = 0, - SSFC_LIGHTBAR_10_LED = 1, - SSFC_LIGHTBAR_12_LED = 2 -}; - -union volteer_cbi_ssfc { - struct { - enum ec_ssfc_base_sensor base_sensor : 3; - enum ec_ssfc_lid_sensor lid_sensor : 3; - enum ec_ssfc_lightbar lightbar : 2; - uint32_t reserved_2 : 24; - }; - uint32_t raw_value; -}; - -/** - * Get the Base sensor type from SSFC_CONFIG. - * - * @return the Base sensor board type. - */ -enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); - -/** - * Get the Lid sensor type from SSFC_CONFIG. - * - * @return the Lid sensor board type. - */ -enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - -/** - * Get lightbar type from SSFC_CONFIG. - * - * @return the lightbar type. - */ -enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void); - -#endif /* _Volteer_CBI_SSFC__H_ */ diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c deleted file mode 100644 index a674b98f41..0000000000 --- a/baseboard/volteer/charger.c +++ /dev/null @@ -1,104 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer family-specific configuration */ -#include "common.h" -#include "charger.h" -#include "charge_manager.h" -#include "charge_state.h" -#include "driver/charger/isl9241_public.h" -#include "gpio.h" -#ifdef CONFIG_ZEPHYR -#include "usbc_config.h" -#endif -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -/* Charger Chip Configuration */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL9241_ADDR_FLAGS, - .drv = &isl9241_drv, - }, -}; - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -void board_overcurrent_event(int port, int is_overcurrented) -{ - /* Note that the level is inverted because the pin is active low. */ - switch (port) { - case USBC_PORT_C0: - gpio_set_level(GPIO_USB_C0_OC_ODL, !is_overcurrented); - break; - case USBC_PORT_C1: - gpio_set_level(GPIO_USB_C1_OC_ODL, !is_overcurrented); - break; - } -} diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c deleted file mode 100644 index fa20cfa93f..0000000000 --- a/baseboard/volteer/power.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "gpio.h" -#include "hooks.h" -#include "power/icelake.h" - -/* - * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure - * 235) in the Tiger Lake Platform Design Guide for the list of potential - * signals. - * - * Volteer uses this power sequence: - * GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to - * the VCCST_PWRGD input to the AP so this signal must be delayed - * 5 ms to meet the tCPU00 timing requirement. - * GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed - * a total of 50 ms after ALL_SYS_PWRGD input is asserted. See - * b/144478941 for full discussion. - * - * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK - * signals. If your board adds these signals to the EC, copy this array - * to your board.c file and modify as needed. - */ -const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { - { - .gpio = GPIO_EN_PPVAR_VCCIN, - .delay_ms = 5, - }, - { - .gpio = GPIO_EC_PCH_SYS_PWROK, - .delay_ms = 50 - 5, - }, -}; -const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); - -const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { - /* No delays needed during S0 exit */ - { - .gpio = GPIO_EC_PCH_SYS_PWROK, - }, - /* Turn off VCCIN last */ - { - .gpio = GPIO_EN_PPVAR_VCCIN, - }, -}; -const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); - -static void baseboard_init(void) -{ - /* Enable monitoring of the PROCHOT input to the EC */ - gpio_enable_interrupt(GPIO_EC_PROCHOT_IN_L); -} -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT); diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c deleted file mode 100644 index f939998b3d..0000000000 --- a/baseboard/volteer/usb_pd_policy.c +++ /dev/null @@ -1,201 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Shared USB-C policy for Volteer boards */ -#include "charge_manager.h" -#include "chipset.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "usb_common.h" -#include "usb_mux.h" -#include "usbc_ppc.h" -#include "usb_pd.h" -#include "system.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* Only allow vconn swap if pp5000_A rail is enabled */ - return gpio_get_level(GPIO_EN_PP5000_A); -} - -void pd_power_supply_reset(int port) -{ - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC -int pd_snk_is_vbus_provided(int port) -{ - return ppc_is_vbus_present(port); -} -#endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */ - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} - -/* ----------------- Vendor Defined Messages ------------------ */ -/* Responses specifically for the enablement of TBT mode in the role of UFP */ - -#define OPOS_TBT 1 - -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT( - CONFIG_USB_PID, CONFIG_USB_BCD_DEV); - -/* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); - -static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) -{ - /* TODO(b/154962766): Get an XID */ - payload[VDO_I(CSTAT)] = VDO_CSTAT(0); - payload[VDO_I(PRODUCT)] = vdo_product; - - if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) { - /* PD Revision 3.0 */ - payload[VDO_I(IDH)] = vdo_idh_rev30; - payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1; - /* TODO(b/156749387): Find power number for USB3/4 */ - payload[VDO_I(PTYPE_UFP2_VDO)] = 0; - payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp; - return VDO_I(PTYPE_DFP_VDO) + 1; - } - - /* PD Revision 2.0 */ - payload[VDO_I(IDH)] = vdo_idh; - return VDO_I(PRODUCT) + 1; -} - -static int svdm_tbt_compat_response_svids(int port, uint32_t *payload) -{ - payload[1] = VDO_SVID(USB_VID_INTEL, 0); - return 2; -} - -static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) -{ - if (PD_VDO_VID(payload[0]) == USB_VID_INTEL) { - memcpy(payload + 1, vdo_tbt_modes, sizeof(vdo_tbt_modes)); - return ARRAY_SIZE(vdo_tbt_modes) + 1; - } else { - return 0; /* NAK */ - } -} - -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) -{ - mux_state_t mux_state = 0; - - /* Do not enter mode while CPU is off. */ - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) - return 0; /* NAK */ - - if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) - return 0; /* NAK */ - - mux_state = usb_mux_get(port); - /* - * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence - * UFP (responder) should be in USB mode or safe mode before sending - * Enter Mode Command response. - */ - if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { - pd_ufp_set_enter_mode(port, payload); - set_tbt_compat_mode_ready(port); - CPRINTS("UFP Enter TBT mode"); - return 1; /* ACK */ - } - - CPRINTS("UFP failed to enter TBT mode(mux=0x%x)", mux_state); - return 0; -} - -const struct svdm_response svdm_rsp = { - .identity = &svdm_tbt_compat_response_identity, - .svids = &svdm_tbt_compat_response_svids, - .modes = &svdm_tbt_compat_response_modes, - .enter_mode = &svdm_tbt_compat_response_enter_mode, - .amode = NULL, - .exit_mode = NULL, -}; diff --git a/baseboard/volteer/usbc_config.c b/baseboard/volteer/usbc_config.c deleted file mode 100644 index 1e483eae34..0000000000 --- a/baseboard/volteer/usbc_config.c +++ /dev/null @@ -1,77 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Volteer family-specific USB-C configuration */ - -#include "common.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state.h" -#include "gpio.h" -#include "task.h" -#ifdef CONFIG_ZEPHYR -#include "usbc_config.h" -#include "baseboard_usbc_config.h" -#endif -#include "usbc_ppc.h" -#include "usb_pd.h" -#include "usb_charge.h" -#include "util.h" -#include "driver/charger/isl9241_public.h" - -/******************************************************************************/ -void tcpc_alert_event(enum gpio_signal signal) -{ - /* TODO: b/140572591 - check correct operation for Volteer */ - - int port = -1; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = USBC_PORT_C0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = USBC_PORT_C1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/** - * Return if VBUS is too low - */ -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage; - - if (charger_get_vbus_voltage(port, &voltage)) - voltage = 0; - - /* - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input - * current until voltage drops to the minimum input voltage of the - * charger, 4.096V. - */ - return voltage < ISL9241_BC12_MIN_VOLTAGE; -} diff --git a/baseboard/zork/analyzestack.yaml b/baseboard/zork/analyzestack.yaml deleted file mode 100644 index 7ff5f39644..0000000000 --- a/baseboard/zork/analyzestack.yaml +++ /dev/null @@ -1,2 +0,0 @@ -remove: -- panic_assert_fail diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c deleted file mode 100644 index 0b48d1075b..0000000000 --- a/baseboard/zork/baseboard.c +++ /dev/null @@ -1,360 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Zork family-specific configuration */ - -#include "adc.h" -#include "button.h" -#include "cbi_ec_fw_config.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state.h" -#include "charge_state_v2.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "cros_board_info.h" -#include "driver/accelgyro_bmi_common.h" -#include "driver/charger/isl9241.h" -#include "driver/retimer/pi3hdx1204.h" -#include "driver/usb_mux/amd_fp5.h" -#include "ec_commands.h" -#include "extpower.h" -#include "gpio.h" -#include "hooks.h" -#include "ioexpander.h" -#include "i2c.h" -#include "keyboard_scan.h" -#include "lid_switch.h" -#include "motion_sense.h" -#include "power.h" -#include "power_button.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "switch.h" -#include "system.h" -#include "task.h" -#include "tcpm/tcpci.h" -#include "temp_sensor.h" -#include "temp_sensor/thermistor.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "util.h" - -#define SAFE_RESET_VBUS_MV 5000 - -/* - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current - * until voltage drops to 4.5V. Don't go lower than this to be kind to the - * charger (see b/67964166). - */ -#define BC12_MIN_VOLTAGE 4500 - -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, - GPIO_EC_RST_ODL, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -__overridable int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) -{ - int rv; - - /* Use the TCPC to set the current limit */ - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); - - return rv; -} - -static void baseboard_chipset_suspend(void) -{ - /* Disable display and keyboard backlights. */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1); - ioex_set_level(IOEX_KB_BL_EN, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, - HOOK_PRIO_DEFAULT); - -static void baseboard_chipset_resume(void) -{ - /* Enable display and keyboard backlights. */ - gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0); - ioex_set_level(IOEX_KB_BL_EN, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); - -__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) -{ - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); -} - -/* Keyboard scan setting */ -__override struct keyboard_scan_config keyscan_config = { - /* - * F3 key scan cycle completed but scan input is not - * charging to logic high when EC start scan next - * column for "T" key, so we set .output_settle_us - * to 80us - */ - .output_settle_us = 80, - .debounce_down_us = 6 * MSEC, - .debounce_up_us = 30 * MSEC, - .scan_period_us = 1500, - .min_post_scan_delay_us = 1000, - .poll_timeout_us = SECOND, - .actual_key_mask = { - 0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ - }, -}; - -/* - * We use 11 as the scaling factor so that the maximum mV value below (2761) - * can be compressed to fit in a uint8_t. - */ -#define THERMISTOR_SCALING_FACTOR 11 - -/* - * Values are calculated from the "Resistance VS. Temperature" table on the - * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. - */ -const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} -}; - -const struct thermistor_info thermistor_info = { - .scaling_factor = THERMISTOR_SCALING_FACTOR, - .num_pairs = ARRAY_SIZE(thermistor_data), - .data = thermistor_data, -}; - -__override void lid_angle_peripheral_enable(int enable) -{ - if (ec_config_has_lid_angle_tablet_mode()) { - int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON); - - if (enable) { - keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE); - } else { - /* - * Ensure that the chipset is off before disabling the - * keyboard. When the chipset is on, the EC keeps the - * keyboard enabled and the AP decides whether to - * ignore input devices or not. - */ - if (!chipset_in_s0) - keyboard_scan_enable(0, - KB_SCAN_DISABLE_LID_ANGLE); - } - } -} - -static void cbi_init(void) -{ - uint32_t val; - - if (cbi_get_board_version(&val) == EC_SUCCESS) - ccprints("Board Version: %d (0x%x)", val, val); - else - ccprints("Board Version: not set in cbi"); - - if (cbi_get_sku_id(&val) == EC_SUCCESS) - ccprints("SKU ID: %d (0x%x)", val, val); - else - ccprints("SKU ID: not set in cbi"); - - val = get_cbi_fw_config(); - if (val != UNINITIALIZED_FW_CONFIG) - ccprints("FW Config: %d (0x%x)", val, val); - else - ccprints("FW Config: not set in cbi"); -} -DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); - -/* - * Returns 1 for boards that are convertible into tablet mode, and zero for - * clamshells. - */ -int board_is_lid_angle_tablet_mode(void) -{ - return ec_config_has_lid_angle_tablet_mode(); -} - -__override uint32_t board_override_feature_flags0(uint32_t flags0) -{ - /* - * Remove keyboard backlight feature for devices that don't support it. - */ - if (ec_config_has_pwm_keyboard_backlight() == PWM_KEYBOARD_BACKLIGHT_NO) - return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); - else - return flags0; -} - -void board_hibernate(void) -{ - int port; - - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851, b/143778351, b/147007265) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) { - pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); - - /* Give PD task and PPC chip time to get to 5V */ - msleep(900); - } -} - -__overridable int check_hdmi_hpd_status(void) -{ - /* Default hdmi insert. */ - return 1; -} - -void sbu_fault_interrupt(enum ioex_signal signal) -{ - int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1; - - pd_handle_overcurrent(port); -} - -static void set_ac_prochot(void) -{ - isl9241_set_ac_prochot(CHARGER_SOLO, ZORK_AC_PROCHOT_CURRENT_MA); -} -DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); - -DECLARE_DEFERRED(board_print_temps); -int temps_interval; - -void board_print_temps(void) -{ - int t, i; - int rv; - - cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW); - for (i = 0; i < TEMP_SENSOR_COUNT; ++i) { - rv = temp_sensor_read(i, &t); - if (rv == EC_SUCCESS) - cprintf(CC_THERMAL, "%s=%dK (%dC) ", - temp_sensors[i].name, t, K_TO_C(t)); - } - cprintf(CC_THERMAL, "]\n"); - - if (temps_interval > 0) - hook_call_deferred(&board_print_temps_data, - temps_interval * SECOND); -} - -static int command_temps_log(int argc, char **argv) -{ - char *e = NULL; - - if (argc != 2) - return EC_ERROR_PARAM_COUNT; - - temps_interval = strtoi(argv[1], &e, 0); - if (*e) - return EC_ERROR_PARAM1; - - board_print_temps(); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, - "seconds", - "Print temp sensors periodically"); - -/* - * b/164921478: On G3->S5, wait for RSMRST_L to be deasserted before asserting - * PWRBTN_L. - */ -void board_pwrbtn_to_pch(int level) -{ - /* Add delay for G3 exit if asserting PWRBTN_L and S5_PGOOD is low. */ - if (!level && !gpio_get_level(GPIO_S5_PGOOD)) { - /* - * From measurement, wait 80 ms for RSMRST_L to rise after - * S5_PGOOD. - */ - msleep(80); - - if (!gpio_get_level(GPIO_S5_PGOOD)) - ccprints("Error: pwrbtn S5_PGOOD low"); - } - gpio_set_level(GPIO_PCH_PWRBTN_L, level); -} - -/** - * Return if VBUS is sagging too low - */ -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage = 0; - int rv; - - rv = charger_get_vbus_voltage(port, &voltage); - - if (rv) { - ccprints("%s rv=%d", __func__, rv); - return 0; - } - - /* - * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown - * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. - * This partly defeats the point of ramping, but will still catch - * VBUS below 4.5V and above 0V. - */ - if (voltage == 0) { - ccprints("%s vbus=0", __func__); - return 0; - } - - if (voltage < BC12_MIN_VOLTAGE) - ccprints("%s vbus=%d", __func__, voltage); - - return voltage < BC12_MIN_VOLTAGE; -} - -/** - * Always ramp up input current since AP needs higher power, even if battery is - * very low or full. We can always re-ramp if input current increases beyond - * what supplier can provide. - */ -__override int charge_is_consuming_full_input_current(void) -{ - return 1; -} diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h deleted file mode 100644 index d84ebbcef8..0000000000 --- a/baseboard/zork/baseboard.h +++ /dev/null @@ -1,368 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Zork baseboard configuration */ - -#ifndef __CROS_EC_BASEBOARD_H -#define __CROS_EC_BASEBOARD_H - -#if (defined(VARIANT_ZORK_TREMBYLE) \ - + defined(VARIANT_ZORK_DALBOZ)) != 1 -#error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ -#endif - -/* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - -/* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */ - -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) - -/* - * Enable 1 slot of secure temporary storage to support - * suspend/resume with read/write memory training. - */ -#define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT 1 - -#define CONFIG_ADC -#define CONFIG_BACKLIGHT_LID -#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW -#define CONFIG_CMD_AP_RESET_LOG -#define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define CONFIG_HIBERNATE_PSL -#define CONFIG_HOSTCMD_ESPI -#define CONFIG_I2C -#define CONFIG_I2C_CONTROLLER -#define CONFIG_I2C_UPDATE_IF_CHANGED -#define CONFIG_LOW_POWER_IDLE -#define CONFIG_LTO -#define CONFIG_PWM -#define CONFIG_PWM_KBLIGHT -#define CONFIG_TEMP_SENSOR -#define CONFIG_THERMISTOR_NCP15WB -#define CONFIG_VBOOT_EFS2 -#define CONFIG_VBOOT_HASH -#define CONFIG_VOLUME_BUTTONS - -/* CBI EEPROM for board version and SKU ID */ -#define CONFIG_CBI_EEPROM -#define CONFIG_BOARD_VERSION_CBI -#define CONFIG_CRC8 - -#define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_FUEL_GAUGE -#define CONFIG_BATTERY_REVIVE_DISCONNECT -#define CONFIG_BATTERY_SMART -/* - * Enable support for battery hostcmd, supporting longer strings. - * - * Vilboz battery options' model names vary in the 8th character, which is - * truncated in the memory mapped battery info; differentiating them requires - * support for EC_CMD_BATTERY_GET_STATIC version 1. - */ -#define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 -#define CONFIG_HOSTCMD_BATTERY_V2 - -#define CONFIG_BC12_DETECT_PI3USB9201 - -#define CONFIG_CHARGER -#define CONFIG_CHARGE_MANAGER -#define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_ISL9241 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 -/* - * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging - * but that feature of ISL9241 is broken (b/160287056) so we have to use - * CONFIG_CHARGE_RAMP_SW instead. - */ -#define CONFIG_CHARGE_RAMP_SW - -#define CONFIG_CHIPSET_STONEY -#define CONFIG_CHIPSET_CAN_THROTTLE -#define CONFIG_CHIPSET_RESET_HOOK - -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 -#define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 -#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM -#define CONFIG_THROTTLE_AP - -#ifdef VARIANT_ZORK_TREMBYLE - #define CONFIG_FANS FAN_CH_COUNT - #undef CONFIG_FAN_INIT_SPEED - #define CONFIG_FAN_INIT_SPEED 50 -#endif - -#define CONFIG_LED_COMMON -#define CONFIG_CMD_LEDTEST -#define CONFIG_LED_ONOFF_STATES - -/* - * On power-on, H1 releases the EC from reset but then quickly asserts and - * releases the reset a second time. This means the EC sees 2 resets: - * (1) power-on reset, (2) reset-pin reset. This config will - * allow the second reset to be treated as a power-on. - */ -#define CONFIG_BOARD_RESET_AFTER_POWER_ON - -#define CONFIG_IO_EXPANDER -#define CONFIG_IO_EXPANDER_NCT38XX - - -#define CONFIG_KEYBOARD_COL2_INVERTED -#define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_KEYBOARD_VIVALDI - -/* - * USB ID - * - * This is allocated specifically for Zork - * http://google3/hardware/standards/usb/ - */ -#define CONFIG_USB_PID 0x5040 - -#define CONFIG_USB_PD_REV30 - -/* Enable the TCPMv2 PD stack */ -#define CONFIG_USB_PD_TCPMV2 - -#ifndef CONFIG_USB_PD_TCPMV2 - #define CONFIG_USB_PD_TCPMV1 -#else - #define CONFIG_USB_PD_DECODE_SOP - #define CONFIG_USB_DRP_ACC_TRYSRC - - /* Enable TCPMv2 Fast Role Swap */ - /* Turn off until FRSwap is working */ - #undef CONFIG_USB_PD_FRS_TCPC -#endif - -#define CONFIG_HOSTCMD_PD_CONTROL -#define CONFIG_CMD_TCPC_DUMP -#define CONFIG_USB_CHARGER -#define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PD_ALT_MODE -#define CONFIG_USB_PD_ALT_MODE_DFP -#define CONFIG_USB_PD_COMM_LOCKED -#define CONFIG_USB_PD_DISCHARGE_TCPC -#define CONFIG_USB_PD_DP_HPD_GPIO -#ifdef VARIANT_ZORK_TREMBYLE -/* - * Use a custom HPD function that supports HPD on IO expander. - * TODO(b/165622386) remove this when HPD is on EC GPIO. - */ -# define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM -#endif -#define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE -#define CONFIG_USB_PD_LOGGING -#define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_USB_PD_TCPM_NCT38XX -#define CONFIG_USB_PD_TCPM_TCPCI -#define CONFIG_USB_PD_TRY_SRC -#define CONFIG_USB_PD_VBUS_DETECT_TCPC -#define CONFIG_USBC_PPC -#define CONFIG_USBC_PPC_SBU -#define CONFIG_USBC_PPC_AOZ1380 -#define CONFIG_USBC_RETIMER_PI3HDX1204 -#define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY -#define CONFIG_USBC_VCONN -#define CONFIG_USBC_VCONN_SWAP -#define CONFIG_USB_MUX_AMD_FP5 - -#if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_USB_PD_PORT_MAX_COUNT 2 - #define CONFIG_USBC_PPC_NX20P3483 - #define CONFIG_USBC_RETIMER_PS8802 - #define CONFIG_USBC_RETIMER_PS8818 - #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT - #define CONFIG_USB_MUX_RUNTIME_CONFIG - /* USB-A config */ - #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L - #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L - /* PS8818 RX Input Termination - default value */ - #define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM -#elif defined(VARIANT_ZORK_DALBOZ) - #define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT -#endif - -/* USB-A config */ -#define USB_PORT_COUNT USBA_PORT_COUNT -#define CONFIG_USB_PORT_POWER_SMART -#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY -#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP -#define CONFIG_USB_PORT_POWER_SMART_INVERTED - -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ - -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 - -/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define ZORK_AC_PROCHOT_CURRENT_MA 3328 - -/* - * EC will boot AP to depthcharge if: (BAT >= 4%) || (AC >= 50W) - * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on - * Depthcharge to boot OS. - */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 - -/* Increase length of history buffer for port80 messages. */ -#undef CONFIG_PORT80_HISTORY_LEN -#define CONFIG_PORT80_HISTORY_LEN 256 - -/* Increase console output buffer since we have the RAM available. */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 4096 - -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 -#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_EEPROM I2C_PORT_SENSOR -#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 - -#if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_CHARGER_RUNTIME_CONFIG - #define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 - #define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 -#elif defined(VARIANT_ZORK_DALBOZ) - #define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 -#endif - -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -#define CONFIG_MKBP_EVENT -/* Host event is required to wake from sleep */ -#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT -/* Required to enable runtime configuration */ -#define CONFIG_MKBP_EVENT_WAKEUP_MASK (BIT(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED)) - -/* Sensors */ -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT - -/* Thermal */ -#define CONFIG_TEMP_SENSOR_SB_TSI - -#ifdef HAS_TASK_MOTIONSENSE -/* Enable sensor fifo, must also define the _SIZE and _THRES */ -#define CONFIG_ACCEL_FIFO -/* FIFO size is a power of 2. */ -#define CONFIG_ACCEL_FIFO_SIZE 256 -/* Depends on how fast the AP boots and typical ODRs. */ -#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#endif - -/* Audio */ -#define CONFIG_AUDIO_CODEC -#define CONFIG_AUDIO_CODEC_DMIC -#define CONFIG_AUDIO_CODEC_I2S_RX - -/* CLI COMMAND */ -#define CONFIG_CMD_CHARGEN - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" -#include "math_util.h" -#include "registers.h" - -enum power_signal { - X86_SLP_S3_N, - X86_SLP_S5_N, - X86_S0_PGOOD, - X86_S5_PGOOD, - POWER_SIGNAL_COUNT -}; - -enum fan_channel { - FAN_CH_0 = 0, - /* Number of FAN channels */ - FAN_CH_COUNT, -}; - -#ifdef VARIANT_ZORK_TREMBYLE -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; -#endif - -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT, -}; - -/* - * Matrix to rotate accelerators into the standard reference frame. The default - * is the identity which is correct for the reference design. Variations of - * Zork may need to change it for manufacturability. - * For the lid: - * +x to the right - * +y up - * +z out of the page - * - * The principle axes of the body are aligned with the lid when the lid is in - * the 180 degree position (open, flat). - * - * Boards within the Zork family may need to modify this definition at - * board_init() time. - */ -extern mat33_fp_t zork_base_standard_ref; - -extern const struct thermistor_info thermistor_info; - -/* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) - -void mst_hpd_interrupt(enum ioex_signal signal); -void sbu_fault_interrupt(enum ioex_signal signal); - -#ifdef VARIANT_ZORK_TREMBYLE -void board_reset_pd_mcu(void); - -/* Common definition for the USB PD interrupt handlers. */ -void tcpc_alert_event(enum gpio_signal signal); -void bc12_interrupt(enum gpio_signal signal); -__override_proto void ppc_interrupt(enum gpio_signal signal); -#endif - -void board_print_temps(void); - -/* GPIO or IOEX signal used to set IN_HPD on DB retimer. */ -extern int board_usbc1_retimer_inhpd; - -#endif /* !__ASSEMBLER__ */ - -#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk deleted file mode 100644 index e79d60cc91..0000000000 --- a/baseboard/zork/build.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Baseboard specific files build -# - -baseboard-y=baseboard.o -baseboard-y+=cbi_ec_fw_config.o -baseboard-y+=cbi_ssfc.o -baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o -baseboard-$(VARIANT_ZORK_TREMBYLE)+=variant_trembyle.o -baseboard-$(VARIANT_ZORK_DALBOZ)+=variant_dalboz.o diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c deleted file mode 100644 index cbb0821c42..0000000000 --- a/baseboard/zork/cbi_ec_fw_config.c +++ /dev/null @@ -1,98 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "cbi_ec_fw_config.h" -#include "cros_board_info.h" - -/**************************************************************************** - * CBI Zork EC FW Configuration - */ -uint32_t get_cbi_fw_config(void) -{ - static uint32_t cached_fw_config = UNINITIALIZED_FW_CONFIG; - - if (cached_fw_config == UNINITIALIZED_FW_CONFIG) { - uint32_t val; - - if (cbi_get_fw_config(&val) == EC_SUCCESS) - cached_fw_config = val; - } - return cached_fw_config; -} - -/* - * get_cbi_ec_cfg_usb_db() will return the DB option number. - */ -enum ec_cfg_usb_db_type ec_config_get_usb_db(void) -{ - return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) - >> EC_CFG_USB_DB_L); -} - -/* - * get_cbi_ec_cfg_usb_mb() will return the MB option number. - */ -enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void) -{ - return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) - >> EC_CFG_USB_MB_L); -} - -/* - * ec_config_has_lid_accel_sensor() will return ec_cfg_lid_accel_sensor_type - */ -enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void) -{ - return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) - >> EC_CFG_LID_ACCEL_SENSOR_L); -} - -/* - * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type - */ -enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void) -{ - return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) - >> EC_CFG_BASE_GYRO_SENSOR_L); -} - -/* - * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0 - */ -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void) -{ - return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) - >> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L); -} - -/* - * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0 - */ -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void) -{ - return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) - >> EC_CFG_LID_ANGLE_TABLET_MODE_L); -} - -/* - * ec_config_lte_present() will return 1 if present else 0. - */ -enum ec_cfg_lte_present_type ec_config_lte_present(void) -{ - return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) - >> EC_CFG_LTE_PRESENT_L); -} - -/* - * ec_config_keyboard_layout() will return keyboard layout type. - */ -enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void) -{ - return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) - >> EC_CFG_KEYBOARD_LAYOUT_L); -} diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h deleted file mode 100644 index 4888298e3a..0000000000 --- a/baseboard/zork/cbi_ec_fw_config.h +++ /dev/null @@ -1,144 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _ZORK_CBI_EC_FW_CONFIG__H_ -#define _ZORK_CBI_EC_FW_CONFIG__H_ - -/**************************************************************************** - * CBI Zork EC FW Configuration - */ -#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF - -/* - * USB Daughter Board (4 bits) - * - * get_cbi_ec_cfg_usb_db() will return the DB option number. - * The option number will be defined in a variant or board level enumeration - */ -#define EC_CFG_USB_DB_L 0 -#define EC_CFG_USB_DB_H 3 -#define EC_CFG_USB_DB_MASK \ - GENMASK(EC_CFG_USB_DB_H,\ - EC_CFG_USB_DB_L) - -/* - * USB Main Board (4 bits) - * - * get_cbi_ec_cfg_usb_mb() will return the MB option number. - * The option number will be defined in a variant or board level enumeration - */ -#define EC_CFG_USB_MB_L 4 -#define EC_CFG_USB_MB_H 7 -#define EC_CFG_USB_MB_MASK \ - GENMASK(EC_CFG_USB_MB_H,\ - EC_CFG_USB_MB_L) - -/* - * Lid Accelerometer Sensor (3 bits) - * - * ec_config_has_lid_accel_sensor() will return ec_cfg_lid_accel_sensor_type - */ -enum ec_cfg_lid_accel_sensor_type { - LID_ACCEL_NONE = 0, - LID_ACCEL_KX022 = 1, - LID_ACCEL_LIS2DWL = 2, -}; -#define EC_CFG_LID_ACCEL_SENSOR_L 8 -#define EC_CFG_LID_ACCEL_SENSOR_H 10 -#define EC_CFG_LID_ACCEL_SENSOR_MASK \ - GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\ - EC_CFG_LID_ACCEL_SENSOR_L) - -/* - * Base Gyro Sensor (3 bits) - * - * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type - */ -enum ec_cfg_base_gyro_sensor_type { - BASE_GYRO_NONE = 0, - BASE_GYRO_BMI160 = 1, - BASE_GYRO_LSM6DSM = 2, - BASE_GYRO_ICM426XX = 3, -}; -#define EC_CFG_BASE_GYRO_SENSOR_L 11 -#define EC_CFG_BASE_GYRO_SENSOR_H 13 -#define EC_CFG_BASE_GYRO_SENSOR_MASK \ - GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\ - EC_CFG_BASE_GYRO_SENSOR_L) - -/* - * PWM Keyboard Backlight (1 bit) - * - * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0 - */ -enum ec_cfg_pwm_keyboard_backlight_type { - PWM_KEYBOARD_BACKLIGHT_NO = 0, - PWM_KEYBOARD_BACKLIGHT_YES = 1, -}; -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \ - GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\ - EC_CFG_PWM_KEYBOARD_BACKLIGHT_L) - -/* - * Lid Angle Tablet Mode (1 bit) - * - * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0 - */ -enum ec_cfg_lid_angle_tablet_mode_type { - LID_ANGLE_TABLET_MODE_NO = 0, - LID_ANGLE_TABLET_MODE_YES = 1, -}; -#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15 -#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15 -#define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \ - GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\ - EC_CFG_LID_ANGLE_TABLET_MODE_L) - -/* - * LTE Modem Present (1 bit) - * - * ec_config_lte_present() will return 1 if present else 0. - */ -enum ec_cfg_lte_present_type { - LTE_NONE = 0, - LTE_PRESENT = 1, -}; -#define EC_CFG_LTE_PRESENT_L 29 -#define EC_CFG_LTE_PRESENT_H 29 -#define EC_CFG_LTE_PRESENT_MASK \ - GENMASK(EC_CFG_LTE_PRESENT_H,\ - EC_CFG_LTE_PRESENT_L) - -/* - * Keyboard Layout (2 bit) - * - * ec_config_keyboard_layout() will return keyboard layout type. - */ -enum ec_cfg_keyboard_layout_type { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1, -}; -#define EC_CFG_KEYBOARD_LAYOUT_L 30 -#define EC_CFG_KEYBOARD_LAYOUT_H 31 -#define EC_CFG_KEYBOARD_LAYOUT_MASK \ - GENMASK(EC_CFG_KEYBOARD_LAYOUT_H,\ - EC_CFG_KEYBOARD_LAYOUT_L) - - -uint32_t get_cbi_fw_config(void); -enum ec_cfg_usb_db_type ec_config_get_usb_db(void); -enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void); -enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void); -enum ec_cfg_base_gyro_sensor_type ec_config_has_base_gyro_sensor(void); -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void); -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void); -enum ec_cfg_lte_present_type ec_config_lte_present(void); -enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void); - -#endif /* _ZORK_CBI_EC_FW_CONFIG__H_ */ diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c deleted file mode 100644 index 1078ec6486..0000000000 --- a/baseboard/zork/cbi_ssfc.c +++ /dev/null @@ -1,48 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "cbi_ssfc.h" -#include "common.h" -#include "console.h" -#include "cros_board_info.h" -#include "hooks.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/* Cache SSFC on init since we don't expect it to change in runtime */ -static uint32_t cached_ssfc; - -static void cbi_ssfc_init(void) -{ - if (cbi_get_ssfc(&cached_ssfc) != EC_SUCCESS) - /* Default to 0 when CBI isn't populated */ - cached_ssfc = 0; - - CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc); -} -DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); - -enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void) -{ - return (cached_ssfc & SSFC_BASE_GYRO_MASK) >> SSFC_BASE_GYRO_OFFSET; -} - -enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void) -{ - return (cached_ssfc & SSFC_SPKR_AUTO_MODE_MASK) >> - SSFC_SPKR_AUTO_MODE_OFFSET; -} - -enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void) -{ - return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >> - SSFC_EDP_PHY_ALT_TUNING_OFFSET; -} - -enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void) -{ - return (cached_ssfc & SSFC_C1_MUX_MASK) >> - SSFC_C1_MUX_OFFSET; -} diff --git a/baseboard/zork/cbi_ssfc.h b/baseboard/zork/cbi_ssfc.h deleted file mode 100644 index c51d612a06..0000000000 --- a/baseboard/zork/cbi_ssfc.h +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef _ZORK_CBI_SSFC__H_ -#define _ZORK_CBI_SSFC__H_ - -#include "stdint.h" - -/**************************************************************************** - * Zork CBI Second Source Factory Cache - */ - -/* - * Base Sensor (Bits 0-2) - */ -enum ec_ssfc_base_gyro_sensor { - SSFC_BASE_GYRO_NONE = 0, - SSFC_BASE_GYRO_BMI160 = 1, - SSFC_BASE_GYRO_LSM6DSM = 2, - SSFC_BASE_GYRO_ICM426XX = 3, -}; -#define SSFC_BASE_GYRO_OFFSET 0 -#define SSFC_BASE_GYRO_MASK GENMASK(2, 0) - -enum ec_ssfc_spkr_auto_mode { - SSFC_SPKR_AUTO_MODE_OFF = 0, - SSFC_SPKR_AUTO_MODE_ON = 1, -}; -#define SSFC_SPKR_AUTO_MODE_OFFSET 3 -#define SSFC_SPKR_AUTO_MODE_MASK GENMASK(3, 3) - -/* - * eDP PHY Alternate Tuning (Bits 4-5) - */ -enum ec_ssfc_edp_phy_alt_tuning { - SSFC_EDP_PHY_ALT_TUNING_0 = 0, - SSFC_EDP_PHY_ALT_TUNING_1 = 1, - SSFC_EDP_PHY_ALT_TUNING_2 = 2, - SSFC_EDP_PHY_ALT_TUNING_3 = 3, -}; -#define SSFC_EDP_PHY_ALT_TUNING_OFFSET 4 -#define SSFC_EDP_PHY_ALT_TUNING_MASK GENMASK(5, 4) - -/* - * TypeC port 1 secondary MUX (Bits 6-7) - */ -enum ec_ssfc_c1_mux { - SSFC_C1_MUX_NONE = 0, - SSFC_C1_MUX_TUSB544 = 1, - SSFC_C1_MUX_PS8818 = 2, -}; -#define SSFC_C1_MUX_OFFSET 6 -#define SSFC_C1_MUX_MASK GENMASK(7, 6) - -/** - * Get the Base sensor type from SSFC_CONFIG. - * - * @return the Base sensor board type. - */ -enum ec_ssfc_base_gyro_sensor get_cbi_ssfc_base_sensor(void); - -/** - * Get whether speaker amp auto mode is enabled from SSFC. - */ -enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void); - -/** - * Get the eDP PHY alternate tuning from SSFC. - */ -enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void); - -/** - * Get the C1 usb mux from SSFC. - */ -enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void); - -#endif /* _ZORK_CBI_SSFC__H_ */ diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c deleted file mode 100644 index 8dcdfa7635..0000000000 --- a/baseboard/zork/usb_pd_policy.c +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Shared USB-C policy for Zork boards */ - -#include "charge_manager.h" -#include "chipset.h" -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "system.h" -#include "usb_mux.h" -#include "usb_pd.h" -#include "usbc_ppc.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -int pd_check_vconn_swap(int port) -{ - /* in G3, do not allow vconn swap since 5V rail is off */ - return gpio_get_level(GPIO_S5_PGOOD); -} - -void pd_power_supply_reset(int port) -{ - /* Don't need to shutoff VBus if we are not sourcing it */ - if (ppc_is_sourcing_vbus(port)) { - /* Disable VBUS. */ - ppc_vbus_source_enable(port, 0); - - /* Enable discharge if we were previously sourcing 5V */ - if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) - pd_set_vbus_discharge(port, 1); - } - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); -} - -int pd_set_power_supply_ready(int port) -{ - int rv; - - /* Disable charging. */ - rv = ppc_vbus_sink_enable(port, 0); - if (rv) - return rv; - - if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) - pd_set_vbus_discharge(port, 0); - - /* Provide Vbus. */ - rv = ppc_vbus_source_enable(port, 1); - if (rv) - return rv; - - /* Notify host of power info change. */ - pd_send_host_event(PD_EVENT_POWER_CHANGE); - - return EC_SUCCESS; -} - -int board_vbus_source_enabled(int port) -{ - return ppc_is_sourcing_vbus(port); -} diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c deleted file mode 100644 index 10058bb8bc..0000000000 --- a/baseboard/zork/variant_dalboz.c +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "charger.h" -#include "chipset.h" -#include "common.h" -#include "driver/charger/isl9241.h" -#include "driver/temp_sensor/sb_tsi.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "power.h" -#include "temp_sensor.h" -#include "temp_sensor/thermistor.h" - -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S3_N] = { - .gpio = GPIO_PCH_SLP_S3_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S3_DEASSERTED", - }, - [X86_SLP_S5_N] = { - .gpio = GPIO_PCH_SLP_S5_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S5_DEASSERTED", - }, - [X86_S0_PGOOD] = { - .gpio = GPIO_S0_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S0_PGOOD", - }, - [X86_S5_PGOOD] = { - .gpio = GPIO_S5_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S5_PGOOD", - }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -int board_get_temp(int idx, int *temp_k) -{ - int mv; - int temp_c; - enum adc_channel channel; - - /* idx is the sensor index set in board temp_sensors[] */ - switch (idx) { - case TEMP_SENSOR_CHARGER: - channel = ADC_TEMP_SENSOR_CHARGER; - break; - case TEMP_SENSOR_SOC: - /* thermistor is not powered in G3 */ - if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return EC_ERROR_NOT_POWERED; - - /* adc power not ready when transition to S5 */ - if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_SOFT_OFF)) - return EC_ERROR_NOT_POWERED; - - channel = ADC_TEMP_SENSOR_SOC; - break; - default: - return EC_ERROR_INVAL; - } - - mv = adc_read_channel(channel); - if (mv < 0) - return EC_ERROR_INVAL; - - temp_c = thermistor_linear_interpolate(mv, &thermistor_info); - *temp_k = C_TO_K(temp_c); - return EC_SUCCESS; -} - -const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_CHARGER] = { - .name = "CHARGER", - .input_ch = NPCX_ADC_CH2, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, - [ADC_TEMP_SENSOR_SOC] = { - .name = "SOC", - .input_ch = NPCX_ADC_CH3, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - -const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = board_get_temp, - .idx = TEMP_SENSOR_CHARGER, - }, - [TEMP_SENSOR_SOC] = { - .name = "SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = board_get_temp, - .idx = TEMP_SENSOR_SOC, - }, - [TEMP_SENSOR_CPU] = { - .name = "CPU", - .type = TEMP_SENSOR_TYPE_CPU, - .read = sb_tsi_get_val, - .idx = 0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - -__overridable struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = { - [TEMP_SENSOR_CHARGER] = { - .temp_host = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(90), - [EC_TEMP_THRESH_HALT] = C_TO_K(92), - }, - .temp_host_release = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), - } - }, - [TEMP_SENSOR_SOC] = { - .temp_host = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(90), - [EC_TEMP_THRESH_HALT] = C_TO_K(92), - }, - .temp_host_release = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), - } - }, - [TEMP_SENSOR_CPU] = { - .temp_host = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(90), - [EC_TEMP_THRESH_HALT] = C_TO_K(92), - }, - .temp_host_release = { - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), - } - }, -}; -BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); - -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A0_C0_SCL, - .sda = GPIO_EC_I2C_USB_A0_C0_SDA, - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A1_C1_SCL, - .sda = GPIO_EC_I2C_USB_A1_C1_SDA, - }, - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA, - }, - { - .name = "ap_mux", - .port = I2C_PORT_USB_AP_MUX, - .kbps = 400, - .scl = GPIO_EC_I2C_USBC_AP_MUX_SCL, - .sda = GPIO_EC_I2C_USBC_AP_MUX_SDA, - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_FCH_SIC, - .sda = GPIO_FCH_SID, - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_CBI_SCL, - .sda = GPIO_EC_I2C_SENSOR_CBI_SDA, - }, - { - .name = "ap_audio", - .port = I2C_PORT_AP_AUDIO, - .kbps = 400, - .scl = GPIO_I2C_AUDIO_USB_HUB_SCL, - .sda = GPIO_I2C_AUDIO_USB_HUB_SDA, - }, - { - .name = "battery", - .port = I2C_PORT_BATTERY_V1, - .kbps = 100, - .scl = GPIO_EC_I2C_BATT_SCL, - .sda = GPIO_EC_I2C_BATT_SDA, - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/***************************************************************************** - * Charger - */ - -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER, - .i2c_addr_flags = ISL9241_ADDR_FLAGS, - .drv = &isl9241_drv, - }, -}; diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c deleted file mode 100644 index b39380db59..0000000000 --- a/baseboard/zork/variant_trembyle.c +++ /dev/null @@ -1,550 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "charger.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/retimer/ps8802.h" -#include "driver/retimer/ps8818.h" -#include "driver/retimer/tusb544.h" -#include "driver/tcpm/nct38xx.h" -#include "driver/usb_mux/amd_fp5.h" -#include "fan.h" -#include "fan_chip.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "ioexpander.h" -#include "task.h" -#include "timer.h" -#include "usb_mux.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) - -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A0_C0_SCL, - .sda = GPIO_EC_I2C_USB_A0_C0_SDA, - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_A1_C1_SCL, - .sda = GPIO_EC_I2C_USB_A1_C1_SDA, - }, - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATT_SCL, - .sda = GPIO_EC_I2C_BATT_SDA, - }, - { - .name = "ap_mux", - .port = I2C_PORT_USB_AP_MUX, - .kbps = 400, - .scl = GPIO_EC_I2C_USBC_AP_MUX_SCL, - .sda = GPIO_EC_I2C_USBC_AP_MUX_SDA, - }, - { - .name = "therm_chg", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_FCH_SIC_POWER_SCL, - .sda = GPIO_FCH_SID_POWER_SDA, - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_CBI_SCL, - .sda = GPIO_EC_I2C_SENSOR_CBI_SDA, - }, - { - .name = "ap_audio", - .port = I2C_PORT_AP_AUDIO, - .kbps = 400, - .scl = GPIO_FCH_I2C_AUDIO_SCL, - .sda = GPIO_FCH_I2C_AUDIO_SDA, - }, - { - .name = "ap_hdmi", - .port = I2C_PORT_AP_HDMI, - .kbps = 400, - .scl = GPIO_FCH_I2C_HDMI_HUB_3V3_SCL, - .sda = GPIO_FCH_I2C_HDMI_HUB_3V3_SDA, - }, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/***************************************************************************** - * Charger - */ - -struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_CHARGER_V1, - .i2c_addr_flags = ISL9241_ADDR_FLAGS, - .drv = &isl9241_drv, - }, -}; - -/***************************************************************************** - * TCPC - */ - -void baseboard_tcpc_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_PPC_FAULT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); - - /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); - - /* Enable BC 1.2 interrupts */ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); - - /* Enable SBU fault interrupts */ - ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL); - ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_DB_ODL); -} -DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1); - -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -__overridable void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_FAULT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - - /* Check if the port is sourcing VBUS. */ - if (ppc_is_sourcing_vbus(port)) { - CPRINTFUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -void board_overcurrent_event(int port, int is_overcurrented) -{ - switch (port) { - case USBC_PORT_C0: - ioex_set_level(IOEX_USB_C0_FAULT_ODL, !is_overcurrented); - break; - - case USBC_PORT_C1: - ioex_set_level(IOEX_USB_C1_FAULT_ODL, !is_overcurrented); - break; - - default: - break; - } -} - -const struct tcpc_config_t tcpc_config[] = { - [USBC_PORT_C0] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC0, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, - [USBC_PORT_C1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_TCPC1, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); -BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); - -const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { - [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); - -static void reset_nct38xx_port(int port) -{ - enum gpio_signal reset_gpio_l; - - if (port == USBC_PORT_C0) - reset_gpio_l = GPIO_USB_C0_TCPC_RST_L; - else if (port == USBC_PORT_C1) - reset_gpio_l = GPIO_USB_C1_TCPC_RST_L; - else - /* Invalid port: do nothing */ - return; - - gpio_set_level(reset_gpio_l, 0); - msleep(NCT38XX_RESET_HOLD_DELAY_MS); - gpio_set_level(reset_gpio_l, 1); - nct38xx_reset_notify(port); - if (NCT3807_RESET_POST_DELAY_MS != 0) - msleep(NCT3807_RESET_POST_DELAY_MS); -} - - -void board_reset_pd_mcu(void) -{ - /* Reset TCPC0 */ - reset_nct38xx_port(USBC_PORT_C0); - - /* Reset TCPC1 */ - reset_nct38xx_port(USBC_PORT_C1); -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0) - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) { - if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port = -1; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - - -int board_pd_set_frs_enable(int port, int enable) -{ - int rv = EC_SUCCESS; - - /* Use the TCPC to enable fast switch when FRS included */ - if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); - } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); - } - - return rv; -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/***************************************************************************** - * IO expander - */ - -struct ioexpander_config_t ioex_config[] = { - [USBC_PORT_C0] = { - .i2c_host_port = I2C_PORT_TCPC0, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - }, - [USBC_PORT_C1] = { - .i2c_host_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT); -BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT); - -/***************************************************************************** - * Custom Zork USB-C1 Retimer/MUX driver - */ - -/* - * PS8802 set mux board tuning. - * Adds in board specific gain and DP lane count configuration - */ -static int board_ps8802_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - int rv = EC_SUCCESS; - - /* Make sure the PS8802 is awake */ - rv = ps8802_i2c_wake(me); - if (rv) - return rv; - - /* USB specific config */ - if (mux_state & USB_PD_MUX_USB_ENABLED) { - /* Boost the USB gain */ - rv = ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_19DB); - if (rv) - return rv; - } - - /* DP specific config */ - if (mux_state & USB_PD_MUX_DP_ENABLED) { - /* Boost the DP gain */ - rv = ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_19DB); - if (rv) - return rv; - } - - return rv; -} - -/* - * PS8818 set mux board tuning. - * Adds in board specific gain and DP lane count configuration - */ -static int board_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - int rv = EC_SUCCESS; - - /* USB specific config */ - if (mux_state & USB_PD_MUX_USB_ENABLED) { - /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); - if (rv) - return rv; - - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); - if (rv) - return rv; - - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); - if (rv) - return rv; - - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); - if (rv) - return rv; - - /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - ZORK_PS8818_RX_INPUT_TERM); - if (rv) - return rv; - } - - /* DP specific config */ - if (mux_state & USB_PD_MUX_DP_ENABLED) { - /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); - if (rv) - return rv; - - /* Enable IN_HPD on the DB */ - gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 1); - } else { - /* Disable IN_HPD on the DB */ - gpio_or_ioex_set_level(board_usbc1_retimer_inhpd, 0); - } - - return rv; -} - -const struct usb_mux usbc1_ps8802 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8802_I2C_ADDR_FLAGS, - .driver = &ps8802_usb_mux_driver, - .board_set = &board_ps8802_mux_set, -}; -const struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_ps8818_mux_set, -}; -struct usb_mux usbc1_amd_fp5_usb_mux = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_AP_MUX, - .i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS, - .driver = &amd_fp5_usb_mux_driver, -}; - -/* - * USB-C1 HPD may go through an IO expander, so we must use a custom HPD GPIO - * control function with CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM. - * - * TODO(b/165622386) revert to non-custom GPIO control when HPD is no longer on - * the IO expander in any variants. - */ -void svdm_set_hpd_gpio(int port, int en) -{ - gpio_or_ioex_set_level(PORT_TO_HPD(port), en); -} - -int svdm_get_hpd_gpio(int port) -{ - int out; - - if (gpio_or_ioex_get_level(PORT_TO_HPD(port), &out) != EC_SUCCESS) { - ccprints("Failed to read current HPD for port C%d", port); - return 0; - } - return out; -} |