diff options
Diffstat (limited to 'board/cr50/scratch_reg1.h')
| -rw-r--r-- | board/cr50/scratch_reg1.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h index f4388ece18..6fdfe12181 100644 --- a/board/cr50/scratch_reg1.h +++ b/board/cr50/scratch_reg1.h @@ -11,8 +11,8 @@ * Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives * all kinds of resets, it is cleared only on the Power ON event. */ -#define BOARD_SLAVE_CONFIG_SPI (1 << 0) /* TPM uses SPI interface */ -#define BOARD_SLAVE_CONFIG_I2C (1 << 1) /* TPM uses I2C interface */ +#define BOARD_SLAVE_CONFIG_SPI BIT(0) /* TPM uses SPI interface */ +#define BOARD_SLAVE_CONFIG_I2C BIT(1) /* TPM uses I2C interface */ /* * The gaps are left to ensure backwards compatibility with the earliest cr50 @@ -21,20 +21,20 @@ */ /* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */ -#define BOARD_NEEDS_SYS_RST_PULL_UP (1 << 5) /* Add a pullup to sys_rst_l */ -#define BOARD_USE_PLT_RESET (1 << 6) /* Use plt_rst_l instead of */ +#define BOARD_NEEDS_SYS_RST_PULL_UP BIT(5) /* Add a pullup to sys_rst_l */ +#define BOARD_USE_PLT_RESET BIT(6) /* Use plt_rst_l instead of */ /* sys_rst_l to monitor the */ /* system resets */ /* Bits to store write protect bit state across deep sleep and resets. */ -#define BOARD_WP_ASSERTED (1 << 8) -#define BOARD_FORCING_WP (1 << 9) +#define BOARD_WP_ASSERTED BIT(8) +#define BOARD_FORCING_WP BIT(9) /* * Bit to signal to compatible RO to suppress its uart output. * Helps to reduce time to resume from deep sleep. */ -#define BOARD_NO_RO_UART (1 << 10) +#define BOARD_NO_RO_UART BIT(10) /* * Bits to store current case-closed debug state across deep sleep. @@ -46,18 +46,18 @@ #define BOARD_CCD_STATE (3 << BOARD_CCD_SHIFT) /* Prevent Cr50 from entering deep sleep when the AP is off */ -#define BOARD_DEEP_SLEEP_DISABLED (1 << 13) +#define BOARD_DEEP_SLEEP_DISABLED BIT(13) /* Use Cr50_RX_AP_TX to determine if the AP is off or on */ -#define BOARD_DETECT_AP_WITH_UART (1 << 14) +#define BOARD_DETECT_AP_WITH_UART BIT(14) /* ITE EC sync sequence generation after reset is required. */ -#define BOARD_ITE_EC_SYNC_NEEDED (1 << 15) +#define BOARD_ITE_EC_SYNC_NEEDED BIT(15) /* * Enable delayed write protect disable for systems that can be opened * in less than 2 minutes */ -#define BOARD_WP_DISABLE_DELAY (1 << 16) +#define BOARD_WP_DISABLE_DELAY BIT(16) /* * Enable custom options required for the closed source EC on the * Sarien/Arcada boards. Includes the following behavior @@ -67,18 +67,18 @@ * EC extended reset * Power+Refresh recovery mode (instead of Power+Refresh+Esc) */ -#define BOARD_CLOSED_SOURCE_SET1 (1 << 17) +#define BOARD_CLOSED_SOURCE_SET1 BIT(17) /* * Wait until PLT_RST_L is asserted before deasserting reset. */ -#define BOARD_CLOSED_LOOP_RESET (1 << 18) +#define BOARD_CLOSED_LOOP_RESET BIT(18) /* * The board uses INA pins as GPIOs, so it can't support reading inas using usb * i2c. */ -#define BOARD_NO_INA_SUPPORT (1 << 19) +#define BOARD_NO_INA_SUPPORT BIT(19) /* * Macro to capture all properties related to board strapping pins. This must be |