5 files changed, 144 insertions, 0 deletions
diff --git a/board/dragonegg/board.c b/board/dragonegg/board.c
new file mode 100644
index 0000000000..11bbb7b78e
--- /dev/null
+++ b/board/dragonegg/board.c
@@ -0,0 +1,34 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* DragonEgg board-specific configuration */
+
+#include "common.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "intc.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "uart.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+/******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* SPI devices */
+/* TODO(b/110880394): Fill out correctly (SPI FLASH) */
+const struct spi_device_t spi_devices[] = {
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/dragonegg/board.h b/board/dragonegg/board.h
new file mode 100644
index 0000000000..5c207d0fb0
--- /dev/null
+++ b/board/dragonegg/board.h
@@ -0,0 +1,40 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* DragonEgg board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Optional features */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_LOW_POWER_IDLE
+
+#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOSTCMD_ESPI_VW_SIGNALS
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+enum adc_channel {
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/dragonegg/build.mk b/board/dragonegg/build.mk
new file mode 100644
index 0000000000..a210ca235a
--- /dev/null
+++ b/board/dragonegg/build.mk
@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+BASEBOARD:=dragonegg
+
+board-y=board.o
diff --git a/board/dragonegg/ec.tasklist b/board/dragonegg/ec.tasklist
new file mode 100644
index 0000000000..2075316904
--- /dev/null
+++ b/board/dragonegg/ec.tasklist
@@ -0,0 +1,28 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+
diff --git a/board/dragonegg/gpio.inc b/board/dragonegg/gpio.inc
new file mode 100644
index 0000000000..d730fe5beb
--- /dev/null
+++ b/board/dragonegg/gpio.inc
@@ -0,0 +1,30 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(LID_OPEN,	 PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(WP_L,		 PIN(F, 1), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
+GPIO_INT(POWER_BUTTON_L, PIN(E, 2), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
+#ifdef CONFIG_LOW_POWER_IDLE
+/* Used to wake up the EC from Deep Doze mode when writing to console */
+GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_SERVO_TX_EC_RX */
+#endif
+
+
+
+#ifdef CONFIG_HOSTCMD_ESPI
+/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
+GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
+#endif
+
+GPIO(SYS_RESET_L,	 PIN(D, 1), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
+GPIO(ENTERING_RW,	 PIN(G, 0), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
+GPIO(PCH_WAKE_L,	 PIN(D, 5), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
+GPIO(PCH_PWRBTN_L, 	 PIN(B, 6), GPIO_ODR_HIGH)	/* EC_PCH_PWR_BTN_ODL */