diff options
Diffstat (limited to 'board/honeybuns/usb_pd_config.h')
-rw-r--r-- | board/honeybuns/usb_pd_config.h | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/board/honeybuns/usb_pd_config.h b/board/honeybuns/usb_pd_config.h new file mode 100644 index 0000000000..e4e16dc5cd --- /dev/null +++ b/board/honeybuns/usb_pd_config.h @@ -0,0 +1,173 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +/* Port and task configuration */ +#define PD_PORT_COUNT 1 +#define PORT_TO_TASK_ID(port) TASK_ID_PD +#define TASK_ID_TO_PORT(id) 0 + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 17 +#define TIM_CLOCK_PD_RX_C0 1 + +#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 +#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 + +/* Timer channel */ +#define TIM_RX_CCR_C0 1 +#define TIM_TX_CCR_C0 1 + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_RX_CCR_REG(p) TIM_CCR_C0 + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX(p) TIM_REG_TX_C0 +#define TIM_REG_RX(p) TIM_REG_RX_C0 + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX is using SPI1 on PB4 */ +#define SPI_REGS(p) STM32_SPI1_REGS + +static inline void spi_enable_clock(int port) +{ + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; +} + +/* SPI1_TX no remap needed */ +#define DMAC_SPI_TX(p) STM32_DMAC_CH3 + +/* RX is using COMP1 triggering TIM1 CH1 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1 +#define CMP2OUTSEL 0 + +#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 +#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 +#define TIM_CCR_CS 1 +#define EXTI_COMP_MASK(p) (1 << 21) +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +#define DMAC_TIM_RX(p) STM32_DMAC_CH2 + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + /* 40 Mhz pin speed on TX_EN (PA15) */ + STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000; + /* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0; +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + /* Reset SPI1 */ + STM32_RCC_APB1RSTR |= (1 << 12); + STM32_RCC_APB1RSTR &= ~(1 << 12); +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + /* PB4 is SPI1_MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, 0); + + gpio_set_level(GPIO_PD_TX_EN, 1); +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + /* TX_DATA on PB4 is an output low GPIO to disable the FET */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4))) + | (1 << (2*4)); + /* + * Tri-state the low side after the high side + * to ensure we are not going above Vnc + */ + gpio_set_level(GPIO_PD_TX_EN, 0); +} + +/* we know the plug polarity, do the right configuration */ +static inline void pd_select_polarity(int port, int polarity) +{ + /* + * use the right comparator : CC1 -> PA1 (COMP1 INP) + * use VrefInt / 2 as INM (about 600mV) + */ + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) + | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} + + +static inline void pd_set_host_mode(int port, int enable) +{ + if (!enable) + gpio_set_level(GPIO_PPVAR_VBUS_EN, 0); +} + +static inline void pd_config_init(int port, uint8_t power_role) +{ + /* Initialize TX pins and put them in Hi-Z */ + pd_tx_init(); +} + +static inline int pd_adc_read(int port, int cc) +{ + /* only one CC line, assume other one is always low */ + return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0; +} + + +static inline void pd_set_vconn(int port, int polarity, int enable) +{ + +} + +static inline int pd_snk_is_vbus_provided(int port) +{ + return 0; +} + +/* Standard-current DFP : no-connect voltage is 1.55V */ +#define PD_SRC_VNC 1550 /* mV */ + +/* UFP-side : threshold for DFP connection detection */ +#define PD_SNK_VA 200 /* mV */ + +/* we are acting only as a source */ +#define PD_DEFAULT_STATE PD_STATE_SRC_DISCONNECTED + +/* delay necessary for the voltage transition on the power supply */ +/* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078) + * Need to measure these and adjust for honeybuns. + */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ + +/* Define typical operating power and max power */ +#define PD_OPERATING_POWER_MW 1000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +#endif /* __USB_PD_CONFIG_H */ |