diff options
Diffstat (limited to 'board/nocturne_fp/flash_fp_mcu')
| -rwxr-xr-x | board/nocturne_fp/flash_fp_mcu | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/board/nocturne_fp/flash_fp_mcu b/board/nocturne_fp/flash_fp_mcu new file mode 100755 index 0000000000..7f5a566c13 --- /dev/null +++ b/board/nocturne_fp/flash_fp_mcu @@ -0,0 +1,102 @@ +#!/bin/sh +# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Cannonlake PCH GPIOs +CNL_GPIOCHIP="gpiochip268" +# Kabylake PCH GPIOs +KBL_GPIOCHIP="gpiochip360" + +if [ -e "/sys/class/gpio/${CNL_GPIOCHIP}" ]; then + # Meowth configuration + + SPIDEV="/dev/spidev1.0" + # GSPI1 ACPI device for FP MCU + SPIID="spi-PRP0001:01" + # FPMCU RST_ODL is on GPP_A23 = 268 + 23 = 291 + GPIO_NRST=291 + # FPMCU BOOT0 is on GPP_A21 = 268 + 21 = 289 + GPIO_BOOT0=289 + # FP_PWR_EN is on GPP_A11 = 268 + 11 = 279 + GPIO_PWREN=279 +elif [ -e "/sys/class/gpio/${KBL_GPIOCHIP}" ]; then + # Nocturne configuration + + SPIDEV="/dev/spidev32765.0" + # GSPI1 ACPI device for FP MCU + SPIID="spi-PRP0001:02" + # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418 + GPIO_NRST=418 + # FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416 + GPIO_BOOT0=416 + # FP_PWR_EN is on GPP_A11 = 360 + 11 = 371 + GPIO_PWREN=371 +else + echo "Cannot find a known GPIO chip." + exit 1 +fi + +if [ ! -f "$1" ]; then + echo "Invalid image file: $1" + echo "Usage: $0 ec.bin" + exit 1 +fi + +if ectool gpioget EC_WP_L | grep -q '= 0'; then + echo "Please make sure WP is deasserted." + exit 1 +fi + +# Ensure the ACPI is not cutting power when unloading cros-ec-spi +echo ${GPIO_PWREN} > /sys/class/gpio/export +echo "out" > /sys/class/gpio/gpio${GPIO_PWREN}/direction +echo 1 > /sys/class/gpio/gpio${GPIO_PWREN}/value + +# Remove cros_fp if present +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/unbind + +# Configure the MCU Boot0 and NRST GPIOs +echo ${GPIO_BOOT0} > /sys/class/gpio/export +echo "out" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction +echo ${GPIO_NRST} > /sys/class/gpio/export +echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction + +# Reset sequence to enter bootloader mode +echo 1 > /sys/class/gpio/gpio${GPIO_BOOT0}/value +echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value +sleep 0.001 + +# load spidev (fail on cros-ec-spi first to change modalias) +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind 2>/dev/null +echo "${SPIID}" > /sys/bus/spi/drivers/spidev/bind + +# Release reset as the SPI bus is now ready +echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value +echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction + +stm32mon -U -u -p -s ${SPIDEV} -e -w $1 + +# unload spidev +echo "${SPIID}" > /sys/bus/spi/drivers/spidev/unbind + +# Go back to normal mode +echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction +echo 0 > /sys/class/gpio/gpio${GPIO_BOOT0}/value +echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value +echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value + +# Give up GPIO control +echo "in" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction +echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction +echo ${GPIO_BOOT0} > /sys/class/gpio/unexport +echo ${GPIO_NRST} > /sys/class/gpio/unexport + +# wait for FP MCU to come back up (including RWSIG delay) +sleep 2 +# Put back cros_fp driver +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind +# Kernel driver is back, we are no longer controlling power +echo ${GPIO_PWREN} > /sys/class/gpio/unexport +# Test it +ectool --name=cros_fp version |