diff options
Diffstat (limited to 'board/phaser/gpio.inc')
| -rw-r--r-- | board/phaser/gpio.inc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index 3effe54d91..7205d1bf9d 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -118,7 +118,6 @@ GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ GPIO(EN_USB_A1_5V, PIN(9, 6), GPIO_OUT_LOW) /* Enable A1 5V Charging */ GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ -/* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ @@ -128,6 +127,10 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) + +/* Not implemented in hardware yet */ +UNIMPLEMENTED(USB_C0_PD_RST) + /* * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it |