diff options
Diffstat (limited to 'board/phaser')
-rw-r--r-- | board/phaser/battery.c | 66 | ||||
-rw-r--r-- | board/phaser/board.c | 59 | ||||
-rw-r--r-- | board/phaser/board.h | 47 | ||||
-rw-r--r-- | board/phaser/build.mk | 16 | ||||
-rw-r--r-- | board/phaser/ec.tasklist | 36 | ||||
-rw-r--r-- | board/phaser/gpio.inc | 135 | ||||
-rw-r--r-- | board/phaser/usb_pd_policy.c | 8 |
7 files changed, 367 insertions, 0 deletions
diff --git a/board/phaser/battery.c b/board/phaser/battery.c new file mode 100644 index 0000000000..6c87b18dfa --- /dev/null +++ b/board/phaser/battery.c @@ -0,0 +1,66 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "common.h" +#include "baseboard_battery.h" +#include "util.h" + +/* + * Battery info for all phaser battery types. Note that the fields + * start_charging_min/max and charging_min/max are not used for the charger. + * The effective temperature limits are given by discharging_min/max_c. + * + * Fuel Gauge (FG) parameters which are used for determining if the battery + * is connected, the appropriate ship mode (battery cutoff) command, and the + * charge/discharge FETs status. + * + * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery + * register. For some batteries, the charge/discharge FET bits are set when + * charging/discharging is active, in other types, these bits set mean that + * charging/discharging is disabled. Therefore, in addition to the mask for + * these bits, a disconnect value must be specified. Note that for TI fuel + * gauge, the charge/discharge FET status is found in Operation Status (0x54), + * but a read of Manufacturer Access (0x00) will return the lower 16 bits of + * Operation status which contains the FET status bits. + * + * The assumption for battery types supported is that the charge/discharge FET + * status can be read with a sb_read() command and therefore, only the register + * address, mask, and disconnect value need to be provided. + */ +const struct board_batt_params board_battery_info[] = { + /* TODO(b/78770233): Add real battery information from datasheets */ + /* Panasonic AP1505L Battery Information */ + [BATTERY_PANASONIC] = { + .fuel_gauge = { + .manuf_name = "PANASONIC", + .ship_mode = { + .reg_addr = 0x3A, + .reg_data = { 0xC574, 0xC574 }, + }, + .fet = { + .reg_addr = 0x0, + .reg_mask = 0x4000, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 13200, + .voltage_normal = 11550, /* mV */ + .voltage_min = 9000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 50, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = 0, + .discharging_max_c = 60, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC; diff --git a/board/phaser/board.c b/board/phaser/board.c new file mode 100644 index 0000000000..3d835ad4dd --- /dev/null +++ b/board/phaser/board.c @@ -0,0 +1,59 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Phaser board-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "common.h" +#include "driver/ppc/nx20p3483.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "lid_switch.h" +#include "power.h" +#include "power_button.h" +#include "switch.h" +#include "tcpci.h" + +static void tcpc_alert_event(enum gpio_signal signal) +{ + if ((signal == GPIO_USB_C1_PD_INT_ODL) && + !gpio_get_level(GPIO_USB_C1_PD_RST_ODL)) + return; + +#ifdef HAS_TASK_PDCMD + /* Exchange status with TCPCs */ + host_command_pd_send_status(PD_CHARGE_NO_CHANGE); +#endif +} + +static void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_PD_C0_INT_L: + nx20p3483_interrupt(0); + break; + + case GPIO_USB_PD_C1_INT_L: + nx20p3483_interrupt(1); + break; + + default: + break; + } +} + +/* Must come after other header files and GPIO interrupts*/ +#include "gpio_list.h" + +/* ADC channels */ +const struct adc_t adc_channels[] = { + [ADC_TEMP_SENSOR_AMB] = { + "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_CHARGER] = { + "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); diff --git a/board/phaser/board.h b/board/phaser/board.h new file mode 100644 index 0000000000..ff2c214702 --- /dev/null +++ b/board/phaser/board.h @@ -0,0 +1,47 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Phaser board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Select Baseboard features */ +#define VARIANT_OCTOPUS_EC_NPCX796FB +#define VARIANT_OCTOPUS_CHARGER_ISL9238 +#include "baseboard.h" + +/* Optional features */ +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ + +/* We don't have Vbus ADCs */ +#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +#define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum adc_channel { + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_CH_COUNT, +}; + +enum pwm_channel { + PWM_CH_KBLIGHT, + PWM_CH_COUNT +}; + +/* List of possible batteries */ +enum battery_type { + BATTERY_PANASONIC, + BATTERY_TYPE_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/phaser/build.mk b/board/phaser/build.mk new file mode 100644 index 0000000000..e25c6bb88d --- /dev/null +++ b/board/phaser/build.mk @@ -0,0 +1,16 @@ +# -*- makefile -*- +# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=npcx +CHIP_FAMILY:=npcx7 +CHIP_VARIANT:=npcx7m6fb +BASEBOARD:=octopus + +board-y=board.o +board-$(CONFIG_BATTERY_SMART)+=battery.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/phaser/ec.tasklist b/board/phaser/ec.tasklist new file mode 100644 index 0000000000..2a5ea99ad1 --- /dev/null +++ b/board/phaser/ec.tasklist @@ -0,0 +1,36 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + * + * For USB PD tasks, IDs must be in consecutive order and correspond to + * the port which they are for. See TASK_ID_TO_PD_PORT() macro. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc new file mode 100644 index 0000000000..a9976b1c2e --- /dev/null +++ b/board/phaser/gpio.inc @@ -0,0 +1,135 @@ +/* -*- mode:c -*- + * + * Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Wake Source interrupts */ +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH, lid_interrupt) +GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */ +GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* ACOK_OD */ + +/* USB-C interrupts */ +GPIO_INT(USB_C0_PD_INT_ODL, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C1_PD_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_PD_C0_INT_L, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(USB_PD_C1_INT_L, PIN(F, 1), GPIO_INT_FALLING, ppc_interrupt) + +/* Power State interrupts */ +#ifdef CONFIG_POWER_S0IX +GPIO_INT(PCH_SLP_S0_L, PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ +#endif +GPIO_INT(PCH_SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ +GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ +GPIO_INT(SUSPWRDNACK, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRDNACK */ +GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */ +GPIO_INT(ALL_SYS_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */ + +/* Other interrupts */ +GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) /* EC_WP_ODL */ + +/* TODO(b/74932344): Make it as an interrupt after driver supports this */ +GPIO(BASE_SIXAXIS_INT_L, PIN(5, 6), GPIO_INPUT | GPIO_SEL_1P8V) +GPIO(LID_ACCEL_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V) + +/* Define PCH_SLP_S0_L after all interrupts if CONFIG_POWER_S0IX not defined. */ +#ifndef CONFIG_POWER_S0IX +GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */ +#endif + +/* + * PLT_RST_L isn't used since there is a Virtual Wire on eSPI for it. It is here + * only for debugging purposes. + */ +GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */ +GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */ +GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ +GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ + +GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW) /* EN_PP5000_A */ +GPIO(PP5000_PG, PIN(C, 0), GPIO_INPUT) /* PP5000_PG_OD */ +GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 3), GPIO_ODR_HIGH) +GPIO(EN_PP3300, PIN(D, 4), GPIO_OUT_LOW) /* EN_PP3300_A */ +GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */ +GPIO(PMIC_EN, PIN(7, 2), GPIO_OUT_LOW) /* Enable A Rails via PMIC */ +GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */ +GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */ + +GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT) + +/* + * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is + * normally driven by the PMIC. The EC can also drive this signal in the event + * that the ambient or charger temperature sensors exceeds their thresholds. + */ +GPIO(CPU_PROCHOT, PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */ + +/* I2C pins - Alternate function below configures I2C module on these pins */ +GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SCL */ +GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SDA */ +GPIO(I2C1_SCL, PIN(9, 0), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SCL */ +GPIO(I2C1_SDA, PIN(8, 7), GPIO_INPUT) /* EC_I2C_USB_C0_MUX_SDA */ +GPIO(I2C2_SCL, PIN(9, 2), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SCL */ +GPIO(I2C2_SDA, PIN(9, 1), GPIO_INPUT) /* EC_I2C_USB_C1_MUX_SDA */ +GPIO(I2C3_SCL, PIN(D, 1), GPIO_INPUT) /* EC_I2C_EEPROM_SCL */ +GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT) /* EC_I2C_EEPROM_SDA */ +GPIO(I2C4_SCL, PIN(F, 3), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SCL */ +GPIO(I2C4_SDA, PIN(F, 2), GPIO_INPUT) /* EC_I2C_CHARGER_3V3_SDA */ +GPIO(I2C7_SCL, PIN(B, 3), GPIO_INPUT | + GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SCL */ +GPIO(I2C7_SDA, PIN(B, 2), GPIO_INPUT | + GPIO_SEL_1P8V) /* EC_I2C_SENSOR_U_SDA */ + +/* USB pins */ +GPIO(EN_USB_A0_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0 5V Charging */ +GPIO(EN_USB_A1_5V, PIN(7, 7), GPIO_OUT_LOW) /* Enable A1 5V Charging */ +GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0 1.5A Charging */ +GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH) /* Enable A1 1.5A Charging */ +/* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ +GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ +GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ +GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ + GPIO_SEL_1P8V) +GPIO(USB_C1_PD_RST_ODL, PIN(7, 0), GPIO_ODR_HIGH) /* C1 PD Reset */ +GPIO(EN_USB_C1_5V_OUT, PIN(0, 3), GPIO_OUT_LOW) /* C1 Source 5V */ +GPIO(USB_C1_CHARGE_ON, PIN(4, 0), GPIO_OUT_LOW) /* C1 Accept input voltage*/ +GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ +GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ +GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ + GPIO_SEL_1P8V) + +/* LED */ +GPIO(BAT_LED_ORANGE_L, PIN(C, 3), GPIO_OUT_HIGH) /* LED_1_L */ +GPIO(BAT_LED_BLUE_L, PIN(C, 4), GPIO_OUT_HIGH) /* LED_2_L */ +GPIO(LED_3_L, PIN(8, 0), GPIO_OUT_HIGH) /* LED_3_L */ + +/* Keyboard Backlight */ +GPIO(KB_BL_PWR_EN, PIN(6, 2), GPIO_OUT_LOW) + +/* Keyboard pins */ +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */ +ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */ +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */ +ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */ +ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-12 */ +GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */ + +/* Alternate functions GPIO definitions */ +/* Cr50 requires no pull-ups on UART pins. */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* UART from EC to Servo */ +ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */ +ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */ +ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */ +ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* I2C3 */ +ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */ +ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0) /* I2C7 */ +ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ +ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3: KB_BL_PWM */ diff --git a/board/phaser/usb_pd_policy.c b/board/phaser/usb_pd_policy.c new file mode 100644 index 0000000000..82922f9a4d --- /dev/null +++ b/board/phaser/usb_pd_policy.c @@ -0,0 +1,8 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +/* TODO(b/78638238): Remove file if still unused after DVT */ |