diff options
Diffstat (limited to 'chip/g')
| -rw-r--r-- | chip/g/alerts.c | 4 | ||||
| -rw-r--r-- | chip/g/board_space.h | 2 | ||||
| -rw-r--r-- | chip/g/flash_config.h | 6 | ||||
| -rw-r--r-- | chip/g/pmu.c | 4 | ||||
| -rw-r--r-- | chip/g/polling_uart.c | 2 | ||||
| -rw-r--r-- | chip/g/registers.h | 146 | ||||
| -rw-r--r-- | chip/g/uart_bitbang.c | 4 | ||||
| -rw-r--r-- | chip/g/uartn.c | 2 | ||||
| -rw-r--r-- | chip/g/usb.c | 6 |
9 files changed, 88 insertions, 88 deletions
diff --git a/chip/g/alerts.c b/chip/g/alerts.c index 6cfb936b9c..b53045ccaf 100644 --- a/chip/g/alerts.c +++ b/chip/g/alerts.c @@ -260,7 +260,7 @@ static int alert_intr_status(int alert) int reg = alert / 32; int offset = alert % 32; - return !!(*INTR_STATUS_ADDR[reg] & (1 << offset)); + return !!(*INTR_STATUS_ADDR[reg] & BIT(offset)); } #ifdef CONFIG_BOARD_ID_SUPPORT @@ -300,7 +300,7 @@ static void command_alerts_list(void) if (fuse == BROM_FWBIT_APPLYSEC_UNKNOWN) fuse_status = '?'; - else if (fuses & (1 << fuse)) + else if (fuses & BIT(fuse)) fuse_status = '+'; else fuse_status = '#'; diff --git a/chip/g/board_space.h b/chip/g/board_space.h index 90b6c02287..1884a5c74c 100644 --- a/chip/g/board_space.h +++ b/chip/g/board_space.h @@ -37,7 +37,7 @@ struct sn_data { /* Number of bits reserved for RMA counter */ #define RMA_COUNT_BITS 7 /* Value used to indicate device has been RMA'd */ -#define RMA_INDICATOR ((uint8_t) ~(1 << RMA_COUNT_BITS)) +#define RMA_INDICATOR ((uint8_t) ~BIT(RMA_COUNT_BITS)) /* Info1 Board space contents. */ struct info1_board_space { diff --git a/chip/g/flash_config.h b/chip/g/flash_config.h index 09ddd872d5..d1bec36871 100644 --- a/chip/g/flash_config.h +++ b/chip/g/flash_config.h @@ -15,9 +15,9 @@ #define FLASH_INFO_MANUFACTURE_STATE_SIZE 0x200 -#define FLASH_REGION_EN_ALL ((1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB) |\ - (1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB) |\ - (1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB)) +#define FLASH_REGION_EN_ALL (BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB) |\ + BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB) |\ + BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB)) /* * The below structure describes a single flash region (the hardware supports diff --git a/chip/g/pmu.c b/chip/g/pmu.c index a324e6cee7..a434a2bde5 100644 --- a/chip/g/pmu.c +++ b/chip/g/pmu.c @@ -22,7 +22,7 @@ void pmu_clock_en(uint32_t periph) { if (periph <= 31) - GR_PMU_PERICLKSET0 = (1 << periph); + GR_PMU_PERICLKSET0 = BIT(periph); else GR_PMU_PERICLKSET1 = (1 << (periph - 32)); } @@ -34,7 +34,7 @@ void pmu_clock_en(uint32_t periph) void pmu_clock_dis(uint32_t periph) { if (periph <= 31) - GR_PMU_PERICLKCLR0 = (1 << periph); + GR_PMU_PERICLKCLR0 = BIT(periph); else GR_PMU_PERICLKCLR1 = (1 << (periph - 32)); } diff --git a/chip/g/polling_uart.c b/chip/g/polling_uart.c index b1e4c4e0e3..e28abc2344 100644 --- a/chip/g/polling_uart.c +++ b/chip/g/polling_uart.c @@ -7,7 +7,7 @@ #include "registers.h" #include "uart.h" -#define UART_NCO ((16 * (1 << UART_NCO_WIDTH) * \ +#define UART_NCO ((16 * BIT(UART_NCO_WIDTH) * \ (long long)CONFIG_UART_BAUD_RATE) / PCLK_FREQ) /* 115200N81 uart0, TX on A0, RX on A1 */ diff --git a/chip/g/registers.h b/chip/g/registers.h index 9127802db3..0e69b75eaa 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -408,8 +408,8 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define USB_TX_DPO BIT(1) #define USB_TX_DMO BIT(0) -#define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) -#define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) #define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) #define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) @@ -418,86 +418,86 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ & GC_USB_GUSBCFG_USBTRDTIM_MASK) #define GUSBCFG_PHYSEL_HS (0 << GC_USB_GUSBCFG_PHYSEL_LSB) -#define GUSBCFG_PHYSEL_FS (1 << GC_USB_GUSBCFG_PHYSEL_LSB) +#define GUSBCFG_PHYSEL_FS BIT(GC_USB_GUSBCFG_PHYSEL_LSB) #define GUSBCFG_FSINTF_6PIN (0 << GC_USB_GUSBCFG_FSINTF_LSB) -#define GUSBCFG_FSINTF_3PIN (1 << GC_USB_GUSBCFG_FSINTF_LSB) -#define GUSBCFG_PHYIF16 (1 << GC_USB_GUSBCFG_PHYIF_LSB) +#define GUSBCFG_FSINTF_3PIN BIT(GC_USB_GUSBCFG_FSINTF_LSB) +#define GUSBCFG_PHYIF16 BIT(GC_USB_GUSBCFG_PHYIF_LSB) #define GUSBCFG_PHYIF8 (0 << GC_USB_GUSBCFG_PHYIF_LSB) -#define GUSBCFG_ULPI (1 << GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) +#define GUSBCFG_ULPI BIT(GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) #define GUSBCFG_UTMI (0 << GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) -#define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE (1 << GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH (1 << GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH (1 << GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) #define GRSTCTL_TXFNUM(n) (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) -#define DCFG_DEVSPD_FS (1 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FS BIT(GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVADDR(a) (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_DESCDMA (1 << GC_USB_DCFG_DESCDMA_LSB) +#define DCFG_DESCDMA BIT(GC_USB_DCFG_DESCDMA_LSB) -#define DCTL_SFTDISCON (1 << GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK (1 << GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK (1 << GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE (1 << GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK (1 << GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK (1 << GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK (1 << GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK (1 << GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK (1 << GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK (1 << GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK (1 << GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK (1 << GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK (1 << GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK (1 << GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK (1 << GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK (1 << GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK (1 << GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK (1 << GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK (1 << GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK (1 << GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK (1 << GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK (1 << GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK (1 << GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK (1 << GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK (1 << GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR (1 << GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR (1 << GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR (1 << GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD (1 << GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF (1 << GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS (1 << GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP (1 << GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT (1 << GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT (1 << GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS (1 << GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT (1 << GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP (1 << GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN (1 << GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL (1 << GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR (1 << GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP (1 << GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR (1 << GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR (1 << GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD (1 << GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT (1 << GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT (1 << GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR (1 << GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS (1 << GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS (1 << GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP (1 << GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD (1 << GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD (1 << GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL (1 << GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) #define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) @@ -505,14 +505,14 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK #define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL (1 << GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK (1 << GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID (1 << GC_USB_DIEPCTL1_DPID_LSB) -#define DXEPCTL_SNAK (1 << GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS (1 << GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA (1 << GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS (1 << GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL1_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) #define DXEPCTL_SET_D0PID BIT(28) diff --git a/chip/g/uart_bitbang.c b/chip/g/uart_bitbang.c index 9f08340d3c..31bce8128a 100644 --- a/chip/g/uart_bitbang.c +++ b/chip/g/uart_bitbang.c @@ -213,7 +213,7 @@ static void uart_bitbang_write_char(char c) /* 8 data bits. */ ones = 0; for (i = 0; i < 8; i++) { - val = !!(c & (1 << i)); + val = !!(c & BIT(i)); gpio_set_level(bitbang_config.tx_gpio, val); /* Count 1's in order to handle parity bit. */ @@ -271,7 +271,7 @@ static int uart_bitbang_receive_char(uint8_t *rxed_char, uint32_t *next_tick) for (i = 0; i < 8; i++) { if (gpio_get_level(bitbang_config.rx_gpio)) { ones++; - rx_char |= (1 << i); + rx_char |= BIT(i); } wait_ticks(next_tick); } diff --git a/chip/g/uartn.c b/chip/g/uartn.c index 8f14f3c54e..da85c5cb0a 100644 --- a/chip/g/uartn.c +++ b/chip/g/uartn.c @@ -144,7 +144,7 @@ int uartn_is_enabled(int uart) void uartn_init(int uart) { - long long setting = (16 * (1 << UART_NCO_WIDTH) * + long long setting = (16 * BIT(UART_NCO_WIDTH) * (long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ); /* set frequency */ diff --git a/chip/g/usb.c b/chip/g/usb.c index 37fef3179d..27ffde40aa 100644 --- a/chip/g/usb.c +++ b/chip/g/usb.c @@ -136,7 +136,7 @@ static void showbits(uint32_t b) int i; for (i = 0; i < 32; i++) - if (b & (1 << i)) { + if (b & BIT(i)) { if (deezbits[i]) ccprintf(" %s", deezbits[i]); else @@ -1255,7 +1255,7 @@ void usb_save_suspended_state(void) /* Record the state the DATA PIDs toggling on each endpoint. */ for (i = 1; i < USB_EP_COUNT; i++) { if (GR_USB_DOEPCTL(i) & DXEPCTL_DPID) - pid |= (1 << i); + pid |= BIT(i); if (GR_USB_DIEPCTL(i) & DXEPCTL_DPID) pid |= (1 << (i + 16)); } @@ -1275,7 +1275,7 @@ void usb_restore_suspended_state(void) /* Restore the DATA PIDs on endpoints. */ pid = GREG32(PMU, PWRDN_SCRATCH19); for (i = 1; i < USB_EP_COUNT; i++) { - GR_USB_DOEPCTL(i) = pid & (1 << i) ? + GR_USB_DOEPCTL(i) = pid & BIT(i) ? DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID; GR_USB_DIEPCTL(i) = pid & (1 << (i + 16)) ? DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID; |