diff options
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 66 |
1 files changed, 35 insertions, 31 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 03aac276fb..7e6b580d76 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -282,46 +282,50 @@ enum ish_i2c_port { #define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ /* Fabric Agent Status register */ -#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) -#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) -#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) -#define FABRIC_M_ERR_BIT BIT(24) +#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) +#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) +#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) +#define FABRIC_M_ERR_BIT BIT(24) #define FABRIC_MIA_STATUS_BIT_ERR (FABRIC_INBAND_ERR_SECONDARY_BIT | \ - FABRIC_INBAND_ERR_PRIMARY_BIT | \ - FABRIC_M_ERR_BIT) + FABRIC_INBAND_ERR_PRIMARY_BIT | \ + FABRIC_M_ERR_BIT) /* CSME Registers */ -#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) +#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) /* IOAPIC registers */ -#define IOAPIC_IDX 0xFEC00000 -#define IOAPIC_WDW 0xFEC00010 -#define IOAPIC_EOI_REG 0xFEC00040 - -#define IOAPIC_VERSION 0x1 -#define IOAPIC_IOREDTBL 0x10 -#define IOAPIC_REDTBL_DELMOD_FIXED 0x00000000 -#define IOAPIC_REDTBL_DESTMOD_PHYS 0x00000000 -#define IOAPIC_REDTBL_INTPOL_HIGH 0x00000000 -#define IOAPIC_REDTBL_INTPOL_LOW 0x00002000 -#define IOAPIC_REDTBL_IRR 0x00004000 -#define IOAPIC_REDTBL_TRIGGER_EDGE 0x00000000 -#define IOAPIC_REDTBL_TRIGGER_LEVEL 0x00008000 -#define IOAPIC_REDTBL_MASK 0x00010000 +#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) +#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) +/* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */ +#define IOAPIC_EOI_REG_ADDR 0xFEC00040 +#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) + +#define IOAPIC_VERSION (0x1) +#define IOAPIC_IOREDTBL (0x10) +#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) +#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) +#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) +#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) +#define IOAPIC_REDTBL_IRR (0x00004000) +#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) +#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) +#define IOAPIC_REDTBL_MASK (0x00010000) /* WDT (Watchdog Timer) Registers */ -#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) -#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) -#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) -#define WDT_CONTROL_ENABLE_BIT BIT(17) +#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) +#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) +#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) +#define WDT_CONTROL_ENABLE_BIT BIT(17) /* LAPIC registers */ -#define LAPIC_EOI_REG 0xFEE000B0 -#define LAPIC_ISR_REG 0xFEE00170 -#define LAPIC_IRR_REG (ISH_LAPIC_BASE + 0x200) -#define LAPIC_ESR_REG (ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL BIT(6) -#define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) +/* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ +#define LAPIC_EOI_REG_ADDR 0xFEE000B0 +#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) +#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x170) +#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) +#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) +#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) /* SRAM control registers */ #define ISH_SRAM_CTRL_BASE 0x00500000 |