diff options
Diffstat (limited to 'chip/it83xx/i2c_slave.c')
| -rw-r--r-- | chip/it83xx/i2c_slave.c | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/chip/it83xx/i2c_slave.c b/chip/it83xx/i2c_slave.c index bce86d25b8..1902285959 100644 --- a/chip/it83xx/i2c_slave.c +++ b/chip/it83xx/i2c_slave.c @@ -230,6 +230,7 @@ void i2c_slave_enable(int port, uint8_t slv_addr) /* Enhanced I2C slave channel D, E, F DMA mode */ else { int ch, idx; + uint32_t in_data_addr, out_data_addr; /* Get enhanced i2c channel */ ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL; @@ -280,13 +281,36 @@ void i2c_slave_enable(int port, uint8_t slv_addr) memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE); memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE); + if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { + in_data_addr = (uint32_t)in_data[idx] & 0xffffff; + out_data_addr = (uint32_t)out_data[idx] & 0xffffff; + } else { + in_data_addr = (uint32_t)in_data[idx] & 0xfff; + out_data_addr = (uint32_t)out_data[idx] & 0xfff; + } + /* DMA write target address register */ - IT83XX_I2C_RAMHA(ch) = ((uint32_t)in_data[idx] >> 8) & 0x0F; - IT83XX_I2C_RAMLA(ch) = (uint32_t)in_data[idx] & 0xFF; + IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8; + IT83XX_I2C_RAMLA(ch) = in_data_addr; - /* DMA read target address register */ - IT83XX_I2C_RAMHA2(ch) = ((uint32_t)out_data[idx] >> 8) & 0x0F; - IT83XX_I2C_RAMLA2(ch) = (uint32_t)out_data[idx] & 0xFF; + if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { + /* + * DMA write target address register + * for high order byte + */ + IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16; + /* + * DMA read target address register + * for high order byte + */ + IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16; + IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8; + IT83XX_I2C_CMD_ADDL(ch) = out_data_addr; + } else { + /* DMA read target address register */ + IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8; + IT83XX_I2C_RAMLA2(ch) = out_data_addr; + } /* I2C module enable and command queue mode */ IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | |