diff options
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 86 |
1 files changed, 44 insertions, 42 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 3536208226..a62753c9b1 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -172,6 +172,10 @@ #define IT83XX_IRQ_WKO142 142 #define IT83XX_IRQ_WKO143 143 /* Group 18 */ +#define IT83XX_IRQ_WKO123 144 +#define IT83XX_IRQ_WKO124 145 +#define IT83XX_IRQ_WKO125 146 +#define IT83XX_IRQ_WKO126 147 #define IT83XX_IRQ_PMC5_OUT 149 #define IT83XX_IRQ_PMC5_IN 150 #define IT83XX_IRQ_V_COMP 151 @@ -192,9 +196,20 @@ #define IT83XX_IRQ_PCH_P80 164 #define IT83XX_IRQ_USBPD0 165 #define IT83XX_IRQ_USBPD1 166 -#define IT83XX_IRQ_ESPI_SLAVE 167 - -#define IT83XX_IRQ_COUNT 168 +/* Group 21 */ +#define IT83XX_IRQ_WKO40 168 +#define IT83XX_IRQ_WKO45 169 +#define IT83XX_IRQ_WKO46 170 +#define IT83XX_IRQ_WKO144 171 +#define IT83XX_IRQ_WKO145 172 +#define IT83XX_IRQ_WKO146 173 +#define IT83XX_IRQ_WKO147 174 +#define IT83XX_IRQ_WKO148 175 +/* Group 22 */ +#define IT83XX_IRQ_WKO149 176 +#define IT83XX_IRQ_WKO150 177 + +#define IT83XX_IRQ_COUNT 178 /* IRQ dispatching to CPU INT vectors */ #define IT83XX_CPU_INT_IRQ_1 2 @@ -337,6 +352,10 @@ #define IT83XX_CPU_INT_IRQ_141 2 #define IT83XX_CPU_INT_IRQ_142 2 #define IT83XX_CPU_INT_IRQ_143 2 +#define IT83XX_CPU_INT_IRQ_144 2 +#define IT83XX_CPU_INT_IRQ_145 2 +#define IT83XX_CPU_INT_IRQ_146 2 +#define IT83XX_CPU_INT_IRQ_147 2 #define IT83XX_CPU_INT_IRQ_149 4 #define IT83XX_CPU_INT_IRQ_150 4 #define IT83XX_CPU_INT_IRQ_151 7 @@ -356,6 +375,16 @@ #define IT83XX_CPU_INT_IRQ_165 12 #define IT83XX_CPU_INT_IRQ_166 12 #define IT83XX_CPU_INT_IRQ_167 12 +#define IT83XX_CPU_INT_IRQ_168 2 +#define IT83XX_CPU_INT_IRQ_169 2 +#define IT83XX_CPU_INT_IRQ_170 2 +#define IT83XX_CPU_INT_IRQ_171 2 +#define IT83XX_CPU_INT_IRQ_172 2 +#define IT83XX_CPU_INT_IRQ_173 2 +#define IT83XX_CPU_INT_IRQ_174 2 +#define IT83XX_CPU_INT_IRQ_175 2 +#define IT83XX_CPU_INT_IRQ_176 2 +#define IT83XX_CPU_INT_IRQ_177 2 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */ #define CPU_INT_2_ALL_GPIOS 255 @@ -412,6 +441,8 @@ #define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE+0x4d) #define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE+0x51) #define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE+0x55) +#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE+0x59) +#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE+0x5d) #define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE+0x00) #define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE+0x01) @@ -434,53 +465,16 @@ #define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE+0x4c) #define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE+0x50) #define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE+0x54) +#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE+0x58) +#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE+0x5c) #define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E) #define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F) #define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52) #define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53) -#define IT83XX_INTC_EXT_IER0 REG8(IT83XX_INTC_BASE+0x60) -#define IT83XX_INTC_EXT_IER1 REG8(IT83XX_INTC_BASE+0x61) -#define IT83XX_INTC_EXT_IER2 REG8(IT83XX_INTC_BASE+0x62) -#define IT83XX_INTC_EXT_IER3 REG8(IT83XX_INTC_BASE+0x63) -#define IT83XX_INTC_EXT_IER4 REG8(IT83XX_INTC_BASE+0x64) -#define IT83XX_INTC_EXT_IER5 REG8(IT83XX_INTC_BASE+0x65) -#define IT83XX_INTC_EXT_IER6 REG8(IT83XX_INTC_BASE+0x66) -#define IT83XX_INTC_EXT_IER7 REG8(IT83XX_INTC_BASE+0x67) -#define IT83XX_INTC_EXT_IER8 REG8(IT83XX_INTC_BASE+0x68) -#define IT83XX_INTC_EXT_IER9 REG8(IT83XX_INTC_BASE+0x69) -#define IT83XX_INTC_EXT_IER10 REG8(IT83XX_INTC_BASE+0x6A) -#define IT83XX_INTC_EXT_IER11 REG8(IT83XX_INTC_BASE+0x6B) -#define IT83XX_INTC_EXT_IER12 REG8(IT83XX_INTC_BASE+0x6C) -#define IT83XX_INTC_EXT_IER13 REG8(IT83XX_INTC_BASE+0x6D) -#define IT83XX_INTC_EXT_IER14 REG8(IT83XX_INTC_BASE+0x6E) -#define IT83XX_INTC_EXT_IER15 REG8(IT83XX_INTC_BASE+0x6F) -#define IT83XX_INTC_EXT_IER16 REG8(IT83XX_INTC_BASE+0x70) -#define IT83XX_INTC_EXT_IER17 REG8(IT83XX_INTC_BASE+0x71) -#define IT83XX_INTC_EXT_IER18 REG8(IT83XX_INTC_BASE+0x72) -#define IT83XX_INTC_EXT_IER19 REG8(IT83XX_INTC_BASE+0x73) -#define IT83XX_INTC_EXT_IER20 REG8(IT83XX_INTC_BASE+0x74) - #define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n)) - #define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE+0x80+(i)) -#define IT83XX_INTC_IVCT0 REG8(IT83XX_INTC_BASE+0x80) -#define IT83XX_INTC_IVCT1 REG8(IT83XX_INTC_BASE+0x81) -#define IT83XX_INTC_IVCT2 REG8(IT83XX_INTC_BASE+0x82) -#define IT83XX_INTC_IVCT3 REG8(IT83XX_INTC_BASE+0x83) -#define IT83XX_INTC_IVCT4 REG8(IT83XX_INTC_BASE+0x84) -#define IT83XX_INTC_IVCT5 REG8(IT83XX_INTC_BASE+0x85) -#define IT83XX_INTC_IVCT6 REG8(IT83XX_INTC_BASE+0x86) -#define IT83XX_INTC_IVCT7 REG8(IT83XX_INTC_BASE+0x87) -#define IT83XX_INTC_IVCT8 REG8(IT83XX_INTC_BASE+0x88) -#define IT83XX_INTC_IVCT9 REG8(IT83XX_INTC_BASE+0x89) -#define IT83XX_INTC_IVCT10 REG8(IT83XX_INTC_BASE+0x8A) -#define IT83XX_INTC_IVCT11 REG8(IT83XX_INTC_BASE+0x8B) -#define IT83XX_INTC_IVCT12 REG8(IT83XX_INTC_BASE+0x8C) -#define IT83XX_INTC_IVCT13 REG8(IT83XX_INTC_BASE+0x8D) -#define IT83XX_INTC_IVCT14 REG8(IT83XX_INTC_BASE+0x8E) -#define IT83XX_INTC_IVCT15 REG8(IT83XX_INTC_BASE+0x8F) /* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */ #define IT83XX_EC2I_BASE 0x00F01200 @@ -503,6 +497,8 @@ #define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c) #define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04) #define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d) +#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c) +#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f) #define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE+0x21) #define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE+0x25) @@ -641,6 +637,10 @@ #define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE+0xE7) #define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE+0xE8) #define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE+0xE9) +#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE+0xD1) +#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE+0xD2) +#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE+0xD3) +#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE+0xD4) #define IT83XX_GPIO_DATA_BASE (IT83XX_GPIO_BASE + 0x00) #define IT83XX_GPIO_OUTPUT_TYPE_BASE (IT83XX_GPIO_BASE + 0x70) @@ -779,6 +779,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) +#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) #define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) #define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) #define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i) @@ -1227,6 +1228,7 @@ enum usbpd_port { #define IT83XX_ESPI_BASE 0x00F03100 +#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE+0x05) #define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE+0x90) #define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE+0xA0) #define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE+0xA1) |