diff options
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 83a0fb4014..483eabe346 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -991,6 +991,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37) #define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) +#define IT83XX_GCTRL_PIN_MUX0 REG8(IT83XX_GCTRL_BASE+0x46) #define IT83XX_DLM14_ENABLE BIT(5) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) @@ -1324,9 +1325,11 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SPI_RXF1OC BIT(3) #define IT83XX_SPI_RXFAR BIT(0) #define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE+0x04) +#define IT83XX_SPI_RX_FIFO_FULL BIT(7) #define IT83XX_SPI_RX_REACH BIT(5) #define IT83XX_SPI_EDIM BIT(2) #define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE+0x05) +#define IT83XX_SPI_TXFSR REG8(IT83XX_SPI_BASE+0x06) #define IT83XX_SPI_ENDDETECTINT BIT(2) #define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE+0x07) #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) @@ -1348,6 +1351,8 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SPI_TCCB0 REG8(IT83XX_SPI_BASE+0x1A) #define IT83XX_SPI_TCCB1 REG8(IT83XX_SPI_BASE+0x1B) #define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE+0x1E) +#define IT83XX_SPI_EMMCBMR REG8(IT83XX_SPI_BASE+0x21) +#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ #define IT83XX_SPI_RX_VLISMR REG8(IT83XX_SPI_BASE+0x26) #define IT83XX_SPI_RVLIM BIT(0) #define IT83XX_SPI_RX_VLISR REG8(IT83XX_SPI_BASE+0x27) |