diff options
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 9e5d115f81..cf9b227711 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -295,6 +295,9 @@ #define CPU_INT_GROUP_5 254 #define IT83XX_CPU_INT_IRQ_254 5 +#define CPU_INT_GROUP_4 252 +#define IT83XX_CPU_INT_IRQ_252 4 + #define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq) /* --- INTC --- */ @@ -571,6 +574,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) #define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) #define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE+0x0A) +#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) /* --- Pulse Width Modulation (PWM) --- */ #define IT83XX_PWM_BASE 0x00F01800 @@ -731,6 +735,12 @@ enum clock_gate_offsets { #define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE+0xFD) #define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE+0xFE) #define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE+0xFF) +#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4)) +#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4)) +#define IT83XX_PMC_PMDI(ch) \ +REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4)) +#define IT83XX_PMC_PMCTL(ch) \ +REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4)) /* Keyboard Matrix Scan control (KBS) */ #define IT83XX_KBS_BASE 0x00F01D00 @@ -774,9 +784,24 @@ enum clock_gate_offsets { #define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE+0x24) #define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE+0x25) +/* Shared Memory Flash Interface Bridge (SMFI) */ +#define IT83XX_SMFI_BASE 0x00F01000 + +#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE+0x5A) +#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE+0x5B) +#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE+0x5C) +#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE+0x5D) +#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE+0x5E) +#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE+0x76) +#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE+0x77) +#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE+0x78) +#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE+0x79) +#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE+0x7A) +#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE+0x7B) +#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE+0x7C) + /* --- MISC (not implemented yet) --- */ -#define IT83XX_SMFI_BASE 0x00F01000 #define IT83XX_PS2_BASE 0x00F01700 #define IT83XX_DAC_BASE 0x00F01A00 #define IT83XX_WUC_BASE 0x00F01B00 |