diff options
Diffstat (limited to 'chip/it83xx/registers.h')
| -rw-r--r-- | chip/it83xx/registers.h | 53 |
1 files changed, 52 insertions, 1 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index bacdc18d33..feb16bbba9 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -420,6 +420,15 @@ #define IT83XX_GPIO_BASE 0x00F01600 +#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE+0x10) +#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE+0x11) +#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE+0x12) +#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE+0x13) +#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE+0x14) +#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE+0x15) +#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE+0x16) +#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE+0x17) + #define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE+0x38) #define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE+0xF0) @@ -531,6 +540,49 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) #define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) +/* --- Pulse Width Modulation (PWM) --- */ +#define IT83XX_PWM_BASE 0x00F01800 + +#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE+0x00) +#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE+0x01) +#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE+0x02) +#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE+0x03) +#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE+0x04) +#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE+0x05) +#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE+0x06) +#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE+0x07) +#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE+0x08) +#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE+0x09) +#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE+0x0A) +#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE+0x0B) +#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE+0x0C) +#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE+0x0D) +#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE+0x0E) +#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE+0x0F) +#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE+0x1E) +#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE+0x1F) +#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE+0x20) +#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE+0x21) +#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE+0x22) +#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE+0x23) +#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE+0x24) +#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE+0x27) +#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE+0x28) +#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE+0x2B) +#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE+0x2C) +#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE+0x2D) +#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE+0x2E) +#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE+0x40) +#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE+0x41) +#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE+0x42) +#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE+0x43) +#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE+0x44) +#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE+0x45) +#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE+0x46) +#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE+0x47) +#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE+0x48) +#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE+0x49) + /* --- MISC (not implemented yet) --- */ #define IT83XX_SMFI_BASE 0x00F01000 @@ -539,7 +591,6 @@ enum clock_gate_offsets { #define IT83XX_SWUC_BASE 0x00F01400 #define IT83XX_PMC_BASE 0x00F01500 #define IT83XX_PS2_BASE 0x00F01700 -#define IT83XX_PWM_BASE 0x00F01800 #define IT83XX_ADC_BASE 0x00F01900 #define IT83XX_DAC_BASE 0x00F01A00 #define IT83XX_WUC_BASE 0x00F01B00 |