diff options
Diffstat (limited to 'chip/it83xx/watchdog.c')
| -rw-r--r-- | chip/it83xx/watchdog.c | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c index d22a3da538..e6941b1de5 100644 --- a/chip/it83xx/watchdog.c +++ b/chip/it83xx/watchdog.c @@ -8,13 +8,14 @@ #include "common.h" #include "cpu.h" #include "hooks.h" +#include "hwtimer_chip.h" #include "panic.h" #include "registers.h" #include "task.h" #include "watchdog.h" /* - * We use timer3 to trigger an interrupt just before the watchdog timer + * We use WDT_EXT_TIMER to trigger an interrupt just before the watchdog timer * will fire so that we can capture important state information before * being reset. */ @@ -25,18 +26,18 @@ void watchdog_warning_irq(void) { /* clear interrupt status */ - task_clear_pending_irq(IT83XX_IRQ_EXT_TIMER3); + task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq); - /* Reset warning timer (timer 3). */ - IT83XX_ETWD_ET3CTRL = 0x03; + /* Reset warning timer. */ + IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03; panic_printf("Pre-watchdog warning! IPC: %08x\n", get_ipc()); } void watchdog_reload(void) { - /* Reset warning timer (timer 3). */ - IT83XX_ETWD_ET3CTRL = 0x03; + /* Reset warning timer. */ + IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03; /* Restart (tickle) watchdog timer. */ IT83XX_ETWD_EWDKEYR = ITE83XX_WATCHDOG_MAGIC_WORD; @@ -45,11 +46,12 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); int watchdog_init(void) { + uint16_t wdt_count = CONFIG_WATCHDOG_PERIOD_MS * 1024 / 1000; + /* Unlock access to watchdog registers. */ IT83XX_ETWD_ETWCFG = 0x00; - /* Set timer 3 and WD timer to use 1.024kHz clock. */ - IT83XX_ETWD_ET3PSR = 0x01; + /* Set WD timer to use 1.024kHz clock. */ IT83XX_ETWD_ET1PSR = 0x01; /* Set WDT key match enabled and WDT clock to use ET1PSR. */ @@ -58,23 +60,19 @@ int watchdog_init(void) /* Specify that watchdog cannot be stopped. */ IT83XX_ETWD_ETWCTRL = 0x00; - /* Set timer 3 load value to 1024 (~1.05 seconds). */ - IT83XX_ETWD_ET3CNTLH2R = 0x00; - IT83XX_ETWD_ET3CNTLHR = 0x04; - IT83XX_ETWD_ET3CNTLLR = 0x00; - - /* Enable interrupt on timer 3 expiration. */ - task_enable_irq(IT83XX_IRQ_EXT_TIMER3); - - /* Start timer 3. */ - IT83XX_ETWD_ET3CTRL = 0x03; + /* Start WDT_EXT_TIMER (CONFIG_AUX_TIMER_PERIOD_MS ms). */ + ext_timer_ms(WDT_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, + CONFIG_AUX_TIMER_PERIOD_MS, 1, 0); /* Start timer 1 (must be started for watchdog timer to run). */ IT83XX_ETWD_ET1CNTLLR = 0x00; - /* Set watchdog timer to ~1.3 seconds. Writing CNTLL starts timer. */ - IT83XX_ETWD_EWDCNTLHR = 0x05; - IT83XX_ETWD_EWDCNTLLR = 0x00; + /* + * Set watchdog timer to CONFIG_WATCHDOG_PERIOD_MS ms. + * Writing CNTLL starts timer. + */ + IT83XX_ETWD_EWDCNTLHR = (wdt_count >> 8) & 0xff; + IT83XX_ETWD_EWDCNTLLR = wdt_count & 0xff; /* Lock access to watchdog registers. */ IT83XX_ETWD_ETWCFG = 0x3f; |