diff options
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/build.mk | 1 | ||||
| -rw-r--r-- | chip/it83xx/it83xx_fpu.S | 81 |
2 files changed, 82 insertions, 0 deletions
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk index 47820aba34..97f41ce287 100644 --- a/chip/it83xx/build.mk +++ b/chip/it83xx/build.mk @@ -18,6 +18,7 @@ chip-y=hwtimer.o uart.o gpio.o system.o jtag.o clock.o irq.o intc.o chip-$(CONFIG_WATCHDOG)+=watchdog.o chip-$(CONFIG_FANS)+=fan.o pwm.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o +chip-$(CONFIG_FPU)+=it83xx_fpu.o chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_EC2I)+=ec2i.o diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S new file mode 100644 index 0000000000..d98ba0fa67 --- /dev/null +++ b/chip/it83xx/it83xx_fpu.S @@ -0,0 +1,81 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * DLMB register = 0x80189: + * Disable all interrupts and switching CPU's + * ALU (Arithmetic Logic Unit) to floating point operation mode. + * (IEEE standard 754 floating point) + * + * DLMB register = 0x80009: + * Restore interrupts and ALU. + */ + .text + .align 2 + .global __addsf3 + .type __addsf3, @function +__addsf3: + sethi $r2, 0x80 /* r2 = 0x80000 */ + addi $r3, $r2, 0x189 /* r3 = 0x80189 */ + addi45 $r2, 0x9 /* r2 = 0x80009 */ + mtsr $r3, $dlmb /* dlmb = 0x80189 */ + dsb + /* Floating-point addition single-precision */ + add45 $r0, $r1 + mtsr $r2, $dlmb /* dlmb = 0x80009 */ + dsb + ret5 $lp + .size __addsf3, .-__addsf3 + + .text + .align 2 + .global __subsf3 + .type __subsf3, @function +__subsf3: + sethi $r2, 0x80 /* r2 = 0x80000 */ + addi $r3, $r2, 0x189 /* r3 = 0x80189 */ + addi45 $r2, 0x9 /* r2 = 0x80009 */ + mtsr $r3, $dlmb /* dlmb = 0x80189 */ + dsb + /* Floating-point subtraction single-precision */ + sub45 $r0, $r1 + mtsr $r2, $dlmb /* dlmb = 0x80009 */ + dsb + ret5 $lp + .size __subsf3, .-__subsf3 + + .text + .align 2 + .global __mulsf3 + .type __mulsf3, @function +__mulsf3: + sethi $r2, 0x80 /* r2 = 0x80000 */ + addi $r3, $r2, 0x189 /* r3 = 0x80189 */ + addi45 $r2, 0x9 /* r2 = 0x80009 */ + mtsr $r3, $dlmb /* dlmb = 0x80189 */ + dsb + /* Floating-point multiplication single-precision */ + mul33 $r0, $r1 + mtsr $r2, $dlmb /* dlmb = 0x80009 */ + dsb + ret5 $lp + .size __mulsf3, .-__mulsf3 + + .text + .align 2 + .global __divsf3 + .type __divsf3, @function +__divsf3: + sethi $r2, 0x80 /* r2 = 0x80000 */ + addi $r3, $r2, 0x189 /* r3 = 0x80189 */ + addi45 $r2, 0x9 /* r2 = 0x80009 */ + mtsr $r3, $dlmb /* dlmb = 0x80189 */ + dsb + /* Floating-point division single-precision */ + divsr $r0,$r0,$r0,$r1 + mtsr $r2, $dlmb /* dlmb = 0x80009 */ + dsb + ret5 $lp + .size __divsf3, .-__divsf3 |