diff options
Diffstat (limited to 'chip/it83xx')
-rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 4 | ||||
-rw-r--r-- | chip/it83xx/spi.c | 108 |
2 files changed, 36 insertions, 76 deletions
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 0e9b344b21..a3113907fd 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -125,10 +125,6 @@ #define IT83XX_INTC_PLUG_IN_OUT_SUPPORT /* Wake up CPU from low power mode even if interrupts are disabled */ #define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED -/* Auto reset rx fifo while CS# deasserted. */ -#define IT83XX_SPI_AUTO_RESET_RX_FIFO -/* CPU accesses FIFO to reach rx valid data length. */ -#define IT83XX_SPI_RX_VALID_INT /* Individual setting CC1 and CC2 resistance. */ #define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE /* Chip actually has TCPC physical port count. */ diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 1fb77f9c3b..bacfe434c5 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -242,12 +242,6 @@ void spi_slv_int_handler(void) * EC responded data, then AP ended the transaction. */ if (IT83XX_SPI_ISR & IT83XX_SPI_ENDDETECTINT) { - /* Reset fifo and prepare to receive next transaction */ - if (!IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO)) - reset_rx_fifo(); - /* Enable Rx byte reach interrupt */ - if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) - IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* @@ -258,39 +252,17 @@ void spi_slv_int_handler(void) /* CS# is deasserted, so write clear all slave status */ IT83XX_SPI_ISR = 0xff; } - - if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) { - /* - * The status of Rx valid length interrupt bit is set that - * indicates reached target count(IT83XX_SPI_FTCB1R, - * IT83XX_SPI_FTCB0R) and the length field of the host - * requested data. - */ - if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) { - /* write clear slave status */ - IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI; - /* Parse header for version of spi-protocol */ - spi_parse_header(); - } - } else { - /* - * The status of Rx byte reach interrupt bit is set, - * start to parse transaction. - * There is a limitation that Rx FIFO starts dropping - * data when the CPU access the the FIFO. So we will - * wait the data until Rx byte reach then to parse. - * The Rx FIFO to reach is mock data generated by - * generate clock that is not the bytes sent from - * the host. - */ - if (IT83XX_SPI_ISR & IT83XX_SPI_RX_REACH) { - /* Disable Rx byte reach interrupt */ - IT83XX_SPI_IMR |= IT83XX_SPI_RX_REACH; - /* write clear slave status */ - IT83XX_SPI_ISR = IT83XX_SPI_RX_REACH; - /* Parse header for version of spi-protocol */ - spi_parse_header(); - } + /* + * The status of Rx valid length interrupt bit is set that + * indicates reached target count(IT83XX_SPI_FTCB1R, + * IT83XX_SPI_FTCB0R) and the length field of the host + * requested data. + */ + if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) { + /* write clear slave status */ + IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI; + /* Parse header for version of spi-protocol */ + spi_parse_header(); } /* Clear the interrupt status */ @@ -299,6 +271,28 @@ void spi_slv_int_handler(void) static void spi_init(void) { + /* Set FIFO data target count */ + struct ec_host_request cmd_head; + + /* + * Target count means the size of host request. + * And plus extra 4 bytes because the CPU accesses FIFO base on + * word. If host requested data length is one byte, we need to + * align the data length to 4 bytes. + */ + int target_count = sizeof(cmd_head) + 4; + /* Offset of data_len member of host request. */ + int offset = (char *)&cmd_head.data_len - (char *)&cmd_head; + + IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff; + IT83XX_SPI_FTCB0R = target_count & 0xff; + /* + * The register setting can capture the length field of host + * request. + */ + IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff; + IT83XX_SPI_TCCB0 = offset & 0xff; + /* Set SPI pins to alternate function */ gpio_config_module(MODULE_SPI, 1); /* @@ -308,43 +302,16 @@ static void spi_init(void) IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE; /* Set unused blocked byte */ IT83XX_SPI_HPR2 = 0x00; - /* Set FIFO data target count */ - if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) { - struct ec_host_request cmd_head; - /* - * Target count means the size of host request. - * And plus extra 4 bytes because the CPU accesses FIFO base on - * word. If host requested data length is one byte, we need to - * align the data length to 4 bytes. - */ - int target_count = sizeof(cmd_head) + 4; - /* Offset of data_len member of host request. */ - int offset = (char *)&cmd_head.data_len - (char *)&cmd_head; - - IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff; - IT83XX_SPI_FTCB0R = target_count & 0xff; - /* - * The register setting can capture the length field of host - * request. - */ - IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff; - IT83XX_SPI_TCCB0 = offset & 0xff; - } else { - IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; - IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff; - } /* Rx valid length interrupt enabled */ - if (IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) - IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM; + IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM; /* * General control register2 * bit4 : Rx FIFO2 will not be overwrited once it's full. * bit3 : Rx FIFO1 will not be overwrited once it's full. * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high. */ - if (IS_ENABLED(IT83XX_SPI_AUTO_RESET_RX_FIFO)) - IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC - | IT83XX_SPI_RXFAR; + IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC + | IT83XX_SPI_RXFAR; /* * Interrupt mask register (0b:Enable, 1b:Mask) * bit5 : Rx byte reach interrupt mask @@ -353,9 +320,6 @@ static void spi_init(void) IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM; /* Reset fifo and prepare to for next transaction */ reset_rx_fifo(); - /* Enable Rx byte reach interrupt */ - if (!IS_ENABLED(IT83XX_SPI_RX_VALID_INT)) - IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH; /* Ready to receive */ spi_set_state(SPI_STATE_READY_TO_RECV); /* Interrupt status register(write one to clear) */ |