diff options
Diffstat (limited to 'chip/lm4/system.c')
| -rw-r--r-- | chip/lm4/system.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 684b520dae..625a4076e2 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -388,6 +388,42 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) hibernate(seconds, microseconds, HIBDATA_WAKE_PIN); } +void chip_pre_init(void) +{ + /* Enable clocks to GPIO block C in run and sleep modes. */ + clock_enable_peripheral(CGC_OFFSET_GPIO, 0x0004, CGC_MODE_ALL); + + /* + * Ensure PC0:3 are set to JTAG function. They should be set this way + * on a cold boot, but on a warm reboot a previous misbehaving image + * could have set them differently. + */ + if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) && + ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) && + ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) && + ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f)) + return; /* Already properly configured */ + + /* Unlock commit register for JTAG pins */ + LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK; + LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f; + + /* Reset JTAG pins */ + LM4_GPIO_PCTL(LM4_GPIO_C) = + (LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111; + LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f; + LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f; + LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f; + + /* Set interrupt on either edge of the JTAG signals */ + LM4_GPIO_IS(LM4_GPIO_C) &= ~0x0f; + LM4_GPIO_IBE(LM4_GPIO_C) |= 0x0f; + + /* Re-lock commit register */ + LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f; + LM4_GPIO_LOCK(LM4_GPIO_C) = 0; +} + void system_pre_init(void) { uint32_t hibctl; |