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-rw-r--r--chip/lm4/gpio.c2
-rw-r--r--chip/lm4/lpc.c15
2 files changed, 10 insertions, 7 deletions
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index 65d6548f90..39baae3bf6 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -328,7 +328,7 @@ static void gpio_interrupt(int port, uint32_t mis)
/**
* Handlers for each GPIO port. These read and clear the interrupt bits for
- * the port, then call the master handler above.
+ * the port, then call the controller handler above.
*/
#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \
void irqfunc(void) \
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 0c672bd63a..8a59d6b434 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -759,16 +759,19 @@ static void lpc_init(void)
#endif
/*
- * Ensure the EC (slave) has control of the memory-mapped I/O space.
- * Once the EC has won arbitration for the memory-mapped space, it will
- * keep control of it until it writes the last byte in the space.
- * (That never happens; we can't use the last byte in the space because
- * ACPI can't see it anyway.)
+ * Ensure the EC (peripheral) has control of the memory-mapped I/O
+ * space. Once the EC has won arbitration for the memory-mapped space,
+ * it will keep control of it until it writes the last byte in the
+ * space. (That never happens; we can't use the last byte in the space
+ * because ACPI can't see it anyway.)
*/
while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
/* Clear HW1ST */
LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
- /* Do a dummy slave write; this should cause SW1ST to be set */
+ /*
+ * Do a dummy peripheral write; this should cause SW1ST to be
+ * set.
+ */
*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
}