diff options
Diffstat (limited to 'chip/lm4')
| -rw-r--r-- | chip/lm4/i2c.c | 30 | ||||
| -rw-r--r-- | chip/lm4/keyboard_raw.c | 4 | ||||
| -rw-r--r-- | chip/lm4/lpc.c | 12 | ||||
| -rw-r--r-- | chip/lm4/registers.h | 60 | ||||
| -rw-r--r-- | chip/lm4/system.c | 6 | ||||
| -rw-r--r-- | chip/lm4/watchdog.c | 2 |
6 files changed, 57 insertions, 57 deletions
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c index 6f3efb700e..6a746fd9b5 100644 --- a/chip/lm4/i2c.c +++ b/chip/lm4/i2c.c @@ -21,22 +21,22 @@ #define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) /* Flags for writes to MCS */ -#define LM4_I2C_MCS_RUN (1 << 0) -#define LM4_I2C_MCS_START (1 << 1) -#define LM4_I2C_MCS_STOP (1 << 2) -#define LM4_I2C_MCS_ACK (1 << 3) -#define LM4_I2C_MCS_HS (1 << 4) -#define LM4_I2C_MCS_QCMD (1 << 5) +#define LM4_I2C_MCS_RUN BIT(0) +#define LM4_I2C_MCS_START BIT(1) +#define LM4_I2C_MCS_STOP BIT(2) +#define LM4_I2C_MCS_ACK BIT(3) +#define LM4_I2C_MCS_HS BIT(4) +#define LM4_I2C_MCS_QCMD BIT(5) /* Flags for reads from MCS */ -#define LM4_I2C_MCS_BUSY (1 << 0) -#define LM4_I2C_MCS_ERROR (1 << 1) -#define LM4_I2C_MCS_ADRACK (1 << 2) -#define LM4_I2C_MCS_DATACK (1 << 3) -#define LM4_I2C_MCS_ARBLST (1 << 4) -#define LM4_I2C_MCS_IDLE (1 << 5) -#define LM4_I2C_MCS_BUSBSY (1 << 6) -#define LM4_I2C_MCS_CLKTO (1 << 7) +#define LM4_I2C_MCS_BUSY BIT(0) +#define LM4_I2C_MCS_ERROR BIT(1) +#define LM4_I2C_MCS_ADRACK BIT(2) +#define LM4_I2C_MCS_DATACK BIT(3) +#define LM4_I2C_MCS_ARBLST BIT(4) +#define LM4_I2C_MCS_IDLE BIT(5) +#define LM4_I2C_MCS_BUSBSY BIT(6) +#define LM4_I2C_MCS_CLKTO BIT(7) /* * Minimum delay between resetting the port or sending a stop condition, and @@ -298,7 +298,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { - /* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */ + /* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */ return LM4_I2C_MBMON(port) & 0x03; } diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c index 66d66de1fa..85042ce85e 100644 --- a/chip/lm4/keyboard_raw.c +++ b/chip/lm4/keyboard_raw.c @@ -34,7 +34,7 @@ void keyboard_raw_init(void) * When column 2 is inverted, the Silego has a pulldown instead of a * pullup. So drive it push-pull instead of open-drain. */ - LM4_GPIO_ODR(LM4_GPIO_P) &= ~(1 << 2); + LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2); #endif /* Set row inputs with pull-up */ @@ -72,7 +72,7 @@ test_mockable void keyboard_raw_drive_column(int col) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* Invert column 2 output */ - mask ^= (1 << 2); + mask ^= BIT(2); #endif LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff; diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index f2f1cb0549..745e5e5465 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -405,7 +405,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) int lpc_get_pltrst_asserted(void) { - return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0; + return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0; } /** @@ -594,8 +594,8 @@ void lpc_interrupt(void) #endif /* Debugging: print changes to LPC0RESET */ - if (mis & (1 << 31)) { - if (LM4_LPC_LPCSTS & (1 << 10)) { + if (mis & BIT(31)) { + if (LM4_LPC_LPCSTS & BIT(10)) { int i; /* Store port 80 reset event */ @@ -682,7 +682,7 @@ static void lpc_init(void) * data writes, pool bytes 0(data)/1(cmd) */ LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60; - LM4_LPC_CTL(LPC_CH_KEYBOARD) = (1 << 24/* IRQSEL1 */) | + LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) | (0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1)); LM4_LPC_ST(LPC_CH_KEYBOARD) = 0; /* Unmask interrupt for host command/data writes and data reads */ @@ -743,7 +743,7 @@ static void lpc_init(void) * Unmask LPC bus reset interrupt. This lets us monitor the PCH * PLTRST# signal for debugging. */ - LM4_LPC_LPCIM |= (1 << 31); + LM4_LPC_LPCIM |= BIT(31); /* Enable LPC channels */ LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 | @@ -820,7 +820,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 2) | (1 << 3); + r->protocol_versions = BIT(2) | BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 15c91d1ca3..7fad67c181 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -41,11 +41,11 @@ static inline int lm4_spi_addr(int ch, int offset) #define LM4_SSI_CR1(ch) LM4SSIREG(ch, 0x004) #define LM4_SSI_DR(ch) LM4SSIREG(ch, 0x008) #define LM4_SSI_SR(ch) LM4SSIREG(ch, 0x00c) -#define LM4_SSI_SR_TFE (1 << 0) /* Transmit FIFO empty */ -#define LM4_SSI_SR_TNF (1 << 1) /* Transmit FIFO not full */ -#define LM4_SSI_SR_RNE (1 << 2) /* Receive FIFO not empty */ -#define LM4_SSI_SR_RFF (1 << 3) /* Receive FIFO full */ -#define LM4_SSI_SR_BSY (1 << 4) /* Busy */ +#define LM4_SSI_SR_TFE BIT(0) /* Transmit FIFO empty */ +#define LM4_SSI_SR_TNF BIT(1) /* Transmit FIFO not full */ +#define LM4_SSI_SR_RNE BIT(2) /* Receive FIFO not empty */ +#define LM4_SSI_SR_RFF BIT(3) /* Receive FIFO full */ +#define LM4_SSI_SR_BSY BIT(4) /* Busy */ #define LM4_SSI_CPSR(ch) LM4SSIREG(ch, 0x010) #define LM4_SSI_IM(ch) LM4SSIREG(ch, 0x014) #define LM4_SSI_RIS(ch) LM4SSIREG(ch, 0x018) @@ -85,7 +85,7 @@ static inline int lm4_adc_addr(int ss, int offset) #define LM4_ADC_SSEMUX(ss) LM4ADCREG(ss, 0x018) #define LM4_LPC_LPCCTL REG32(0x40080000) -#define LM4_LPC_SCI_START (1 << 9) /* Start a pulse on LPC0SCI signal */ +#define LM4_LPC_SCI_START BIT(9) /* Start a pulse on LPC0SCI signal */ #define LM4_LPC_SCI_CLK_1 (0 << 10) /* SCI asserted for 1 clock period */ #define LM4_LPC_SCI_CLK_2 (1 << 10) /* SCI asserted for 2 clock periods */ #define LM4_LPC_SCI_CLK_4 (2 << 10) /* SCI asserted for 4 clock periods */ @@ -115,13 +115,13 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4LPCREG(ch, offset) REG32(lm4_lpc_addr(ch, offset)) #define LM4_LPC_CTL(ch) LM4LPCREG(ch, 0x000) #define LM4_LPC_ST(ch) LM4LPCREG(ch, 0x004) -#define LM4_LPC_ST_TOH (1 << 0) /* TO Host bit */ -#define LM4_LPC_ST_FRMH (1 << 1) /* FRoM Host bit */ -#define LM4_LPC_ST_CMD (1 << 3) /* Last from-host byte was command */ -#define LM4_LPC_ST_BURST (1 << 8) -#define LM4_LPC_ST_SCI (1 << 9) -#define LM4_LPC_ST_SMI (1 << 10) -#define LM4_LPC_ST_BUSY (1 << 12) +#define LM4_LPC_ST_TOH BIT(0) /* TO Host bit */ +#define LM4_LPC_ST_FRMH BIT(1) /* FRoM Host bit */ +#define LM4_LPC_ST_CMD BIT(3) /* Last from-host byte was command */ +#define LM4_LPC_ST_BURST BIT(8) +#define LM4_LPC_ST_SCI BIT(9) +#define LM4_LPC_ST_SMI BIT(10) +#define LM4_LPC_ST_BUSY BIT(12) #define LM4_LPC_ADR(ch) LM4LPCREG(ch, 0x008) #define LM4_LPC_POOL_BYTES 1024 /* Size of LPCPOOL in bytes */ #define LM4_LPC_LPCPOOL ((volatile unsigned char *)0x40080400) @@ -186,12 +186,12 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004) #define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c) #define LM4_HIBERNATE_HIBCTL REG32(0x400fc010) -#define LM4_HIBCTL_WRC (1 << 31) -#define LM4_HIBCTL_CLK32EN (1 << 6) -#define LM4_HIBCTL_PINWEN (1 << 4) -#define LM4_HIBCTL_RTCWEN (1 << 3) -#define LM4_HIBCTL_HIBREQ (1 << 1) -#define LM4_HIBCTL_RTCEN (1 << 0) +#define LM4_HIBCTL_WRC BIT(31) +#define LM4_HIBCTL_CLK32EN BIT(6) +#define LM4_HIBCTL_PINWEN BIT(4) +#define LM4_HIBCTL_RTCWEN BIT(3) +#define LM4_HIBCTL_HIBREQ BIT(1) +#define LM4_HIBCTL_RTCEN BIT(0) #define LM4_HIBERNATE_HIBIM REG32(0x400fc014) #define LM4_HIBERNATE_HIBRIS REG32(0x400fc018) #define LM4_HIBERNATE_HIBMIS REG32(0x400fc01c) @@ -228,22 +228,22 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_SYSTEM_MISC REG32(0x400fe058) #define LM4_SYSTEM_RESC REG32(0x400fe05c) #define LM4_SYSTEM_RCC REG32(0x400fe060) -#define LM4_SYSTEM_RCC_ACG (1 << 27) +#define LM4_SYSTEM_RCC_ACG BIT(27) #define LM4_SYSTEM_RCC_SYSDIV(x) (((x) & 0xf) << 23) -#define LM4_SYSTEM_RCC_USESYSDIV (1 << 22) -#define LM4_SYSTEM_RCC_PWRDN (1 << 13) -#define LM4_SYSTEM_RCC_BYPASS (1 << 11) +#define LM4_SYSTEM_RCC_USESYSDIV BIT(22) +#define LM4_SYSTEM_RCC_PWRDN BIT(13) +#define LM4_SYSTEM_RCC_BYPASS BIT(11) #define LM4_SYSTEM_RCC_XTAL(x) (((x) & 0x1f) << 6) #define LM4_SYSTEM_RCC_OSCSRC(x) (((x) & 0x3) << 4) -#define LM4_SYSTEM_RCC_IOSCDIS (1 << 1) -#define LM4_SYSTEM_RCC_MOSCDIS (1 << 0) +#define LM4_SYSTEM_RCC_IOSCDIS BIT(1) +#define LM4_SYSTEM_RCC_MOSCDIS BIT(0) #define LM4_SYSTEM_RCC2 REG32(0x400fe070) -#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31) -#define LM4_SYSTEM_RCC2_DIV400 (1 << 30) +#define LM4_SYSTEM_RCC2_USERCC2 BIT(31) +#define LM4_SYSTEM_RCC2_DIV400 BIT(30) #define LM4_SYSTEM_RCC2_SYSDIV2(x) (((x) & 0x3f) << 23) -#define LM4_SYSTEM_RCC2_SYSDIV2LSB (1 << 22) -#define LM4_SYSTEM_RCC2_PWRDN2 (1 << 13) -#define LM4_SYSTEM_RCC2_BYPASS2 (1 << 11) +#define LM4_SYSTEM_RCC2_SYSDIV2LSB BIT(22) +#define LM4_SYSTEM_RCC2_PWRDN2 BIT(13) +#define LM4_SYSTEM_RCC2_BYPASS2 BIT(11) #define LM4_SYSTEM_RCC2_OSCSRC2(x) (((x) & 0x7) << 4) #define LM4_SYSTEM_MOSCCTL REG32(0x400fe07c) #define LM4_SYSTEM_DSLPCLKCFG REG32(0x400fe144) diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 45f6b91809..ce3d353bed 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -30,9 +30,9 @@ enum hibdata_index { }; /* Flags for HIBDATA_INDEX_WAKE */ -#define HIBDATA_WAKE_RTC (1 << 0) /* RTC alarm */ -#define HIBDATA_WAKE_HARD_RESET (1 << 1) /* Hard reset via short RTC alarm */ -#define HIBDATA_WAKE_PIN (1 << 2) /* Wake pin */ +#define HIBDATA_WAKE_RTC BIT(0) /* RTC alarm */ +#define HIBDATA_WAKE_HARD_RESET BIT(1) /* Hard reset via short RTC alarm */ +#define HIBDATA_WAKE_PIN BIT(2) /* Wake pin */ /* * Time to hibernate to trigger a power-on reset. 50 ms is sufficient for the diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 583ace0582..e7ff5e2e83 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -101,7 +101,7 @@ int watchdog_init(void) LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD; /* De-activate the watchdog when the JTAG stops the CPU */ - LM4_WATCHDOG_TEST(0) |= 1 << 8; + LM4_WATCHDOG_TEST(0) |= BIT(8); /* Reset after 2 time-out, activate the watchdog and lock the control * register. */ |