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Diffstat (limited to 'chip/mchp/config_flash_layout.h')
| -rw-r--r-- | chip/mchp/config_flash_layout.h | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h new file mode 100644 index 0000000000..56b69f1d32 --- /dev/null +++ b/chip/mchp/config_flash_layout.h @@ -0,0 +1,103 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H +#define __CROS_EC_CONFIG_FLASH_LAYOUT_H + +/* + * mec17xx flash layout: + * - Non memory-mapped, external SPI. + * - RW image at the beginning of writable region. + * - Bootloader at the beginning of protected region, followed by RO image. + * - Loader + (RO | RW) loaded into program memory. + */ + +/* Non-memmapped, external SPI */ +#define CONFIG_EXTERNAL_STORAGE +#undef CONFIG_MAPPED_STORAGE +#undef CONFIG_FLASH_PSTATE +#define CONFIG_SPI_FLASH + +/* + * MEC17xx BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04. + * One valid TAG must be present. + * TAG's point to a Header which must be located on a 256 byte + * boundary anywhere in the flash (24-bit addressing). + * Locate BootROM load Header + LFW + EC_RO at start of second + * 4KB sector (offset 0x1000). + * Locate BootROM load Header + EC_RW at start of second half of + * SPI flash. + * LFW size is 4KB + * EC_RO and EC_RW padded sizes from the build are 188KB each. + * Storage size is 1/2 flash size. + */ +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +/* Lower 256KB of flash is protected region */ +#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 +/* Writable storage for EC_RW starts at 256KB */ +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +/* Writeable storage is 256KB */ +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 + + +/* Loader resides at the beginning of program memory */ +#define CONFIG_LOADER_MEM_OFF 0 +#define CONFIG_LOADER_SIZE 0x1000 + +/* Write protect Loader and RO Image */ +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +/* + * Write protect LFW + EC_RO + */ +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE + +/* + * RO / RW images follow the loader in program memory. Either RO or RW + * image will be loaded -- both cannot be loaded at the same time. + */ +#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ + CONFIG_LOADER_SIZE) +/* + * MEC1701H Code + Data SRAM size = 256KB + * Allocate 32KB for data leaving 192KB for Code. + * The loader is resident in first 4KB of Code SRAM. + * EC_RO/RW can load 192 - 4 = 188 KB maximum. + * !!! This size MUST be a multiple of flash erase block size. + * defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h !!! + */ +#define CONFIG_RO_SIZE (188 * 1024) +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE + +/* + * WP region consists of first half of SPI containing TAGs at beginning + * of SPI flash and header + binary(LFW+EC_RO) at offset 0x1000. + * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device. + * We only use first TAG pointing to LFW + EC_RO. + * Header size is 128 bytes. Firmware binary is located immediately + * after the header. + * Second half of SPI flash contains: + * Header(128 bytes) + EC_RW + */ +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 +#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0x0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 + +/* Loader / lfw image immediately follows the boot header on SPI */ +#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ + CONFIG_BOOT_HEADER_STORAGE_SIZE) + +/* RO image immediately follows the loader image */ +#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ + CONFIG_LOADER_SIZE) + +/* + * Header + RW image starts at offset 0 of second half of SPI. + */ +#define CONFIG_RW_STORAGE_OFF (CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \ + CONFIG_BOOT_HEADER_STORAGE_SIZE) + + +#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ |