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-rw-r--r--chip/mchp/uart.c130
1 files changed, 83 insertions, 47 deletions
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
index 0f8bd62db8..56c99646a4 100644
--- a/chip/mchp/uart.c
+++ b/chip/mchp/uart.c
@@ -17,7 +17,42 @@
#include "util.h"
#include "tfdp_chip.h"
-#define TX_FIFO_SIZE 16
+#define TX_FIFO_SIZE 16
+
+BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) &&
+ (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES));
+
+#if CONFIG_UART_CONSOLE == 2
+
+#define UART_IRQ MCHP_IRQ_UART2
+#define UART_IRQ_BIT MCHP_UART2_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART2
+#define GPIO_UART_RX GPIO_UART2_RX
+/* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(5)
+
+#elif CONFIG_UART_CONSOLE == 1
+
+#define UART_IRQ MCHP_IRQ_UART1
+#define UART_IRQ_BIT MCHP_UART1_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART1
+#define GPIO_UART_RX GPIO_UART1_RX
+/* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(25)
+
+#else
+
+#define UART_IRQ MCHP_IRQ_UART0
+#define UART_IRQ_BIT MCHP_UART0_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART0
+#define GPIO_UART_RX GPIO_UART0_RX
+/* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */
+#define UART_RX_PIN_GIRQ 9
+#define UART_RX_PIN_BIT BIT(5)
+
+#endif /* CONFIG_UART_CONSOLE == 2 */
static int init_done;
static int tx_fifo_used;
@@ -30,7 +65,7 @@ int uart_init_done(void)
void uart_tx_start(void)
{
/* If interrupt is already enabled, nothing to do */
- if (MCHP_UART_IER(0) & BIT(1))
+ if (MCHP_UART_IER(CONFIG_UART_CONSOLE) & BIT(1))
return;
/* Do not allow deep sleep while transmit in progress */
@@ -42,13 +77,13 @@ void uart_tx_start(void)
* UART where the FIFO only triggers the interrupt when its
* threshold is _crossed_, not just met.
*/
- MCHP_UART_IER(0) |= BIT(1);
- task_trigger_irq(MCHP_IRQ_UART0);
+ MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(1);
+ task_trigger_irq(UART_IRQ);
}
void uart_tx_stop(void)
{
- MCHP_UART_IER(0) &= ~BIT(1);
+ MCHP_UART_IER(CONFIG_UART_CONSOLE) &= ~BIT(1);
/* Re-allow deep sleep */
enable_sleep(SLEEP_MASK_UART);
@@ -57,7 +92,7 @@ void uart_tx_stop(void)
void uart_tx_flush(void)
{
/* Wait for transmit FIFO empty */
- while (!(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY))
+ while (!(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY))
;
}
@@ -68,18 +103,18 @@ int uart_tx_ready(void)
* this, we check transmit FIFO empty bit every 16 characters written.
*/
return tx_fifo_used != 0 ||
- (MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY);
+ (MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
}
int uart_tx_in_progress(void)
{
/* return 0: FIFO is empty, 1: FIFO NOT Empty */
- return !(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY);
+ return !(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
}
int uart_rx_available(void)
{
- return MCHP_UART_LSR(0) & BIT(0);
+ return MCHP_UART_LSR(CONFIG_UART_CONSOLE) & BIT(0);
}
void uart_write_char(char c)
@@ -89,27 +124,27 @@ void uart_write_char(char c)
;
tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
- MCHP_UART_TB(0) = c;
+ MCHP_UART_TB(CONFIG_UART_CONSOLE) = c;
}
int uart_read_char(void)
{
- return MCHP_UART_RB(0);
+ return MCHP_UART_RB(CONFIG_UART_CONSOLE);
}
static void uart_clear_rx_fifo(int channel)
{
- MCHP_UART_FCR(0) = BIT(0) | BIT(1);
+ MCHP_UART_FCR(channel) = BIT(0) | BIT(1);
}
void uart_disable_interrupt(void)
{
- task_disable_irq(MCHP_IRQ_UART0);
+ task_disable_irq(UART_IRQ);
}
void uart_enable_interrupt(void)
{
- task_enable_irq(MCHP_IRQ_UART0);
+ task_enable_irq(UART_IRQ);
}
/**
@@ -123,51 +158,52 @@ void uart_ec_interrupt(void)
/* Trace statement to provide time marker for UART output? */
uart_process_output();
}
-DECLARE_IRQ(MCHP_IRQ_UART0, uart_ec_interrupt, 2);
+DECLARE_IRQ(UART_IRQ, uart_ec_interrupt, 2);
void uart_init(void)
{
/* Clear UART PCR sleep enable */
- MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0);
+ MCHP_PCR_SLP_DIS_DEV(UART_PCR);
/* Set UART to reset on VCC1_RESET instead of nSIO_RESET */
- MCHP_UART_CFG(0) &= ~BIT(1);
+ MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(1);
/* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */
/* Set CLK_SRC = 0 */
- MCHP_UART_CFG(0) &= ~BIT(0);
+ MCHP_UART_CFG(CONFIG_UART_CONSOLE) &= ~BIT(0);
/* Set DLAB = 1 */
- MCHP_UART_LCR(0) |= BIT(7);
+ MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(7);
/* PBRG0/PBRG1 */
- MCHP_UART_PBRG0(0) = 1;
- MCHP_UART_PBRG1(0) = 0;
+ MCHP_UART_PBRG0(CONFIG_UART_CONSOLE) = 1;
+ MCHP_UART_PBRG1(CONFIG_UART_CONSOLE) = 0;
/* Set DLAB = 0 */
- MCHP_UART_LCR(0) &= ~BIT(7);
+ MCHP_UART_LCR(CONFIG_UART_CONSOLE) &= ~BIT(7);
/* Set word length to 8-bit */
- MCHP_UART_LCR(0) |= BIT(0) | BIT(1);
+ MCHP_UART_LCR(CONFIG_UART_CONSOLE) |= BIT(0) | BIT(1);
/* Enable FIFO */
- MCHP_UART_FCR(0) = BIT(0);
+ MCHP_UART_FCR(CONFIG_UART_CONSOLE) = BIT(0);
/* Activate UART */
- MCHP_UART_ACT(0) |= BIT(0);
+ MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
gpio_config_module(MODULE_UART, 1);
/*
- * Enable interrupts for UART0.
+ * Enable interrupts for UART
*/
- uart_clear_rx_fifo(0);
- MCHP_UART_IER(0) |= BIT(0);
- MCHP_UART_MCR(0) |= BIT(3);
- MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
+ uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
+ MCHP_UART_IER(CONFIG_UART_CONSOLE) |= BIT(0);
+ MCHP_UART_MCR(CONFIG_UART_CONSOLE) |= BIT(3);
+
+ MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
- task_enable_irq(MCHP_IRQ_UART0);
+ task_enable_irq(UART_IRQ);
init_done = 1;
}
@@ -176,25 +212,25 @@ void uart_init(void)
void uart_enter_dsleep(void)
{
/* Disable the UART interrupt. */
- task_disable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART=13 */
+ task_disable_irq(UART_IRQ); /* NVIC interrupt for UART=13 */
/*
* Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
* with the flags defined in the gpio.inc file.
*/
- gpio_reset(GPIO_UART0_RX);
+ gpio_reset(GPIO_UART_RX);
- /* power-down/de-activate UART0 */
- MCHP_UART_ACT(0) &= ~BIT(0);
+ /* power-down/deactivate UART */
+ MCHP_UART_ACT(CONFIG_UART_CONSOLE) &= ~BIT(0);
- /* clear interrupt enable for UART0 */
- MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
+ /* clear interrupt enable for UART */
+ MCHP_INT_DISABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
- /* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */
- MCHP_INT_SOURCE(9) = BIT(5);
+ /* Clear pending interrupts on UART RX pin */
+ MCHP_INT_SOURCE(UART_RX_PIN_GIRQ) = UART_RX_PIN_BIT;
/* Enable GPIO interrupts on the UART0 RX pin. */
- gpio_enable_interrupt(GPIO_UART0_RX);
+ gpio_enable_interrupt(GPIO_UART_RX);
}
@@ -208,19 +244,19 @@ void uart_exit_dsleep(void)
* because then the IRQ will not run at all.
*/
if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */
- gpio_disable_interrupt(GPIO_UART0_RX);
+ gpio_disable_interrupt(GPIO_UART_RX);
/* Configure UART0 pins for use in UART peripheral. */
gpio_config_module(MODULE_UART, 1);
/* Clear pending interrupts on UART peripheral and enable interrupts. */
- uart_clear_rx_fifo(0);
- MCHP_INT_SOURCE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
- MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0);
- task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */
+ uart_clear_rx_fifo(CONFIG_UART_CONSOLE);
+ MCHP_INT_SOURCE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
+ MCHP_INT_ENABLE(MCHP_UART_GIRQ) = UART_IRQ_BIT;
+ task_enable_irq(UART_IRQ);
/* power-up/activate UART0 */
- MCHP_UART_ACT(0) |= BIT(0);
+ MCHP_UART_ACT(CONFIG_UART_CONSOLE) |= BIT(0);
}
void uart_deepsleep_interrupt(enum gpio_signal signal)
@@ -233,6 +269,6 @@ void uart_deepsleep_interrupt(enum gpio_signal signal)
clock_refresh_console_in_use();
/* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */
- gpio_disable_interrupt(GPIO_UART0_RX);
+ gpio_disable_interrupt(GPIO_UART_RX);
}
#endif /* CONFIG_LOW_POWER_IDLE */
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