diff options
Diffstat (limited to 'chip/mt_scp/rv32i_common/registers.h')
| -rw-r--r-- | chip/mt_scp/rv32i_common/registers.h | 73 |
1 files changed, 2 insertions, 71 deletions
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index f4d03aa228..b19afe5e0d 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -17,15 +17,6 @@ /* clock control */ #define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) -/* clock source select */ -#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) -#define CLK_SW_SEL_26M 0 -#define CLK_SW_SEL_32K 1 -#define CLK_SW_SEL_ULPOSC2 2 -#define CLK_SW_SEL_ULPOSC1 3 -#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) -#define CLK_HIGH_EN BIT(1) /* ULPOSC */ -#define CLK_HIGH_CG BIT(2) /* system clock counter value */ #define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) #define CLK_SYS_VAL_MASK (0x3ff << 0) @@ -117,9 +108,6 @@ #define HIGH_CORE_AO BIT(4) #define HIGH_CORE_DIS_SUB BIT(5) #define HIGH_CORE_CG_AO BIT(6) -/* clock general control */ -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) -#define VREQ_PMIC_WRAP_SEL (0x2) /* system control */ #define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) @@ -212,22 +200,6 @@ /* external address: AP */ #define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ -/* OSC meter */ -#define TOPCK_BASE AP_REG_BASE -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) -#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16) -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN BIT(4) -#define CFG_FREQ_METER_ENABLE BIT(12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) /* AP GPIO */ #define AP_GPIO_BASE (AP_REG_BASE + 0x5000) #define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) @@ -236,49 +208,8 @@ #define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) #define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) #define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) -/* - * ULPOSC - * osc: 0 for ULPOSC1, 1 for ULPOSC2. - */ -#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) -#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) -#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8) -#define AP_ULPOSC_CON0(osc) \ - REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON1(osc) \ - REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON2(osc) \ - REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10) -/* - * AP_ULPOSC_CON0 - * bit0-6: calibration - * bit7-13: iband - * bit14-17: fband - * bit18-23: div - * bit24: cp_en - * bit25-31: reserved - */ -#define OSC_CALI_MASK 0x7f -#define OSC_IBAND_SHIFT 7 -#define OSC_FBAND_SHIFT 14 -#define OSC_DIV_SHIFT 18 -#define OSC_CP_EN BIT(24) -/* AP_ULPOSC_CON1 - * bit0-7: 32K calibration - * bit 8-15: rsv1 - * bit 16-23: rsv2 - * bit 24-25: mod - * bit26: div2_en - * bit27-31: reserved - */ -#define OSC_RSV1_SHIFT 8 -#define OSC_RSV2_SHIFT 16 -#define OSC_MOD_SHIFT 24 -#define OSC_DIV2_EN BIT(26) -/* AP_ULPOSC_CON2 - * bit0-7: bias - * bit8-31: reserved - */ + +#include "clock_regs.h" /* IRQ numbers */ #define SCP_IRQ_GIPC_IN0 0 |