diff options
Diffstat (limited to 'chip/mt_scp/rv32i_common')
23 files changed, 598 insertions, 602 deletions
diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk index ac7e13db77..eff299f98d 100644 --- a/chip/mt_scp/rv32i_common/build.mk +++ b/chip/mt_scp/rv32i_common/build.mk @@ -1,5 +1,5 @@ # -*- makefile -*- -# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Copyright 2020 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. # diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c index 62147590fe..b04f28ebae 100644 --- a/chip/mt_scp/rv32i_common/cache.c +++ b/chip/mt_scp/rv32i_common/cache.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,8 +33,9 @@ void cache_init(void) #pragma GCC unroll 16 for (i = 0; i < NR_MPU_ENTRIES; ++i) { if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) { - write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr | - mpu_entries[i].attribute); + write_csr(CSR_MPU_L(i), + mpu_entries[i].start_addr | + mpu_entries[i].attribute); write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr); mpu_en |= BIT(i); } @@ -47,7 +48,7 @@ void cache_init(void) set_csr(CSR_MCTREN, CSR_MCTREN_MPU); /* fence */ - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); } #ifdef DEBUG @@ -56,15 +57,11 @@ void cache_init(void) * D for D-cache * C for control transfer instructions (branch, jump, ret, interrupt, ...) */ -static enum { - PMU_SELECT_I = 0, - PMU_SELECT_D, - PMU_SELECT_C -} pmu_select; +static enum { PMU_SELECT_I = 0, PMU_SELECT_D, PMU_SELECT_C } pmu_select; -int command_enable_pmu(int argc, char **argv) +int command_enable_pmu(int argc, const char **argv) { - static const char * const selectors[] = { + static const char *const selectors[] = { [PMU_SELECT_I] = "I", [PMU_SELECT_D] = "D", [PMU_SELECT_C] = "C", @@ -87,9 +84,8 @@ int command_enable_pmu(int argc, char **argv) /* disable all PMU */ clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); /* reset cycle count */ write_csr(CSR_PMU_MCYCLE, 0); @@ -138,45 +134,43 @@ int command_enable_pmu(int argc, char **argv) /* enable all PMU */ set_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, - "[I | D | C]", "Enable PMU"); +DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, "[I | D | C]", + "Enable PMU"); -int command_disable_pmu(int argc, char **argv) +int command_disable_pmu(int argc, const char **argv) { clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, - NULL, "Disable PMU"); +DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, NULL, + "Disable PMU"); -int command_show_pmu(int argc, char **argv) +int command_show_pmu(int argc, const char **argv) { uint64_t val3, val4, val5; uint32_t p; val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) | - read_csr(CSR_PMU_MCYCLE); + read_csr(CSR_PMU_MCYCLE); ccprintf("cycles: %lld\n", val3); val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) | - read_csr(CSR_PMU_MINSTRET); + read_csr(CSR_PMU_MINSTRET); ccprintf("retired instructions: %lld\n", val3); val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER3); + read_csr(CSR_PMU_MHPMCOUNTER3); val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER4); + read_csr(CSR_PMU_MHPMCOUNTER4); val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER5); + read_csr(CSR_PMU_MHPMCOUNTER5); if (val3) p = val4 * 10000 / val3; @@ -199,8 +193,8 @@ int command_show_pmu(int argc, char **argv) case PMU_SELECT_C: ccprintf("control transfer instruction:\n"); ccprintf(" total: %lld\n", val3); - ccprintf(" miss-predict: %lld (%d.%d%%)\n", - val4, p / 100, p % 100); + ccprintf(" miss-predict: %lld (%d.%d%%)\n", val4, p / 100, + p % 100); ccprintf("interrupts: %lld\n", val5); break; } diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h index 13e5ad1a42..15572962ac 100644 --- a/chip/mt_scp/rv32i_common/cache.h +++ b/chip/mt_scp/rv32i_common/cache.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,23 +14,23 @@ /* rs1 0~31 register X0~X31 */ #define COP(rs1) (((rs1) << 15) | 0x400f) -#define COP_OP_BARRIER_ICACHE 0x0 -#define COP_OP_INVALIDATE_ICACHE 0x8 -#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9 +#define COP_OP_BARRIER_ICACHE 0x0 +#define COP_OP_INVALIDATE_ICACHE 0x8 +#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9 -#define COP_OP_BARRIER_DCACHE 0x10 -#define COP_OP_WRITEBACK_DCACHE 0x14 -#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15 -#define COP_OP_INVALIDATE_DCACHE 0x18 -#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19 +#define COP_OP_BARRIER_DCACHE 0x10 +#define COP_OP_WRITEBACK_DCACHE 0x14 +#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15 +#define COP_OP_INVALIDATE_DCACHE 0x18 +#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19 /* FLUSH = WRITEBACK + INVALIDATE */ -#define COP_OP_FLUSH_DCACHE 0x1C -#define COP_OP_FLUSH_DCACHE_ADDR 0x1D +#define COP_OP_FLUSH_DCACHE 0x1C +#define COP_OP_FLUSH_DCACHE_ADDR 0x1D static inline void cache_op_all(uint32_t op) { register int t0 asm("t0") = op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); + asm volatile(".word " STRINGIFY(COP(5))::"r"(t0)); } static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op) @@ -44,7 +44,7 @@ static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op) for (offset = 0; offset < length; offset += 4) { t0 = addr + offset + op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); + asm volatile(".word " STRINGIFY(COP(5))::"r"(t0)); } return EC_SUCCESS; @@ -132,9 +132,9 @@ struct mpu_entry { void cache_init(void); #ifdef DEBUG -int command_enable_pmu(int argc, char **argv); -int command_disable_pmu(int argc, char **argv); -int command_show_pmu(int argc, char **argv); +int command_enable_pmu(int argc, const char **argv); +int command_disable_pmu(int argc, const char **argv); +int command_show_pmu(int argc, const char **argv); #endif #endif /* #ifndef __CROS_EC_CACHE_H */ diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h index ac53d51732..775dd02461 100644 --- a/chip/mt_scp/rv32i_common/config_chip.h +++ b/chip/mt_scp/rv32i_common/config_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -10,10 +10,10 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_FW_INCLUDE_RO #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE 0 #define CONFIG_RW_MEM_OFF 0 diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h index 7c767d0592..88ea869cbd 100644 --- a/chip/mt_scp/rv32i_common/csr.h +++ b/chip/mt_scp/rv32i_common/csr.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,14 +22,14 @@ static inline uint32_t read_csr(uint32_t reg) static inline void write_csr(uint32_t reg, uint32_t val) { - asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val)); + asm volatile("csrw %0, %1" ::"i"(reg), "r"(val)); } static inline uint32_t set_csr(uint32_t reg, uint32_t bit) { uint32_t val; - asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); + asm volatile("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); return val; } @@ -37,75 +37,75 @@ static inline uint32_t clear_csr(uint32_t reg, uint32_t bit) { uint32_t val; - asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); + asm volatile("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); return val; } /* VIC */ -#define CSR_VIC_MICAUSE (0x5c0) -#define CSR_VIC_MIEMS (0x5c2) -#define CSR_VIC_MIPEND_G0 (0x5d0) -#define CSR_VIC_MIMASK_G0 (0x5d8) -#define CSR_VIC_MIWAKEUP_G0 (0x5e0) -#define CSR_VIC_MILSEL_G0 (0x5e8) -#define CSR_VIC_MIEMASK_G0 (0x5f0) +#define CSR_VIC_MICAUSE (0x5c0) +#define CSR_VIC_MIEMS (0x5c2) +#define CSR_VIC_MIPEND_G0 (0x5d0) +#define CSR_VIC_MIMASK_G0 (0x5d8) +#define CSR_VIC_MIWAKEUP_G0 (0x5e0) +#define CSR_VIC_MILSEL_G0 (0x5e8) +#define CSR_VIC_MIEMASK_G0 (0x5f0) /* centralized control enable */ -#define CSR_MCTREN (0x7c0) +#define CSR_MCTREN (0x7c0) /* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */ -#define CSR_MCTREN_ICACHE BIT(0) -#define CSR_MCTREN_DCACHE BIT(1) -#define CSR_MCTREN_ITCM BIT(2) -#define CSR_MCTREN_DTCM BIT(3) -#define CSR_MCTREN_BTB BIT(4) -#define CSR_MCTREN_RAS BIT(5) -#define CSR_MCTREN_VIC BIT(6) -#define CSR_MCTREN_CG BIT(7) -#define CSR_MCTREN_MPU BIT(8) +#define CSR_MCTREN_ICACHE BIT(0) +#define CSR_MCTREN_DCACHE BIT(1) +#define CSR_MCTREN_ITCM BIT(2) +#define CSR_MCTREN_DTCM BIT(3) +#define CSR_MCTREN_BTB BIT(4) +#define CSR_MCTREN_RAS BIT(5) +#define CSR_MCTREN_VIC BIT(6) +#define CSR_MCTREN_CG BIT(7) +#define CSR_MCTREN_MPU BIT(8) /* MPU */ -#define CSR_MPU_ENTRY_EN (0x9c0) -#define CSR_MPU_LITCM (0x9dc) -#define CSR_MPU_LDTCM (0x9dd) -#define CSR_MPU_HITCM (0x9de) -#define CSR_MPU_HDTCM (0x9df) -#define CSR_MPU_L(n) (0x9e0 + (n)) -#define CSR_MPU_H(n) (0x9f0 + (n)) +#define CSR_MPU_ENTRY_EN (0x9c0) +#define CSR_MPU_LITCM (0x9dc) +#define CSR_MPU_LDTCM (0x9dd) +#define CSR_MPU_HITCM (0x9de) +#define CSR_MPU_HDTCM (0x9df) +#define CSR_MPU_L(n) (0x9e0 + (n)) +#define CSR_MPU_H(n) (0x9f0 + (n)) /* MPU attributes: set if permitted */ /* Privilege, machine mode in RISC-V. We don't use the flag because * we don't separate user / machine mode in EC OS. */ -#define MPU_ATTR_P BIT(5) +#define MPU_ATTR_P BIT(5) /* Readable */ -#define MPU_ATTR_R BIT(6) +#define MPU_ATTR_R BIT(6) /* Writable */ -#define MPU_ATTR_W BIT(7) +#define MPU_ATTR_W BIT(7) /* Cacheable */ -#define MPU_ATTR_C BIT(8) +#define MPU_ATTR_C BIT(8) /* Bufferable */ -#define MPU_ATTR_B BIT(9) +#define MPU_ATTR_B BIT(9) /* PMU */ -#define CSR_PMU_MPMUCTR (0xbc0) -#define CSR_PMU_MPMUCTR_C BIT(0) -#define CSR_PMU_MPMUCTR_I BIT(1) -#define CSR_PMU_MPMUCTR_H3 BIT(2) -#define CSR_PMU_MPMUCTR_H4 BIT(3) -#define CSR_PMU_MPMUCTR_H5 BIT(4) - -#define CSR_PMU_MCYCLE (0xb00) -#define CSR_PMU_MINSTRET (0xb02) -#define CSR_PMU_MHPMCOUNTER3 (0xb03) -#define CSR_PMU_MHPMCOUNTER4 (0xb04) -#define CSR_PMU_MHPMCOUNTER5 (0xb05) - -#define CSR_PMU_MCYCLEH (0xb80) -#define CSR_PMU_MINSTRETH (0xb82) -#define CSR_PMU_MHPMCOUNTER3H (0xb83) -#define CSR_PMU_MHPMCOUNTER4H (0xb84) -#define CSR_PMU_MHPMCOUNTER5H (0xb85) - -#define CSR_PMU_MHPMEVENT3 (0x323) -#define CSR_PMU_MHPMEVENT4 (0x324) -#define CSR_PMU_MHPMEVENT5 (0x325) +#define CSR_PMU_MPMUCTR (0xbc0) +#define CSR_PMU_MPMUCTR_C BIT(0) +#define CSR_PMU_MPMUCTR_I BIT(1) +#define CSR_PMU_MPMUCTR_H3 BIT(2) +#define CSR_PMU_MPMUCTR_H4 BIT(3) +#define CSR_PMU_MPMUCTR_H5 BIT(4) + +#define CSR_PMU_MCYCLE (0xb00) +#define CSR_PMU_MINSTRET (0xb02) +#define CSR_PMU_MHPMCOUNTER3 (0xb03) +#define CSR_PMU_MHPMCOUNTER4 (0xb04) +#define CSR_PMU_MHPMCOUNTER5 (0xb05) + +#define CSR_PMU_MCYCLEH (0xb80) +#define CSR_PMU_MINSTRETH (0xb82) +#define CSR_PMU_MHPMCOUNTER3H (0xb83) +#define CSR_PMU_MHPMCOUNTER4H (0xb84) +#define CSR_PMU_MHPMCOUNTER5H (0xb85) + +#define CSR_PMU_MHPMEVENT3 (0x323) +#define CSR_PMU_MHPMEVENT4 (0x324) +#define CSR_PMU_MHPMEVENT5 (0x325) #endif /* __CROS_EC_CSR_H */ diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c index 0ca3e3ac25..d56cff97fb 100644 --- a/chip/mt_scp/rv32i_common/gpio.c +++ b/chip/mt_scp/rv32i_common/gpio.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c index 42a463ee56..fee1ce110a 100644 --- a/chip/mt_scp/rv32i_common/hostcmd.c +++ b/chip/mt_scp/rv32i_common/hostcmd.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -97,7 +97,8 @@ DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0); /* * Get protocol information */ -static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args) +static enum ec_status +hostcmd_get_protocol_info(struct host_cmd_handler_args *args) { struct ec_response_get_protocol_info *r = args->response; diff --git a/chip/mt_scp/rv32i_common/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h index b93f1e725d..067a4c14ab 100644 --- a/chip/mt_scp/rv32i_common/hostcmd.h +++ b/chip/mt_scp/rv32i_common/hostcmd.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c index a844527494..fff5fb6436 100644 --- a/chip/mt_scp/rv32i_common/hrtimer.c +++ b/chip/mt_scp/rv32i_common/hrtimer.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -65,8 +65,8 @@ static void timer_set_reset_value(int n, uint32_t reset_value) static void timer_set_clock(int n, uint32_t clock_source) { - SCP_CORE0_TIMER_EN(n) = - (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source; + SCP_CORE0_TIMER_EN(n) = (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | + clock_source; } static void timer_reset(int n) @@ -88,8 +88,8 @@ static uint64_t timer_read_raw_system(void) * sys_high value. */ if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) - : (TIMER_CLOCK_MHZ - 1); + sys_high_adj = sys_high ? (sys_high - 1) : + (TIMER_CLOCK_MHZ - 1); return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM)); @@ -159,8 +159,8 @@ uint32_t __hw_clock_source_read(void) uint32_t __hw_clock_event_get(void) { - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; + return (timer_read_raw_event() + timer_read_raw_system()) / + TIMER_CLOCK_MHZ; } void __hw_clock_event_clear(void) diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c index 606f487ed5..641d0cf516 100644 --- a/chip/mt_scp/rv32i_common/intc.c +++ b/chip/mt_scp/rv32i_common/intc.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -39,114 +39,114 @@ static struct { uint8_t group; } irqs[SCP_INTC_IRQ_COUNT] = { /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, + [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, + [SCP_IRQ_SPM] = { INTC_GRP_0 }, + [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_EINT] = { INTC_GRP_0 }, + [SCP_IRQ_PMIC] = { INTC_GRP_0 }, /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, + [SCP_IRQ_I2C0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, + [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, + [SCP_IRQ_VOW] = { INTC_GRP_0 }, + [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, + [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, + [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_GDMA] = { INTC_GRP_0 }, + [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, + [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, + [SCP_IRQ_ADSP] = { INTC_GRP_0 }, /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, + [SCP_IRQ_SPI0] = { INTC_GRP_0 }, + [SCP_IRQ_SPI1] = { INTC_GRP_0 }, + [SCP_IRQ_SPI2] = { INTC_GRP_0 }, /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF0] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF1] = { INTC_GRP_0 }, + [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_DBG] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF0] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF1] = { INTC_GRP_0 }, /* 36 */ - [SCP_IRQ_CCIF2] = { INTC_GRP_0 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_USB0] = { INTC_GRP_0 }, - [SCP_IRQ_USB1] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF2] = { INTC_GRP_0 }, + [SCP_IRQ_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_USB0] = { INTC_GRP_0 }, + [SCP_IRQ_USB1] = { INTC_GRP_0 }, /* 40 */ - [SCP_IRQ_DPMAIF] = { INTC_GRP_0 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_DPMAIF] = { INTC_GRP_0 }, + [SCP_IRQ_INFRA] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, + [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, + [SCP_IRQ_MET0] = { INTC_GRP_0 }, + [SCP_IRQ_MET1] = { INTC_GRP_0 }, + [SCP_IRQ_MET2] = { INTC_GRP_0 }, + [SCP_IRQ_MET3] = { INTC_GRP_0 }, /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 }, - [SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 }, + [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 }, + [SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 }, /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, /* 72 */ /* 76 */ - [SCP_IRQ_I2C1_2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C2] = { INTC_GRP_0 }, /* 80 */ - [SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 }, - [SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 }, + [SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 }, + [SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 }, /* 84 */ - [SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 }, - [SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 }, + [SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 }, /* 88 */ - [SCP_IRQ_CCIF3] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF3] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 }, /* 92 */ - [SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 }, }; BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); #endif @@ -156,153 +156,153 @@ static struct { uint8_t group; } irqs[SCP_INTC_IRQ_COUNT] = { /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, + [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, + [SCP_IRQ_SPM] = { INTC_GRP_0 }, + [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_EINT] = { INTC_GRP_0 }, + [SCP_IRQ_PMIC] = { INTC_GRP_0 }, /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, + [SCP_IRQ_I2C0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, + [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, + [SCP_IRQ_VOW] = { INTC_GRP_0 }, + [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, + [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, + [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_GDMA] = { INTC_GRP_0 }, + [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, + [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, + [SCP_IRQ_ADSP] = { INTC_GRP_0 }, /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, + [SCP_IRQ_SPI0] = { INTC_GRP_0 }, + [SCP_IRQ_SPI1] = { INTC_GRP_0 }, + [SCP_IRQ_SPI2] = { INTC_GRP_0 }, /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_GCE] = { INTC_GRP_0 }, - [SCP_IRQ_MDP_GCE] = { INTC_GRP_0 }, + [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_DBG] = { INTC_GRP_0 }, + [SCP_IRQ_GCE] = { INTC_GRP_0 }, + [SCP_IRQ_MDP_GCE] = { INTC_GRP_0 }, /* 36 */ - [SCP_IRQ_VDEC] = { INTC_GRP_8 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_VDEC1] = { INTC_GRP_8 }, + [SCP_IRQ_VDEC] = { INTC_GRP_8 }, + [SCP_IRQ_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 }, + [SCP_IRQ_VDEC1] = { INTC_GRP_8 }, /* 40 */ - [SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 }, + [SCP_IRQ_INFRA] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, + [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, + [SCP_IRQ_MET0] = { INTC_GRP_0 }, + [SCP_IRQ_MET1] = { INTC_GRP_0 }, + [SCP_IRQ_MET2] = { INTC_GRP_0 }, + [SCP_IRQ_MET3] = { INTC_GRP_0 }, /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 }, - [SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 }, + [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 }, + [SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 }, /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_VENC] = { INTC_GRP_8 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_VENC] = { INTC_GRP_8 }, + [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, + [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, /* 72 */ - [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, /* 76 */ - [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, - [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_1] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_0] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_1] = { INTC_GRP_0 }, /* 80 */ - [SCP_IRQ_NNA0_2] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_1] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_2] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_2] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_0] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_1] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_2] = { INTC_GRP_0 }, /* 84 */ - [SCP_IRQ_JPEGENC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 }, - [SCP_IRQ_VENC_C1] = { INTC_GRP_8 }, + [SCP_IRQ_JPEGENC] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 }, + [SCP_IRQ_VENC_C1] = { INTC_GRP_8 }, /* 88 */ - [SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_HDMITX] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 }, + [SCP_IRQ_HDMITX] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, /* 92 */ - [SCP_IRQ_EARC] = { INTC_GRP_0 }, - [SCP_IRQ_CEC] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, - [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, + [SCP_IRQ_EARC] = { INTC_GRP_0 }, + [SCP_IRQ_CEC] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, /* 96 */ - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C3] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I2C2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C3] = { INTC_GRP_0 }, + [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 }, /* 100 */ - [SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 }, /* 104 */ - [SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 }, /* 108 */ - [SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 }, /* 112 */ - [SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 }, /* 116 */ - [SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 }, - [SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 }, + [SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 }, + [SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 }, }; BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); #endif diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c index a7fc720d42..b8db16b9ea 100644 --- a/chip/mt_scp/rv32i_common/ipi.c +++ b/chip/mt_scp/rv32i_common/ipi.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -177,7 +177,7 @@ static void irq_group7_handler(void) if (SCP_GIPC_IN_SET & GIPC_IN(0)) { ipi_handler(); SCP_GIPC_IN_CLR = GIPC_IN(0); - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); } } diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h index 47a9434b09..22ab85b39e 100644 --- a/chip/mt_scp/rv32i_common/ipi_chip.h +++ b/chip/mt_scp/rv32i_common/ipi_chip.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -72,15 +72,15 @@ extern int *const ipi_wakeup_table[]; * handler: The IPI handler function * is_wakeup_src: Declare IPI ID as a wake-up source or not */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int tmp1[_id < IPI_COUNT ? 1 : -1]; \ +#define DECLARE_IPI(_id, handler, is_wakeup_src) \ + struct ipi_num_check##_id { \ + int tmp1[_id < IPI_COUNT ? 1 : -1]; \ int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ + }; \ + void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ + { \ + handler(id, buf, len); \ + } \ const int __keep IPI_WAKEUP(_id) = is_wakeup_src #endif /* __CROS_EC_IPI_CHIP_H */ diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c index 8fe3f1e598..3a6411d4d2 100644 --- a/chip/mt_scp/rv32i_common/ipi_table.c +++ b/chip/mt_scp/rv32i_common/ipi_table.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -17,21 +17,24 @@ typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); #define ipi_arguments int32_t id, void *data, uint32_t len #if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } +void ipi_handler_undefined(ipi_arguments) +{ +} const int ipi_wakeup_undefined; #define table(type, name, x) x -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ +#define ipi_x_func(suffix, args, number) \ + extern void \ + __attribute__((used, weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ ipi_##number##_##suffix(args); #define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; + extern int __attribute__((weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ + ipi_##number##_##suffix; #endif /* PASS == 1 */ @@ -41,11 +44,11 @@ const int ipi_wakeup_undefined; #undef ipi_x_func #undef ipi_x_var -#define table(type, name, x) \ - type const name[] \ - __attribute__((aligned(4), used, section(".rodata.ipi"))) = {x} +#define table(type, name, x) \ + type const name[] __attribute__((aligned(4), used, \ + section(".rodata.ipi"))) = { x } -#define ipi_x_var(suffix, number) \ +#define ipi_x_var(suffix, number) \ [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, #define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c index a666bb23d7..8ae64cf585 100644 --- a/chip/mt_scp/rv32i_common/memmap.c +++ b/chip/mt_scp/rv32i_common/memmap.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -33,53 +33,48 @@ * 0xf000_0000 0x6000_0000 */ -#define REMAP_ADDR_SHIFT 28 -#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1) -#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT) +#define REMAP_ADDR_SHIFT 28 +#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1) +#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT) #define MAP_INVALID 0xff static const uint8_t addr_map[16] = { - MAP_INVALID, /* SRAM */ - 0x5, /* ext_addr_0x1 */ - 0x7, /* ext_addr_0x2 */ - MAP_INVALID, /* no ext_addr_0x3 */ - - MAP_INVALID, /* no ext_addr_0x4 */ - 0x0, /* ext_addr_0x5 */ - 0x1, /* ext_addr_0x6 */ - 0xa, /* ext_addr_0x7 */ - - MAP_INVALID, /* no ext_addr_0x8 */ - 0x8, /* ext_addr_0x9 */ - 0x9, /* ext_addr_0xa */ - MAP_INVALID, /* no ext_addr_0xb */ - - 0x8, /* ext_addr_0xc */ - 0x2, /* ext_addr_0xd */ - 0x3, /* ext_addr_0xe */ - 0x6, /* ext_addr_0xf */ + MAP_INVALID, /* SRAM */ + 0x5, /* ext_addr_0x1 */ + 0x7, /* ext_addr_0x2 */ + MAP_INVALID, /* no ext_addr_0x3 */ + + MAP_INVALID, /* no ext_addr_0x4 */ + 0x0, /* ext_addr_0x5 */ + 0x1, /* ext_addr_0x6 */ + 0xa, /* ext_addr_0x7 */ + + MAP_INVALID, /* no ext_addr_0x8 */ + 0x8, /* ext_addr_0x9 */ + 0x9, /* ext_addr_0xa */ + MAP_INVALID, /* no ext_addr_0xb */ + + 0x8, /* ext_addr_0xc */ + 0x2, /* ext_addr_0xd */ + 0x3, /* ext_addr_0xe */ + 0x6, /* ext_addr_0xf */ }; void memmap_init(void) { - SCP_R_REMAP_0X0123 = - (uint32_t)addr_map[0x1] << 8 | - (uint32_t)addr_map[0x2] << 16; + SCP_R_REMAP_0X0123 = (uint32_t)addr_map[0x1] << 8 | + (uint32_t)addr_map[0x2] << 16; - SCP_R_REMAP_0X4567 = - (uint32_t)addr_map[0x5] << 8 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x7] << 24; + SCP_R_REMAP_0X4567 = (uint32_t)addr_map[0x5] << 8 | + (uint32_t)addr_map[0x6] << 16 | + (uint32_t)addr_map[0x7] << 24; - SCP_R_REMAP_0X89AB = - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0xa] << 16; + SCP_R_REMAP_0X89AB = (uint32_t)addr_map[0x9] << 8 | + (uint32_t)addr_map[0xa] << 16; SCP_R_REMAP_0XCDEF = - (uint32_t)addr_map[0xc] | - (uint32_t)addr_map[0xd] << 8 | - (uint32_t)addr_map[0xe] << 16 | - (uint32_t)addr_map[0xf] << 24; + (uint32_t)addr_map[0xc] | (uint32_t)addr_map[0xd] << 8 | + (uint32_t)addr_map[0xe] << 16 | (uint32_t)addr_map[0xf] << 24; cache_init(); } @@ -94,7 +89,7 @@ int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) continue; *scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) | - (i << REMAP_ADDR_SHIFT); + (i << REMAP_ADDR_SHIFT); return EC_SUCCESS; } @@ -109,6 +104,6 @@ int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) return EC_ERROR_INVAL; *ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) | - (addr_map[i] << REMAP_ADDR_SHIFT); + (addr_map[i] << REMAP_ADDR_SHIFT); return EC_SUCCESS; } diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h index 0857c9a89e..2c043fbe9c 100644 --- a/chip/mt_scp/rv32i_common/memmap.h +++ b/chip/mt_scp/rv32i_common/memmap.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index afe706948e..8688bbc033 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -14,200 +14,202 @@ #define UNIMPLEMENTED_GPIO_BANK 0 -#define SCP_REG_BASE 0x70000000 +#define SCP_REG_BASE 0x70000000 /* clock control */ -#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) +#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) /* system clock counter value */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) -#define CLK_SYS_VAL_MASK (0x3ff << 0) -#define CLK_SYS_VAL_VAL(v) ((v) & CLK_SYS_VAL_MASK) +#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) +#define CLK_SYS_VAL_MASK (0x3ff << 0) +#define CLK_SYS_VAL_VAL(v) ((v)&CLK_SYS_VAL_MASK) /* ULPOSC clock counter value */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018) -#define CLK_HIGH_VAL_MASK (0x1f << 0) -#define CLK_HIGH_VAL_VAL(v) ((v) & CLK_HIGH_VAL_MASK) +#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018) +#define CLK_HIGH_VAL_MASK (0x1f << 0) +#define CLK_HIGH_VAL_VAL(v) ((v)&CLK_HIGH_VAL_MASK) /* sleep mode control */ -#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020) -#define SLP_CTRL_EN BIT(0) -#define VREQ_COUNT_MASK (0x7F << 1) -#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK) -#define SPM_SLP_MODE BIT(8) +#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020) +#define SLP_CTRL_EN BIT(0) +#define VREQ_COUNT_MASK (0x7F << 1) +#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK) +#define SPM_SLP_MODE BIT(8) /* clock divider select */ -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024) -#define CLK_DIV_SEL1 0 -#define CLK_DIV_SEL2 1 -#define CLK_DIV_SEL4 2 -#define CLK_DIV_SEL3 3 +#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024) +#define CLK_DIV_SEL1 0 +#define CLK_DIV_SEL2 1 +#define CLK_DIV_SEL4 2 +#define CLK_DIV_SEL3 3 /* clock gate */ -#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030) -#define CG_TIMER_MCLK BIT(0) -#define CG_TIMER_BCLK BIT(1) -#define CG_MAD_MCLK BIT(2) -#define CG_I2C_MCLK BIT(3) -#define CG_I2C_BCLK BIT(4) -#define CG_GPIO_MCLK BIT(5) -#define CG_AP2P_MCLK BIT(6) -#define CG_UART0_MCLK BIT(7) -#define CG_UART0_BCLK BIT(8) -#define CG_UART0_RST BIT(9) -#define CG_UART1_MCLK BIT(10) -#define CG_UART1_BCLK BIT(11) -#define CG_UART1_RST BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_I3C0 BIT(21) -#define CG_I3C1 BIT(22) -#define CG_DMA2_CH0 BIT(23) -#define CG_DMA2_CH1 BIT(24) -#define CG_DMA2_CH2 BIT(25) -#define CG_DMA2_CH3 BIT(26) +#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030) +#define CG_TIMER_MCLK BIT(0) +#define CG_TIMER_BCLK BIT(1) +#define CG_MAD_MCLK BIT(2) +#define CG_I2C_MCLK BIT(3) +#define CG_I2C_BCLK BIT(4) +#define CG_GPIO_MCLK BIT(5) +#define CG_AP2P_MCLK BIT(6) +#define CG_UART0_MCLK BIT(7) +#define CG_UART0_BCLK BIT(8) +#define CG_UART0_RST BIT(9) +#define CG_UART1_MCLK BIT(10) +#define CG_UART1_BCLK BIT(11) +#define CG_UART1_RST BIT(12) +#define CG_SPI0 BIT(13) +#define CG_SPI1 BIT(14) +#define CG_SPI2 BIT(15) +#define CG_DMA_CH0 BIT(16) +#define CG_DMA_CH1 BIT(17) +#define CG_DMA_CH2 BIT(18) +#define CG_DMA_CH3 BIT(19) +#define CG_I3C0 BIT(21) +#define CG_I3C1 BIT(22) +#define CG_DMA2_CH0 BIT(23) +#define CG_DMA2_CH1 BIT(24) +#define CG_DMA2_CH2 BIT(25) +#define CG_DMA2_CH3 BIT(26) /* UART clock select */ -#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044) -#define UART0_CK_SEL_SHIFT 0 -#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT) -#define UART0_CK_SEL_VAL(v) ((v) & UART0_CK_SEL_MASK) -#define UART0_CK_SW_STATUS_MASK (0xf << 8) -#define UART0_CK_SW_STATUS_VAL(v) ((v) & UART0_CK_SW_STATUS_MASK) -#define UART1_CK_SEL_SHIFT 16 -#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT) -#define UART1_CK_SEL_VAL(v) ((v) & UART1_CK_SEL_MASK) -#define UART1_CK_SW_STATUS_MASK (0xf << 24) -#define UART1_CK_SW_STATUS_VAL(v) ((v) & UART1_CK_SW_STATUS_MASK) -#define UART_CK_SEL_26M 0 -#define UART_CK_SEL_32K 1 -#define UART_CK_SEL_ULPOSC 2 -#define UART_CK_SW_STATUS_26M BIT(0) -#define UART_CK_SW_STATUS_32K BIT(1) -#define UART_CK_SW_STATUS_ULPOS BIT(2) +#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044) +#define UART0_CK_SEL_SHIFT 0 +#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT) +#define UART0_CK_SEL_VAL(v) ((v)&UART0_CK_SEL_MASK) +#define UART0_CK_SW_STATUS_MASK (0xf << 8) +#define UART0_CK_SW_STATUS_VAL(v) ((v)&UART0_CK_SW_STATUS_MASK) +#define UART1_CK_SEL_SHIFT 16 +#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT) +#define UART1_CK_SEL_VAL(v) ((v)&UART1_CK_SEL_MASK) +#define UART1_CK_SW_STATUS_MASK (0xf << 24) +#define UART1_CK_SW_STATUS_VAL(v) ((v)&UART1_CK_SW_STATUS_MASK) +#define UART_CK_SEL_26M 0 +#define UART_CK_SEL_32K 1 +#define UART_CK_SEL_ULPOSC 2 +#define UART_CK_SW_STATUS_26M BIT(0) +#define UART_CK_SW_STATUS_32K BIT(1) +#define UART_CK_SW_STATUS_ULPOS BIT(2) /* BCLK clock select */ -#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) -#define BCLK_CK_SEL_SYS_DIV8 0 -#define BCLK_CK_SEL_32K 1 -#define BCLK_CK_SEL_ULPOSC_DIV8 2 +#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) +#define BCLK_CK_SEL_SYS_DIV8 0 +#define BCLK_CK_SEL_32K 1 +#define BCLK_CK_SEL_ULPOSC_DIV8 2 /* VREQ control */ -#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) -#define VREQ_SEL BIT(0) -#define VREQ_VALUE BIT(4) -#define VREQ_EXT_SEL BIT(8) -#define VREQ_DVFS_SEL BIT(16) -#define VREQ_DVFS_VALUE BIT(20) -#define VREQ_DVFS_EXT_SEL BIT(24) -#define VREQ_SRCLKEN_SEL BIT(27) -#define VREQ_SRCLKEN_VALUE BIT(28) +#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) +#define VREQ_SEL BIT(0) +#define VREQ_VALUE BIT(4) +#define VREQ_EXT_SEL BIT(8) +#define VREQ_DVFS_SEL BIT(16) +#define VREQ_DVFS_VALUE BIT(20) +#define VREQ_DVFS_EXT_SEL BIT(24) +#define VREQ_SRCLKEN_SEL BIT(27) +#define VREQ_SRCLKEN_VALUE BIT(28) /* clock on control */ -#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C) -#define HIGH_CORE_CG BIT(1) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C) -#define HIGH_AO BIT(0) -#define HIGH_DIS_SUB BIT(1) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) +#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C) +#define HIGH_CORE_CG BIT(1) +#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C) +#define HIGH_AO BIT(0) +#define HIGH_DIS_SUB BIT(1) +#define HIGH_CG_AO BIT(2) +#define HIGH_CORE_AO BIT(4) +#define HIGH_CORE_DIS_SUB BIT(5) +#define HIGH_CORE_CG_AO BIT(6) /* system control */ -#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) -#define AUTO_DDREN BIT(9) +#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) +#define AUTO_DDREN BIT(9) /* IPC */ -#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080) -#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090) -#define IPC_SCP2HOST BIT(0) -#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098) -#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C) -#define GIPC_IN(n) BIT(n) +#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080) +#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090) +#define IPC_SCP2HOST BIT(0) +#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098) +#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C) +#define GIPC_IN(n) BIT(n) /* UART */ -#define SCP_UART_COUNT 2 -#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) -#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000) -#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000) -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] +#define SCP_UART_COUNT 2 +#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX) +#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) +#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000) +#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000) +#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) +#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] /* WDT */ -#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030) -#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034) -#define WDT_FREQ 33825 /* 0xFFFFF / 31 */ -#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000) -#define WDT_EN BIT(31) -#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) -#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) -#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0) -#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4) -#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8) +#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030) +#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034) +#define WDT_FREQ 33825 /* 0xFFFFF / 31 */ +#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ +#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000) +#define WDT_EN BIT(31) +#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) +#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) +#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0) +#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4) +#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8) /* INTC */ -#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ -#define SCP_INTC_BIT(irq) ((irq) & 0x1F) /* bit shift =LSB[0:4] */ -#define SCP_INTC_GRP_COUNT 15 -#define SCP_INTC_GRP_GAP 4 +#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ +#define SCP_INTC_BIT(irq) ((irq)&0x1F) /* bit shift =LSB[0:4] */ +#define SCP_INTC_GRP_COUNT 15 +#define SCP_INTC_GRP_GAP 4 -#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000) +#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000) #define SCP_CORE0_INTC_IRQ_STA(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)] #define SCP_CORE0_INTC_IRQ_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)] #define SCP_CORE0_INTC_IRQ_POL(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)] -#define SCP_CORE0_INTC_IRQ_GRP(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] -#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)] +#define SCP_CORE0_INTC_IRQ_GRP(g, w) \ + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \ + ((g) << SCP_INTC_GRP_GAP)) \ + [(w)] +#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \ + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \ + ((g) << SCP_INTC_GRP_GAP)) \ + [(w)] #define SCP_CORE0_INTC_SLP_WAKE_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)] -#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250) + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)] +#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250) /* UART */ -#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258) -#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C) -#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ) +#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258) +#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C) +#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ) /* XGPT (general purpose timer) */ -#define NUM_TIMERS 6 -#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n))) -#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000) -#define TIMER_EN BIT(0) -#define TIMER_CLK_SRC_32K (0 << 4) -#define TIMER_CLK_SRC_26M (1 << 4) -#define TIMER_CLK_SRC_BCLK (2 << 4) -#define TIMER_CLK_SRC_MCLK (3 << 4) -#define TIMER_CLK_SRC_MASK (3 << 4) -#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004) -#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008) -#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C) -#define TIMER_IRQ_EN BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLR BIT(5) -#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) +#define NUM_TIMERS 6 +#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n))) +#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000) +#define TIMER_EN BIT(0) +#define TIMER_CLK_SRC_32K (0 << 4) +#define TIMER_CLK_SRC_26M (1 << 4) +#define TIMER_CLK_SRC_BCLK (2 << 4) +#define TIMER_CLK_SRC_MCLK (3 << 4) +#define TIMER_CLK_SRC_MASK (3 << 4) +#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004) +#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008) +#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C) +#define TIMER_IRQ_EN BIT(0) +#define TIMER_IRQ_STATUS BIT(4) +#define TIMER_IRQ_CLR BIT(5) +#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) /* secure control */ -#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000) -#define VREQ_SECURE_DIS BIT(4) +#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000) +#define VREQ_SECURE_DIS BIT(4) /* memory remap */ -#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060) -#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064) -#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068) -#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C) +#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060) +#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064) +#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068) +#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C) /* external address: AP */ -#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ +#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ /* AP GPIO */ -#define AP_GPIO_BASE (AP_REG_BASE + 0x5000) -#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) -#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) -#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) -#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) -#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) -#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) +#define AP_GPIO_BASE (AP_REG_BASE + 0x5000) +#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) +#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) +#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) +#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) +#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) +#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) #include "clock_regs.h" diff --git a/chip/mt_scp/rv32i_common/scp_timer.h b/chip/mt_scp/rv32i_common/scp_timer.h index 5c0650f913..1eed1d7792 100644 --- a/chip/mt_scp/rv32i_common/scp_timer.h +++ b/chip/mt_scp/rv32i_common/scp_timer.h @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/scp_watchdog.h b/chip/mt_scp/rv32i_common/scp_watchdog.h index 87309a2f82..2a8225c047 100644 --- a/chip/mt_scp/rv32i_common/scp_watchdog.h +++ b/chip/mt_scp/rv32i_common/scp_watchdog.h @@ -1,5 +1,5 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c index 0e12154f6d..0eed2ae3ff 100644 --- a/chip/mt_scp/rv32i_common/system.c +++ b/chip/mt_scp/rv32i_common/system.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c index 35b4003c9f..a67a0bb276 100644 --- a/chip/mt_scp/rv32i_common/uart.c +++ b/chip/mt_scp/rv32i_common/uart.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -31,9 +31,8 @@ void uart_init(void) uart_init_pinmux(); /* Clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; + UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT; /* Line control: parity none, 8 bit, 1 stop bit */ UART_LCR(UARTN) = UART_LCR_WLEN8; /* For baud rate <= 115200 */ @@ -137,7 +136,7 @@ static void uart_irq_handler(void) case UART_RX_IRQ(UARTN): uart_process(); SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0); - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); break; } diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h index c88b9c758b..d0eeaa81c2 100644 --- a/chip/mt_scp/rv32i_common/uart_regs.h +++ b/chip/mt_scp/rv32i_common/uart_regs.h @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -16,65 +16,65 @@ void uart_init_pinmux(void); /* DLAB (Divisor Latch Access Bit) == 0 */ /* (Read) receiver buffer register */ -#define UART_RBR(n) UART_REG(n, 0) +#define UART_RBR(n) UART_REG(n, 0) /* (Write) transmitter holding register */ -#define UART_THR(n) UART_REG(n, 0) +#define UART_THR(n) UART_REG(n, 0) /* (Write) interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* received data */ -#define UART_IER_THRI BIT(1) /* THR empty */ -#define UART_IER_RLSI BIT(2) /* receiver LSR change */ -#define UART_IER_MSI BIT(3) /* MSR change */ +#define UART_IER(n) UART_REG(n, 1) +#define UART_IER_RDI BIT(0) /* received data */ +#define UART_IER_THRI BIT(1) /* THR empty */ +#define UART_IER_RLSI BIT(2) /* receiver LSR change */ +#define UART_IER_MSI BIT(3) /* MSR change */ /* (Read) interrupt identification register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_ID_MASK 0x0e -#define UART_IIR_MSI 0x00 /* modem status change */ -#define UART_IIR_NO_INT 0x01 /* no int pending */ -#define UART_IIR_THRI 0x02 /* THR empty */ -#define UART_IIR_RDI 0x04 /* received data available */ -#define UART_IIR_RLSI 0x06 /* line status change */ +#define UART_IIR(n) UART_REG(n, 2) +#define UART_IIR_ID_MASK 0x0e +#define UART_IIR_MSI 0x00 /* modem status change */ +#define UART_IIR_NO_INT 0x01 /* no int pending */ +#define UART_IIR_THRI 0x02 /* THR empty */ +#define UART_IIR_RDI 0x04 /* received data available */ +#define UART_IIR_RLSI 0x06 /* line status change */ /* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */ +#define UART_FCR(n) UART_REG(n, 2) +#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */ /* (Write) line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* parity enable */ -#define UART_LCR_EPAR BIT(4) /* even parity */ -#define UART_LCR_SPAR BIT(5) /* stick parity */ -#define UART_LCR_SBC BIT(6) /* set break control */ -#define UART_LCR_DLAB BIT(7) /* divisor latch access */ +#define UART_LCR(n) UART_REG(n, 3) +#define UART_LCR_WLEN5 0 /* word length 5 bits */ +#define UART_LCR_WLEN6 1 +#define UART_LCR_WLEN7 2 +#define UART_LCR_WLEN8 3 +#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* parity enable */ +#define UART_LCR_EPAR BIT(4) /* even parity */ +#define UART_LCR_SPAR BIT(5) /* stick parity */ +#define UART_LCR_SBC BIT(6) /* set break control */ +#define UART_LCR_DLAB BIT(7) /* divisor latch access */ /* (Write) modem control register */ -#define UART_MCR(n) UART_REG(n, 4) +#define UART_MCR(n) UART_REG(n, 4) /* (Read) line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* data ready */ -#define UART_LSR_OE BIT(1) /* overrun error */ -#define UART_LSR_PE BIT(2) /* parity error */ -#define UART_LSR_FE BIT(3) /* frame error */ -#define UART_LSR_BI BIT(4) /* break interrupt */ -#define UART_LSR_THRE BIT(5) /* THR empty */ -#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ +#define UART_LSR(n) UART_REG(n, 5) +#define UART_LSR_DR BIT(0) /* data ready */ +#define UART_LSR_OE BIT(1) /* overrun error */ +#define UART_LSR_PE BIT(2) /* parity error */ +#define UART_LSR_FE BIT(3) /* frame error */ +#define UART_LSR_BI BIT(4) /* break interrupt */ +#define UART_LSR_THRE BIT(5) /* THR empty */ +#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* (Read) modem status register */ -#define UART_MSR(n) UART_REG(n, 6) +#define UART_MSR(n) UART_REG(n, 6) /* (Read/Write) scratch register */ -#define UART_SCR(n) UART_REG(n, 7) +#define UART_SCR(n) UART_REG(n, 7) /* DLAB == 1 */ /* (Write) divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) -#define UART_DLH(n) UART_REG(n, 1) +#define UART_DLL(n) UART_REG(n, 0) +#define UART_DLH(n) UART_REG(n, 1) /* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) +#define UART_HIGHSPEED(n) UART_REG(n, 9) #endif /* __CROS_EC_UART_REGS_H */ diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h index e4538c4456..d5bb49ceac 100644 --- a/chip/mt_scp/rv32i_common/video.h +++ b/chip/mt_scp/rv32i_common/video.h @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,7 +17,9 @@ #define VDEC_CAP_H264_SLICE BIT(8) #define VDEC_CAP_VP8_FRAME BIT(9) #define VDEC_CAP_VP9_FRAME BIT(10) +#define VDEC_CAP_AV1_FRAME BIT(11) #define VDEC_CAP_IRQ_IN_SCP BIT(16) +#define VDEC_CAP_INNER_RACING BIT(17) /* * Video encoder supported capability: diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c index f77a948da3..e8f5b5c3f9 100644 --- a/chip/mt_scp/rv32i_common/watchdog.c +++ b/chip/mt_scp/rv32i_common/watchdog.c @@ -1,4 +1,4 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. +/* Copyright 2020 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ |