diff options
Diffstat (limited to 'chip/mt_scp/serial_reg.h')
| -rw-r--r-- | chip/mt_scp/serial_reg.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/serial_reg.h index a23b19ded3..5344566272 100644 --- a/chip/mt_scp/serial_reg.h +++ b/chip/mt_scp/serial_reg.h @@ -22,13 +22,13 @@ #define UART_DATA(n) UART_REG(n, 0) /* (Write) Interrupt enable register */ #define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI (1 << 0) /* Recv data int */ -#define UART_IER_THRI (1 << 1) /* Xmit holding register int */ -#define UART_IER_RLSI (1 << 2) /* Rcvr line status int */ -#define UART_IER_MSI (1 << 3) /* Modem status int */ +#define UART_IER_RDI BIT(0) /* Recv data int */ +#define UART_IER_THRI BIT(1) /* Xmit holding register int */ +#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ +#define UART_IER_MSI BIT(3) /* Modem status int */ /* (Read) Interrupt ID register */ #define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT (1 << 0) /* No int pending */ +#define UART_IIR_NO_INT BIT(0) /* No int pending */ #define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ #define UART_IIR_MSI 0x00 #define UART_IIR_THRI 0x02 @@ -37,10 +37,10 @@ #define UART_IIR_BUSY 0x07 /* DW APB busy */ /* (Write) FIFO control register */ #define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO (1 << 0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR (1 << 1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT (1 << 2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT (1 << 3) +#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* FIFO trigger levels */ #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 @@ -56,24 +56,24 @@ #define UART_LCR_WLEN6 1 #define UART_LCR_WLEN7 2 #define UART_LCR_WLEN8 3 -#define UART_LCR_STOP (1 << 2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY (1 << 3) /* Parity enable */ -#define UART_LCR_EPAR (1 << 4) /* Even parity */ -#define UART_LCR_SPAR (1 << 5) /* Stick parity */ -#define UART_LCR_SBC (1 << 6) /* Set break control */ -#define UART_LCR_DLAB (1 << 7) /* Divisor latch access */ +#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* Parity enable */ +#define UART_LCR_EPAR BIT(4) /* Even parity */ +#define UART_LCR_SPAR BIT(5) /* Stick parity */ +#define UART_LCR_SBC BIT(6) /* Set break control */ +#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ /* (Write) Modem control register */ #define UART_MCR(n) UART_REG(n, 4) /* (Read) Line status register */ #define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR (1 << 0) /* Data ready */ -#define UART_LSR_OE (1 << 1) /* Overrun error */ -#define UART_LSR_PE (1 << 2) /* Parity error */ -#define UART_LSR_FE (1 << 3) /* Frame error */ -#define UART_LSR_BI (1 << 4) /* Break interrupt */ -#define UART_LSR_THRE (1 << 5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT (1 << 6) /* Xmit empty */ -#define UART_LSR_FIFOE (1 << 7) /* FIFO error */ +#define UART_LSR_DR BIT(0) /* Data ready */ +#define UART_LSR_OE BIT(1) /* Overrun error */ +#define UART_LSR_PE BIT(2) /* Parity error */ +#define UART_LSR_FE BIT(3) /* Frame error */ +#define UART_LSR_BI BIT(4) /* Break interrupt */ +#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ +#define UART_LSR_TEMT BIT(6) /* Xmit empty */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* DLAB == 1 */ |