diff options
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 48 |
1 files changed, 26 insertions, 22 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index cd951e1f22..f7e1541250 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -35,9 +35,9 @@ /*****************************************************************************/ /* Memory mapping */ #define CONFIG_RAM_BASE 0x200C0000 /* memory map address of data ram */ -#define CONFIG_RAM_SIZE 0x00008000 /* 32KB data ram */ -#define CONFIG_CDRAM_BASE 0x10088000 /* memory map address of code ram */ -#define CONFIG_CDRAM_SIZE 0x00020000 /* 128KB code ram */ +#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ +#define CONFIG_CDRAM_BASE 0x100A8000 /* memory map address of code ram */ +#define CONFIG_CDRAM_SIZE 0x00018000 /* 96KB code ram */ #define CONFIG_FLASH_BASE 0x64000000 /* memory address of spi-flash */ #define CONFIG_LPRAM_BASE 0x40001600 /* memory address of low power ram */ #define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ @@ -61,38 +61,44 @@ #define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* sector erase size 4K bytes */ #define CONFIG_FLASH_WRITE_SIZE 0x00000001 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000 /* 256KB Flash used for EC */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +/* 128 KB alignment for SPI status registers protection */ +#define CONFIG_FLASH_PHYSICAL_SIZE 0x40000 /* 256 KB Flash used for EC */ /* No PSTATE; uses a real SPI flash */ #undef CONFIG_FLASH_PSTATE +/* Header support which is used by booter to copy FW from flash to code ram */ +#define NPCX_RO_HEADER + /****************************************************************************/ -/* Define our flash layout. */ +/* Define npcx flash layout. */ /* Size of one firmware image in flash */ #ifndef CONFIG_FW_IMAGE_SIZE #define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) #endif -/* RO firmware offset of flash */ -#define CONFIG_RO_MEM_OFF 0 +/* The storage offset of ec.RO.flat which is used for CONFIG_CDRAM_ARCH */ #define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE +#ifdef NPCX_RO_HEADER +#define CONFIG_RO_HDR_MEM_OFF 0x0 +#define CONFIG_RO_HDR_SIZE 0x40 +/* RO firmware offset in flash */ +#define CONFIG_RO_MEM_OFF CONFIG_RO_HDR_SIZE +#else +#define CONFIG_RO_MEM_OFF 0x0 +#endif +#define CONFIG_RO_SIZE CONFIG_CDRAM_SIZE /* 96KB for RO FW */ #define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE -/* RW firmware is one firmware image offset from the start */ -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE +/* The storage offset of ec.RW.flat which is used for CONFIG_CDRAM_ARCH */ +#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE /* 128 KB alignemnt */ +/* RW firmware offset in flash */ +#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF +#define CONFIG_RW_SIZE CONFIG_CDRAM_SIZE /* 96KB for RW FW */ #define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE - -/* - * The offset from top of flash wich used by booter - * the main funcationality to copy iamge from spi-flash to code ram - */ -#define CONFIG_LFW_OFFSET 0x1000 +#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE /****************************************************************************/ /* Customize the build */ @@ -101,11 +107,9 @@ #define CONFIG_ADC #define CONFIG_FPU #define CONFIG_I2C -#define CONFIG_LPC #define CONFIG_PECI #define CONFIG_SWITCH #define CONFIG_MPU -#define CONFIG_SPI /* Compile for running from RAM instead of flash */ /* #define COMPILE_FOR_RAM */ |