diff options
Diffstat (limited to 'chip/npcx/lpc.c')
| -rw-r--r-- | chip/npcx/lpc.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 4eee50d714..c80bf2960b 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -86,7 +86,7 @@ static void lpc_task_enable_irq(void) #endif task_enable_irq(NPCX_IRQ_PM_CHAN_IBF); task_enable_irq(NPCX_IRQ_PORT80); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI task_enable_irq(NPCX_IRQ_ESPI); /* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */ task_enable_irq(NPCX_IRQ_WKINTA_2); @@ -105,7 +105,7 @@ static void lpc_task_disable_irq(void) #endif task_disable_irq(NPCX_IRQ_PM_CHAN_IBF); task_disable_irq(NPCX_IRQ_PORT80); -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI task_disable_irq(NPCX_IRQ_ESPI); /* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */ task_disable_irq(NPCX_IRQ_WKINTA_2); @@ -137,7 +137,7 @@ static void lpc_generate_smi(void) udelay(65); /* Set signal high, now that we've generated the edge */ gpio_set_level(GPIO_PCH_SMI_L, 1); -#elif defined(CONFIG_HOSTCMD_ESPI) +#elif defined(CONFIG_HOST_INTERFACE_ESPI) /* * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead. @@ -183,7 +183,7 @@ static void lpc_generate_sci(void) udelay(65); /* Set signal high, now that we've generated the edge */ gpio_set_level(CONFIG_SCI_GPIO, 1); -#elif defined(CONFIG_HOSTCMD_ESPI) +#elif defined(CONFIG_HOST_INTERFACE_ESPI) /* * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead. @@ -519,7 +519,7 @@ static void handle_host_write(int is_cmd) /* Interrupt handlers */ #ifdef HAS_TASK_KEYPROTO /* KB controller input buffer full ISR */ -void lpc_kbc_ibf_interrupt(void) +static void lpc_kbc_ibf_interrupt(void) { uint8_t status; uint8_t ibf; @@ -543,7 +543,7 @@ void lpc_kbc_ibf_interrupt(void) DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 4); /* KB controller output buffer empty ISR */ -void lpc_kbc_obe_interrupt(void) +static void lpc_kbc_obe_interrupt(void) { /* Disable KBC OBE interrupt */ CLEAR_BIT(NPCX_HICTRL, NPCX_HICTRL_OBECIE); @@ -559,7 +559,7 @@ DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4); #endif /* PM channel input buffer full ISR */ -void lpc_pmc_ibf_interrupt(void) +static void lpc_pmc_ibf_interrupt(void) { /* Channel-1 for ACPI usage*/ /* Channel-2 for Host Command usage , so the argument data had been @@ -572,12 +572,12 @@ void lpc_pmc_ibf_interrupt(void) DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4); /* PM channel output buffer empty ISR */ -void lpc_pmc_obe_interrupt(void) +static void lpc_pmc_obe_interrupt(void) { } DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 4); -void lpc_port80_interrupt(void) +static void lpc_port80_interrupt(void) { uint8_t i; uint8_t count = 0; @@ -698,7 +698,7 @@ void host_register_init(void) * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO. * This is only supported when CHIP_FAMILY >= NPCX9. */ - if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) sib_write_reg(SIO_OFFSET, 0xFD, 0x0F); /* enable SHM */ sib_write_reg(SIO_OFFSET, 0x30, 0x01); @@ -721,7 +721,7 @@ int lpc_get_pltrst_asserted(void) return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT); } -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* Initialize host settings by interrupt */ void lpc_lreset_pltrst_handler(void) { @@ -771,7 +771,7 @@ static void lpc_init(void) * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL * field should be set by firmware. */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI /* Initialize eSPI module */ NPCX_DEVCNT |= 0x08; espi_init(); @@ -787,7 +787,7 @@ static void lpc_init(void) /* Clear Host Access Hold state */ NPCX_SMC_CTL = 0xC0; -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under * continuous or quiet mode. @@ -800,7 +800,7 @@ static void lpc_init(void) * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW * automatically by toggling them, too. It's unnecessary to set pin mux. */ -#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI) +#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOST_INTERFACE_ESPI) SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL); SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL); #endif @@ -876,7 +876,7 @@ static void lpc_init(void) * Init PORT80 * Enable Port80, Enable Port80 function & Interrupt & Read auto */ -#ifdef CONFIG_HOSTCMD_ESPI +#ifdef CONFIG_HOST_INTERFACE_ESPI NPCX_DP80CTL = 0x2b; #else NPCX_DP80CTL = 0x29; @@ -926,7 +926,7 @@ static void lpc_init(void) /* initial IO port address via SIB-write modules */ host_register_init(); #else -#ifndef CONFIG_HOSTCMD_ESPI +#ifndef CONFIG_HOST_INTERFACE_ESPI /* * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW |