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-rw-r--r--chip/npcx/cec.c2
-rw-r--r--chip/npcx/clock.c2
-rw-r--r--chip/npcx/fan.c2
-rw-r--r--chip/npcx/lpc.c2
-rw-r--r--chip/npcx/registers.h46
-rw-r--r--chip/npcx/shi.c2
-rw-r--r--chip/npcx/system.c4
-rw-r--r--chip/npcx/system_chip.h4
-rw-r--r--chip/npcx/wov.c4
-rw-r--r--chip/npcx/wov_chip.h4
10 files changed, 36 insertions, 36 deletions
diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
index ea016805c0..d996695dfc 100644
--- a/chip/npcx/cec.c
+++ b/chip/npcx/cec.c
@@ -34,7 +34,7 @@
#endif
/* Notification from interrupt to CEC task that data has been received */
-#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(1 << 0)
+#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(BIT(0))
/* CEC broadcast address. Also the highest possible CEC address */
#define CEC_BROADCAST_ADDR 15
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index ecd48197b2..178f398434 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -160,7 +160,7 @@ void clock_turbo(void)
* CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1.
*/
NPCX_HFCGP = 0x01;
- NPCX_HFCBCD = (1 << 4);
+ NPCX_HFCBCD = BIT(4);
}
void clock_normal(void)
diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c
index e6280c97db..381be8a018 100644
--- a/chip/npcx/fan.c
+++ b/chip/npcx/fan.c
@@ -89,7 +89,7 @@ static int rpm_pre[FAN_CH_COUNT];
((fan_status[ch].mft_freq * 60 / PULSES_ROUND) / MAX((tach), 1))
/* MFT TCNT default count */
-#define TACHO_MAX_CNT ((1 << 16) - 1)
+#define TACHO_MAX_CNT (BIT(16) - 1)
/* Margin of target rpm */
#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100)
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index a86a5879ba..971512ec72 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -1041,7 +1041,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
struct ec_response_get_protocol_info *r = args->response;
memset(r, 0, sizeof(*r));
- r->protocol_versions = (1 << 3);
+ r->protocol_versions = BIT(3);
r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
r->flags = 0;
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 3db1c79190..7c812e5da2 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -480,14 +480,14 @@ enum {
};
enum {
- MASK_PIN0 = (1<<0),
- MASK_PIN1 = (1<<1),
- MASK_PIN2 = (1<<2),
- MASK_PIN3 = (1<<3),
- MASK_PIN4 = (1<<4),
- MASK_PIN5 = (1<<5),
- MASK_PIN6 = (1<<6),
- MASK_PIN7 = (1<<7),
+ MASK_PIN0 = BIT(0),
+ MASK_PIN1 = BIT(1),
+ MASK_PIN2 = BIT(2),
+ MASK_PIN3 = BIT(3),
+ MASK_PIN4 = BIT(4),
+ MASK_PIN5 = BIT(5),
+ MASK_PIN6 = BIT(6),
+ MASK_PIN7 = BIT(7),
};
/* Chip-independent aliases for port base group */
@@ -1863,21 +1863,21 @@ enum {
/*
* Status registers for the W25Q16CV SPI flash
*/
-#define SPI_FLASH_SR2_SUS (1 << 7)
-#define SPI_FLASH_SR2_CMP (1 << 6)
-#define SPI_FLASH_SR2_LB3 (1 << 5)
-#define SPI_FLASH_SR2_LB2 (1 << 4)
-#define SPI_FLASH_SR2_LB1 (1 << 3)
-#define SPI_FLASH_SR2_QE (1 << 1)
-#define SPI_FLASH_SR2_SRP1 (1 << 0)
-#define SPI_FLASH_SR1_SRP0 (1 << 7)
-#define SPI_FLASH_SR1_SEC (1 << 6)
-#define SPI_FLASH_SR1_TB (1 << 5)
-#define SPI_FLASH_SR1_BP2 (1 << 4)
-#define SPI_FLASH_SR1_BP1 (1 << 3)
-#define SPI_FLASH_SR1_BP0 (1 << 2)
-#define SPI_FLASH_SR1_WEL (1 << 1)
-#define SPI_FLASH_SR1_BUSY (1 << 0)
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
/* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
index 464ad9db5f..2e061ad2c2 100644
--- a/chip/npcx/shi.c
+++ b/chip/npcx/shi.c
@@ -1055,7 +1055,7 @@ static int shi_get_protocol_info(struct host_cmd_handler_args *args)
struct ec_response_get_protocol_info *r = args->response;
memset(r, 0, sizeof(*r));
- r->protocol_versions = (1 << 3);
+ r->protocol_versions = BIT(3);
r->max_request_packet_size = SHI_MAX_REQUEST_SIZE;
r->max_response_packet_size = SHI_MAX_RESPONSE_SIZE;
r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 726aa30350..b9d3367d91 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -25,7 +25,7 @@
/* Delay after writing TTC for value to latch */
#define MTC_TTC_LOAD_DELAY_US 250
-#define MTC_ALARM_MASK ((1 << 25) - 1)
+#define MTC_ALARM_MASK (BIT(25) - 1)
#define MTC_WUI_GROUP MIWU_GROUP_4
#define MTC_WUI_MASK MASK_PIN7
@@ -266,7 +266,7 @@ void system_set_rtc(uint32_t seconds)
#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16)
#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20)
-#define BKUP_PANIC_DATA_VALID (1 << 0)
+#define BKUP_PANIC_DATA_VALID BIT(0)
void chip_panic_data_backup(void)
{
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index da400f79bb..5700143e2a 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -9,8 +9,8 @@
#define __CROS_EC_SYSTEM_CHIP_H
/* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC (1 << 0) /* MTC alarm */
-#define HIBERNATE_WAKE_PIN (1 << 1) /* Wake pin */
+#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */
+#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */
/* Indices for battery-backed ram (BBRAM) data position */
enum bbram_data_index {
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index 2d0574ff01..3bbeee90a0 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -1743,12 +1743,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock)
* first bit (MSB) of channel 1 (right channel).
* If channel 1 is not used set this field to -1.
*
- * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a
+ * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a
* channel adjacent to channel 0, so float SDAT when
* driving the last bit (LSB) of the channel during the
* second half of the clock cycle to avoid bus contention.
*
- * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel
+ * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
* adjacent to channel 1.
*
* @return EC error code.
diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h
index 96bc03c2b8..dce534c501 100644
--- a/chip/npcx/wov_chip.h
+++ b/chip/npcx/wov_chip.h
@@ -427,12 +427,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock);
* first bit (MSB) of channel 1 (right channel).
* If channel 1 is not used set this field to -1.
*
- * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a
+ * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a
* channel adjacent to channel 0, so float SDAT when
* driving the last bit (LSB) of the channel during the
* second half of the clock cycle to avoid bus contention.
*
- * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel
+ * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel
* adjacent to channel 1.
*
* @return EC error code.
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