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-rw-r--r--chip/stm32/build.mk15
1 files changed, 5 insertions, 10 deletions
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 13a6aa752a..5b2d7d9994 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -9,33 +9,28 @@
ifeq ($(CHIP_FAMILY),stm32f0)
# STM32F0xx sub-family has a Cortex-M0 ARM core
CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
+CFLAGS_CPU+=-mcpu=cortex-m0
else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
stm32g4))
# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
CORE:=cortex-m
# Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
# STM32FH7xx family has a Cortex-M7 ARM core
CORE:=cortex-m
# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
# STM32FL5xx family has a Cortex-M33 ARM core
CORE:=cortex-m
# Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
+CFLAGS_CPU+=-mcpu=cortex-m33
else
# other STM32 SoCs have a Cortex-M3 ARM core
CORE:=cortex-m
# Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
+CFLAGS_CPU+=-mcpu=cortex-m3
endif
# Select between 16-bit and 32-bit timer for clock source