diff options
Diffstat (limited to 'chip/stm32/config-stm32f100.h')
| -rw-r--r-- | chip/stm32/config-stm32f100.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chip/stm32/config-stm32f100.h b/chip/stm32/config-stm32f100.h index bb4c4c33dc..dfb59c3cbe 100644 --- a/chip/stm32/config-stm32f100.h +++ b/chip/stm32/config-stm32f100.h @@ -17,7 +17,8 @@ #define CONFIG_FW_IMAGE_SIZE (64 * 1024) #define CONFIG_FW_RO_OFF 0 -#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ + - CONFIG_SECTION_FLASH_PSTATE_SIZE) #define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE #define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE @@ -27,12 +28,11 @@ #define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE /* - * The EC uses the top bank of flash to emulate a SPI-like write protect - * register with persistent state. Put that up at the top. + * Put this after RO to give RW more space. This also makes RO write protect + * region contiguous. */ #define CONFIG_SECTION_FLASH_PSTATE_SIZE (1 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FLASH_SIZE \ - - CONFIG_SECTION_FLASH_PSTATE_SIZE) +#define CONFIG_SECTION_FLASH_PSTATE_OFF CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 61 |