diff options
Diffstat (limited to 'chip/stm32/config-stm32f4.h')
| -rw-r--r-- | chip/stm32/config-stm32f4.h | 47 |
1 files changed, 23 insertions, 24 deletions
diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h index ee1d594116..d7ef668886 100644 --- a/chip/stm32/config-stm32f4.h +++ b/chip/stm32/config-stm32f4.h @@ -1,13 +1,13 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. +/* Copyright 2016 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* Memory mapping */ #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) #else -# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #endif /* 3 regions type: 16K, 64K and 128K */ @@ -31,33 +31,32 @@ #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ #else -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ #endif -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (256 * 1024) -#define CONFIG_RW_MEM_OFF (256 * 1024) -#define CONFIG_RW_SIZE (256 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (256 * 1024) +#define CONFIG_RW_MEM_OFF (256 * 1024) +#define CONFIG_RW_SIZE (256 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Use PSTATE embedded in the RO image, not in its own erase block */ #define CONFIG_FLASH_PSTATE @@ -67,12 +66,12 @@ #define CONFIG_OTP /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 97 +#define CONFIG_IRQ_COUNT 97 #undef CONFIG_CMD_CHARGEN /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 /* * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm |