diff options
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 432fc9a221..3a549beb5f 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1388,6 +1388,21 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CFGR_SWS_HSE (2 << 3) #define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) #define STM32_RCC_CFGR_SWS_MASK (3 << 3) +#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) +#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) +#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (11 << 8) #define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) #define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) #define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) @@ -1411,6 +1426,19 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) #define STM32_RCC_PLLDIV_DIVR(r) (((r) - 1) << 24) #define STM32_RCC_PLLFRAC(n) ((n) << 3) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) +#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) #define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0) |