diff options
Diffstat (limited to 'chip/stm32/usart-stm32l5.c')
| -rw-r--r-- | chip/stm32/usart-stm32l5.c | 80 |
1 files changed, 49 insertions, 31 deletions
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 2306f54606..30e0f009ff 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2021 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -17,13 +17,13 @@ * each USART, an entry will be NULL if no USART driver is initialized for the * corresponding hardware instance. */ -#define STM32_USARTS_MAX 5 +#define STM32_USARTS_MAX 6 static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; static void usart3_interrupt(void) @@ -133,12 +133,12 @@ DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); #if defined(CONFIG_STREAM_USART4) struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART4, + .index = 3, + .base = STM32_USART4_BASE, + .irq = STM32_IRQ_USART4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART4, + .ops = &usart_variant_hw_ops, }; static void usart4_interrupt(void) @@ -151,12 +151,12 @@ DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2); #if defined(CONFIG_STREAM_USART5) struct usart_hw_config const usart5_hw = { - .index = 4, - .base = STM32_USART5_BASE, - .irq = STM32_IRQ_USART5, + .index = 4, + .base = STM32_USART5_BASE, + .irq = STM32_IRQ_USART5, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART5, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART5, + .ops = &usart_variant_hw_ops, }; static void usart5_interrupt(void) @@ -166,3 +166,21 @@ static void usart5_interrupt(void) DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2); #endif + +#if defined(CONFIG_STREAM_USART9) +struct usart_hw_config const usart9_hw = { + .index = 5, + .base = STM32_USART9_BASE, + .irq = STM32_IRQ_USART9, + .clock_register = &STM32_RCC_APB1ENR2, + .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, + .ops = &usart_variant_hw_ops, +}; + +static void usart9_interrupt(void) +{ + usart_interrupt(configs[5]); +} + +DECLARE_IRQ(STM32_IRQ_USART9, usart9_interrupt, 2); +#endif |