diff options
Diffstat (limited to 'chip')
32 files changed, 58 insertions, 58 deletions
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index 195744c556..84e254d8a0 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -10,14 +10,14 @@ /* Memory mapping */ #if !defined(TEST_NVMEM) && !defined(TEST_CR50_FUZZ) -#define CONFIG_FLASH_SIZE 0x00020000 +#define CONFIG_FLASH_SIZE_BYTES 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #else -#define CONFIG_FLASH_SIZE (512 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x800 #endif -extern char __host_flash[CONFIG_FLASH_SIZE]; +extern char __host_flash[CONFIG_FLASH_SIZE_BYTES]; #define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash) #define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ diff --git a/chip/host/flash.c b/chip/host/flash.c index 9f79298d60..486c418065 100644 --- a/chip/host/flash.c +++ b/chip/host/flash.c @@ -14,7 +14,7 @@ #include "util.h" /* This needs to be aligned to the erase bank size for NVCTR. */ -__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE]; +__aligned(CONFIG_FLASH_ERASE_SIZE) char __host_flash[CONFIG_FLASH_SIZE_BYTES]; uint8_t __host_flash_protect[PHYSICAL_BANKS]; /* Override this function to make flash erase/write operation fail */ diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h index 0430baf3eb..9a6cc4f28b 100644 --- a/chip/ish/config_flash_layout.h +++ b/chip/ish/config_flash_layout.h @@ -26,9 +26,9 @@ #define CONFIG_MAPPED_STORAGE_BASE 0x0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Unused for ISH - loader is external to ISH FW */ diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h index 6163ef8fb9..2918698e64 100644 --- a/chip/it83xx/config_chip_it8320.h +++ b/chip/it83xx/config_chip_it8320.h @@ -36,7 +36,7 @@ * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* For IT8320BX, we have to reload cc parameters after ec softreset. */ #define IT83XX_USBPD_CC_PARAMETER_RELOAD /* @@ -53,7 +53,7 @@ */ #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES #elif defined(CHIP_VARIANT_IT8320DX) -#define CONFIG_FLASH_SIZE 0x00080000 +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * Disable eSPI pad, then PLL change diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 0bd8963e6e..2934ec65dc 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -37,7 +37,7 @@ #if defined(CHIP_VARIANT_IT83202BX) /* TODO(b/133460224): enable properly chip config option. */ -#define CONFIG_FLASH_SIZE 0x00080000 +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 #define CONFIG_RAM_BASE 0x80080000 #define CONFIG_RAM_SIZE 0x00010000 @@ -80,7 +80,7 @@ || defined(CHIP_VARIANT_IT81202AX_1024) \ || defined(CHIP_VARIANT_IT81302BX_1024) \ || defined(CHIP_VARIANT_IT81202BX_1024) -#define CONFIG_FLASH_SIZE 0x00100000 +#define CONFIG_FLASH_SIZE_BYTES 0x00100000 #define CONFIG_RAM_BASE 0x80100000 #define CONFIG_RAM_SIZE 0x0000f000 diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index c0f46552fd..aa1e280159 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -48,7 +48,7 @@ /* Read status register */ #define FLASH_CMD_RS 0x05 -#if (CONFIG_FLASH_SIZE == 0x80000) && defined(CHIP_CORE_NDS32) +#if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32) #define FLASH_TEXT_START ((uint32_t) &__flash_text_start) /* Apply workaround of the issue (b:111808417) */ #define IMMU_CACHE_TAG_INVALID @@ -370,7 +370,7 @@ static enum flash_wp_status flash_check_wp(void) enum flash_wp_status wp_status; int all_bank_count, bank; - all_bank_count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE; + all_bank_count = CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE; for (bank = 0; bank < all_bank_count; bank++) { if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank))) @@ -555,7 +555,7 @@ int flash_physical_protect_now(int all) if (all) { /* Protect the entire flash */ flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_EC); all_protected = 1; } else { @@ -756,11 +756,11 @@ int flash_pre_init(void) if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { /* Protect the entire flash of host interface */ flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_HOST); /* Protect the entire flash of DBGR interface */ flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, + CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_DBGR); /* * Write protect is asserted. If we want RO flash protected, diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 8abe059e5b..4e442004c9 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -61,7 +61,7 @@ * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /****************************************************************************/ /* Define our flash layout. */ diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c index 4f7e905e21..5e0c6510f3 100644 --- a/chip/lm4/flash.c +++ b/chip/lm4/flash.c @@ -193,7 +193,7 @@ int flash_physical_protect_now(int all) if (all) { /* Protect the entire flash */ all_protected = 1; - protect_banks(0, CONFIG_FLASH_SIZE / + protect_banks(0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE); } else /* Protect the WP region (read-only section and pstate) */ diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h index b74ec591ad..c97c246bb7 100644 --- a/chip/max32660/config_chip.h +++ b/chip/max32660/config_chip.h @@ -61,7 +61,7 @@ * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE 0x00040000 /* 256K MAX32660 FLASH Size */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256K MAX32660 FLASH Size */ /****************************************************************************/ /* Define our flash layout. */ diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c index 8bf52efe49..c2fe9d6515 100644 --- a/chip/mchp/lfw/ec_lfw.c +++ b/chip/mchp/lfw/ec_lfw.c @@ -141,7 +141,7 @@ static int spi_flash_readloc(uint8_t *buf_usr, (offset >> 8) & 0xFF, offset & 0xFF}; - if (offset + bytes > CONFIG_FLASH_SIZE) + if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; __hw_clock_source_set(0); /* restart free run timer */ diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h index 3ab249668d..a5b064b8cc 100644 --- a/chip/mec1322/config_flash_layout.h +++ b/chip/mec1322/config_flash_layout.h @@ -21,9 +21,9 @@ #define CONFIG_SPI_FLASH /* EC region of SPI resides at end of ROM, protected region follows writable */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Loader resides at the beginning of program memory */ diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 9db5f7717f..ccee9f8967 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -83,7 +83,7 @@ static int spi_flash_readloc(uint8_t *buf_usr, (offset >> 8) & 0xFF, offset & 0xFF}; - if (offset + bytes > CONFIG_FLASH_SIZE) + if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes); diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index a13723f980..da17cc76ae 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -100,7 +100,7 @@ /* Internal spi-flash setting */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ -#define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */ diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 7afb413c2c..a5f656f8ca 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -329,7 +329,7 @@ static int flash_set_status_for_prot(int reg1, int reg2) static int flash_check_prot_range(unsigned int offset, unsigned int bytes) { /* Invalid value */ - if (offset + bytes > CONFIG_FLASH_SIZE) + if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; /* Check if ranges overlap */ if (MAX(addr_prot_start, offset) < MIN(addr_prot_start + @@ -362,7 +362,7 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) sr2 = flash_get_status2(); /* Invalid value */ - if (offset + bytes > CONFIG_FLASH_SIZE) + if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; /* Compute current protect range */ @@ -386,7 +386,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, uint8_t sr2 = flash_get_status2(); /* Invalid values */ - if (offset + bytes > CONFIG_FLASH_SIZE) + if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; /* Compute desired protect range */ diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index 7295ab9360..f63fff0fe3 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -37,7 +37,7 @@ /* Flash mapping */ #define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x1000 /* Memory-mapped internal flash */ diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 84266cdbfc..3c51086c26 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -4,10 +4,10 @@ */ #ifdef CHIP_VARIANT_STM32F03X8 -#define CONFIG_FLASH_SIZE 0x00010000 +#define CONFIG_FLASH_SIZE_BYTES 0x00010000 #define CONFIG_RAM_SIZE 0x00002000 #else -#define CONFIG_FLASH_SIZE 0x00008000 +#define CONFIG_FLASH_SIZE_BYTES 0x00008000 #define CONFIG_RAM_SIZE 0x00001000 #endif diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h index cab7b62d50..00bf45fde5 100644 --- a/chip/stm32/config-stm32f05x.h +++ b/chip/stm32/config-stm32f05x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE (64 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (64 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h index 199aef3361..918a117a22 100644 --- a/chip/stm32/config-stm32f07x.h +++ b/chip/stm32/config-stm32f07x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE (128 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h index 3da8a342f2..9dc27a1fb2 100644 --- a/chip/stm32/config-stm32f09x.h +++ b/chip/stm32/config-stm32f09x.h @@ -8,7 +8,7 @@ * Flash physical size: 256KB * Write protect sectors: 31 4KB sectors, one 132KB sector */ -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -62,7 +62,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE - \ +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index b77b1d98a6..3df5bfce67 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 #define CONFIG_FLASH_BANK_SIZE 0x2000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h index c64cc3089a..60b1affd3c 100644 --- a/chip/stm32/config-stm32f4.h +++ b/chip/stm32/config-stm32f4.h @@ -5,9 +5,9 @@ /* Memory mapping */ #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE (1 * 1024 * 1024) +# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) #else -# define CONFIG_FLASH_SIZE (512 * 1024) +# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #endif /* 3 regions type: 16K, 64K and 128K */ @@ -16,7 +16,7 @@ #define SIZE_128KB (128 * 1024) #define CONFIG_FLASH_REGION_TYPE_COUNT 3 #define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB) + (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB) /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -50,7 +50,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h index 665bec36bf..d027ad62fb 100644 --- a/chip/stm32/config-stm32f76x.h +++ b/chip/stm32/config-stm32f76x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE (2048 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) /* 3 regions type: 32K, 128K and 256K */ #define SIZE_32KB (32 * 1024) @@ -12,7 +12,7 @@ #define SIZE_256KB (256 * 1024) #define CONFIG_FLASH_REGION_TYPE_COUNT 3 #define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB) + (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB) /* Erasing 256K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -44,7 +44,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index ab8642b9e6..da42faf2c3 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -21,7 +21,7 @@ * without being constrained by flash space issue. Currently only using RO image * flashed with STM32 debugger. */ -#define CONFIG_FLASH_SIZE (256 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (256 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index 399e6a6f1a..da94b09069 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE (2048 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) #define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ /* always use 256-bit writes due to ECC */ #define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ @@ -32,7 +32,7 @@ #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) #define CONFIG_RW_SIZE (512 * 1024) #define CONFIG_RO_STORAGE_OFF 0 @@ -42,7 +42,7 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF #define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) #define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h index 579e31cb5b..2c4efcc6df 100644 --- a/chip/stm32/config-stm32l100.h +++ b/chip/stm32/config-stm32l100.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00020000 +#define CONFIG_FLASH_SIZE_BYTES 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index afdc241e96..0b32f95572 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00020000 +#define CONFIG_FLASH_SIZE_BYTES 0x00020000 #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h index e9f3e04c53..54ba9bac8d 100644 --- a/chip/stm32/config-stm32l442.h +++ b/chip/stm32/config-stm32l442.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ #define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ #define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ #define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h index 9f6b35b8b1..2e0084fd94 100644 --- a/chip/stm32/config-stm32l476.h +++ b/chip/stm32/config-stm32l476.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ #define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ #define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ #define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index e2ff2c779c..a0aef5fe3f 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -26,7 +26,7 @@ uint32_t flash_physical_get_protect_flags(void) { uint32_t flags = 0; uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01); -#if CONFIG_FLASH_SIZE > 64 * 1024 +#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23); #endif @@ -76,12 +76,12 @@ uint32_t flash_physical_get_protect_flags(void) switch (i) { case 8: -#if CONFIG_FLASH_SIZE > 64 * 1024 +#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 case 24: #endif shift += 8; break; -#if CONFIG_FLASH_SIZE > 64 * 1024 +#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 case 16: reg = 1; shift = 0; @@ -96,7 +96,7 @@ uint32_t flash_physical_get_protect_flags(void) for (i = 0; i < FLASH_REGION_COUNT; i++) { if (!(wrp01 & wrp_mask[i][0]) && (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) -#if CONFIG_FLASH_SIZE > 64 * 1024 +#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 if (!(wrp23 & wrp_mask[i][1]) && (wrp23 & wrp_mask[i][1] << 8) == (wrp_mask[i][1] << 8)) @@ -106,7 +106,7 @@ uint32_t flash_physical_get_protect_flags(void) #endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */ if (wrp01 == 0xff00ff00) -#if CONFIG_FLASH_SIZE > 64 * 1024 +#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 if (wrp23 == 0xff00ff00) #endif flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index ea5ba1a1b6..bae4315b67 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -36,7 +36,7 @@ struct ec_flash_bank const flash_bank_array[] = { .protect_size_exp = __fls(SIZE_128KB), }, { - .count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB, + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB, .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), .size_exp = __fls(SIZE_256KB), .erase_size_exp = __fls(SIZE_256KB), @@ -70,7 +70,7 @@ struct ec_flash_bank const flash_bank_array[] = { .protect_size_exp = __fls(SIZE_64KB), }, { - .count = (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB, + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB, .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), .size_exp = __fls(SIZE_128KB), .erase_size_exp = __fls(SIZE_128KB), diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c index 27092a1156..360d63a739 100644 --- a/chip/stm32/flash-stm32g4-l4.c +++ b/chip/stm32/flash-stm32g4-l4.c @@ -46,7 +46,7 @@ * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes */ #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE -#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE / FLASH_PAGE_SIZE) +#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE) #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET #define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \ + FLASH_RO_FIRST_PAGE_IDX - 1) diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index a541b962d2..2797720b8f 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -44,7 +44,7 @@ * not what is called 'bank' in the common code (ie Write-Protect sectors) * both have the same number of 128KB blocks. */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE / 2) +#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) |