5 files changed, 24 insertions, 12 deletions
diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c
index bbd2e503d1..3f40264ef5 100644
--- a/chip/lm4/clock.c
+++ b/chip/lm4/clock.c
@@ -168,10 +168,11 @@ void clock_init(void)
 #endif
 
 	/*
-	 * TODO: UART seems to glitch unless we wait 500k cycles before
-	 * enabling the PLL, but only if this is a cold boot.  Why?  UART
-	 * doesn't even use the PLL'd system clock.  I've heard rumors the
-	 * Stellaris ROM library does this too, but why?
+	 * TODO(crosbug.com/p/23794): UART seems to glitch unless we wait 500k
+	 * cycles before enabling the PLL, but only if this is a cold boot.
+	 * Why?  UART doesn't even use the PLL'd system clock.  I've heard
+	 * rumors the Stellaris ROM library does this too, but why?  Revisit on
+	 * current systems to see if this is is still needed.
 	 */
 	if (!system_jumped_to_this_image())
 		clock_wait_cycles(500000);
@@ -457,9 +458,10 @@ static int command_sleep(int argc, char **argv)
 		}
 
 		/*
-		 * TODO: move this to the UART module; ugly to have
-		 * UARTisms here.  Also note this only fixes UART0,
-		 * not UART1.
+		 * TODO(crosbug.com/p/23795): move this to the UART module;
+		 * ugly to have UARTisms here.  Also note this only fixes
+		 * UART0, not UART1.  Should just be able to trigger
+		 * HOOK_FREQ_CHANGE and have that take care of it.
 		 */
 		if (uartfbrd) {
 			/* Disable the port via UARTCTL and add HSE. */
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index a534bb7a57..81ceed1b09 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -98,7 +98,7 @@
 #define CONFIG_FW_RW_OFF		CONFIG_FW_IMAGE_SIZE
 #define CONFIG_FW_RW_SIZE		CONFIG_FW_IMAGE_SIZE
 
-/* TODO: why 2 sets of configs with the same numbers? */
+/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
 #define CONFIG_FW_WP_RO_OFF		CONFIG_FW_RO_OFF
 #define CONFIG_FW_WP_RO_SIZE		CONFIG_FW_RO_SIZE
 
diff --git a/chip/stm32/flash-stm32f.c b/chip/stm32/flash-stm32f.c
index c0f5ae4cd3..c14e37044c 100644
--- a/chip/stm32/flash-stm32f.c
+++ b/chip/stm32/flash-stm32f.c
@@ -48,8 +48,9 @@ static int entire_flash_locked;
 #define FLASH_HOOK_VERSION 1
 /* The previous write protect state before sys jump */
 /*
- * TODO: check if STM32L code works here too - that is, check if entire flash
- * is locked by attempting to lock it rather than keeping a global variable.
+ * TODO(crosbug.com/p/23798): check if STM32L code works here too - that is,
+ * check if entire flash is locked by attempting to lock it rather than keeping
+ * a global variable.
  */
 struct flash_wp_state {
 	int entire_flash_locked;
@@ -478,8 +479,9 @@ int flash_pre_init(void)
 			 * Write protect register was in an inconsistent state.
 			 * Set it back to a good state and reboot.
 			 *
-			 * TODO: this seems really similar to the check above.
-			 * One of them should be able to go away.
+			 * TODO(crosbug.com/p/23798): this seems really similar
+			 * to the check above.  One of them should be able to
+			 * go away.
 			 */
 			flash_protect_ro_at_boot(
 				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
diff --git a/chip/stm32/i2c-stm32f.c b/chip/stm32/i2c-stm32f.c
index 29d88b5660..52b56c363a 100644
--- a/chip/stm32/i2c-stm32f.c
+++ b/chip/stm32/i2c-stm32f.c
@@ -377,6 +377,10 @@ static void unwedge_i2c_bus(int port)
 
 	ASSERT(port == I2C1 || port == I2C2);
 
+	/*
+	 * TODO(crosbug.com/p/23802): This requires defining GPIOs for both
+	 * ports even if the board only supports one port.
+	 */
 	if (port == I2C1) {
 		sda = GPIO_I2C1_SDA;
 		scl = GPIO_I2C1_SCL;
diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c
index 27f6eb92bb..6ff355c0ff 100644
--- a/chip/stm32/i2c-stm32l.c
+++ b/chip/stm32/i2c-stm32l.c
@@ -178,6 +178,10 @@ static void i2c_try_unwedge(int port, int force_unwedge)
 	enum gpio_signal scl, sda;
 	int i;
 
+	/*
+	 * TODO(crosbug.com/p/23802): This requires defining GPIOs for both
+	 * ports even if the board only supports one port.
+	 */
 	if (port == I2C1) {
 		sda = GPIO_I2C1_SDA;
 		scl = GPIO_I2C1_SCL;