diff options
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mchp/gpio.c | 41 | ||||
| -rw-r--r-- | chip/mchp/registers-mec152x.h | 1 | ||||
| -rw-r--r-- | chip/mchp/registers-mec1701.h | 8 |
3 files changed, 32 insertions, 18 deletions
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index 1de74dafcc..32a9e36c79 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -38,12 +38,11 @@ struct gpio_int_mapping { * 4 0200 - 0235 12 * 5 0240 - 0276 26 */ -static const struct gpio_int_mapping int_map[6] = { +static const struct gpio_int_mapping int_map[] = { { 11, 0 }, { 10, 1 }, { 9, 2 }, { 8, 3 }, { 12, 4 }, { 26, 5 } }; - - +BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT); /* * NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant @@ -55,6 +54,9 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int i; uint32_t val; + if (port >= MCHP_GPIO_MAX_PORT) + return; + while (mask) { i = __builtin_ffs(mask) - 1; val = MCHP_GPIO_CTL(port, i); @@ -98,18 +100,21 @@ void gpio_set_level(enum gpio_signal signal, int value) /* * Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN. - * If GPIO_POWER_DONW flag is set force GPIO Control to + * If GPIO_POWER_DOWN flag is set force GPIO Control to * GPIO input, interrupt detect disabled, power control field * in bits[3:2]=10b. * NOTE: if interrupt detect is enabled when pin is powered down * then a false edge may be detected. - * + * NOTE 2: MEC152x family implements input pad disable (bit[15]=1). */ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) { int i; uint32_t val; + if (port >= MCHP_GPIO_MAX_PORT) + return; + while (mask) { i = GPIO_MASK_TO_NUM(mask); mask &= ~BIT(i); @@ -117,15 +122,18 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) #ifdef CONFIG_GPIO_POWER_DOWN if (flags & GPIO_POWER_DOWN) { - val = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); + val = (MCHP_GPIO_CTRL_PWR_OFF + | MCHP_GPIO_INTDET_DISABLED + | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + MCHP_GPIO_CTL(port, i) = val; continue; } #endif - val &= ~(MCHP_GPIO_CTRL_PWR_MASK); - val |= MCHP_GPIO_CTRL_PWR_VTR; + val &= ~(MCHP_GPIO_CTRL_PWR_MASK + | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + val |= MCHP_GPIO_CTRL_PWR_VTR; /* * Select open drain first, so that we don't * glitch the signal when changing the line to @@ -190,12 +198,15 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask) { int i; + if (port >= MCHP_GPIO_MAX_PORT) + return; + while (mask) { i = GPIO_MASK_TO_NUM(mask); mask &= ~BIT(i); - - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); + MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + | MCHP_GPIO_INTDET_DISABLED + | MCHP_GPIO_CTRL_DIS_INPUT_BIT); } } @@ -208,9 +219,9 @@ int gpio_power_off(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); port = gpio_list[signal].port; - - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); + MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + | MCHP_GPIO_INTDET_DISABLED + | MCHP_GPIO_CTRL_DIS_INPUT_BIT); return EC_SUCCESS; } diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h index 251a0be1b4..cbea8a2d4e 100644 --- a/chip/mchp/registers-mec152x.h +++ b/chip/mchp/registers-mec152x.h @@ -729,6 +729,7 @@ /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT 6 +#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT /* * In MECxxxx documentation GPIO numbers are octal, each control diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h index 90b2d5ef83..4d8ef775df 100644 --- a/chip/mchp/registers-mec1701.h +++ b/chip/mchp/registers-mec1701.h @@ -474,13 +474,12 @@ /* Bit defines for MCHP_PCR_PWR_RST_STS */ #define MCHP_PWR_RST_STS_MASK_RO 0xc8c -#define MCHP_PWR_RST_STS_MASK_RWC 0x170 +#define MCHP_PWR_RST_STS_MASK_RWC 0x060 #define MCHP_PWR_RST_STS_MASK \ ((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC)) #define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ #define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ -#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ #define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ #define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ /* same function, old bit name */ @@ -764,7 +763,7 @@ /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT 6 - +#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT /* * In MECxxxx documentation GPIO numbers are octal, each control * register is located on a 32-bit boundary. @@ -811,6 +810,9 @@ #define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) #define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) #define MCHP_GPIO_CTRL_OUT_LVL BIT(16) +/* MEC170x reserved read-only 0 bit. Value set to 0 */ +#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 +#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0 /* * GPIO Parallel Input and Output registers. |