20 files changed, 57 insertions, 56 deletions

diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index bbff9f009b..cffd7c68f8 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -29,7 +29,7 @@ chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DAC)+=dac.o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
 chip-$(CONFIG_SPI)+=spi.o
 chip-$(CONFIG_PECI)+=peci.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 41f800721a..72cfa3e2b4 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -232,7 +232,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
 				1, 1, 5, 1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 		/*
 		 * Workaround for (b:70537592):
 		 * We have to set chip select pin as input mode in order to
@@ -249,7 +249,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 #endif
 		/* Update PLL settings. */
 		clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
 		/* Enable eSPI pad after changing PLL sequence. */
 		espi_enable_pad(1);
@@ -301,7 +301,8 @@ void clock_init(void)
 	 */
 	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
 
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && \
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Because we don't support eSPI HW reset function (b/111480168) on DX
 	 * version, so we have to reset eSPI configurations during init to
@@ -539,7 +540,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	/* EC sleep */
 	ec_sleep = 1;
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
 	/* Disable eSPI pad. */
 	espi_enable_pad(0);
 #endif
@@ -565,7 +566,7 @@ void clock_sleep_mode_wakeup_isr(void)
 	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
 	if (clock_ec_wake_from_sleep()) {
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
 		/*
 		 * Enable eSPI pad.
 		 * We will not need to enable eSPI pad here if Dx is able to
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index be02a8f813..5542d455a9 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -20,7 +20,7 @@ static const struct ec2i_t keyboard_settings[] = {
 	/* Set IRQ=01h for logical device */
 	{HOST_INDEX_IRQNUMX, 0x01},
 	/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Interrupt request type select (IRQTP) for KBC.
 	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 5e6fd734c4..45fff30c1e 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -84,7 +84,7 @@ static void intc_cpu_int_group_12(void)
 		peci_interrupt();
 		break;
 #endif
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	case IT83XX_IRQ_ESPI:
 		espi_interrupt();
 		break;
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 867d9e024f..8a90bd426d 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -136,7 +136,7 @@ static void keyboard_irq_assert(void)
  */
 static void lpc_generate_smi(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SMI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SMI_L, 1);
@@ -149,7 +149,7 @@ static void lpc_generate_smi(void)
 
 static void lpc_generate_sci(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SCI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SCI_L, 1);
@@ -377,7 +377,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
 	pm_set_status(LPC_ACPI_CMD, mask, 0);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 int lpc_get_pltrst_asserted(void)
 {
 	return !gpio_get_level(GPIO_PCH_PLTRST_L);
@@ -688,7 +688,7 @@ static void lpc_init(void)
 	 */
 	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
 #endif
 
@@ -711,7 +711,7 @@ static void lpc_init(void)
 	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
 	task_enable_irq(IT83XX_IRQ_PMC3_IN);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_init();
 #endif
 	/* Sufficiently initialized */
@@ -726,7 +726,7 @@ static void lpc_init(void)
  */
 DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal)
 {
 	if (lpc_get_pltrst_asserted())
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 2fde34f8f0..39aba42315 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1456,7 +1456,7 @@ enum bram_indices {
 	BRAM_IDX_EC_LOG_STATUS = 0xc,
 
 	/* offset 0x0d ~ 0x1f are reserved for future use. */
-#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * offset 0x20 ~ 0x7b are reserved for future use.
 	 * (apply to x86 platform)
@@ -1508,7 +1508,7 @@ enum bram_ec_logs_status {
  * And they will be used to save panic data if the GPG1 reset mechanism
  * is enabled.
  */
-#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 /* offset 0x80 ~ 0xbf */
 #define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
 #else
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 9725ba4525..ae7fd627bf 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -50,7 +50,7 @@ static void clear_reset_flags(void)
 }
 DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
 
-#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOST_INTERFACE_ESPI)
 static void system_save_panic_data_to_bram(void)
 {
 	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 155fbf385f..226fe23363 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -32,7 +32,7 @@ endif
 chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index 362025ee1c..7a3914194b 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -395,7 +395,7 @@ static void prepare_for_deep_sleep(void)
 #endif
 
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 #else
@@ -475,7 +475,7 @@ static void resume_from_deep_sleep(void)
 	 */
 	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
index a7db914f3b..778990b852 100644
--- a/chip/mchp/espi.c
+++ b/chip/mchp/espi.c
@@ -1386,7 +1386,7 @@ void espi_init(void)
 				(CONFIG_HOSTCMD_ESPI_EC_MODE
 				<< MCHP_ESPI_CAP1_IO_BITPOS);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
 #else
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 9f6a731eb5..9e64281276 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -88,7 +88,7 @@ static void keyboard_irq_assert(void)
 static void lpc_generate_smi(void)
 {
 	CPUTS("LPC Pulse SMI");
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* eSPI: pulse SMI# Virtual Wire low */
 	espi_vw_pulse_wire(VW_SMI_L, 0);
 #else
@@ -106,7 +106,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
 #else
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_pulse_wire(VW_SCI_L, 0);
 #else
 	MCHP_ACPI_PM_STS |= 1;
@@ -129,7 +129,7 @@ static void lpc_update_wake(host_event_t wake_events)
 	 */
 	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_WAKE_L, !wake_events);
 #else
 	/* Signal is asserted low when wake events is non-zero */
@@ -304,7 +304,7 @@ const int acpi_ec_nvic_ibf[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 const int acpi_ec_espi_bar_id[] = {
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
@@ -326,7 +326,7 @@ void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
 
 	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
 			mask;
 	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
@@ -350,7 +350,7 @@ void chip_8042_config(uint32_t io_base)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
 			(io_base << 16) + 0x01ul;
@@ -372,7 +372,7 @@ void chip_8042_config(uint32_t io_base)
 #ifndef CONFIG_KEYBOARD_IRQ_GPIO
 	/* Set up SERIRQ for keyboard */
 	MCHP_8042_KB_CTRL |= BIT(5);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
 	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
 #else
@@ -392,7 +392,7 @@ void chip_8042_config(uint32_t io_base)
  */
 void chip_emi0_config(uint32_t io_base)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
 			(io_base << 16) + 0x01ul;
@@ -442,7 +442,7 @@ void chip_port80_config(uint32_t io_base)
 	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
 			MCHP_P80_RESET_TIMESTAMP_WO;
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
 			(io_base << 16) + 0x01ul;
@@ -484,7 +484,7 @@ static void chip_lpc_iobar_debug(void)
  * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
  *
  */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 static void setup_lpc(void)
 {
 	MCHP_LPC_CFG_BAR |= (1ul << 15);
@@ -545,7 +545,7 @@ static void lpc_init(void)
 		MCHP_PCR_SLP_EN2_ACPI_EC0 +
 		MCHP_PCR_SLP_EN2_MIF8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 	espi_init();
 
@@ -621,7 +621,7 @@ void lpc_set_init_done(int val)
  */
 void lpcrst_interrupt(enum gpio_signal signal)
 {
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/* Initialize LPC module when LRESET# is de-asserted */
 	if (!lpc_get_pltrst_asserted()) {
 		setup_lpc();
@@ -941,10 +941,10 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
  */
 int lpc_get_pltrst_asserted(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * eSPI PLTRST# a VWire or side-band signal
-	 * Controlled by CONFIG_HOSTCMD_ESPI
+	 * Controlled by CONFIG_HOST_INTERFACE_ESPI
 	 */
 	return !espi_vw_get_wire(VW_PLTRST_L);
 #else
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
index dcb5577fc1..434b307968 100644
--- a/chip/mchp/lpc_chip.h
+++ b/chip/mchp/lpc_chip.h
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_LPC_CHIP_H
 #define __CROS_EC_LPC_CHIP_H
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 #include "espi.h"
 
@@ -37,7 +37,7 @@ void lpc_set_init_done(int val);
 
 void lpc_mem_mapped_init(void);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal);
 #endif
 
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
index 5591c818c4..72c96bef8f 100644
--- a/chip/mchp/system.c
+++ b/chip/mchp/system.c
@@ -178,7 +178,7 @@ void system_pre_init(void)
 	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
 
 	/* Manual voltage selection only required for MEC170x and MEC152x */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
 		vtr3_voltage_select(1);
 	else
 		vtr3_voltage_select(0);
@@ -427,7 +427,7 @@ int system_get_scratchpad(uint32_t *value)
  * defined for MEC170x and the IS_ENABLED() macro causes the
  * compiler to evaluate both true and false code paths.
  */
-#if defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_ESPI)
 static void disable_host_ifc_clocks(void)
 {
 	MCHP_ESPI_ACTIVATE &= ~0x01;
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 3a41cfbd53..f872b2d051 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -33,7 +33,7 @@ chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_PECI)+=peci.o
 chip-$(CONFIG_HOSTCMD_SHI)+=shi.o
 chip-$(CONFIG_CEC)+=cec.o
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index ad611973be..ab3bd7f119 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -422,7 +422,7 @@ void __idle(void)
 			 * CSAE bit is set. Please notice this symptom only
 			 * occurs at npcx5.
 			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI)
 			/* Enable Host access wakeup */
 			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
index c6fcf7351b..8e7c76abf1 100644
--- a/chip/npcx/gpio-npcx5.c
+++ b/chip/npcx/gpio-npcx5.c
@@ -67,7 +67,7 @@ static void __gpio_wk0efgh_interrupt(void)
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
 				&&
 			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
index e9e8ad2ad9..c5b7e900f7 100644
--- a/chip/npcx/gpio-npcx9.c
+++ b/chip/npcx/gpio-npcx9.c
@@ -70,7 +70,7 @@ static void __gpio_host_interrupt(void)
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
 					&&
 			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 9bb2de8936..c80bf2960b 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -86,7 +86,7 @@ static void lpc_task_enable_irq(void)
 #endif
 	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_enable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_enable_irq(NPCX_IRQ_WKINTA_2);
@@ -105,7 +105,7 @@ static void lpc_task_disable_irq(void)
 #endif
 	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_disable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_disable_irq(NPCX_IRQ_WKINTA_2);
@@ -137,7 +137,7 @@ static void lpc_generate_smi(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -183,7 +183,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -698,7 +698,7 @@ void host_register_init(void)
 	 * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO.
 	 * This is only supported when CHIP_FAMILY >= NPCX9.
 	 */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
 		sib_write_reg(SIO_OFFSET, 0xFD, 0x0F);
 	/* enable SHM */
 	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
@@ -721,7 +721,7 @@ int lpc_get_pltrst_asserted(void)
 	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 /* Initialize host settings by interrupt */
 void lpc_lreset_pltrst_handler(void)
 {
@@ -771,7 +771,7 @@ static void lpc_init(void)
 	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
 	 * field should be set by firmware.
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* Initialize eSPI module */
 	NPCX_DEVCNT |= 0x08;
 	espi_init();
@@ -787,7 +787,7 @@ static void lpc_init(void)
 	/* Clear Host Access Hold state */
 	NPCX_SMC_CTL = 0xC0;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
 	 * continuous or quiet mode.
@@ -800,7 +800,7 @@ static void lpc_init(void)
 	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
 	 * automatically by toggling them, too. It's unnecessary to set pin mux.
 	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOST_INTERFACE_ESPI)
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
 #endif
@@ -876,7 +876,7 @@ static void lpc_init(void)
 	 * Init PORT80
 	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	NPCX_DP80CTL = 0x2b;
 #else
 	NPCX_DP80CTL = 0x29;
@@ -926,7 +926,7 @@ static void lpc_init(void)
 	/* initial IO port address via SIB-write modules */
 	host_register_init();
 #else
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
 	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
index b62946fc96..424048518e 100644
--- a/chip/npcx/sib.c
+++ b/chip/npcx/sib.c
@@ -19,7 +19,7 @@
  * For eSPI - it is 200 us.
  * For LPC - it is 5 us.
  */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #define HOST_TRANSACTION_TIMEOUT_US 200
 #else
 #define HOST_TRANSACTION_TIMEOUT_US 5
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index ac7056330f..97fcd01c41 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -872,7 +872,7 @@ void system_pre_init(void)
 		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
 #endif
 		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_HOST_INTERFACE_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;