diff options
Diffstat (limited to 'chip')
322 files changed, 0 insertions, 92506 deletions
diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h deleted file mode 100644 index e804bd72e8..0000000000 --- a/chip/ish/aontaskfw/ish_aon_share.h +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ISH_AON_SHARE_H -#define __CROS_EC_ISH_AON_SHARE_H - -#include "common.h" -#include "ia_structs.h" -#include "power_mgt.h" - -/* magic ID for valid aontask image sanity check */ -#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ - -/* aontask error code */ -#define AON_SUCCESS 0 -#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 -#define AON_ERROR_DMA_FAILED 2 - - -/* shared data structure between main FW and aontask */ -struct ish_aon_share { - /* magic ID */ - uint32_t magic_id; - /* error counter */ - uint32_t error_count; - /* last error */ - int last_error; - /* aontask's TSS segment entry */ - struct tss_entry *aon_tss; - /* aontask's LDT start address */ - ldt_entry *aon_ldt; - /* aontask's LDT's limit size */ - uint32_t aon_ldt_size; - /* current power state, see chip/ish/power_mgt.h */ - enum ish_pm_state pm_state; - /* for store/restore main FW's IDT */ - struct idt_header main_fw_idt_hdr; - - /** - * main FW's read only code and data region in main SRAM, - * address need 64 bytes align due to DMA requirement - */ - uint32_t main_fw_ro_addr; - uint32_t main_fw_ro_size; - - /** - * main FW's read and write data region in main SRAM, - * address need 64 bytes align due to DMA requirement - */ - uint32_t main_fw_rw_addr; - uint32_t main_fw_rw_size; -} __packed; - -#endif /* __CROS_EC_ISH_AON_SHARE_H */ diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c deleted file mode 100644 index 183c61f97a..0000000000 --- a/chip/ish/aontaskfw/ish_aontask.c +++ /dev/null @@ -1,708 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * ISH aontask is a seprated very small program from main FW, not like main FW - * resides in main SRAM, aontask resides in a small AON memory (ISH3 has no - * seprated AON memory, reserved last 4KB of main SRAM for AON use, from ISH4, - * there is seprated AON memory, 4KB for ISH4, and 8KB for ISH5). - * - * When ISH entered into low power states, aontask may get switched and run, - * aontask managments the main SRAM and is responsible for store and restore - * main FW's running context, for example, when entering D0i2 state, put main - * SRAM into retention mode, when exit D0i2 state and before switch back to - * main FW, put main SRAM into normal access mode, when entering D0i3 state, - * at first stores main FW's writeable data into IMR DDR (read only code and - * data already have copies in IMR), then power off the main SRAM completely, - * when exit D0i3 state, at first power on the main SRAM, and restore main FW's - * code and data from IMR to main SRAM, then switch back to main FW. - * - * On ISH, except the hpet timer, also have other wakeup sources, peripheral - * events, such as gpio interrupt, uart interrupt, ipc interrupt, I2C and SPI - * access are also can wakeup ISH. ISH's PMU (power management unit HW) will - * manage these wakeup sources and transfer to a PMU wakeup interrupt which - * can wakeup aontask, and aontask will handle it, when aontask got up, and - * swiched back to main FW, main FW will receive the original wakeup source - * interrupt which triggered the PMU wakeup interrupt in aontask, then main FW - * handle the original interrupt normally. - * - * In most of the time, aontask is in halt state, and waiting for PMU wakeup - * interrupt to wakeup (reset prep interrupt also can wakeup aontask - * if CONFIG_ISH_PM_RESET_PREP defined), after wakeup, aontask will handle the - * low power states exit process and finaly switch back to main FW. - * - * aontask is running in the 32bit protection mode with flat memory segment - * settings, paging and cache are disabled (cache will be power gated). - * - * We use x86's hardware context switching mechanism for the switching of - * main FW and aontask. - * see https://wiki.osdev.org/Context_Switching - * https://en.wikipedia.org/wiki/Task_state_segment - * - */ - -#include "common.h" -#include "ia_structs.h" -#include "ish_aon_share.h" -#include "ish_dma.h" -#include "power_mgt.h" - -/** - * ISH aontask only need handle PMU wakeup interrupt and reset prep interrupt - * (if CONFIG_ISH_PM_RESET_PREP defined), before switch to aontask, all other - * interrupts should be masked. Since aontask is a seprated program from - * main FW, and the main SRAM will be power offed or will be put in in - * retention mode, aontask need its own IDT to handle PMU wakeup interrupt and - * reset prep interrupt (if CONFIG_ISH_PM_RESET_PREP defined) - * - * Due to very limit AON memory size (typically total 4KB), we don't want to - * define and allocate whole 256 entries for aontask'IDT, that almost need 2KB - * (256 * 8), so we just defined the only needed IDT entries: - * AON_IDT_ENTRY_VEC_FIRST ~ AON_IDT_ENTRY_VEC_LAST - */ -#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC - -#ifdef CONFIG_ISH_PM_RESET_PREP -/** - * assume reset prep interrupt vector is greater than PMU wakeup interrupt - * vector, and also need handle reset prep interrupt - * (if CONFIG_ISH_PM_RESET_PREP defined) - */ -#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC -#else -/* only need handle single PMU wakeup interrupt */ -#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC -#endif - -static void handle_reset(enum ish_pm_state pm_state); - -/* ISR for PMU wakeup interrupt */ -static void pmu_wakeup_isr(void) -{ - /** - * Indicate completion of servicing the interrupt to IOAPIC first - * then indicate completion of servicing the interrupt to LAPIC - */ - IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC; - LAPIC_EOI_REG = 0x0; - - __asm__ volatile ("iret;"); - - __builtin_unreachable(); -} - -/* ISR for reset prep interrupt */ -static void reset_prep_isr(void) -{ - /* mask reset prep avail interrupt */ - PMU_RST_PREP = PMU_RST_PREP_INT_MASK; - - /** - * Indicate completion of servicing the interrupt to IOAPIC first - * then indicate completion of servicing the interrupt to LAPIC - */ - IOAPIC_EOI_REG = ISH_RESET_PREP_VEC; - LAPIC_EOI_REG = 0x0; - - handle_reset(ISH_PM_STATE_RESET_PREP); - - __builtin_unreachable(); -} - -/** - * Use a static data array for aon IDT, and setting IDT header for IDTR - * register - * - * Due to very limit AON memory size (typically total 4KB), we don't want to - * define and allocate whole 256 entries for aontask'IDT, that almost need 2KB - * (256 * 8), so we just defined the only needed IDT entries: - * AON_IDT_ENTRY_VEC_FIRST ~ AON_IDT_ENTRY_VEC_LAST - * - * Since on x86, the IDT entry index (count from 0) is also the interrupt - * vector number, for IDT header, the 'start' filed still need to point to - * the entry 0, and 'size' must count from entry 0. - * - * We only allocated memory for entry AON_IDT_ENTRY_VEC_FIRST to - * AON_IDT_ENTRY_VEC_LAST, a little trick, but works well on ISH - * - * ------>---------------------------<----- aon_idt_hdr.start - * | | entry 0 | - * | +-------------------------+ - * | | ... | - * | +-------------------------+<----- - * aon_idt_hdr.size | AON_IDT_ENTRY_VEC_FIRST | | - * | +-------------------------+ | - * | | ... | allocated memory in aon_idt - * | +-------------------------+ | - * | | AON_IDT_ENTRY_VEC_LAST | | - * ------>+-------------------------+<----- - * | ... | - * +-------------------------+ - * | entry 255 | - * --------------------------- - */ - -static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST + 1]; - -static struct idt_header aon_idt_hdr = { - - .limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1, - .entries = (struct idt_entry *)((uint32_t)&aon_idt - - (sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST)) -}; - -/* aontask entry point function */ -void ish_aon_main(void); - -/** - * 8 bytes reserved on stack, just for GDB to show the correct stack - * information when doing source code level debuging - */ -#define AON_SP_RESERVED (8) - -/* TSS segment for aon task */ -static struct tss_entry aon_tss = { - .prev_task_link = 0, - .reserved1 = 0, - .esp0 = (uint8_t *)(CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED), - /* entry 1 in LDT for data segment */ - .ss0 = 0xc, - .reserved2 = 0, - .esp1 = 0, - .ss1 = 0, - .reserved3 = 0, - .esp2 = 0, - .ss2 = 0, - .reserved4 = 0, - .cr3 = 0, - /* task excute entry point */ - .eip = (uint32_t)&ish_aon_main, - .eflags = 0, - .eax = 0, - .ecx = 0, - .edx = 0, - .ebx = 0, - /* set stack top pointer at the end of usable aon memory */ - .esp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED, - .ebp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED, - .esi = 0, - .edi = 0, - /* entry 1 in LDT for data segment */ - .es = 0xc, - .reserved5 = 0, - /* entry 0 in LDT for code segment */ - .cs = 0x4, - .reserved6 = 0, - /* entry 1 in LDT for data segment */ - .ss = 0xc, - .reserved7 = 0, - /* entry 1 in LDT for data segment */ - .ds = 0xc, - .reserved8 = 0, - /* entry 1 in LDT for data segment */ - .fs = 0xc, - .reserved9 = 0, - /* entry 1 in LDT for data segment */ - .gs = 0xc, - .reserved10 = 0, - .ldt_seg_selector = 0, - .reserved11 = 0, - .trap_debug = 0, - - /** - * TSS's limit specified as 0x67, to allow the task has permission to - * access I/O port using IN/OUT instructions,'iomap_base_addr' field - * must be greater than or equal to TSS' limit - * see 'I/O port permissions' on - * https://en.wikipedia.org/wiki/Task_state_segment - */ - .iomap_base_addr = GDT_DESC_TSS_LIMIT -}; - -/** - * define code and data LDT segements for aontask - * code : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0 - * data : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0 - */ -static ldt_entry aon_ldt[2] = { - - /** - * entry 0 for code segment - * base: 0x0 - * limit: 0xFFFFFFFF - * flag: 0x9B, Present = 1, DPL = 0, code segment - */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS), - - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS) - }, - - /** - * entry 1 for data segment - * base: 0x0 - * limit: 0xFFFFFFFF - * flag: 0x93, Present = 1, DPL = 0, data segment - */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS), - - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS) - } -}; - - -/* shared data structure between main FW and aon task */ -struct ish_aon_share aon_share = { - .magic_id = AON_MAGIC_ID, - .error_count = 0, - .last_error = AON_SUCCESS, - .aon_tss = &aon_tss, - .aon_ldt = &aon_ldt[0], - .aon_ldt_size = sizeof(aon_ldt), -}; - -/* snowball structure */ -#if defined(CHIP_FAMILY_ISH3) -/* on ISH3, reused ISH2PMC IPC message registers */ -#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE -#else -/* from ISH4, used reserved rom part of AON memory */ -#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) -#endif - -struct snowball_struct *snowball = (void *)SNOWBALL_BASE; - - -/* In IMR DDR, ISH FW image has a manifest header */ -#define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000) - -/* simple count based delay */ -static inline void delay(uint32_t count) -{ - while (count) - count--; -} - -static int store_main_fw(void) -{ - int ret; - uint64_t imr_fw_addr; - uint64_t imr_fw_rw_addr; - - imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + - ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); - - /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ - CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA; - - /* store main FW's read and write data region to IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - imr_fw_rw_addr, - aon_share.main_fw_rw_addr, - aon_share.main_fw_rw_size, - SRAM_TO_UMA); - - /* enable BCG for DMA, DMA can't be accessed now */ - CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; - - if (ret != DMA_RC_OK) { - - aon_share.last_error = AON_ERROR_DMA_FAILED; - aon_share.error_count++; - - return AON_ERROR_DMA_FAILED; - } - - return AON_SUCCESS; -} - -static int restore_main_fw(void) -{ - int ret; - uint64_t imr_fw_addr; - uint64_t imr_fw_ro_addr; - uint64_t imr_fw_rw_addr; - - imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + - ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - - imr_fw_ro_addr = (imr_fw_addr - + aon_share.main_fw_ro_addr - - CONFIG_RAM_BASE); - - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); - - /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ - CCU_BCG_EN = CCU_BCG_EN & ~CCU_BCG_BIT_DMA; - - /* restore main FW's read only code and data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_ro_addr, - imr_fw_ro_addr, - aon_share.main_fw_ro_size, - UMA_TO_SRAM); - - if (ret != DMA_RC_OK) { - - aon_share.last_error = AON_ERROR_DMA_FAILED; - aon_share.error_count++; - - /* enable BCG for DMA, DMA can't be accessed now */ - CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; - - return AON_ERROR_DMA_FAILED; - } - - /* restore main FW's read and write data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_rw_addr, - imr_fw_rw_addr, - aon_share.main_fw_rw_size, - UMA_TO_SRAM - ); - - /* enable BCG for DMA, DMA can't be accessed now */ - CCU_BCG_EN = CCU_BCG_EN | CCU_BCG_BIT_DMA; - - if (ret != DMA_RC_OK) { - - aon_share.last_error = AON_ERROR_DMA_FAILED; - aon_share.error_count++; - - return AON_ERROR_DMA_FAILED; - } - - return AON_SUCCESS; -} - -#if defined(CHIP_FAMILY_ISH3) -/* on ISH3, the last SRAM bank is reserved for AON use */ -#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1) -#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) -/* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */ -#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS -#else -#error "CHIP_FAMILY_ISH(3|4|5) must be defined" -#endif - -/** - * check SRAM bank i power gated status in PMU_SRAM_PG_EN register - * 1: power gated 0: not power gated - */ -#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) - -/* enable power gate of a SRAM bank */ -#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) - -/* disable power gate of a SRAM bank */ -#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) - -/** - * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register - * 1: disabled 0: enabled - */ -#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) - -/* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) - -/* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) - -/* SRAM needs time to warm up after power on */ -#define SRAM_WARM_UP_DELAY_CNT 10 - -/* SRAM needs time to enter retention mode */ -#define CYCLES_PER_US 100 -#define SRAM_RETENTION_US_DELAY 5 -#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) - -static void sram_power(int on) -{ - int i; - uint32_t bank_size; - uint32_t sram_addr; - uint32_t erase_cfg; - - bank_size = CONFIG_RAM_BANK_SIZE; - sram_addr = CONFIG_RAM_BASE; - - /** - * set erase size as one bank, erase control register using DWORD as - * size unit, and using 0 based length, i.e if set 0, will erase one - * DWORD - */ - erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1; - - for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) { - - if (on && (BANK_PG_STATUS(i) || BANK_DISABLE_STATUS(i))) { - - /* power on and enable a bank */ - BANK_PG_DISABLE(i); - - delay(SRAM_WARM_UP_DELAY_CNT); - - BANK_ENABLE(i); - - /* erase a bank */ - ISH_SRAM_CTRL_ERASE_ADDR = sram_addr + (i * bank_size); - ISH_SRAM_CTRL_ERASE_CTRL = erase_cfg; - - /* wait erase complete */ - while (ISH_SRAM_CTRL_ERASE_CTRL & 0x1) - continue; - - } else { - /* disable and power off a bank */ - BANK_DISABLE(i); - BANK_PG_ENABLE(i); - } - - /** - * clear interrupt status register, not allow generate SRAM - * interrupts. Bringup already masked all SRAM interrupts when - * booting ISH - */ - ISH_SRAM_CTRL_INTR = 0xFFFFFFFF; - - } -} - -static void handle_d0i2(void) -{ - /* set main SRAM into retention mode*/ - PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT - | PMU_LDO_RETENTION_BIT; - - /* delay some cycles before halt */ - delay(SRAM_RETENTION_CYCLES_DELAY); - - ish_mia_halt(); - /* wakeup from PMU interrupt */ - - /* set main SRAM intto normal mode */ - PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT; - - /** - * poll LDO_READY status to make sure SRAM LDO is on - * (exited retention mode) - */ - while (!(PMU_LDO_CTRL & PMU_LDO_READY_BIT)) - continue; -} - -static void handle_d0i3(void) -{ - int ret; - - /* store main FW 's context to IMR DDR from main SRAM */ - ret = store_main_fw(); - - /* if store main FW failed, then switch back to main FW */ - if (ret != AON_SUCCESS) - return; - - /* power off main SRAM */ - sram_power(0); - - ish_mia_halt(); - /* wakeup from PMU interrupt */ - - /* power on main SRAM */ - sram_power(1); - - /* restore main FW 's context to main SRAM from IMR DDR */ - ret = restore_main_fw(); - - if (ret != AON_SUCCESS) { - /* we can't switch back to main FW now, reset ISH */ - handle_reset(ISH_PM_STATE_RESET); - } -} - -static void handle_d3(void) -{ - /* handle D3 */ - handle_reset(ISH_PM_STATE_RESET); -} - -static void handle_reset(enum ish_pm_state pm_state) -{ - /* disable watch dog */ - WDT_CONTROL &= ~WDT_CONTROL_ENABLE_BIT; - - /* disable all gpio interrupts */ - ISH_GPIO_GRER = 0; - ISH_GPIO_GFER = 0; - ISH_GPIO_GIMR = 0; - - /* disable CSME CSR irq */ - IPC_PIMR &= ~IPC_PIMR_CSME_CSR_BIT; - - /* power off main SRAM */ - sram_power(0); - - while (1) { - /** - * check if host ish driver already set the DMA enable flag - * - * ISH FW and ISH ipc host driver using IPC_ISH_RMP2 register - * for synchronization during ISH boot. - * ISH ipc host driver will set DMA_ENABLED_MASK bit when it - * is loaded and starts, and clear this bit when it is removed. - * - * see: https://github.com/torvalds/linux/blob/master/drivers/ - * hid/intel-ish-hid/ipc/ipc.c - * - * we have two kinds of reset situations need to handle here: - * 1: reset ISH via uart console cmd or ectool host cmd - * 2: S0 -> Sx (reset_prep interrupt) - * - * for #1, ISH ipc host driver no changed states, - * DMA_ENABLED_MASK bit always set, so, will reset ISH directly - * - * for #2, ISH ipc host driver changed states, and cleared - * DMA_ENABLED_MASK bit, then ISH FW received reset_prep - * interrupt, ISH will stay in this while loop (most time in - * halt state), waiting for DMA_ENABLED_MASK bit was set and - * reset ISH then. Since ISH ROM have no power managment, stay - * in aontask can save more power especially if system stay in - * Sx for long time. - * - */ - if (IPC_ISH_RMP2 & DMA_ENABLED_MASK) { - - /* clear ISH2HOST doorbell register */ - *IPC_ISH2HOST_DOORBELL_ADDR = 0; - - /* clear error register in MISC space */ - MISC_ISH_ECC_ERR_SRESP = 1; - - /* - * Disable power gating of RF(Cache) and ROMs. - * - * Before switch to aon task, RF and ROMs are already - * power gated, so we need disable the power gating - * before reset to ROM, to make sure ROM code runs - * correctly. - */ - PMU_RF_ROM_PWR_CTRL = 0; - - /* reset ISH minute-ia cpu core, will goto ISH ROM */ - ish_mia_reset(); - - __builtin_unreachable(); - } - - ish_mia_halt(); - } - -} - -static void handle_unknown_state(void) -{ - aon_share.last_error = AON_ERROR_NOT_SUPPORT_POWER_MODE; - aon_share.error_count++; - - /* switch back to main FW */ -} - -void ish_aon_main(void) -{ - - /* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */ - aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); - - aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) { - /* - * set reset prep interrupt gate using LDT code segment - * selector(0x4) - */ - aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] - .dword_lo = - GEN_IDT_DESC_LO(&reset_prep_isr, 0x4, IDT_DESC_FLAGS); - - aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] - .dword_up = - GEN_IDT_DESC_UP(&reset_prep_isr, 0x4, IDT_DESC_FLAGS); - } - - while (1) { - - /** - * will start to run from here when switched to aontask from - * the second time - */ - - /* save main FW's IDT and load aontask's IDT */ - __asm__ volatile ( - "sidtl %0;\n" - "lidtl %1;\n" - : - : "m" (aon_share.main_fw_idt_hdr), - "m" (aon_idt_hdr) - ); - - aon_share.last_error = AON_SUCCESS; - - switch (aon_share.pm_state) { - case ISH_PM_STATE_D0I2: - handle_d0i2(); - break; - case ISH_PM_STATE_D0I3: - handle_d0i3(); - break; - case ISH_PM_STATE_D3: - handle_d3(); - break; - case ISH_PM_STATE_RESET: - case ISH_PM_STATE_RESET_PREP: - handle_reset(aon_share.pm_state); - break; - default: - handle_unknown_state(); - break; - } - - /* check if D3 rising status */ - if (PMU_D3_STATUS & - (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) { - aon_share.pm_state = ISH_PM_STATE_D3; - handle_d3(); - } - - /* restore main FW's IDT and switch back to main FW */ - __asm__ volatile( - "lidtl %0;\n" - "iret;" - : - : "m" (aon_share.main_fw_idt_hdr) - ); - } -} diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S deleted file mode 100644 index ca5f54f705..0000000000 --- a/chip/ish/aontaskfw/ish_aontask.lds.S +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <config_chip.h> - -ENTRY(ish_aon_main); - -#define SRAM_START CONFIG_AON_RAM_BASE -#define SRAM_RW_LEN (CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE) - -/* reserved stack size */ -#define STACK_SIZE (256) - -/** - * resered 8 bytes for GDB showing correct stack - * information during source code level debuging - */ -#define RESERVED_GDB_SIZE (8) - -#define RAM_LEN (SRAM_RW_LEN - STACK_SIZE - RESERVED_GDB_SIZE) - -/** - * AON memory layout - * +---------+------------+-----------------+-----------------+ - * | RAM_LEN | STACK_SIZE | 8 Bytes for GDB | ROM (384 Bytes) | - * +---------+------------+-----------------+-----------------+ - * - * The first 256 bytes of the AON ROM is reserved for ECOS use. - * The remaining 128 bytes of the AON ROM may be used by the shim - * loader. - */ - -MEMORY -{ - /* leave STACK_SIZE bytes in the end of memory for stack */ - RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN -} - -SECTIONS -{ - /* AON parts visible to FW are linked to the beginning of the AON area */ - .data.aon_share : AT(SRAM_START) - { - KEEP(*(.data.aon_share)) - } > RAM - - .data : - { - *(.data) - *(.data*) - } > RAM - - .text : - { - *(.text) - *(.text*) - } > RAM - - .bss : - { - *(.bss) - *(.bss*) - } > RAM - - .stack_tag : - { - KEEP(*(.stack_tag)) - } > RAM - -} diff --git a/chip/ish/build.mk b/chip/ish/build.mk deleted file mode 100644 index bce9322184..0000000000 --- a/chip/ish/build.mk +++ /dev/null @@ -1,92 +0,0 @@ -# -*- makefile -*- -# Copyright 2016 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# ISH chip specific files build -# - -# ISH SoC has a Minute-IA core -CORE:=minute-ia -# Allow the i486 instruction set -CFLAGS_CPU+=-march=pentium -mtune=i486 -m32 - -ifeq ($(CONFIG_LTO),y) -# Re-include the core's build.mk file so we can remove the lto flag. -include core/$(CORE)/build.mk -endif - -# Required chip modules -chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o -chip-$(CHIP_VARIANT_ISH5P4)+=reset_prep_wr.o -chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o -chip-$(CONFIG_HOSTCMD_HECI)+=heci.o system_state_subsys.o ipc_heci.o -chip-$(CONFIG_HID_HECI)+=hid_subsys.o -chip-$(CONFIG_HID_HECI)+=heci.o system_state_subsys.o ipc_heci.o -chip-$(CONFIG_DMA_PAGING)+=dma.o -chip-$(CONFIG_LOW_POWER_IDLE)+=power_mgt.o - -# There is no framework for on-board tests in ISH. Do not specify any. -test-list-y= - -# Build ish aon task fw -ish-aon-name=ish_aontask -ish-aon-$(CONFIG_ISH_PM_AONTASK)=aontaskfw/ish_aontask.o dma.o - -# Rules for building ish aon task fw -ish-aon-out=$(out)/aontaskfw -ish-aon-bin-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).bin -ish-aon-elf-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).elf -ish-aon-lds-$(CONFIG_ISH_PM_AONTASK)=$(ish-aon-out)/$(ish-aon-name).lds - -ish-aon-objs=$(call objs_from_dir,$(ish-aon-out)/chip/$(CHIP),ish-aon) -ish-aon-deps+=$(addsuffix .d, $(ish-aon-objs)) $(ish-aon-lds-y).d - -cmd_ish_aon_elf = $(CC) $(ish-aon-objs) $(LDFLAGS) \ - -o $@ -Wl,-T,$< -Wl,-Map,$(patsubst %.elf,%.map,$@) - -PROJECT_EXTRA+=$(ish-aon-bin-y) -deps-$(CONFIG_ISH_PM_AONTASK)+=$(ish-aon-deps) - -$(out)/$(PROJECT).bin: $(ish-aon-bin-y) $(out)/RW/$(PROJECT).RW.flat - -$(ish-aon-bin-y): $(ish-aon-elf-y) - $(call quiet,elf_to_bin,EXTBIN ) - -$(ish-aon-elf-y): $(ish-aon-lds-y) $(ish-aon-objs) - $(call quiet,ish_aon_elf,LD ) - -$(ish-aon-lds-y): chip/$(CHIP)/aontaskfw/ish_aontask.lds.S - -@ mkdir -p $(@D) - $(call quiet,lds,LDS ) - -$(ish-aon-out)/%.o: %.c - -@ mkdir -p $(@D) - $(call quiet,c_to_o,CC ) - -# Location of the scripts used to pack image -SCRIPTDIR:=./chip/${CHIP}/util - -# Calculate aon binary file size and kernel binary file size -_aon_size_str=$(shell stat -L -c %s $(ish-aon-bin-y)) -_aon_size=$(shell echo "$$(($(_aon_size_str)))") - -_kernel_size_str=$(shell stat -L -c %s $(out)/RW/$(PROJECT).RW.flat) -_kernel_size=$(shell echo "$$(($(_kernel_size_str)))") - -# Commands to convert ec.RW.flat to $@.tmp - This will add the manifest header -# needed to load the FW onto the ISH HW. - -ifeq ($(CONFIG_ISH_PM_AONTASK),y) -cmd_obj_to_bin = ${SCRIPTDIR}/pack_ec.py -o $@.tmp \ - -k $(out)/RW/$(PROJECT).RW.flat \ - --kernel-size $(_kernel_size) \ - -a $(ish-aon-bin-y) \ - --aon-size $(_aon_size); -else -cmd_obj_to_bin = ${SCRIPTDIR}/pack_ec.py -o $@.tmp \ - -k $(out)/RW/$(PROJECT).RW.flat \ - --kernel-size $(_kernel_size); -endif diff --git a/chip/ish/clock.c b/chip/ish/clock.c deleted file mode 100644 index ac818f5733..0000000000 --- a/chip/ish/clock.c +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "clock.h" -#include "common.h" -#include "util.h" -#include "power_mgt.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - - -void clock_init(void) -{ - /* No initialization for clock on ISH */ -} - -void clock_refresh_console_in_use(void) -{ - /** - * on ISH, uart interrupt can only wakeup ISH from low power state via - * CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin - * exposed, so, we need block ISH enter low power state for a while - * when console is in use - */ - ish_pm_refresh_console_in_use(); -} diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h deleted file mode 100644 index b4dea95767..0000000000 --- a/chip/ish/config_chip.h +++ /dev/null @@ -1,132 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -/* CPU core BFD configuration */ -#include "core/minute-ia/config_core.h" - -#ifndef __ASSEMBLER__ -/* Needed for PANIC_DATA_BASE */ -#include "ish_persistent_data.h" -#endif - -/* Number of IRQ vectors on the ISH */ -#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1) - -/* Use a bigger console output buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Maximum number of deferrable functions */ -#define DEFERRABLE_MAX_COUNT 8 - -/* this macro causes 'pause' and reduces loop counts inside loop. */ -#define CPU_RELAX() asm volatile("rep; nop" ::: "memory") - -/*****************************************************************************/ -/* Memory Layout */ -/*****************************************************************************/ - -#ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_RAM_BASE 0xFF200000 -#else -#define CONFIG_RAM_BASE 0xFF000000 -#endif -#define CONFIG_RAM_SIZE 0x000A0000 -#define CONFIG_RAM_BANK_SIZE 0x00008000 - -#if defined(CHIP_FAMILY_ISH3) -/* On ISH3, there is no separate AON memory; use last 4KB of SRAM */ -#define CONFIG_AON_RAM_BASE 0xFF09F000 -#define CONFIG_AON_RAM_SIZE 0x00001000 -#elif defined(CHIP_FAMILY_ISH4) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00001000 -#elif defined(CHIP_FAMILY_ISH5) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00002000 -#else -#error "CHIP_FAMILY_ISH(3|4|5) must be defined" -#endif - -/* The end of the AON memory is reserved for read-only use */ -#define CONFIG_AON_PERSISTENT_SIZE 0x180 -#define CONFIG_AON_PERSISTENT_BASE (CONFIG_AON_RAM_BASE \ - + CONFIG_AON_RAM_SIZE \ - - CONFIG_AON_PERSISTENT_SIZE) - -/* Store persistent panic data in AON memory. */ -#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data)) - -/* System stack size */ -#define CONFIG_STACK_SIZE 1024 - -/* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 640 -#define LARGER_TASK_STACK_SIZE 1024 -#define HUGE_TASK_STACK_SIZE 2048 -/* Default task stack size */ -#define TASK_STACK_SIZE 640 - -/****************************************************************************/ -/* Define our flash layout. */ -/* Note: The 4 macros below are unnecesasry for the ISH chip. However they are - * referenced in common files and hence retained to avoid build errors. - */ - -/* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 -/* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00000000 -/* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000000 -/* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 - -#include "config_flash_layout.h" - -/*****************************************************************************/ -/* Watchdog Timer Configuration */ -/*****************************************************************************/ -#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define WDT_CLOCK_HZ (120000000) /* 120 MHz */ -#elif defined(CHIP_FAMILY_ISH4) -#define WDT_CLOCK_HZ (100000000) /* 100 MHz */ -#else -#error "CHIP_FAMILY_ISH(3|4|5) must be defined" -#endif - -/* Provide WDT vec number to Minute-IA core implementation */ -#undef CONFIG_MIA_WDT_VEC -#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC - -/****************************************************************************/ -/* Customize the build */ -/* Optional features present on this chip */ - -/* ISH uses 64-bit hardware timer */ -#define CONFIG_HWTIMER_64BIT - -/* Macro used with gpio.inc, ISH only has port 0 */ -#define GPIO_PIN(index) 0, (1 << (index)) -#define GPIO_PIN_MASK(m) .port = 0, .mask = (m) - -#ifdef CHIP_VARIANT_ISH5P4 -/* Use combined ISR for ipc communication between host and ISH */ -#define CONFIG_ISH_HOST2ISH_COMBINED_ISR -/* Use Synopsys Designware uart */ -#define CONFIG_ISH_DW_UART -#else -/* Need to clear ISH fabric error */ -#define CONFIG_ISH_CLEAR_FABRIC_ERRORS -#endif - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h deleted file mode 100644 index 0430baf3eb..0000000000 --- a/chip/ish/config_flash_layout.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H -#define __CROS_EC_CONFIG_FLASH_LAYOUT_H - -/* Mem-mapped, No external SPI for ISH */ -#undef CONFIG_EXTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_SPI_FLASH - -#ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_ISH_BOOT_START 0xFF200000 -#else -#define CONFIG_ISH_BOOT_START 0xFF000000 -#endif - -/*****************************************************************************/ -/* The following macros are not applicable for ISH, however the build fails if - * they are not defined. Ideally, there should be an option in EC build to - * turn off SPI and flash, making these unnecessary. - */ - -#define CONFIG_MAPPED_STORAGE_BASE 0x0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) -#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 - -/* Unused for ISH - loader is external to ISH FW */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 - - -/* RO/RW images - not relevant for ISH - */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE - -/*****************************************************************************/ - -/* Not relevant for ISH */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 - -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) - -/* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) - -/* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 - -#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/ish/dma.c b/chip/ish/dma.c deleted file mode 100644 index a409dc6ad3..0000000000 --- a/chip/ish/dma.c +++ /dev/null @@ -1,193 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* DMA module for ISH */ - -#include "common.h" -#include "console.h" -#include "registers.h" -#include "ish_dma.h" -#include "util.h" - -static int dma_init_called; /* If ish_dma_init is called */ - -static int dma_poll(uint32_t addr, uint32_t expected, uint32_t mask) -{ - int retval = -1; - uint32_t counter = 0; - - /* - * The timeout is approximately 2.2 seconds according to - * value of UINT32_MAX, 120MHZ ISH clock frequency and - * instruction count which is around 4. - */ - while (counter < (UINT32_MAX / 64)) { - /* test condition */ - if ((REG32(addr) & mask) == expected) { - retval = DMA_RC_OK; - break; - } - counter++; - } - - return retval; -} - -void ish_dma_ocp_timeout_disable(void) -{ - uint32_t ctrl = OCP_AGENT_CONTROL; - - OCP_AGENT_CONTROL = ctrl & OCP_RESPONSE_TO_DISABLE; -} - -static inline uint32_t interrupt_lock(void) -{ - uint32_t eflags = 0; - __asm__ volatile("pushfl;" /* save eflag value */ - "popl %0;" - "cli;" - : "=r"(eflags)); /* shut off interrupts */ - return eflags; -} - -static inline void interrupt_unlock(uint32_t eflags) -{ - __asm__ volatile("pushl %0;" /* restore elfag values */ - "popfl;" - : - : "r"(eflags)); -} - -void dma_configure_psize(void) -{ - /* Give chan0 512 bytes for high performance, and chan1 128 bytes. */ - DMA_PSIZE_01 = DMA_PSIZE_UPDATE | - (DMA_PSIZE_CHAN1_SIZE << DMA_PSIZE_CHAN1_OFFSET) | - (DMA_PSIZE_CHAN0_SIZE << DMA_PSIZE_CHAN0_OFFSET); -} - -void ish_dma_init(void) -{ - uint32_t uma_msb; - - ish_dma_ocp_timeout_disable(); - - /* configure DMA partition size */ - dma_configure_psize(); - - /* set DRAM address 32 MSB for DMA transactions on UMA */ - uma_msb = IPC_UMA_RANGE_LOWER_1; - ish_dma_set_msb(PAGING_CHAN, uma_msb, uma_msb); - - dma_init_called = 1; -} - -int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, - enum dma_mode mode) -{ - uint32_t chan_reg = DMA_REG_BASE + (DMA_CH_REGS_SIZE * chan); - int rc = DMA_RC_OK; - uint32_t eflags; - uint32_t chunk; - - __asm__ volatile("\twbinvd\n"); /* Flush cache before dma start */ - - /* Bringup VNN power rail for accessing SoC fabric */ - PMU_VNN_REQ = (1 << VNN_ID_DMA(chan)); - while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) - continue; - - /* - * shut off interrupts to assure no simultanious - * access to DMA registers - */ - eflags = interrupt_lock(); - - MISC_CHID_CFG_REG = chan; /* Set channel to configure */ - - mode |= NON_SNOOP; - MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */ - - DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */ - DMA_LLP(chan_reg) = 0; /* Linked lists are not used */ - DMA_CTL_LOW(chan_reg) = - 0 /* Set transfer parameters */ | - (DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) | - (DMA_CTL_ADDR_INC << DMA_CTL_SINC_SHIFT) | - (DMA_CTL_ADDR_INC << DMA_CTL_DINC_SHIFT) | - (SRC_TR_WIDTH << DMA_CTL_SRC_TR_WIDTH_SHIFT) | - (DEST_TR_WIDTH << DMA_CTL_DST_TR_WIDTH_SHIFT) | - (SRC_BURST_SIZE << DMA_CTL_SRC_MSIZE_SHIFT) | - (DEST_BURST_SIZE << DMA_CTL_DEST_MSIZE_SHIFT); - - interrupt_unlock(eflags); - while (length) { - chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE - : length; - - if (rc != DMA_RC_OK) - break; - - eflags = interrupt_lock(); - MISC_CHID_CFG_REG = chan; /* Set channel to configure */ - DMA_CTL_HIGH(chan_reg) = - chunk; /* Set number of bytes to transfer */ - DMA_DAR(chan_reg) = dst; /* Destination address */ - DMA_SAR(chan_reg) = src; /* Source address */ - DMA_EN_REG = DMA_CH_EN_BIT(chan) | - DMA_CH_EN_WE_BIT(chan); /* Enable the channel */ - interrupt_unlock(eflags); - - rc = ish_wait_for_dma_done( - chan); /* Wait for trans completion */ - - dst += chunk; - src += chunk; - length -= chunk; - } - - /* Mark the DMA VNN power rail as no longer needed */ - PMU_VNN_REQ = (1 << VNN_ID_DMA(chan)); - return rc; -} - -void ish_dma_disable(void) -{ - uint32_t channel; - uint32_t counter; - - /* Disable DMA on per-channel basis. */ - for (channel = 0; channel <= DMA_MAX_CHANNEL; channel++) { - MISC_CHID_CFG_REG = channel; - if (DMA_EN_REG & DMA_CH_EN_BIT(channel)) { - /* Write 0 to channel enable bit ... */ - DMA_EN_REG = DMA_CH_EN_WE_BIT(channel); - - /* Wait till it shuts up. */ - counter = 0; - while ((DMA_EN_REG & DMA_CH_EN_BIT(channel)) && - counter < (UINT32_MAX / 64)) - counter++; - } - } - DMA_CLR_ERR_REG = 0xFFFFFFFF; - DMA_CLR_BLOCK_REG = 0xFFFFFFFF; - - DMA_CFG_REG = 0; /* Disable DMA module */ -} - -int ish_wait_for_dma_done(uint32_t ch) -{ - return dma_poll(DMA_EN_REG_ADDR, 0, DMA_CH_EN_BIT(ch)); -} - -void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb) -{ - uint32_t eflags = interrupt_lock(); - MISC_CHID_CFG_REG = chan; /* Set channel to configure */ - MISC_SRC_FILLIN_DMA(chan) = src_msb; - MISC_DST_FILLIN_DMA(chan) = dst_msb; - interrupt_unlock(eflags); -} diff --git a/chip/ish/flash.c b/chip/ish/flash.c deleted file mode 100644 index 8ef4d1a73c..0000000000 --- a/chip/ish/flash.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "flash.h" - - -/** - * Initialize the module. - * - * Applies at-boot protection settings if necessary. - */ -int flash_pre_init(void) -{ - return EC_SUCCESS; -} diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c deleted file mode 100644 index 3d374f3cb8..0000000000 --- a/chip/ish/gpio.c +++ /dev/null @@ -1,172 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for ISH */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define ISH_TOTAL_GPIO_PINS 8 - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) - return 0; - - return !!(ISH_GPIO_GPLR & g->mask); -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - const struct gpio_info *g = gpio_list + signal; - - /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) - return; - - if (value) - ISH_GPIO_GPSR |= g->mask; - else - ISH_GPIO_GPCR |= g->mask; -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - /* Unimplemented GPIOs shouldn't do anything */ - if (port == DUMMY_GPIO_BANK) - return; - - /* ISH does not support level-trigger interrupts; only edge. */ - if (flags & (GPIO_INT_F_HIGH | GPIO_INT_F_LOW)) { - ccprintf("\n\nISH does not support level trigger GPIO for %d " - "0x%02x!\n\n", - port, mask); - } - - /* ISH 3 can't support both rising and falling edge */ - if (IS_ENABLED(CHIP_FAMILY_ISH3) && - (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { - ccprintf("\n\nISH 2/3 does not support both rising & falling " - "edge for %d 0x%02x\n\n", - port, mask); - } - - /* GPSR/GPCR Output high/low */ - if (flags & GPIO_HIGH) /* Output high */ - ISH_GPIO_GPSR |= mask; - else if (flags & GPIO_LOW) /* output low */ - ISH_GPIO_GPCR |= mask; - - /* GPDR pin direction 1 = output, 0 = input*/ - if (flags & GPIO_OUTPUT) - ISH_GPIO_GPDR |= mask; - else /* GPIO_INPUT or un-configured */ - ISH_GPIO_GPDR &= ~mask; - - /* Interrupt is asserted on rising edge */ - if (flags & GPIO_INT_F_RISING) - ISH_GPIO_GRER |= mask; - else - ISH_GPIO_GRER &= ~mask; - - /* Interrupt is asserted on falling edge */ - if (flags & GPIO_INT_F_FALLING) - ISH_GPIO_GFER |= mask; - else - ISH_GPIO_GFER &= ~mask; -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - /* Unimplemented GPIOs shouldn't do anything */ - if (g->port == DUMMY_GPIO_BANK) - return EC_SUCCESS; - - ISH_GPIO_GIMR |= g->mask; - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - ISH_GPIO_GIMR &= ~g->mask; - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - ISH_GPIO_GISR = g->mask; - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - int i; - int flags; - int is_warm = system_is_reboot_warm(); - const struct gpio_info *g = gpio_list; - - for (i = 0; i < GPIO_COUNT; i++, g++) { - - flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels - * or we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - } - - /* disable GPIO interrupts */ - ISH_GPIO_GIMR = 0; - /* clear pending GPIO interrupts */ - ISH_GPIO_GISR = 0xFFFFFFFF; -} - -static void gpio_init(void) -{ - task_enable_irq(ISH_GPIO_IRQ); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -static void gpio_interrupt(void) -{ - int i; - const struct gpio_info *g = gpio_list; - uint32_t gisr = ISH_GPIO_GISR; - uint32_t gimr = ISH_GPIO_GIMR; - - /* mask off any not enabled pins */ - gisr &= gimr; - - for (i = 0; i < GPIO_IH_COUNT; i++, g++) { - if (gisr & g->mask) { - /* write 1 to clear interrupt status bit */ - ISH_GPIO_GISR = g->mask; - gpio_irq_handlers[i](i); - } - } -} -DECLARE_IRQ(ISH_GPIO_IRQ, gpio_interrupt); diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h deleted file mode 100644 index edfb587d21..0000000000 --- a/chip/ish/hbm.h +++ /dev/null @@ -1,195 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __HBM_H -#define __HBM_H - -#include <stdint.h> -#include <stddef.h> - -#include "heci_client.h" - -#define HBM_MAJOR_VERSION 1 -#ifdef HECI_ENABLE_DMA -#define HBM_MINOR_VERSION 2 -#else -#define HBM_MINOR_VERSION 0 -#endif - -#define __packed __attribute__((packed)) - -#define HECI_MSG_REPONSE_FLAG 0x80 - -enum HECI_BUS_MSG { - /* requests */ - HECI_BUS_MSG_VERSION_REQ = 1, - HECI_BUS_MSG_HOST_STOP_REQ = 2, - HECI_BUS_MSG_ME_STOP_REQ = 3, - HECI_BUS_MSG_HOST_ENUM_REQ = 4, - HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5, - HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6, - HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7, - HECI_BUS_MSG_FLOW_CONTROL = 8, - HECI_BUS_MSG_RESET_REQ = 9, - HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A, - HECI_BUS_MSG_DMA_REQ = 0x10, - HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11, - HECI_BUS_MSG_DMA_XFER_REQ = 0x12, - - /* responses */ - HECI_BUS_MSG_VERSION_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ), - HECI_BUS_MSG_HOST_STOP_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ), - HECI_BUS_MSG_HOST_ENUM_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ), - HECI_BUS_MSG_HOST_CLIENT_PROP_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ), - HECI_BUS_MSG_CLIENT_CONNECT_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ), - HECI_BUS_MSG_CLIENT_DISCONNECT_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ), - HECI_BUS_MSG_RESET_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ), - HECI_BUS_MSG_ADD_CLIENT_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ), - HECI_BUS_MSG_DMA_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ), - HECI_BUS_MSG_DMA_ALLOC_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY), - HECI_BUS_MSG_DMA_XFER_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ) -}; - -enum { - HECI_CONNECT_STATUS_SUCCESS = 0, - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1, - HECI_CONNECT_STATUS_ALREADY_EXISTS = 2, - HECI_CONNECT_STATUS_REJECTED = 3, - HECI_CONNECT_STATUS_INVALID_PARAMETER = 4, - HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5, -}; - -struct hbm_version { - uint8_t minor; - uint8_t major; -} __packed; - -struct hbm_version_req { - uint8_t reserved; - struct hbm_version version; -} __packed; - -struct hbm_version_res { - uint8_t supported; - struct hbm_version version; -} __packed; - -struct hbm_enum_req { - uint8_t reserved[3]; -} __packed; - -struct hbm_enum_res { - uint8_t reserved[3]; - uint8_t valid_addresses[32]; -} __packed; - -struct hbm_client_prop_req { - uint8_t address; - uint8_t reserved[2]; -} __packed; - -#define CLIENT_DMA_ENABLE 0x80 - -struct hbm_client_properties { - struct heci_guid protocol_name; /* heci client protocol ID */ - uint8_t protocol_version; /* protocol version */ - /* max connection from host to client. currently only 1 is allowed */ - uint8_t max_number_of_connections; - uint8_t fixed_address; /* not yet supported */ - uint8_t single_recv_buf; /* not yet supported */ - uint32_t max_msg_length; /* max payload size */ - /* not yet supported. [7] enable/disable, [6:0] dma length */ - uint8_t dma_hdr_len; - uint8_t reserved4; - uint8_t reserved5; - uint8_t reserved6; -} __packed; - -struct hbm_client_prop_res { - uint8_t address; - uint8_t status; - uint8_t reserved[1]; - struct hbm_client_properties client_prop; -} __packed; - -struct hbm_client_connect_req { - uint8_t fw_addr; - uint8_t host_addr; - uint8_t reserved; -} __packed; - -struct hbm_client_connect_res { - uint8_t fw_addr; - uint8_t host_addr; - uint8_t status; -} __packed; - -struct hbm_flow_control { - uint8_t fw_addr; - uint8_t host_addr; - uint8_t reserved[5]; -} __packed; - -struct hbm_client_disconnect_req { - uint8_t fw_addr; - uint8_t host_addr; - uint8_t reserved; -} __packed; - -struct hbm_client_disconnect_res { - uint8_t fw_addr; - uint8_t host_addr; - uint8_t status; -} __packed; - -struct hbm_host_stop_req { - uint8_t reason; - uint8_t reserved[2]; -}; - -struct hbm_host_stop_res { - uint8_t reserved[3]; -}; - -/* host bus message : host -> ish */ -struct hbm_h2i { - uint8_t cmd; - union { - struct hbm_version_req ver_req; - struct hbm_enum_req enum_req; - struct hbm_client_prop_req client_prop_req; - struct hbm_client_connect_req client_connect_req; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_req client_disconnect_req; - struct hbm_host_stop_req host_stop_req; - } data; -} __packed; - -/* host bus message : i2h -> host */ -struct hbm_i2h { - uint8_t cmd; - union { - struct hbm_version_res ver_res; - struct hbm_enum_res enum_res; - struct hbm_client_prop_res client_prop_res; - struct hbm_client_connect_res client_connect_res; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_res client_disconnect_res; - struct hbm_host_stop_res host_stop_res; - } data; -} __packed; - -#endif /* __HBM_H */ diff --git a/chip/ish/heci.c b/chip/ish/heci.c deleted file mode 100644 index 309a17c0a1..0000000000 --- a/chip/ish/heci.c +++ /dev/null @@ -1,1026 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "compile_time_macros.h" -#include "console.h" -#include "hbm.h" -#include "heci_client.h" -#include "ipc_heci.h" -#include "system_state.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -struct heci_header { - uint8_t fw_addr; - uint8_t host_addr; - uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */ -} __packed; -#define HECI_MSG_CMPL_SHIFT 15 -#define HECI_MSG_LENGTH_MASK 0x01FF -#define HECI_MSG_LENGTH(length) ((length) & HECI_MSG_LENGTH_MASK) -#define HECI_MSG_IS_COMPLETED(length) \ - (!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT))) - -BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE == - (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header))); - -struct heci_msg { - struct heci_header hdr; - uint8_t payload[HECI_IPC_PAYLOAD_SIZE]; -} __packed; - -/* HECI addresses */ -#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */ -#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */ - -/* A fw client has the same value for both handle and fw address */ -#define TO_FW_ADDR(handle) ((uintptr_t)(handle)) -#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr)) -/* convert client fw address to client context index */ -#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr) - HECI_DYN_CLIENT_ADDR_START) - -/* should be less than HECI_INVALID_HANDLE - 1 */ -BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE); - -struct heci_client_connect { - uint8_t is_connected; /* client is connected to host */ - uint8_t host_addr; /* connected host address */ - - /* receiving message */ - uint8_t ignore_rx_msg; - uint8_t rx_msg[HECI_MAX_MSG_SIZE]; - size_t rx_msg_length; - - uint32_t flow_ctrl_creds; /* flow control */ - struct mutex lock; /* protects against 2 writers */ - struct mutex cred_lock; /* protects flow ctrl */ - int waiting_task; -}; - -struct heci_client_context { - const struct heci_client *client; - void *data; /* client specific data */ - - struct heci_client_connect connect; /* connection context */ - struct ss_subsys_device ss_device; /* system state receiver device */ -}; - -struct heci_bus_context { - ipc_handle_t ipc_handle; /* ipc handle for heci protocol */ - - int num_of_clients; - struct heci_client_context client_ctxs[HECI_MAX_NUM_OF_CLIENTS]; -}; - -/* declare heci bus */ -struct heci_bus_context heci_bus_ctx = { - .ipc_handle = IPC_INVALID_HANDLE, -}; - -static inline struct heci_client_context * -heci_get_client_context(const uint8_t fw_addr) -{ - return &heci_bus_ctx.client_ctxs[TO_CLIENT_CTX_IDX(fw_addr)]; -} - -static inline struct heci_client_connect * -heci_get_client_connect(const uint8_t fw_addr) -{ - struct heci_client_context *cli_ctx = heci_get_client_context(fw_addr); - return &cli_ctx->connect; -} - -static inline int heci_is_client_connected(const uint8_t fw_addr) -{ - struct heci_client_context *cli_ctx = heci_get_client_context(fw_addr); - return cli_ctx->connect.is_connected; -} - -static inline int heci_is_valid_client_addr(const uint8_t fw_addr) -{ - uint8_t cli_idx = TO_CLIENT_CTX_IDX(fw_addr); - - return cli_idx < heci_bus_ctx.num_of_clients; -} - -static inline int heci_is_valid_handle(const heci_handle_t handle) -{ - return heci_is_valid_client_addr((uintptr_t)(handle)); -} - -/* find heci device that contains this system state device in it */ -#define ss_device_to_heci_client_context(ss_dev) \ - ((struct heci_client_context *)((void *)(ss_dev) - \ - (void *)(&(((struct heci_client_context *)0)->ss_device)))) -#define client_context_to_handle(cli_ctx) \ - ((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \ - / sizeof(heci_bus_ctx.client_ctxs[0]) + 1)) - -/* - * each heci device registered as system state device which gets - * system state(e.g. suspend/resume, portrait/landscape) events - * through system state subsystem from host - */ -static int heci_client_suspend(struct ss_subsys_device *ss_device) -{ - struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); - heci_handle_t handle = client_context_to_handle(cli_ctx); - - if (cli_ctx->client->cbs->suspend) - cli_ctx->client->cbs->suspend(handle); - - return EC_SUCCESS; -} - -static int heci_client_resume(struct ss_subsys_device *ss_device) -{ - struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); - heci_handle_t handle = client_context_to_handle(cli_ctx); - - if (cli_ctx->client->cbs->resume) - cli_ctx->client->cbs->resume(handle); - - return EC_SUCCESS; -} - -struct system_state_callbacks heci_ss_cbs = { - .suspend = heci_client_suspend, - .resume = heci_client_resume, -}; - -/* - * This function should be called only by HECI_CLIENT_ENTRY() - */ -heci_handle_t heci_register_client(const struct heci_client *client) -{ - int ret; - heci_handle_t handle; - struct heci_client_context *cli_ctx; - - if (client == NULL || client->cbs == NULL) - return HECI_INVALID_HANDLE; - - /* - * we don't need mutex here since this function is called by - * entry function which is serialized among heci clients. - */ - if (heci_bus_ctx.num_of_clients >= HECI_MAX_NUM_OF_CLIENTS) - return HECI_INVALID_HANDLE; - - /* we only support 1 connection */ - if (client->max_n_of_connections > 1) - return HECI_INVALID_HANDLE; - - if (client->max_msg_size > HECI_MAX_MSG_SIZE) - return HECI_INVALID_HANDLE; - - /* create handle with the same value of fw address */ - handle = (heci_handle_t)(heci_bus_ctx.num_of_clients + - HECI_DYN_CLIENT_ADDR_START); - cli_ctx = &heci_bus_ctx.client_ctxs[heci_bus_ctx.num_of_clients++]; - cli_ctx->client = client; - - if (client->cbs->initialize) { - ret = client->cbs->initialize(handle); - if (ret) { - heci_bus_ctx.num_of_clients--; - return HECI_INVALID_HANDLE; - } - } - - if (client->cbs->suspend || client->cbs->resume) { - cli_ctx->ss_device.cbs = &heci_ss_cbs; - ss_subsys_register_client(&cli_ctx->ss_device); - } - - return handle; -} - -static void heci_build_hbm_header(struct heci_header *hdr, uint32_t length) -{ - hdr->fw_addr = HECI_HBM_ADDRESS; - hdr->host_addr = HECI_HBM_ADDRESS; - hdr->length = length; - /* payload of hbm is less than IPC payload */ - hdr->length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT; -} - -static void heci_build_fixed_client_header(struct heci_header *hdr, - const uint8_t fw_addr, - const uint32_t length) -{ - hdr->fw_addr = fw_addr; - hdr->host_addr = 0; - hdr->length = length; - /* Fixed client payload < IPC payload */ - hdr->length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT; -} - -static int heci_send_heci_msg_timestamp(struct heci_msg *msg, - uint32_t *timestamp) -{ - int length, written; - - if (heci_bus_ctx.ipc_handle == IPC_INVALID_HANDLE) - return -1; - - length = sizeof(msg->hdr) + HECI_MSG_LENGTH(msg->hdr.length); - written = ipc_write_timestamp(heci_bus_ctx.ipc_handle, msg, length, - timestamp); - - if (written != length) { - CPRINTF("%s error : len = %d err = %d\n", __func__, - (int)length, written); - return -EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -static int heci_send_heci_msg(struct heci_msg *msg) -{ - return heci_send_heci_msg_timestamp(msg, NULL); -} - -int heci_set_client_data(const heci_handle_t handle, void *data) -{ - struct heci_client_context *cli_ctx; - const uint8_t fw_addr = TO_FW_ADDR(handle); - - if (!heci_is_valid_handle(handle)) - return -EC_ERROR_INVAL; - - cli_ctx = heci_get_client_context(fw_addr); - cli_ctx->data = data; - - return EC_SUCCESS; -} - -void *heci_get_client_data(const heci_handle_t handle) -{ - struct heci_client_context *cli_ctx; - const uint8_t fw_addr = TO_FW_ADDR(handle); - - if (!heci_is_valid_handle(handle)) - return NULL; - - cli_ctx = heci_get_client_context(fw_addr); - return cli_ctx->data; -} - -/* - * Waits for flow control credit that allows TX transactions - * - * Returns true if credit was acquired, otherwise false - */ -static int wait_for_flow_ctrl_cred(struct heci_client_connect *connect) -{ - int need_to_wait; - - do { - mutex_lock(&connect->cred_lock); - need_to_wait = !connect->flow_ctrl_creds; - if (need_to_wait) { - connect->waiting_task = task_get_current(); - } else { - connect->flow_ctrl_creds = 0; - connect->waiting_task = 0; - } - mutex_unlock(&connect->cred_lock); - if (need_to_wait) { - /* - * A second is more than enough, otherwise if will - * probably never happen. - */ - int ev = task_wait_event_mask(TASK_EVENT_IPC_READY, - SECOND); - if (ev & TASK_EVENT_TIMER) { - /* Return false, not able to get credit */ - return 0; - } - } - } while (need_to_wait); - - /* We successfully got flow control credit */ - return 1; -} - -int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size, uint32_t *timestamp) -{ - int buf_offset = 0, ret = 0, remain, payload_size; - struct heci_client_connect *connect; - struct heci_msg msg; - const uint8_t fw_addr = TO_FW_ADDR(handle); - - if (!heci_is_valid_handle(handle)) - return -EC_ERROR_INVAL; - - if (buf_size > HECI_MAX_MSG_SIZE) - return -EC_ERROR_OVERFLOW; - - connect = heci_get_client_connect(fw_addr); - mutex_lock(&connect->lock); - - if (!heci_is_client_connected(fw_addr)) { - ret = -HECI_ERR_CLIENT_IS_NOT_CONNECTED; - goto err_locked; - } - - if (!wait_for_flow_ctrl_cred(connect)) { - CPRINTF("no cred\n"); - ret = -HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST; - goto err_locked; - } - - msg.hdr.fw_addr = fw_addr; - msg.hdr.host_addr = connect->host_addr; - - remain = buf_size; - while (remain) { - if (remain > HECI_IPC_PAYLOAD_SIZE) { - msg.hdr.length = HECI_IPC_PAYLOAD_SIZE; - payload_size = HECI_IPC_PAYLOAD_SIZE; - } else { - msg.hdr.length = remain; - /* set as last heci msg */ - msg.hdr.length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT; - payload_size = remain; - } - - memcpy(msg.payload, buf + buf_offset, payload_size); - - heci_send_heci_msg_timestamp(&msg, timestamp); - - remain -= payload_size; - buf_offset += payload_size; - } - mutex_unlock(&connect->lock); - - return buf_size; - -err_locked: - mutex_unlock(&connect->lock); - - return ret; -} - -int heci_send_msg(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size) -{ - return heci_send_msg_timestamp(handle, buf, buf_size, NULL); -} - - -int heci_send_msgs(const heci_handle_t handle, - const struct heci_msg_list *msg_list) -{ - struct heci_msg_item *cur_item; - int total_size = 0; - int i, msg_cur_pos, buf_size, copy_size, msg_sent; - struct heci_client_connect *connect; - struct heci_msg msg; - const uint8_t fw_addr = TO_FW_ADDR(handle); - - if (!heci_is_valid_handle(handle)) - return -EC_ERROR_INVAL; - - for (i = 0; i < msg_list->num_of_items; i++) { - if (!msg_list->items[i]->size || !msg_list->items[i]->buf) - return -EC_ERROR_INVAL; - - total_size += msg_list->items[i]->size; - } - - if (total_size > HECI_MAX_MSG_SIZE) - return -EC_ERROR_OVERFLOW; - - if (msg_list->num_of_items > HECI_MAX_MSGS) - return -HECI_ERR_TOO_MANY_MSG_ITEMS; - - connect = heci_get_client_connect(fw_addr); - mutex_lock(&connect->lock); - - if (!heci_is_client_connected(fw_addr)) { - total_size = -HECI_ERR_CLIENT_IS_NOT_CONNECTED; - goto err_locked; - } - - if (!wait_for_flow_ctrl_cred(connect)) { - CPRINTF("no cred\n"); - total_size = -HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST; - goto err_locked; - } - - msg.hdr.fw_addr = fw_addr; - msg.hdr.host_addr = connect->host_addr; - - i = 1; - msg_cur_pos = 0; - buf_size = 0; - cur_item = msg_list->items[0]; - msg_sent = 0; - while (1) { - /* get next item if current item is consumed */ - if (msg_cur_pos == cur_item->size) { - /* - * break if no more item. - * if "msg" contains data to be sent - * it will be sent after break. - */ - if (i == msg_list->num_of_items) - break; - - /* get next item and reset msg_cur_pos */ - cur_item = msg_list->items[i++]; - msg_cur_pos = 0; - } - - /* send data in ipc buf if it's completely filled */ - if (buf_size == HECI_IPC_PAYLOAD_SIZE) { - msg.hdr.length = buf_size; - msg_sent += buf_size; - - /* no leftovers, send the last msg here */ - if (msg_sent == total_size) { - msg.hdr.length |= - (uint16_t)1 << HECI_MSG_CMPL_SHIFT; - } - - heci_send_heci_msg(&msg); - buf_size = 0; - } - - /* fill ipc msg buffer */ - if (cur_item->size - msg_cur_pos > - HECI_IPC_PAYLOAD_SIZE - buf_size) { - copy_size = HECI_IPC_PAYLOAD_SIZE - buf_size; - } else { - copy_size = cur_item->size - msg_cur_pos; - } - - memcpy(msg.payload + buf_size, cur_item->buf + msg_cur_pos, - copy_size); - - msg_cur_pos += copy_size; - buf_size += copy_size; - } - - /* leftovers ? send last msg */ - if (buf_size != 0) { - msg.hdr.length = buf_size; - msg.hdr.length |= (uint16_t)1 << HECI_MSG_CMPL_SHIFT; - - heci_send_heci_msg(&msg); - } - -err_locked: - mutex_unlock(&connect->lock); - - return total_size; - -} - -/* For now, we only support fixed client payload size < IPC payload size */ -int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf, - const size_t buf_size) -{ - struct heci_msg msg; - - heci_build_fixed_client_header(&msg.hdr, fw_addr, buf_size); - - memcpy(msg.payload, buf, buf_size); - - heci_send_heci_msg(&msg); - - return EC_SUCCESS; -} - -static int handle_version_req(struct hbm_version_req *ver_req) -{ - struct hbm_version_res *ver_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*ver_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_VERSION_RESP; - ver_res = (struct hbm_version_res *)&i2h->data; - - memset(ver_res, 0, sizeof(*ver_res)); - - ver_res->version.major = HBM_MAJOR_VERSION; - ver_res->version.minor = HBM_MINOR_VERSION; - if (ver_req->version.major == HBM_MAJOR_VERSION && - ver_req->version.minor == HBM_MINOR_VERSION) { - ver_res->supported = 1; - } else { - ver_res->supported = 0; - } - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -#define BITS_PER_BYTE 8 -/* get number of bits for one element of "valid_addresses" array */ -#define BITS_PER_ELEMENT \ - (sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE) - -static int handle_enum_req(struct hbm_enum_req *enum_req) -{ - struct hbm_enum_res *enum_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - int i; - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*enum_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_HOST_ENUM_RESP; - enum_res = (struct hbm_enum_res *)&i2h->data; - - memset(enum_res, 0, sizeof(*enum_res)); - - /* - * fw address 0 is reserved for HECI Bus Message - * fw address 1 ~ 0x1f are reserved for fixed clients - * fw address 0x20 ~ 0xFF is for dynamic clients - * bit-0 set -> fw address "0", bit-1 set -> fw address "1" - */ - for (i = HECI_DYN_CLIENT_ADDR_START; - i < heci_bus_ctx.num_of_clients + HECI_DYN_CLIENT_ADDR_START; - i++) { - enum_res->valid_addresses[i / BITS_PER_ELEMENT] |= - 1 << (i & (BITS_PER_ELEMENT - 1)); - } - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req) -{ - struct hbm_client_prop_res *client_prop_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - struct heci_client_context *client_ctx; - const struct heci_client *client; - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*client_prop_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_HOST_CLIENT_PROP_RESP; - client_prop_res = (struct hbm_client_prop_res *)&i2h->data; - - memset(client_prop_res, 0, sizeof(*client_prop_res)); - - client_prop_res->address = client_prop_req->address; - if (!heci_is_valid_client_addr(client_prop_req->address)) { - client_prop_res->status = HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; - } else { - struct hbm_client_properties *client_prop; - - client_ctx = heci_get_client_context(client_prop_req->address); - client = client_ctx->client; - client_prop = &client_prop_res->client_prop; - - client_prop->protocol_name = client->protocol_id; - client_prop->protocol_version = client->protocol_ver; - client_prop->max_number_of_connections = - client->max_n_of_connections; - client_prop->max_msg_length = client->max_msg_size; - client_prop->dma_hdr_len = client->dma_header_length; - client_prop->dma_hdr_len |= client->dma_enabled ? - CLIENT_DMA_ENABLE : 0; - } - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -static int heci_send_flow_control(uint8_t fw_addr) -{ - struct heci_client_connect *connect; - struct hbm_i2h *i2h; - struct hbm_flow_control *flow_ctrl; - struct heci_msg heci_msg; - - connect = heci_get_client_connect(fw_addr); - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*flow_ctrl)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_FLOW_CONTROL; - flow_ctrl = (struct hbm_flow_control *)&i2h->data; - - memset(flow_ctrl, 0, sizeof(*flow_ctrl)); - - flow_ctrl->fw_addr = fw_addr; - flow_ctrl->host_addr = connect->host_addr; - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -static int handle_client_connect_req( - struct hbm_client_connect_req *client_connect_req) -{ - struct hbm_client_connect_res *client_connect_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - struct heci_client_connect *connect; - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*client_connect_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_CLIENT_CONNECT_RESP; - client_connect_res = (struct hbm_client_connect_res *)&i2h->data; - - memset(client_connect_res, 0, sizeof(*client_connect_res)); - - client_connect_res->fw_addr = client_connect_req->fw_addr; - client_connect_res->host_addr = client_connect_req->host_addr; - if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) { - client_connect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; - } else if (!client_connect_req->host_addr) { - client_connect_res->status = - HECI_CONNECT_STATUS_INVALID_PARAMETER; - } else { - connect = heci_get_client_connect(client_connect_req->fw_addr); - if (connect->is_connected) { - client_connect_res->status = - HECI_CONNECT_STATUS_ALREADY_EXISTS; - } else { - connect->is_connected = 1; - connect->host_addr = client_connect_req->host_addr; - } - } - - heci_send_heci_msg(&heci_msg); - - /* no error, send flow control */ - if (!client_connect_res->status) - heci_send_flow_control(client_connect_req->fw_addr); - - return EC_SUCCESS; -} - -static int handle_flow_control_cmd(struct hbm_flow_control *flow_ctrl) -{ - struct heci_client_connect *connect; - int waiting_task; - - if (!heci_is_valid_client_addr(flow_ctrl->fw_addr)) - return -1; - - if (!heci_is_client_connected(flow_ctrl->fw_addr)) - return -1; - - connect = heci_get_client_connect(flow_ctrl->fw_addr); - - mutex_lock(&connect->cred_lock); - connect->flow_ctrl_creds = 1; - waiting_task = connect->waiting_task; - mutex_unlock(&connect->cred_lock); - - if (waiting_task) - task_set_event(waiting_task, TASK_EVENT_IPC_READY, 0); - - return EC_SUCCESS; -} - -static void heci_handle_client_msg(struct heci_msg *msg, size_t length) -{ - struct heci_client_context *cli_ctx; - struct heci_client_connect *connect; - const struct heci_client_callbacks *cbs; - int payload_size; - - if (!heci_is_valid_client_addr(msg->hdr.fw_addr)) - return; - - if (!heci_is_client_connected(msg->hdr.fw_addr)) - return; - - cli_ctx = heci_get_client_context(msg->hdr.fw_addr); - cbs = cli_ctx->client->cbs; - connect = &cli_ctx->connect; - - payload_size = HECI_MSG_LENGTH(msg->hdr.length); - if (connect->is_connected && - msg->hdr.host_addr == connect->host_addr) { - if (!connect->ignore_rx_msg && - connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) { - connect->ignore_rx_msg = 1; /* too big. discard */ - } - - if (!connect->ignore_rx_msg) { - memcpy(connect->rx_msg + connect->rx_msg_length, - msg->payload, payload_size); - - connect->rx_msg_length += payload_size; - } - - if (HECI_MSG_IS_COMPLETED(msg->hdr.length)) { - if (!connect->ignore_rx_msg) { - cbs->new_msg_received( - TO_HECI_HANDLE(msg->hdr.fw_addr), - connect->rx_msg, - connect->rx_msg_length); - } - - connect->rx_msg_length = 0; - connect->ignore_rx_msg = 0; - - heci_send_flow_control(msg->hdr.fw_addr); - } - } -} - -static int handle_client_disconnect_req( - struct hbm_client_disconnect_req *client_disconnect_req) -{ - struct hbm_client_disconnect_res *client_disconnect_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - struct heci_client_context *cli_ctx; - struct heci_client_connect *connect; - const struct heci_client_callbacks *cbs; - uint8_t fw_addr, host_addr; - - CPRINTS("Got HECI disconnect request"); - - heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) + - sizeof(*client_disconnect_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP; - client_disconnect_res = (struct hbm_client_disconnect_res *)&i2h->data; - - memset(client_disconnect_res, 0, sizeof(*client_disconnect_res)); - - fw_addr = client_disconnect_req->fw_addr; - host_addr = client_disconnect_req->host_addr; - - client_disconnect_res->fw_addr = fw_addr; - client_disconnect_res->host_addr = host_addr; - if (!heci_is_valid_client_addr(fw_addr) || - !heci_is_client_connected(fw_addr)) { - client_disconnect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; - } else { - connect = heci_get_client_connect(fw_addr); - if (connect->host_addr != host_addr) { - client_disconnect_res->status = - HECI_CONNECT_STATUS_INVALID_PARAMETER; - } else { - cli_ctx = heci_get_client_context(fw_addr); - cbs = cli_ctx->client->cbs; - mutex_lock(&connect->lock); - if (connect->is_connected) { - cbs->disconnected(TO_HECI_HANDLE(fw_addr)); - connect->is_connected = 0; - } - mutex_unlock(&connect->lock); - } - } - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -/* host stops due to version mismatch */ -static int handle_host_stop_req(struct hbm_host_stop_req *host_stop_req) -{ - struct hbm_host_stop_res *host_stop_res; - struct heci_msg heci_msg; - struct hbm_i2h *i2h; - - heci_build_hbm_header(&heci_msg.hdr, - sizeof(i2h->cmd) + sizeof(*host_stop_res)); - - i2h = (struct hbm_i2h *)heci_msg.payload; - i2h->cmd = HECI_BUS_MSG_HOST_STOP_RESP; - host_stop_res = (struct hbm_host_stop_res *)&i2h->data; - - memset(host_stop_res, 0, sizeof(*host_stop_res)); - - heci_send_heci_msg(&heci_msg); - - return EC_SUCCESS; -} - -static int is_hbm_validity(struct hbm_h2i *h2i, size_t length) -{ - int valid_msg_len; - - valid_msg_len = sizeof(h2i->cmd); - - switch (h2i->cmd) { - case HECI_BUS_MSG_VERSION_REQ: - valid_msg_len += sizeof(struct hbm_version_req); - break; - - case HECI_BUS_MSG_HOST_ENUM_REQ: - valid_msg_len += sizeof(struct hbm_enum_req); - break; - - case HECI_BUS_MSG_HOST_CLIENT_PROP_REQ: - valid_msg_len += sizeof(struct hbm_client_prop_req); - break; - - case HECI_BUS_MSG_CLIENT_CONNECT_REQ: - valid_msg_len += sizeof(struct hbm_client_connect_req); - break; - - case HECI_BUS_MSG_FLOW_CONTROL: - valid_msg_len += sizeof(struct hbm_flow_control); - break; - - case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ: - valid_msg_len += sizeof(struct hbm_client_disconnect_req); - break; - - case HECI_BUS_MSG_HOST_STOP_REQ: - valid_msg_len += sizeof(struct hbm_host_stop_req); - break; - -/* TODO: DMA support for large data */ -#if 0 - case HECI_BUS_MSG_DMA_REQ: - valid_msg_len += sizeof(struct hbm_dma_req); - break; - - case HECI_BUS_MSG_DMA_ALLOC_NOTIFY: - valid_msg_len += sizeof(struct hbm_dma_alloc_notify); - break; - - case HECI_BUS_MSG_DMA_XFER_REQ: /* DMA transfer to FW */ - valid_msg_len += sizeof(struct hbm_dma_xfer_req); - break; - - case HECI_BUS_MSG_DMA_XFER_RESP: /* Ack for DMA transfer from FW */ - valid_msg_len += sizeof(struct hbm_dma_xfer_resp); - break; -#endif - default: - break; - } - - if (valid_msg_len != length) { - CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", - h2i->cmd, valid_msg_len, length); - /* TODO: invalid cmd. not sure to reply with error ? */ - return 0; - } - - return 1; -} - -static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length) -{ - void *data = (void *)&h2i->data; - - if (!is_hbm_validity(h2i, length)) - return; - - switch (h2i->cmd) { - case HECI_BUS_MSG_VERSION_REQ: - handle_version_req((struct hbm_version_req *)data); - break; - - case HECI_BUS_MSG_HOST_ENUM_REQ: - handle_enum_req((struct hbm_enum_req *)data); - break; - - case HECI_BUS_MSG_HOST_CLIENT_PROP_REQ: - handle_client_prop_req((struct hbm_client_prop_req *)data); - break; - - case HECI_BUS_MSG_CLIENT_CONNECT_REQ: - handle_client_connect_req( - (struct hbm_client_connect_req *)data); - break; - - case HECI_BUS_MSG_FLOW_CONTROL: - handle_flow_control_cmd((struct hbm_flow_control *)data); - break; - - case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ: - handle_client_disconnect_req( - (struct hbm_client_disconnect_req *)data); - break; - - case HECI_BUS_MSG_HOST_STOP_REQ: - handle_host_stop_req((struct hbm_host_stop_req *)data); - break; - -/* TODO: DMA transfer if data is too big >= ? KB */ -#if 0 - case HECI_BUS_MSG_DMA_REQ: - handle_dma_req((struct hbm_dma_req *)data); - break; - - case HECI_BUS_MSG_DMA_ALLOC_NOTIFY: - handle_dma_alloc_notify((struct hbm_dma_alloc_notify *)); - break; - - case HECI_BUS_MSG_DMA_XFER_REQ: /* DMA transfer to FW */ - handle_dma_xfer_req((struct hbm_dma_xfer_req *)data); - break; - - case HECI_BUS_MSG_DMA_XFER_RESP: /* Ack for DMA transfer from FW */ - handle_dma_xfer_resp((struct hbm_dma_xfer_resp *)data); - break; -#endif - default: - break; - } -} - -static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length) -{ - if (!heci_msg->hdr.host_addr) { - /* - * message for HECI bus or a fixed client should fit - * into one IPC message - */ - if (!HECI_MSG_IS_COMPLETED(heci_msg->hdr.length)) { - CPRINTS("message not completed"); - return; - } - - if (heci_msg->hdr.fw_addr == HECI_FIXED_SYSTEM_STATE_ADDR) - heci_handle_system_state_msg( - heci_msg->payload, - HECI_MSG_LENGTH(heci_msg->hdr.length)); - else if (!heci_msg->hdr.fw_addr) - /* HECI Bus Message(fw_addr == 0 && host_addr == 0) */ - heci_handle_hbm((struct hbm_h2i *)heci_msg->payload, - HECI_MSG_LENGTH(heci_msg->hdr.length)); - else - CPRINTS("not supported fixed client(%d)", - heci_msg->hdr.fw_addr); - } else { - /* host_addr != 0 : Msg for Dynamic client */ - heci_handle_client_msg(heci_msg, msg_length); - } -} - -/* event flag for HECI msg */ -#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0) - -void heci_rx_task(void) -{ - int msg_len; - struct heci_msg heci_msg; - ipc_handle_t ipc_handle; - - /* open IPC for HECI protocol */ - heci_bus_ctx.ipc_handle = ipc_open(IPC_PEER_ID_HOST, IPC_PROTOCOL_HECI, - EVENT_FLAG_BIT_HECI_MSG); - - ASSERT(heci_bus_ctx.ipc_handle != IPC_INVALID_HANDLE); - - /* get ipc handle */ - ipc_handle = heci_bus_ctx.ipc_handle; - - while (1) { - /* task will be blocked here, waiting for event */ - msg_len = ipc_read(ipc_handle, &heci_msg, sizeof(heci_msg), -1); - - if (msg_len <= 0) { - CPRINTS("discard heci packet"); - continue; - } - - if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr) - == msg_len) - heci_handle_heci_msg(&heci_msg, msg_len); - else - CPRINTS("msg len mismatch.. discard.."); - } -} diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h deleted file mode 100644 index 9dca4bff90..0000000000 --- a/chip/ish/heci_client.h +++ /dev/null @@ -1,112 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __HECI_CLIENT_H -#define __HECI_CLIENT_H - -#include <stdint.h> -#include <stddef.h> - -#include "hooks.h" - -#define HECI_MAX_NUM_OF_CLIENTS 2 - -#define HECI_MAX_MSG_SIZE 4960 -#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4) -#define HECI_MAX_MSGS 3 - -enum HECI_ERR { - HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0, - HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1, - HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2, -}; - -typedef void * heci_handle_t; - -#define HECI_INVALID_HANDLE NULL - -struct heci_guid { - uint32_t data1; - uint16_t data2; - uint16_t data3; - uint8_t data4[8]; -}; - -struct heci_client_callbacks { - /* - * called while registering heci client. - * if returns non-zero, the registration will fail. - */ - int (*initialize)(const heci_handle_t handle); - /* called when new heci msg for the client is arrived */ - void (*new_msg_received)(const heci_handle_t handle, uint8_t *msg, - const size_t msg_size); - /* called when the heci client is disconnected */ - void (*disconnected)(const heci_handle_t handle); - - /* called when ISH goes to suspend */ - int (*suspend)(const heci_handle_t); - /* called when ISH resumes */ - int (*resume)(const heci_handle_t); -}; - -struct heci_client { - struct heci_guid protocol_id; - uint32_t max_msg_size; - uint8_t protocol_ver; - uint8_t max_n_of_connections; - uint8_t dma_header_length :7; - uint8_t dma_enabled :1; - - const struct heci_client_callbacks *cbs; -}; - -struct heci_msg_item { - size_t size; - uint8_t *buf; -}; - -struct heci_msg_list { - int num_of_items; - struct heci_msg_item *items[HECI_MAX_MSGS]; -}; - -/* - * Do not call this function directly. - * The function should be called only by HECI_CLIENT_ENTRY() - */ -heci_handle_t heci_register_client(const struct heci_client *client); -int heci_set_client_data(const heci_handle_t handle, void *data); -void *heci_get_client_data(const heci_handle_t handle); - -/* - * Send a client message. Note this function waits a short while for the HECI - * bus to become available for sending. This method blocks until either the heci - * message is sent or the message as been queued to send in the lower IPC layer. - * - * All callers that use the same underlying IPC channel will be serialized. - */ -int heci_send_msg(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size); -int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size, uint32_t *timestamp); -/* - * send client msgs(using list of buffer&size). - * heci_msg_item with size == 0 is not acceptable. - */ -int heci_send_msgs(const heci_handle_t handle, - const struct heci_msg_list *msg_list); -/* send msg to fixed client(system level client) */ -int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf, - const size_t buf_size); - -#define HECI_CLIENT_ENTRY(heci_client) \ - void _heci_entry_##heci_client(void) \ - { \ - heci_register_client(&(heci_client)); \ - } \ - DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1) - -#endif /* __HECI_CLIENT_H */ diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h deleted file mode 100644 index 0a32e305af..0000000000 --- a/chip/ish/hid_device.h +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __HID_DEVICE_H -#define __HID_DEVICE_H - -#include <stdint.h> -#include <stddef.h> - -#include "hooks.h" - -#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954 - -enum HID_SUBSYS_ERR { - HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1, -}; - -typedef void * hid_handle_t; -#define HID_INVALID_HANDLE NULL - -struct hid_callbacks { - /* - * function called during registration. - * if returns non-zero, the registration will fail. - */ - int (*initialize)(const hid_handle_t handle); - - /* return size of data copied to buf. if returns <= 0, error */ - int (*get_hid_descriptor)(const hid_handle_t handle, uint8_t *buf, - const size_t buf_size); - /* return size of data copied to buf. if return <= 0, error */ - int (*get_report_descriptor)(const hid_handle_t handle, uint8_t *buf, - const size_t buf_size); - /* return size of data copied to buf. if return <= 0, error */ - int (*get_feature_report)(const hid_handle_t handle, - const uint8_t report_id, uint8_t *buf, - const size_t buf_size); - /* return tranferred data size. if returns <= 0, error */ - int (*set_feature_report)(const hid_handle_t handle, - const uint8_t report_id, const uint8_t *data, - const size_t data_size); - /* return size of data copied to buf. if returns <= 0, error */ - int (*get_input_report)(const hid_handle_t handle, - const uint8_t report_id, uint8_t *buf, - const size_t buf_size); - - /* suspend/resume, if returns non-zero, error */ - int (*resume)(const hid_handle_t handle); - int (*suspend)(const hid_handle_t handle); -}; - -struct hid_device { - uint8_t dev_class; - uint16_t pid; - uint16_t vid; - - const struct hid_callbacks *cbs; -}; - -/* - * Do not call this function directly. - * The function should be called only by HID_DEVICE_ENTRY() - */ -hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info); -/* send HID input report */ -int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf, - const size_t buf_size); -/* store HID device specific data */ -int hid_subsys_set_device_data(const hid_handle_t handle, void *data); -/* retrieve HID device specific data */ -void *hid_subsys_get_device_data(const hid_handle_t handle); - -#define HID_DEVICE_ENTRY(hid_dev) \ - void _hid_dev_entry_##hid_dev(void) \ - { \ - hid_subsys_register_device(&(hid_dev)); \ - } \ - DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2) - -#endif /* __HID_DEVICE_H */ diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c deleted file mode 100644 index bd3f331fdc..0000000000 --- a/chip/ish/hid_subsys.c +++ /dev/null @@ -1,447 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "compile_time_macros.h" -#include "console.h" -#include "heci_client.h" -#include "hid_device.h" -#include "util.h" - -#ifdef HID_SUBSYS_DEBUG -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) -#else -#define CPUTS(outstr) -#define CPRINTS(format, args...) -#define CPRINTF(format, args...) -#endif - -#define __packed __attribute__((packed)) - -#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\ - { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } } - -#define HID_SUBSYS_MAX_HID_DEVICES 3 - -/* - * the following enum values and data structures with __packed are used for - * communicating with host driver and they are copied from host driver. - */ -enum { - HID_GET_HID_DESCRIPTOR = 0, - HID_GET_REPORT_DESCRIPTOR, - HID_GET_FEATURE_REPORT, - HID_SET_FEATURE_REPORT, - HID_GET_INPUT_REPORT, - HID_PUBLISH_INPUT_REPORT, - HID_PUBLISH_INPUT_REPORT_LIST, /* TODO: need to support batch report */ - - HID_HID_CLIENT_READY_CMD = 30, - HID_HID_COMMAND_MAX = 31, - - HID_DM_COMMAND_BASE, - HID_DM_ENUM_DEVICES, - HID_DM_ADD_DEVICE, - HID_COMMAND_LAST -}; - -struct hid_device_info { - uint32_t dev_id; - uint8_t dev_class; - uint16_t pid; - uint16_t vid; -} __packed; - -struct hid_enum_payload { - uint8_t num_of_hid_devices; - struct hid_device_info dev_info[0]; -} __packed; - -#define COMMAND_MASK 0x7F -#define RESPONSE_FLAG 0x80 -struct hid_msg_hdr { - uint8_t command; /* bit 7 is used to indicate "response" */ - uint8_t device_id; - uint8_t status; - uint8_t flags; - uint16_t size; -} __packed; - -struct hid_msg { - struct hid_msg_hdr hdr; - uint8_t payload[HID_SUBSYS_MAX_PAYLOAD_SIZE]; -} __packed; - -struct hid_subsys_hid_device { - struct hid_device_info info; - const struct hid_callbacks *cbs; - int can_send_hid_input; - - void *data; -}; - -struct hid_subsystem { - heci_handle_t heci_handle; - - uint32_t num_of_hid_devices; - struct hid_subsys_hid_device hid_devices[HID_SUBSYS_MAX_HID_DEVICES]; -}; - -static struct hid_subsystem hid_subsys_ctx = { - .heci_handle = HECI_INVALID_HANDLE, -}; - -#define handle_to_dev_id(_handle) ((uintptr_t)(_handle)) -#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id)) - -static inline hid_handle_t device_index_to_handle(int device_index) -{ - return (hid_handle_t)(uintptr_t)(device_index + 1); -} - -static inline int is_valid_handle(hid_handle_t handle) -{ - return (uintptr_t)handle > 0 && - (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices; -} - -static inline -struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle) -{ - if (!is_valid_handle(handle)) - return NULL; - - return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1]; -} - - -hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info) -{ - struct hid_subsys_hid_device *hid_device; - hid_handle_t handle; - int ret, hid_device_index; - - if (hid_subsys_ctx.num_of_hid_devices >= HID_SUBSYS_MAX_HID_DEVICES) - return HID_INVALID_HANDLE; - - hid_device_index = hid_subsys_ctx.num_of_hid_devices++; - - handle = device_index_to_handle(hid_device_index); - - hid_device = &hid_subsys_ctx.hid_devices[hid_device_index]; - - hid_device->info.dev_class = dev_info->dev_class; - hid_device->info.pid = dev_info->pid; - hid_device->info.vid = dev_info->vid; - hid_device->info.dev_id = handle_to_dev_id(handle); - - hid_device->cbs = dev_info->cbs; - - if (dev_info->cbs->initialize) { - ret = dev_info->cbs->initialize(handle); - if (ret) { - CPRINTF("initialize error %d\n", ret); - hid_subsys_ctx.num_of_hid_devices--; - return HID_INVALID_HANDLE; - } - } - - return handle; -} - -int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf, - const size_t buf_size) -{ - struct hid_subsys_hid_device *hid_device; - struct hid_msg_hdr hid_msg_hdr = {0}; - struct heci_msg_item msg_item[2]; - struct heci_msg_list msg_list; - - hid_device = handle_to_hid_device(handle); - if (!hid_device) - return -EC_ERROR_INVAL; - - if (buf_size > HID_SUBSYS_MAX_PAYLOAD_SIZE) - return -EC_ERROR_OVERFLOW; - - if (hid_subsys_ctx.heci_handle == HECI_INVALID_HANDLE) - return -HID_SUBSYS_ERR_NOT_READY; - - if (!hid_device->can_send_hid_input) - return -HID_SUBSYS_ERR_NOT_READY; - - hid_msg_hdr.command = HID_PUBLISH_INPUT_REPORT; - hid_msg_hdr.device_id = hid_device->info.dev_id; - hid_msg_hdr.size = buf_size; - - msg_item[0].size = sizeof(hid_msg_hdr); - msg_item[0].buf = (uint8_t *)&hid_msg_hdr; - - msg_item[1].size = buf_size; - msg_item[1].buf = buf; - - msg_list.num_of_items = 2; - msg_list.items[0] = &msg_item[0]; - msg_list.items[1] = &msg_item[1]; - - heci_send_msgs(hid_subsys_ctx.heci_handle, &msg_list); - - return 0; -} - -int hid_subsys_set_device_data(const hid_handle_t handle, void *data) -{ - struct hid_subsys_hid_device *hid_device; - - hid_device = handle_to_hid_device(handle); - if (!hid_device) - return -EC_ERROR_INVAL; - - hid_device->data = data; - - return 0; -} - -void *hid_subsys_get_device_data(const hid_handle_t handle) -{ - struct hid_subsys_hid_device *hid_device; - - hid_device = handle_to_hid_device(handle); - if (!hid_device) - return NULL; - - return hid_device->data; -} - -static int handle_hid_device_msg(struct hid_msg *hid_msg) -{ - int ret = 0, payload_size, buf_size; - uint8_t *payload; - struct hid_subsys_hid_device *hid_dev; - const struct hid_callbacks *cbs; - hid_handle_t handle; - - handle = dev_id_to_handle(hid_msg->hdr.device_id); - hid_dev = handle_to_hid_device(handle); - - if (!hid_dev) { - /* - * use HID_HID_COMMAND_MAX as error message. - * host driver will reset ISH. - */ - hid_msg->hdr.size = 0; - hid_msg->hdr.status = 0; - hid_msg->hdr.command |= RESPONSE_FLAG | HID_HID_COMMAND_MAX; - hid_msg->hdr.flags = 0; - - heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg, - sizeof(hid_msg->hdr)); - - return 0; - } - - cbs = hid_dev->cbs; - - payload = hid_msg->payload; - payload_size = hid_msg->hdr.size; /* input data */ - buf_size = sizeof(hid_msg->payload); /* buffer to be written by cb */ - - /* - * re-use hid_msg from host for reply. - */ - switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_GET_HID_DESCRIPTOR: - if (cbs->get_hid_descriptor) - ret = cbs->get_hid_descriptor(handle, payload, - buf_size); - - break; - case HID_GET_REPORT_DESCRIPTOR: - if (cbs->get_report_descriptor) - ret = cbs->get_report_descriptor(handle, payload, - buf_size); - - hid_dev->can_send_hid_input = 1; - - break; - - case HID_GET_FEATURE_REPORT: - if (cbs->get_feature_report) - ret = cbs->get_feature_report(handle, payload[0], - payload, buf_size); - - break; - - case HID_SET_FEATURE_REPORT: - if (cbs->set_feature_report) { - ret = cbs->set_feature_report(handle, - payload[0], - payload, - payload_size); - /* - * if no error, reply only with the report id. - * re-use the first byte of payload - * from host that has report id - */ - if (ret >= 0) - ret = sizeof(uint8_t); - } - - break; - case HID_GET_INPUT_REPORT: - if (cbs->get_input_report) - ret = cbs->get_input_report(handle, payload[0], - payload, buf_size); - - break; - - default: - CPRINTF("invalid hid command %d, ignoring request\n", - hid_msg->hdr.command & COMMAND_MASK); - ret = -1; /* send error */ - } - - if (ret > 0) { - hid_msg->hdr.size = ret; - hid_msg->hdr.status = 0; - } else { /* error in callback */ - /* - * Note : errors of HID device should be transferred - * through their HID formatted data. - */ - hid_msg->hdr.size = 0; - hid_msg->hdr.status = -ret; - } - - hid_msg->hdr.command |= RESPONSE_FLAG; - hid_msg->hdr.flags = 0; - - heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg, - sizeof(hid_msg->hdr) + hid_msg->hdr.size); - - return 0; -} - -static int handle_hid_subsys_msg(struct hid_msg *hid_msg) -{ - int size = 0, i; - struct hid_enum_payload *enum_payload; - - switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_DM_ENUM_DEVICES: - enum_payload = (struct hid_enum_payload *)hid_msg->payload; - - for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { - enum_payload->dev_info[i] = - hid_subsys_ctx.hid_devices[i].info; - } - - enum_payload->num_of_hid_devices = - hid_subsys_ctx.num_of_hid_devices; - - /* reply payload size */ - size = sizeof(enum_payload->num_of_hid_devices); - size += enum_payload->num_of_hid_devices * - sizeof(enum_payload->dev_info[0]); - - break; - - default: - CPRINTF("invalid hid command %d, ignoring request\n", - hid_msg->hdr.command & COMMAND_MASK); - size = -1; /* send error */ - } - - if (size > 0) { - hid_msg->hdr.size = size; - hid_msg->hdr.status = 0; - } else { /* error in callback */ - hid_msg->hdr.size = 0; - hid_msg->hdr.status = -size; - } - - hid_msg->hdr.command |= RESPONSE_FLAG; - hid_msg->hdr.flags = 0; - - heci_send_msg(hid_subsys_ctx.heci_handle, (uint8_t *)hid_msg, - sizeof(hid_msg->hdr) + hid_msg->hdr.size); - - return 0; -} - -static void hid_subsys_new_msg_received(const heci_handle_t handle, - uint8_t *msg, const size_t msg_size) -{ - struct hid_msg *hid_msg = (struct hid_msg *)msg; - - /* workaround, since Host driver doesn't set size properly */ - if (hid_msg->hdr.size == 0 && msg_size > sizeof(hid_msg->hdr)) - hid_msg->hdr.size = msg_size - sizeof(hid_msg->hdr); - - if (hid_msg->hdr.size > HID_SUBSYS_MAX_PAYLOAD_SIZE) { - CPRINTF("too big payload size : %d. discard heci msg\n", - hid_msg->hdr); - return; /* invalid hdr. discard */ - } - - if (hid_msg->hdr.device_id) - handle_hid_device_msg(hid_msg); - else - handle_hid_subsys_msg(hid_msg); -} - -static int hid_subsys_initialize(const heci_handle_t heci_handle) -{ - hid_subsys_ctx.heci_handle = heci_handle; - - return 0; -} - -/* return zero if resume request handled successfully */ -static int hid_subsys_resume(const heci_handle_t heci_handle) -{ - int i, ret = 0; - - for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { - if (hid_subsys_ctx.hid_devices[i].cbs->resume) - ret |= hid_subsys_ctx.hid_devices[i].cbs->resume( - device_index_to_handle(i)); - } - - return ret; -} - -/* return zero if suspend request handled successfully */ -static int hid_subsys_suspend(const heci_handle_t heci_handle) -{ - int i, ret = 0; - - for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) { - if (hid_subsys_ctx.hid_devices[i].cbs->suspend) - ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend( - device_index_to_handle(i)); - } - - return ret; -} - -static const struct heci_client_callbacks hid_subsys_heci_cbs = { - .initialize = hid_subsys_initialize, - .new_msg_received = hid_subsys_new_msg_received, - .suspend = hid_subsys_suspend, - .resume = hid_subsys_resume, -}; - -static const struct heci_client hid_subsys_heci_client = { - .protocol_id = HECI_CLIENT_HID_GUID, - .max_msg_size = HECI_MAX_MSG_SIZE, - .protocol_ver = 1, - .max_n_of_connections = 1, - - .cbs = &hid_subsys_heci_cbs, -}; - -HECI_CLIENT_ENTRY(hid_subsys_heci_client); diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c deleted file mode 100644 index 2fcab44b8b..0000000000 --- a/chip/ish/host_command_heci.c +++ /dev/null @@ -1,177 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "heci_client.h" -#include "host_command.h" -#include "host_command_heci.h" -#include "ipc_heci.h" -#include "ish_fwst.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\ - { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } } - -/* Handle for all heci cros_ec interactions */ -static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE; - -/* - * If we hit response buffer size issues, we can increase this. This is the - * current size of a single HECI packet. - * - * Aligning with other assumptions in host command stack, only a single host - * command can be processed at a given time. - */ - -struct cros_ec_ishtp_msg_hdr { - uint8_t channel; - uint8_t status; - uint8_t id; /* Pairs up request and responses */ - uint8_t reserved; -} __ec_align4; - -#define CROS_EC_ISHTP_MSG_HDR_SIZE sizeof(struct cros_ec_ishtp_msg_hdr) -#define HECI_CROS_EC_RESPONSE_MAX \ - (HECI_IPC_PAYLOAD_SIZE - CROS_EC_ISHTP_MSG_HDR_SIZE) - -struct cros_ec_ishtp_msg { - struct cros_ec_ishtp_msg_hdr hdr; - uint8_t data[0]; -} __ec_align4; - -enum heci_cros_ec_channel { - CROS_EC_COMMAND = 1, /* initiated from AP */ - CROS_MKBP_EVENT = 2, /* initiated from EC */ -}; - -static uint8_t response_buffer[IPC_MAX_PAYLOAD_SIZE] __aligned(4); -static struct host_packet heci_packet; - -int heci_send_mkbp_event(uint32_t *timestamp) -{ - struct cros_ec_ishtp_msg evt; - int rv; - - evt.hdr.channel = CROS_MKBP_EVENT; - evt.hdr.status = 0; - - rv = heci_send_msg_timestamp(heci_cros_ec_handle, (uint8_t *)&evt, - sizeof(evt), timestamp); - /* - * heci_send_msg_timestamp sends back negative error codes. Change to - * EC style codes - */ - return rv < 0 ? -rv : EC_SUCCESS; -} - -static void heci_send_hostcmd_response(struct host_packet *pkt) -{ - int rv; - struct cros_ec_ishtp_msg *out = - (struct cros_ec_ishtp_msg *)response_buffer; - - out->hdr.channel = CROS_EC_COMMAND; - out->hdr.status = 0; - /* id is already set in the receiving method */ - - rv = heci_send_msg(heci_cros_ec_handle, (uint8_t *)out, - pkt->response_size + CROS_EC_ISHTP_MSG_HDR_SIZE); - if (rv < 0) - CPRINTS("HC response failed %d", -rv); -} - -static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle, - uint8_t *msg, const size_t msg_size) -{ - struct cros_ec_ishtp_msg *in = (void *) msg; - struct cros_ec_ishtp_msg *out = (void *) response_buffer; - - if (in->hdr.channel != CROS_EC_COMMAND) { - CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel); - return; - } - memset(&heci_packet, 0, sizeof(heci_packet)); - - /* Copy over id from sender so they can pair up messages */ - out->hdr.id = in->hdr.id; - - heci_packet.send_response = heci_send_hostcmd_response; - - heci_packet.request = in->data; - heci_packet.request_max = HECI_MAX_MSG_SIZE; - heci_packet.request_size = msg_size - CROS_EC_ISHTP_MSG_HDR_SIZE; - - heci_packet.response = out->data; - heci_packet.response_max = HECI_CROS_EC_RESPONSE_MAX; - heci_packet.response_size = 0; - - heci_packet.driver_result = EC_RES_SUCCESS; - host_packet_receive(&heci_packet); -} - -/* - * IPC transfer max is actual 4K, but we don't need kernel buffers that big - * - * Basing size off of existing cros_ec implementations ranging from 128 to 512 - */ -#define HECI_CROS_EC_LIMIT_PACKET_SIZE 256 - -/** - * Get protocol information - */ -static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = HECI_CROS_EC_LIMIT_PACKET_SIZE; - r->max_response_packet_size = HECI_CROS_EC_RESPONSE_MAX; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info, -EC_VER_MASK(0)); - -static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle) -{ - heci_cros_ec_handle = heci_handle; - ish_fwst_set_fw_status(FWSTS_SENSOR_APP_RUNNING); - return EC_SUCCESS; -} - -static int cros_ec_ishtp_no_op(const heci_handle_t heci_handle) -{ - return EC_SUCCESS; -} - -static void cros_ec_ishtp_disconneted(const heci_handle_t heci_handle) -{ -} - -static const struct heci_client_callbacks cros_ec_ishtp_subsys_heci_cbs = { - .initialize = cros_ec_ishtp_subsys_initialize, - .new_msg_received = cros_ec_ishtp_subsys_new_msg_received, - .suspend = cros_ec_ishtp_no_op, - .resume = cros_ec_ishtp_no_op, - .disconnected = cros_ec_ishtp_disconneted, -}; - -static const struct heci_client cros_ec_ishtp_heci_client = { - .protocol_id = HECI_CLIENT_CROS_EC_ISH_GUID, - .max_msg_size = HECI_MAX_MSG_SIZE, - .protocol_ver = 1, - .max_n_of_connections = 1, - .cbs = &cros_ec_ishtp_subsys_heci_cbs, -}; - -HECI_CLIENT_ENTRY(cros_ec_ishtp_heci_client); diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h deleted file mode 100644 index 06738fafb1..0000000000 --- a/chip/ish/hpet.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_HPET_H -#define __CROS_EC_HPET_H - -#include "common.h" - -/* ISH HPET config and timer registers */ - -#define TIMER0_CONF_CAP_REG 0x100 -#define TIMER0_COMP_VAL_REG 0x108 - - -/* HPET_GENERAL_CONFIG settings */ -#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10) -#define HPET_ENABLE_CNF BIT(0) -#define HPET_LEGACY_RT_CNF BIT(1) - -/* Interrupt status acknowledge register */ -#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20) - -/* Main counter register. 64-bit */ -#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4) - -/* HPET Timer 0/1/2 configuration*/ -#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20)) -#define HPET_Tn_INT_TYPE_CNF BIT(1) -#define HPET_Tn_INT_ENB_CNF BIT(2) -#define HPET_Tn_TYPE_CNF BIT(3) -#define HPET_Tn_VAL_SET_CNF BIT(6) -#define HPET_Tn_32MODE_CNF BIT(8) -#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9 -#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) - -/* - * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be - * configured as 64-bit. - */ -#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20)) -#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108) - -/* ISH 4/5: Special status register - * Use this register to see HPET timer are settled after a write. - */ -#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) -#define HPET_INT_STATUS_SETTLING BIT(1) -#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3)) -#define HPET_T0_CAP_SETTLING BIT(4) -#define HPET_T1_CAP_SETTLING BIT(5) -#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8)) -#define HPET_T1_CMP_SETTLING BIT(9) -#define HPET_MAIN_COUNTER_VALID BIT(13) -#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \ - HPET_T1_CMP_SETTLING) -#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | \ - HPET_T0_CMP_SETTLING) -#define HPET_ANY_SETTLING (BIT(12) - 1) - -#if defined(CHIP_FAMILY_ISH3) -#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */ -#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) -#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */ -#endif - -#endif /* __CROS_EC_HPET_H */ diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c deleted file mode 100644 index 1259dae7f4..0000000000 --- a/chip/ish/hwtimer.c +++ /dev/null @@ -1,265 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver for ISH High Precision Event Timers (HPET) */ - -#include "console.h" -#include "hpet.h" -#include "hwtimer.h" -#include "timer.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) - -static uint32_t last_deadline; - -/* - * The ISH hardware needs at least 25 ticks of leeway to arms the timer. - * ISH4/5 are the slowest with 32kHz timers, so we wait at least 800us when - * scheduling events in the future - */ -#define MINIMUM_EVENT_DELAY_US 800 - -/* - * ISH HPET timer HW has latency for interrupt, on ISH5, this latency is about - * 3 ticks, defined this configuration to calibrate the 'last_deadline' which is - * updated in event timer interrupt ISR. Without this calibration, we could - * get negative sleep time in idle task for low power sleep process. - */ -#define HPET_INT_LATENCY_TICKS 3 - -/* Scaling helper methods for different ISH chip variants */ -#ifdef CHIP_FAMILY_ISH3 -#define CLOCK_FACTOR 12 -BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ); - -static inline uint64_t scale_us2ticks(uint64_t us) -{ - return us * CLOCK_FACTOR; -} - -static inline uint32_t scale_us2ticks_32(uint32_t us) -{ - /* no optimization for ISH3 */ - return us * CLOCK_FACTOR; -} - -static inline uint64_t scale_ticks2us(uint64_t ticks) -{ - return ticks / CLOCK_FACTOR; -} - -static inline void wait_while_settling(uint32_t mask) -{ - /* Do nothing on ISH3, only ISH4 and ISH5 need settling */ -} - -#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) -#define CLOCK_SCALE_BITS 15 -BUILD_ASSERT(BIT(CLOCK_SCALE_BITS) == ISH_HPET_CLK_FREQ); - -/* Slow version, for 64-bit precision */ -static inline uint64_t scale_us2ticks(uint64_t us) -{ - /* ticks = us * ISH_HPET_CLK_FREQ / SECOND */ - - return (us << CLOCK_SCALE_BITS) / SECOND; -} - -/* Fast version, for 32-bit precision */ -static inline uint32_t scale_us2ticks_32(uint32_t us) -{ - /* - * GCC optimizes this shift/divide into multiplication by a - * magic number - */ - return (us << CLOCK_SCALE_BITS) / SECOND; -} - -static inline uint64_t scale_ticks2us(uint64_t ticks) -{ - return (ticks * SECOND) >> CLOCK_SCALE_BITS; -} - -/* - * HPET Control & Status register may indicate that a value which has - * been written still needs propogated by hardware. Before updating - * HPET_TIMER_CONF_CAP(N), be sure to wait on the value settling with - * the corresponding mask (see hpet.h). - */ -static inline void wait_while_settling(uint32_t mask) -{ - /* Wait for timer settings to settle ~ 150us */ - while (HPET_CTRL_STATUS & mask) - continue; -} - -#else -#error "Must define CHIP_FAMILY_ISH(3|4|5)" -#endif - -/* - * The 64-bit read on a 32-bit chip can tear during the read. Ensure that the - * value returned for 64-bit didn't rollover while we were reading it. - */ -static inline uint64_t read_main_timer(void) -{ - timestamp_t t; - uint32_t hi; - - /* need check main counter if valid when exit low power TCG mode */ - wait_while_settling(HPET_MAIN_COUNTER_VALID); - - do { - t.le.hi = HPET_MAIN_COUNTER_64_HI; - t.le.lo = HPET_MAIN_COUNTER_64_LO; - hi = HPET_MAIN_COUNTER_64_HI; - } while (t.le.hi != hi); - - return t.val; -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint32_t remaining_us; - uint32_t current_us; - uint64_t current_ticks; - - /* 'current_ticks' is the current absolute 64bit HW timer counter */ - current_ticks = read_main_timer(); - - /* - * 'current_us' is the low 32bit part of current time in 64bit micro - * seconds format, it's can express 2^32 micro seconds in maximum. - */ - current_us = scale_ticks2us(current_ticks); - - /* - * To ensure HW has enough time to react to the new timer value, - * we make remaining time not less than 'MINIMUM_EVENT_DELAY_US' - */ - remaining_us = deadline - current_us; - remaining_us = MAX(remaining_us, MINIMUM_EVENT_DELAY_US); - - /* - * Set new 64bit absolute timeout ticks to Timer 1 comparator - * register. - * For ISH3, this assumes that remaining_us is less than 360 seconds - * (2^32 us / 12Mhz), otherwise we would need to handle 32-bit rollover - * of 12Mhz timer comparator value. Watchdog refresh happens at least - * every 10 seconds. - */ - wait_while_settling(HPET_T1_CMP_SETTLING); - HPET_TIMER_COMP(1) = current_ticks + scale_us2ticks_32(remaining_us); - - /* - * Update 'last_deadline' and add calibrate delta due to HPET timer - * interrupt latency. - */ - last_deadline = current_us + remaining_us; - last_deadline += scale_ticks2us(HPET_INT_LATENCY_TICKS); - - /* Enable timer interrupt */ - wait_while_settling(HPET_T1_SETTLING); - HPET_TIMER_CONF_CAP(1) |= HPET_Tn_INT_ENB_CNF; -} - -uint32_t __hw_clock_event_get(void) -{ - return last_deadline; -} - -void __hw_clock_event_clear(void) -{ - /* - * We need to make sure that process_timers is called when the - * event timer rolls over, set for deadline when - * process_timers clears the event timer. - */ - __hw_clock_event_set(0xFFFFFFFF); -} - -uint64_t __hw_clock_source_read64(void) -{ - return scale_ticks2us(read_main_timer()); -} - -void __hw_clock_source_set64(uint64_t timestamp) -{ - /* Reset both clock and overflow comparators */ - wait_while_settling(HPET_ANY_SETTLING); - HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF; - - HPET_MAIN_COUNTER_64 = scale_us2ticks(timestamp); - - wait_while_settling(HPET_ANY_SETTLING); - HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF; -} - -static void hw_clock_event_isr(void) -{ - /* Clear interrupt */ - wait_while_settling(HPET_INT_STATUS_SETTLING); - HPET_INTR_CLEAR = BIT(1); - - process_timers(0); -} -DECLARE_IRQ(ISH_HPET_TIMER1_IRQ, hw_clock_event_isr); - -int __hw_clock_source_init64(uint64_t start_t) -{ - /* - * Timer 1 is used as an event timer. Timer 0 is unused, as - * CONFIG_HWTIMER_64BIT is enabled. - */ - uint32_t timer1_config = 0x00000000; - - /* Disable HPET */ - wait_while_settling(HPET_ANY_SETTLING); - HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF; - - /* Disable T0 */ - HPET_TIMER_CONF_CAP(0) &= ~HPET_Tn_INT_ENB_CNF; - - /* Disable T1 until we get it set up (below) */ - HPET_TIMER_CONF_CAP(1) &= ~HPET_Tn_INT_ENB_CNF; - - /* Initialize main counter */ - HPET_MAIN_COUNTER_64 = scale_us2ticks(start_t); - - /* Clear any interrupts from previously running image */ - HPET_INTR_CLEAR = BIT(0); - HPET_INTR_CLEAR = BIT(1); - - /* Timer 1 - IRQ routing */ - timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK; - timer1_config |= (ISH_HPET_TIMER1_IRQ << - HPET_Tn_INT_ROUTE_CNF_SHIFT); - - /* Level triggered interrupt */ - timer1_config |= HPET_Tn_INT_TYPE_CNF; - - /* Initialize last_deadline until an event is scheduled */ - last_deadline = 0xFFFFFFFF; - - /* Before enabling, previous values must have settled */ - wait_while_settling(HPET_ANY_SETTLING); - - /* Unmask HPET IRQ in IOAPIC */ - task_enable_irq(ISH_HPET_TIMER1_IRQ); - - /* Copy timer config to hardware register */ - HPET_TIMER_CONF_CAP(1) |= timer1_config; - - /* Enable HPET */ - HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF); - - /* Return IRQ value for OS event timer */ - return ISH_HPET_TIMER1_IRQ; -} diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c deleted file mode 100644 index 7e297a20eb..0000000000 --- a/chip/ish/i2c.c +++ /dev/null @@ -1,546 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C port module for ISH */ - -#include "common.h" -#include "console.h" -#include "config_chip.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "ish_i2c.h" -#include "task.h" -#include "timer.h" -#include "hwtimer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) - -/*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/ -static uint16_t default_hcnt_scl_100[] = { - 4000, 4420, 4920, 4400, 4000, 4000, 4300 -}; - -static uint16_t default_lcnt_scl_100[] = { - 4720, 5180, 4990, 5333, 4700, 5200, 4950 -}; - -static uint16_t default_hcnt_scl_400[] = { - 600, 820, 1120, 800, 600, 600, 450 -}; - -static uint16_t default_lcnt_scl_400[] = { - 1320, 1380, 1300, 1550, 1300, 1200, 1250 -}; - -static uint16_t default_hcnt_scl_1000[] = { - 260, 260, 260, 305, 260, 260, 260 -}; - -static uint16_t default_lcnt_scl_1000[] = { - 500, 500, 500, 525, 500, 500, 500 -}; - -static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 }; -static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 }; - - -#ifdef CHIP_VARIANT_ISH5P4 -/* Change to I2C_FREQ_100 in real silicon platform */ -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100 -}; -#else -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120 -}; -#endif - -static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = { - { - .bus = 0, - .base = (uint32_t *) ISH_I2C0_BASE, - .speed = I2C_SPEED_400KHZ, - .int_pin = ISH_I2C0_IRQ, - }, - { - .bus = 1, - .base = (uint32_t *) ISH_I2C1_BASE, - .speed = I2C_SPEED_400KHZ, - .int_pin = ISH_I2C1_IRQ, - }, - { - .bus = 2, - .base = (uint32_t *) ISH_I2C2_BASE, - .speed = I2C_SPEED_400KHZ, - .int_pin = ISH_I2C2_IRQ, - }, -}; - -static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = { - { - .bus_id = 0, - .std_speed.sda_hold = DEFAULT_SDA_HOLD_STD, - .fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST, - .fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS, - .high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH, - }, - { - .bus_id = 1, - .std_speed.sda_hold = DEFAULT_SDA_HOLD_STD, - .fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST, - .fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS, - .high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH, - }, - { - .bus_id = 2, - .std_speed.sda_hold = DEFAULT_SDA_HOLD_STD, - .fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST, - .fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS, - .high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH, - }, -}; - -static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, - uint32_t data) -{ - REG32((uint32_t) ((uint8_t *)base + offset)) = data; -} - -static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset) -{ - return REG32((uint32_t) ((uint8_t *)base + offset)); -} - -static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, - uint8_t offset) -{ - uint32_t ret = i2c_mmio_read(addr, reg) >> offset; - - return ret & 0xff; -} - -static void i2c_intr_switch(uint32_t *base, int mode) -{ - switch (mode) { - - case ENABLE_WRITE_INT: - i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL); - break; - - case ENABLE_READ_INT: - i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_READ_MASK_VAL); - break; - - case DISABLE_INT: - i2c_mmio_write(base, IC_INTR_MASK, 0); - /* clear interrupts: TX_ABORT - * Because the DW_apb_i2c's TX FIFO is forced into a - * flushed/reset state whenever a TX_ABRT event occurs, it - * is necessary for software to release the DW_apb_i2c from - * this state by reading the IC_CLR_TX_ABRT register before - * attempting to write into the TX FIFO - */ - i2c_mmio_read(base, IC_CLR_TX_ABRT); - /* STOP_DET */ - i2c_mmio_read(base, IC_CLR_STOP_DET); - break; - - default: - break; - } -} - -static void i2c_init_transaction(struct i2c_context *ctx, - uint16_t slave_addr, uint8_t flags) -{ - uint32_t con_value; - uint32_t *base = ctx->base; - struct i2c_bus_info *bus_info = &board_config[ctx->bus]; - uint32_t clk_in_val = clk_in[bus_freq[ctx->bus]]; - - /* disable interrupts */ - i2c_intr_switch(base, DISABLE_INT); - - i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_TAR, (slave_addr << IC_TAR_OFFSET) | - TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL); - - /* set Clock SCL Count */ - switch (ctx->speed) { - - case I2C_SPEED_100KHZ: - i2c_mmio_write(base, IC_SS_SCL_HCNT, - NS_2_COUNTERS(bus_info->std_speed.hcnt, - clk_in_val)); - i2c_mmio_write(base, IC_SS_SCL_LCNT, - NS_2_COUNTERS(bus_info->std_speed.lcnt, - clk_in_val)); - i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->std_speed.sda_hold, - clk_in_val)); - break; - - case I2C_SPEED_400KHZ: - i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, - clk_in_val)); - i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, - clk_in_val)); - i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_speed.sda_hold, - clk_in_val)); - break; - - case I2C_SPEED_1MHZ: - i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt, - clk_in_val)); - i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt, - clk_in_val)); - i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold, - clk_in_val)); - break; - - case I2C_SPEED_3M4HZ: - i2c_mmio_write(base, IC_HS_SCL_HCNT, - NS_2_COUNTERS(bus_info->high_speed.hcnt, - clk_in_val)); - i2c_mmio_write(base, IC_HS_SCL_LCNT, - NS_2_COUNTERS(bus_info->high_speed.lcnt, - clk_in_val)); - i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->high_speed.sda_hold, - clk_in_val)); - - i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, - clk_in_val)); - i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, - clk_in_val)); - break; - - default: - break; - } - - /* in SPT HW we need to sync between I2C clock and data signals */ - con_value = i2c_mmio_read(base, IC_CON); - - if (flags != 0) - con_value |= IC_RESTART_EN_VAL; - else - con_value &= ~IC_RESTART_EN_VAL; - - i2c_mmio_write(base, IC_CON, con_value); - i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]); - i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]); - i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE); -} - -static void i2c_write_buffer(uint32_t *base, uint8_t len, - const uint8_t *buffer, ssize_t *cur_index, - ssize_t total_len) -{ - int i; - uint16_t out; - - for (i = 0; i < len; i++) { - - ++(*cur_index); - out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL; - - /* if Write ONLY and Last byte */ - if (*cur_index == total_len) { - out |= DATA_CMD_STOP_VAL; - } - - i2c_mmio_write(base, IC_DATA_CMD, out); - } -} - -static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data, - unsigned restart_flag) -{ - /* this routine just set RX FIFO's control bit(s), - * READ command or RESTART */ - int i; - uint32_t data_cmd; - - for (i = 0; i < len; i++) { - data_cmd = DATA_CMD_READ_VAL; - - if ((i == 0) && restart_flag) - /* if restart for first byte */ - data_cmd |= DATA_CMD_RESTART_VAL; - - /* if last byte & less than FIFO size - * or only one byte to read */ - if (i == (len - 1) && !more_data) - data_cmd |= DATA_CMD_STOP_VAL; - - i2c_mmio_write(base, IC_DATA_CMD, data_cmd); - } -} - -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) -{ - int i; - ssize_t total_len; - uint64_t expire_ts; - struct i2c_context *ctx; - ssize_t curr_index = 0; - uint16_t addr = I2C_GET_ADDR(slave_addr_flags); - int begin_indx; - uint8_t repeat_start = 0; - - if (out_size == 0 && in_size == 0) - return EC_SUCCESS; - - if (port < 0 || port >= ISH_I2C_PORT_COUNT) - return EC_ERROR_INVAL; - - /* Check for reserved I2C addresses, pg. 74 in DW_apb_i2c.pdf - * Address cannot be any of the reserved address locations - */ - if (addr < I2C_FIRST_VALID_ADDR || addr > I2C_LAST_VALID_ADDR) - return EC_ERROR_INVAL; - - /* assume that if both out_size and in_size are not zero, - * then, it is 'repeated Start' condition. */ - if (in_size != 0 && out_size != 0) - repeat_start = 1; - - ctx = &i2c_ctxs[port]; - ctx->error_flag = 0; - ctx->wait_task_id = task_get_current(); - - total_len = in_size + out_size; - - i2c_init_transaction(ctx, addr, repeat_start); - - /* Write W data */ - if (out_size) - i2c_write_buffer(ctx->base, out_size, out, - &curr_index, total_len); - - /* Wait here until Tx is completed so that FIFO becomes empty. - * This is optimized for smaller Tx data size. - * If need to write big data ( > ISH_I2C_FIFO_SIZE ), - * it is better to use Tx FIFO threshold interrupt(as in Rx) for - * better CPU usuage. - * */ - expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC; - if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) { - - while ((i2c_mmio_read(ctx->base, IC_STATUS) & - BIT(IC_STATUS_TFE)) == 0) { - - if (__hw_clock_source_read() >= expire_ts) { - ctx->error_flag = 1; - break; - } - CPU_RELAX(); - } - } - - begin_indx = 0; - while (in_size) { - int rd_size; /* read size for on i2c transaction */ - - /* - * check if in_size > ISH_I2C_FIFO_SIZE, then try to read - * FIFO_SIZE each time. - */ - if (in_size > ISH_I2C_FIFO_SIZE) { - rd_size = ISH_I2C_FIFO_SIZE; - in_size -= ISH_I2C_FIFO_SIZE; - } else { - rd_size = in_size; - in_size = 0; - } - /* Set rx_threshold */ - i2c_mmio_write(ctx->base, IC_RX_TL, rd_size - 1); - - i2c_intr_switch(ctx->base, ENABLE_READ_INT); - - /* - * RESTART only once for entire i2c transaction. - * assume that if both out_size and in_size are not zero, - * then, it is 'repeated Start' condition. - * set R commands bit, start to read - */ - i2c_write_read_commands(ctx->base, rd_size, in_size, - (begin_indx == 0) && (repeat_start != 0)); - - - /* need timeout in case no ACK from slave */ - task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC); - - if (ctx->interrupts & M_TX_ABRT) { - ctx->error_flag = 1; - break; /* when bus abort, no more reading !*/ - } - - /* read data */ - for (i = begin_indx; i < begin_indx + rd_size; i++) - in[i] = i2c_read_byte(ctx->base, - IC_DATA_CMD, 0); - - begin_indx += rd_size; - } /* while (in_size) */ - - ctx->reason = 0; - ctx->interrupts = 0; - - /* do not disable device before master is idle */ - expire_ts = __hw_clock_source_read() + I2C_TSC_TIMEOUT; - - while ((i2c_mmio_read(ctx->base, IC_STATUS) & - (BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) != - BIT(IC_STATUS_TFE)) { - - if (__hw_clock_source_read() >= expire_ts) { - ctx->error_flag = 1; - break; - } - } - - i2c_intr_switch(ctx->base, DISABLE_INT); - i2c_mmio_write(ctx->base, IC_ENABLE, IC_ENABLE_DISABLE); - - if (ctx->error_flag) - return EC_ERROR_INVAL; - - return EC_SUCCESS; -} - -static void i2c_interrupt_handler(struct i2c_context *ctx) -{ - uint32_t raw_intr; - - if (IS_ENABLED(INTR_DEBUG)) - raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base, - IC_RAW_INTR_STAT); - - /* check interrupts */ - ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT); - ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); - - if (IS_ENABLED(INTR_DEBUG)) - CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, " - "RAW_INTR_STAT = 0x%04x", - ctx->interrupts, ctx->reason, raw_intr); - - /* disable interrupts */ - i2c_intr_switch(ctx->base, DISABLE_INT); - task_set_event(ctx->wait_task_id, TASK_EVENT_I2C_IDLE, 0); -} - -static void i2c_isr_bus0(void) -{ - i2c_interrupt_handler(&i2c_ctxs[0]); -} -DECLARE_IRQ(ISH_I2C0_IRQ, i2c_isr_bus0); - -static void i2c_isr_bus1(void) -{ - i2c_interrupt_handler(&i2c_ctxs[1]); -} -DECLARE_IRQ(ISH_I2C1_IRQ, i2c_isr_bus1); - -static void i2c_isr_bus2(void) -{ - i2c_interrupt_handler(&i2c_ctxs[2]); -} -DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2); - -static void i2c_config_speed(struct i2c_context *ctx, int kbps) -{ - - if (kbps > 1000) - ctx->speed = I2C_SPEED_3M4HZ; - else if (kbps > 400) - ctx->speed = I2C_SPEED_1MHZ; - else if (kbps > 100) - ctx->speed = I2C_SPEED_400KHZ; - else - ctx->speed = I2C_SPEED_100KHZ; - -} - -static void i2c_init_hardware(struct i2c_context *ctx) -{ - static const uint8_t speed_val_arr[] = { - [I2C_SPEED_100KHZ] = STD_SPEED_VAL, - [I2C_SPEED_400KHZ] = FAST_SPEED_VAL, - [I2C_SPEED_1MHZ] = FAST_SPEED_VAL, - [I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL, - }; - - uint32_t *base = ctx->base; - - /* disable interrupts */ - i2c_intr_switch(base, DISABLE_INT); - i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL - | speed_val_arr[ctx->speed] - | IC_RESTART_EN_VAL - | IC_SLAVE_DISABLE_VAL)); - - i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]); - i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]); - - /* get RX_FIFO and TX_FIFO depth */ - ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - RX_BUFFER_DEPTH_OFFSET) + 1; - ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - TX_BUFFER_DEPTH_OFFSET) + 1; -} - -static void i2c_initial_board_config(struct i2c_context *ctx) -{ - uint8_t freq = bus_freq[ctx->bus]; - struct i2c_bus_info *bus_info = &board_config[ctx->bus]; - - bus_info->std_speed.hcnt = default_hcnt_scl_100[freq]; - bus_info->std_speed.lcnt = default_lcnt_scl_100[freq]; - - bus_info->fast_speed.hcnt = default_hcnt_scl_400[freq]; - bus_info->fast_speed.lcnt = default_lcnt_scl_400[freq]; - - bus_info->fast_plus_speed.hcnt = default_hcnt_scl_1000[freq]; - bus_info->fast_plus_speed.lcnt = default_lcnt_scl_1000[freq]; - - bus_info->high_speed.hcnt = default_hcnt_scl_hs[freq]; - bus_info->high_speed.lcnt = default_lcnt_scl_hs[freq]; -} - -void i2c_init(void) -{ - int i; - - for (i = 0; i < i2c_ports_used; i++) { - int port = i2c_ports[i].port; - i2c_initial_board_config(&i2c_ctxs[port]); - /* Config speed from i2c_ports[] defined in board.c */ - i2c_config_speed(&i2c_ctxs[port], i2c_ports[i].kbps); - i2c_init_hardware(&i2c_ctxs[port]); - - task_enable_irq((&i2c_ctxs[port])->int_pin); - } - - CPRINTS("Done i2c_init"); -} diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c deleted file mode 100644 index 5271aa3a91..0000000000 --- a/chip/ish/ipc_heci.c +++ /dev/null @@ -1,743 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* IPC module for ISH */ - -/** - * IPC - Inter Processor Communication - * ----------------------------------- - * - * IPC is a bi-directional doorbell based message passing interface sans - * session and transport layers, between hardware blocks. ISH uses IPC to - * communicate with the Host, PMC (Power Management Controller), CSME - * (Converged Security and Manageability Engine), Audio, Graphics and ISP. - * - * Both the initiator and target ends each have a 32-bit doorbell register and - * 128-byte message regions. In addition, the following register pairs help in - * synchronizing IPC. - * - * - Peripheral Interrupt Status Register (PISR) - * - Peripheral Interrupt Mask Register (PIMR) - * - Doorbell Clear Status Register (DB CSR) - */ - -#include "registers.h" -#include "console.h" -#include "task.h" -#include "util.h" -#include "ipc_heci.h" -#include "ish_fwst.h" -#include "queue.h" -#include "hooks.h" -#include "hwtimer.h" - -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -/* - * comminucation protocol is defined in Linux Documentation - * <kernel_root>/Documentation/hid/intel-ish-hid.txt - */ - -/* MNG commands */ -/* The ipc_mng_task manages IPC link. It should be the highest priority */ -#define MNG_RX_CMPL_ENABLE 0 -#define MNG_RX_CMPL_DISABLE 1 -#define MNG_RX_CMPL_INDICATION 2 -#define MNG_RESET_NOTIFY 3 -#define MNG_RESET_NOTIFY_ACK 4 -#define MNG_SYNC_FW_CLOCK 5 -#define MNG_ILLEGAL_CMD 0xFF - -/* Doorbell */ -#define IPC_DB_MSG_LENGTH_FIELD 0x3FF -#define IPC_DB_MSG_LENGTH_SHIFT 0 -#define IPC_DB_MSG_LENGTH_MASK \ - (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT) - -#define IPC_DB_PROTOCOL_FIELD 0x0F -#define IPC_DB_PROTOCOL_SHIFT 10 -#define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT) - -#define IPC_DB_CMD_FIELD 0x0F -#define IPC_DB_CMD_SHIFT 16 -#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) - -#define IPC_DB_BUSY_SHIFT 31 -#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) - -#define IPC_DB_MSG_LENGTH(drbl) \ - (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) -#define IPC_DB_PROTOCOL(drbl) \ - (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT) -#define IPC_DB_CMD(drbl) \ - (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT) -#define IPC_DB_BUSY(drbl) (!!((drbl) & IPC_DB_BUSY_MASK)) - -#define IPC_BUILD_DB(length, proto, cmd, busy) \ - (((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \ - ((proto) << IPC_DB_PROTOCOL_SHIFT) | \ - ((length) << IPC_DB_MSG_LENGTH_SHIFT)) - -#define IPC_BUILD_MNG_DB(cmd, length) \ - IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1) - -#define IPC_BUILD_HECI_DB(length) \ - IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1) - -#define IPC_MSG_MAX_SIZE 0x80 -#define IPC_HOST_MSG_QUEUE_SIZE 8 -#define IPC_PMC_MSG_QUEUE_SIZE 2 - -#define IPC_HANDLE_PEER_ID_SHIFT 4 -#define IPC_HANDLE_PROTOCOL_SHIFT 0 -#define IPC_HANDLE_PROTOCOL_MASK 0x0F -#define IPC_BUILD_HANDLE(peer_id, protocol) \ - ((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol))) -#define IPC_BUILD_MNG_HANDLE(peer_id) \ - IPC_BUILD_HANDLE((peer_id), IPC_PROTOCOL_MNG) -#define IPC_BUILD_HOST_MNG_HANDLE() IPC_BUILD_MNG_HANDLE(IPC_PEER_ID_HOST) -#define IPC_HANDLE_PEER_ID(handle) \ - ((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT) -#define IPC_HANDLE_PROTOCOL(handle) \ - ((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK) -#define IPC_IS_VALID_HANDLE(handle) \ - (IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \ - IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT) - -struct ipc_msg { - uint32_t drbl; - uint32_t *timestamp_of_outgoing_doorbell; - uint8_t payload[IPC_MSG_MAX_SIZE]; -} __packed; - -struct ipc_rst_payload { - uint16_t reset_id; - uint16_t reserved; -}; - -struct ipc_oob_msg { - uint32_t address; - uint32_t length; -}; - -struct ipc_msg_event { - task_id_t task_id; - uint32_t event; - uint8_t enabled; -}; - -/* - * IPC interface context - * This is per-IPC context. - */ -struct ipc_if_ctx { - volatile uint8_t *in_msg_reg; - volatile uint8_t *out_msg_reg; - volatile uint32_t *in_drbl_reg; - volatile uint32_t *out_drbl_reg; - uint32_t clr_busy_bit; - uint32_t pimr_2ish_bit; - uint32_t pimr_2host_clearing_bit; - uint8_t irq_in; - uint8_t irq_clr; - uint16_t reset_id; - struct ipc_msg_event msg_events[IPC_PROTOCOL_COUNT]; - struct mutex lock; - struct mutex write_lock; - - struct queue tx_queue; - uint8_t is_tx_ipc_busy; - uint8_t initialized; -}; - -/* list of peer contexts */ -static struct ipc_if_ctx ipc_peer_ctxs[IPC_PEERS_COUNT] = { - [IPC_PEER_ID_HOST] = { - .in_msg_reg = IPC_HOST2ISH_MSG_BASE, - .out_msg_reg = IPC_ISH2HOST_MSG_BASE, - .in_drbl_reg = IPC_HOST2ISH_DOORBELL_ADDR, - .out_drbl_reg = IPC_ISH2HOST_DOORBELL_ADDR, - .clr_busy_bit = IPC_DB_CLR_STS_ISH2HOST_BIT, - .pimr_2ish_bit = IPC_PIMR_HOST2ISH_BIT, - .pimr_2host_clearing_bit = IPC_PIMR_ISH2HOST_CLR_BIT, - .irq_in = ISH_IPC_HOST2ISH_IRQ, - .irq_clr = ISH_IPC_ISH2HOST_CLR_IRQ, - .tx_queue = QUEUE_NULL(IPC_HOST_MSG_QUEUE_SIZE, struct ipc_msg), - }, - /* Other peers (PMC, CSME, etc) to be added when required */ -}; - -static inline struct ipc_if_ctx *ipc_get_if_ctx(const uint32_t peer_id) -{ - return &ipc_peer_ctxs[peer_id]; -} - -static inline struct ipc_if_ctx *ipc_handle_to_if_ctx(const ipc_handle_t handle) -{ - return ipc_get_if_ctx(IPC_HANDLE_PEER_ID(handle)); -} - -static inline void ipc_enable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) -{ - IPC_PIMR |= ctx->pimr_2ish_bit; -} - -static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) -{ - IPC_PIMR &= ~ctx->pimr_2ish_bit; -} - -static inline void ipc_enable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) -{ - IPC_PIMR |= ctx->pimr_2host_clearing_bit; -} - -static inline void ipc_disable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) -{ - IPC_PIMR &= ~ctx->pimr_2host_clearing_bit; -} - -static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx, - uint32_t drbl, - const uint8_t *payload, - size_t payload_size) -{ - memcpy((void *)(ctx->out_msg_reg), payload, payload_size); - *(ctx->out_drbl_reg) = drbl; -} - -static int ipc_write_raw_timestamp(struct ipc_if_ctx *ctx, uint32_t drbl, - const uint8_t *payload, size_t payload_size, - uint32_t *timestamp) -{ - struct queue *q = &ctx->tx_queue; - struct ipc_msg *msg; - size_t tail, space; - int res = 0; - - mutex_lock(&ctx->write_lock); - - ipc_disable_pimr_clearing_interrupt(ctx); - if (ctx->is_tx_ipc_busy) { - space = queue_space(q); - if (space) { - tail = q->state->tail & (q->buffer_units - 1); - msg = (struct ipc_msg *)q->buffer + tail; - msg->drbl = drbl; - msg->timestamp_of_outgoing_doorbell = timestamp; - memcpy(msg->payload, payload, payload_size); - queue_advance_tail(q, 1); - } else { - CPRINTS("tx queue is full"); - res = -IPC_ERR_TX_QUEUE_FULL; - } - - ipc_enable_pimr_clearing_interrupt(ctx); - goto write_unlock; - } - ctx->is_tx_ipc_busy = 1; - ipc_enable_pimr_clearing_interrupt(ctx); - - write_payload_and_ring_drbl(ctx, drbl, payload, payload_size); - - /* We wrote inline, take timestamp now */ - if (timestamp) - *timestamp = __hw_clock_source_read(); - -write_unlock: - mutex_unlock(&ctx->write_lock); - return res; -} - -static int ipc_write_raw(struct ipc_if_ctx *ctx, uint32_t drbl, - const uint8_t *payload, size_t payload_size) -{ - return ipc_write_raw_timestamp(ctx, drbl, payload, payload_size, NULL); -} - -static int ipc_send_reset_notify(const ipc_handle_t handle) -{ - struct ipc_rst_payload *ipc_rst; - struct ipc_if_ctx *ctx; - struct ipc_msg msg; - - ctx = ipc_handle_to_if_ctx(handle); - ctx->reset_id = (uint16_t)ish_fwst_get_reset_id(); - ipc_rst = (struct ipc_rst_payload *)msg.payload; - ipc_rst->reset_id = ctx->reset_id; - - msg.drbl = IPC_BUILD_MNG_DB(MNG_RESET_NOTIFY, sizeof(*ipc_rst)); - ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl)); - - return 0; -} - -static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx) -{ - struct ipc_msg msg; - - msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0); - ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl)); - - return 0; -} - -static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, - const uint32_t protocol, - uint8_t *buf, const size_t buf_size) -{ - int len = 0, payload_size; - uint8_t *src = NULL, *dest = NULL; - struct ipc_msg *msg; - uint32_t drbl_val; - - drbl_val = *(ctx->in_drbl_reg); - payload_size = IPC_DB_MSG_LENGTH(drbl_val); - - if (payload_size > IPC_MAX_PAYLOAD_SIZE) { - CPRINTS("invalid msg : payload is too big"); - return -IPC_ERR_INVALID_MSG; - } - - switch (protocol) { - case IPC_PROTOCOL_HECI: - /* copy only payload which is a heci packet */ - len = payload_size; - break; - case IPC_PROTOCOL_MNG: - /* copy including doorbell which forms a ipc packet */ - len = payload_size + sizeof(drbl_val); - break; - default: - CPRINTS("protocol %d not supported yet", protocol); - break; - } - - if (len > buf_size) { - CPRINTS("buffer is smaller than payload"); - return -IPC_ERR_TOO_SMALL_BUFFER; - } - - if (IS_ENABLED(IPC_HECI_DEBUG)) - CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", - protocol, drbl_val, - IPC_DB_MSG_LENGTH(drbl_val)); - - switch (protocol) { - case IPC_PROTOCOL_HECI: - src = (uint8_t *)ctx->in_msg_reg; - dest = buf; - break; - case IPC_PROTOCOL_MNG: - src = (uint8_t *)ctx->in_msg_reg; - msg = (struct ipc_msg *)buf; - msg->drbl = drbl_val; - dest = msg->payload; - break; - default : - break; - } - - if (src && dest) - memcpy(dest, src, payload_size); - - return len; -} - -static void set_pimr_and_send_rx_complete(struct ipc_if_ctx *ctx) -{ - ipc_enable_pimr_db_interrupt(ctx); - ipc_send_cmpl_indication(ctx); -} - -static void handle_msg_recv_interrupt(const uint32_t peer_id) -{ - struct ipc_if_ctx *ctx; - uint32_t drbl_val, payload_size, protocol, invalid_msg = 0; - - ctx = ipc_get_if_ctx(peer_id); - ipc_disable_pimr_db_interrupt(ctx); - - drbl_val = *(ctx->in_drbl_reg); - protocol = IPC_DB_PROTOCOL(drbl_val); - payload_size = IPC_DB_MSG_LENGTH(drbl_val); - - if (payload_size > IPC_MSG_MAX_SIZE) - invalid_msg = 1; - - if (!ctx->msg_events[protocol].enabled) - invalid_msg = 2; - - if (!invalid_msg) { - /* send event to task */ - task_set_event(ctx->msg_events[protocol].task_id, - ctx->msg_events[protocol].event, 0); - } else { - CPRINTS("discard msg (%d) : %d", protocol, invalid_msg); - - *(ctx->in_drbl_reg) = 0; - set_pimr_and_send_rx_complete(ctx); - } -} - -static void handle_busy_clear_interrupt(const uint32_t peer_id) -{ - struct ipc_if_ctx *ctx; - struct ipc_msg *msg; - struct queue *q; - size_t head; - - ctx = ipc_get_if_ctx(peer_id); - - /* - * Resetting interrupt status bit should be done - * before sending an item in tx_queue. - */ - IPC_BUSY_CLEAR = ctx->clr_busy_bit; - - /* - * No need to use sync mechanism here since the accesing the queue - * happens only when either this IRQ is disabled or - * in ISR context(here) of this IRQ. - */ - if (!queue_is_empty(&ctx->tx_queue)) { - q = &ctx->tx_queue; - head = q->state->head & (q->buffer_units - 1); - msg = (struct ipc_msg *)(q->buffer + head * q->unit_bytes); - write_payload_and_ring_drbl(ctx, msg->drbl, msg->payload, - IPC_DB_MSG_LENGTH(msg->drbl)); - if (msg->timestamp_of_outgoing_doorbell) - *msg->timestamp_of_outgoing_doorbell = - __hw_clock_source_read(); - - queue_advance_head(q, 1); - } else { - ctx->is_tx_ipc_busy = 0; - } -} - -/** - * IPC interrupts are received by the FW when a) Host SW rings doorbell and - * b) when Host SW clears doorbell busy bit [31]. - * - * Doorbell Register (DB) bits - * ----+-------+--------+-----------+--------+------------+-------------------- - * 31 | 30 29 | 28-20 |19 18 17 16| 15 14 | 13 12 11 10| 9 8 7 6 5 4 3 2 1 0 - * ----+-------+--------+-----------+--------+------------+-------------------- - * Busy|Options|Reserved| Command |Reserved| Protocol | Message Length - * ----+-------+--------+-----------+--------+------------+-------------------- - * - * ISH Peripheral Interrupt Status Register: - * Bit 0 - If set, indicates interrupt was caused by setting Host2ISH DB - * - * ISH Peripheral Interrupt Mask Register - * Bit 0 - If set, mask interrupt caused by Host2ISH DB - * - * ISH Peripheral DB Clear Status Register - * Bit 0 - If set, indicates interrupt was caused by clearing Host2ISH DB - */ -static void ipc_host2ish_isr(void) -{ - uint32_t pisr = IPC_PISR; - uint32_t pimr = IPC_PIMR; - - /* - * Ensure that the host IPC write power is requested after getting an - * interrupt otherwise the resume message will never get delivered (via - * host ipc communication). Resume is where we would like to restore all - * power settings, but that is too late for this power request. - */ - if (IS_ENABLED(CHIP_FAMILY_ISH5)) - PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; - - if ((pisr & IPC_PISR_HOST2ISH_BIT) && (pimr & IPC_PIMR_HOST2ISH_BIT)) - handle_msg_recv_interrupt(IPC_PEER_ID_HOST); -} -#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR -DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_isr); -#endif - -static void ipc_host2ish_busy_clear_isr(void) -{ - uint32_t busy_clear = IPC_BUSY_CLEAR; - uint32_t pimr = IPC_PIMR; - - if ((busy_clear & IPC_DB_CLR_STS_ISH2HOST_BIT) && - (pimr & IPC_PIMR_ISH2HOST_CLR_BIT)) - handle_busy_clear_interrupt(IPC_PEER_ID_HOST); -} -#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR -DECLARE_IRQ(ISH_IPC_ISH2HOST_CLR_IRQ, ipc_host2ish_busy_clear_isr); -#endif - -static __maybe_unused void ipc_host2ish_combined_isr(void) -{ - ipc_host2ish_isr(); - ipc_host2ish_busy_clear_isr(); -} -#ifdef CONFIG_ISH_HOST2ISH_COMBINED_ISR -DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_combined_isr); -#endif - -int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, - const size_t buf_size, uint32_t *timestamp) -{ - int ret; - struct ipc_if_ctx *ctx; - uint32_t drbl = 0; - const uint8_t *payload = NULL; - int payload_size; - uint32_t protocol; - - if (!IPC_IS_VALID_HANDLE(handle)) - return -EC_ERROR_INVAL; - - protocol = IPC_HANDLE_PROTOCOL(handle); - ctx = ipc_handle_to_if_ctx(handle); - - if (ctx->initialized == 0) { - CPRINTS("open_ipc() for the peer is never called"); - return -EC_ERROR_INVAL; - } - - if (!ctx->msg_events[protocol].enabled) { - CPRINTS("call open_ipc() for the protocol first"); - return -EC_ERROR_INVAL; - } - - switch (protocol) { - case IPC_PROTOCOL_BOOT: - break; - case IPC_PROTOCOL_HECI: - drbl = IPC_BUILD_HECI_DB(buf_size); - payload = buf; - break; - case IPC_PROTOCOL_MCTP: - break; - case IPC_PROTOCOL_MNG: - drbl = ((struct ipc_msg *)buf)->drbl; - payload = ((struct ipc_msg *)buf)->payload; - break; - case IPC_PROTOCOL_ECP: - /* TODO : EC protocol */ - break; - } - - payload_size = IPC_DB_MSG_LENGTH(drbl); - if (payload_size > IPC_MSG_MAX_SIZE) { - /* too much input */ - return -EC_ERROR_OVERFLOW; - } - - ret = ipc_write_raw_timestamp(ctx, drbl, payload, payload_size, - timestamp); - if (ret) - return ret; - - return buf_size; -} - -ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event) -{ - struct ipc_if_ctx *ctx; - - if (protocol >= IPC_PROTOCOL_COUNT || - peer_id >= IPC_PEERS_COUNT) - return IPC_INVALID_HANDLE; - - ctx = ipc_get_if_ctx(peer_id); - mutex_lock(&ctx->lock); - if (ctx->msg_events[protocol].enabled) { - mutex_unlock(&ctx->lock); - return IPC_INVALID_HANDLE; - } - - ctx->msg_events[protocol].task_id = task_get_current(); - ctx->msg_events[protocol].enabled = 1; - ctx->msg_events[protocol].event = event; - - /* For HECI protocol, set HECI UP status when IPC link is ready */ - if (peer_id == IPC_PEER_ID_HOST && - protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set()) - ish_fwst_set_hup(); - - if (ctx->initialized == 0) { - task_enable_irq(ctx->irq_in); - if (!IS_ENABLED(CONFIG_ISH_HOST2ISH_COMBINED_ISR)) - task_enable_irq(ctx->irq_clr); - - ipc_enable_pimr_db_interrupt(ctx); - ipc_enable_pimr_clearing_interrupt(ctx); - - ctx->initialized = 1; - } - mutex_unlock(&ctx->lock); - - return IPC_BUILD_HANDLE(peer_id, protocol); -} - -static void handle_mng_commands(const ipc_handle_t handle, - const struct ipc_msg *msg) -{ - struct ipc_rst_payload *ipc_rst; - struct ipc_if_ctx *ctx; - uint32_t peer_id = IPC_HANDLE_PEER_ID(handle); - - ctx = ipc_handle_to_if_ctx(handle); - - switch (IPC_DB_CMD(msg->drbl)) { - case MNG_RX_CMPL_ENABLE: - case MNG_RX_CMPL_DISABLE: - case MNG_RX_CMPL_INDICATION: - case MNG_RESET_NOTIFY: - CPRINTS("msg not handled %d", IPC_DB_CMD(msg->drbl)); - break; - case MNG_RESET_NOTIFY_ACK: - ipc_rst = (struct ipc_rst_payload *)msg->payload; - if (peer_id == IPC_PEER_ID_HOST && - ipc_rst->reset_id == ctx->reset_id) { - ish_fwst_set_ilup(); - if (ctx->msg_events[IPC_PROTOCOL_HECI].enabled) - ish_fwst_set_hup(); - } - - break; - case MNG_SYNC_FW_CLOCK: - /* Not supported currently, but kernel sends this about ~20s */ - break; - } -} - -static int do_ipc_read(struct ipc_if_ctx *ctx, const uint32_t protocol, - uint8_t *buf, const size_t buf_size) -{ - int len; - - len = ipc_get_protocol_data(ctx, protocol, buf, buf_size); - - *(ctx->in_drbl_reg) = 0; - set_pimr_and_send_rx_complete(ctx); - - return len; -} - -static int ipc_check_read_validity(const struct ipc_if_ctx *ctx, - const uint32_t protocol) -{ - if (ctx->initialized == 0) - return -EC_ERROR_INVAL; - - if (!ctx->msg_events[protocol].enabled) - return -EC_ERROR_INVAL; - - /* ipc_read() should be called by the same task called ipc_open() */ - if (ctx->msg_events[protocol].task_id != task_get_current()) - return -IPC_ERR_INVALID_TASK; - - return 0; -} - -/* - * ipc_read should be called by the same task context which called ipc_open() - */ -int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, - int timeout_us) -{ - struct ipc_if_ctx *ctx; - uint32_t events, protocol, drbl_protocol, drbl_val; - int ret; - - if (!IPC_IS_VALID_HANDLE(handle)) - return -EC_ERROR_INVAL; - - protocol = IPC_HANDLE_PROTOCOL(handle); - ctx = ipc_handle_to_if_ctx(handle); - - ret = ipc_check_read_validity(ctx, protocol); - if (ret) - return ret; - - if (timeout_us) { - events = task_wait_event_mask(ctx->msg_events[protocol].event, - timeout_us); - - if (events & TASK_EVENT_TIMER) - return -EC_ERROR_TIMEOUT; - - if (!(events & ctx->msg_events[protocol].event)) - return -EC_ERROR_UNKNOWN; - } else { - /* check if msg for the protocol is available */ - drbl_val = *(ctx->in_drbl_reg); - drbl_protocol = IPC_DB_PROTOCOL(drbl_val); - if (!(protocol == drbl_protocol) || !IPC_DB_BUSY(drbl_val)) - return -IPC_ERR_MSG_NOT_AVAILABLE; - } - - return do_ipc_read(ctx, protocol, buf, buf_size); -} - -/* event flag for MNG msg */ -#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0) - -/* - * This task handles MNG messages - */ -void ipc_mng_task(void) -{ - int payload_size; - struct ipc_msg msg; - ipc_handle_t handle; - - /* - * Ensure that power for host IPC writes is requested and ack'ed - */ - if (IS_ENABLED(CHIP_FAMILY_ISH5)) { - PMU_VNN_REQ = VNN_REQ_IPC_HOST_WRITE & ~PMU_VNN_REQ; - while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) - continue; - } - - handle = ipc_open(IPC_PEER_ID_HOST, IPC_PROTOCOL_MNG, - EVENT_FLAG_BIT_MNG_MSG); - - ASSERT(handle != IPC_INVALID_HANDLE); - - ipc_send_reset_notify(handle); - - while (1) { - payload_size = ipc_read(handle, &msg, sizeof(msg), -1); - - /* allow doorbell with any payload */ - if (payload_size < 0) { - CPRINTS("ipc_read error. discard msg"); - continue; /* TODO: retry several and exit */ - } - - /* handle MNG commands */ - handle_mng_commands(handle, &msg); - } -} - -void ipc_init(void) -{ - int i; - struct ipc_if_ctx *ctx; - - for (i = 0; i < IPC_PEERS_COUNT; i++) { - ctx = ipc_get_if_ctx(i); - queue_init(&ctx->tx_queue); - } - - /* inform host firmware is running */ - ish_fwst_set_fw_status(FWSTS_FW_IS_RUNNING); -} -DECLARE_HOOK(HOOK_INIT, ipc_init, HOOK_PRIO_DEFAULT); diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h deleted file mode 100644 index 183e6a2c6b..0000000000 --- a/chip/ish/ipc_heci.h +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* IPC module for ISH */ -#ifndef __IPC_HECI_H -#define __IPC_HECI_H - -enum IPC_ERR { - IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1, - IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2, - IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3, - IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4, - IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5, -}; - -enum ipc_peer_id { - IPC_PEER_ID_HOST = 0, /* x64 host */ -#if 0 /* other peers are not implemented yet */ - IPC_PEER_ID_PMC = 1, /* Power Management Controller */ - IPC_PEER_ID_CSME = 2, /* Converged Security Management Engine */ - IPC_PEER_ID_CAVS = 3, /* Audio, Voice, and Speech engine */ - IPC_PEER_ID_ISP = 4, /* Image Signal Processor */ -#endif - IPC_PEERS_COUNT, -}; -/* - * Currently ipc handle encoding only allows maximum 16 peers which is - * enough for ISH3, ISH4, and ISH5. They have 5 peers. - */ -BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F); - -enum ipc_protocol { - IPC_PROTOCOL_BOOT = 0, /* Not supported */ - IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */ - IPC_PROTOCOL_MCTP, /* not supported */ - IPC_PROTOCOL_MNG, /* Management protocol */ - IPC_PROTOCOL_ECP, /* EC Protocol. not supported */ - IPC_PROTOCOL_COUNT -}; -/* - * IPC handle enconding only supports 16 protocols which is the - * maximum protocols supported by IPC doorbell encoding. - */ -BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F); - -typedef void * ipc_handle_t; - -#define IPC_MAX_PAYLOAD_SIZE 128 -#define IPC_INVALID_HANDLE NULL - -/* - * Open ipc channel - * - * @param peer_id select peer to communicate. - * @param protocol select protocol - * @param event set event flag - * - * @return ipc handle or IPC_INVALID_HANDLE if there's error - */ -ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event); -void ipc_close(const ipc_handle_t handle); - -/* - * Read message from ipc channel. - * The function should be call by the same task called ipc_open(). - * The function waits until message is available. - * @param timeout_us if == -1, wait until message is available. - * if == 0, return immediately. - * if > 0, wait for the specified microsecond duration time - */ -int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, - int timeout_us); - -/* Write message to ipc channel. */ -int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, - const size_t buf_size, uint32_t *timestamp); - -#endif /* __IPC_HECI_H */ diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h deleted file mode 100644 index 2c76c7d319..0000000000 --- a/chip/ish/ish_dma.h +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ISH_DMA_H -#define __CROS_EC_ISH_DMA_H - -/* DMA return codes */ -#define DMA_RC_OK 0 /* Success */ -#define DMA_RC_TO 1 /* Time out */ -#define DMA_RC_HW 2 /* HW error (OCP) */ - -/* DMA channels */ -#define PAGING_CHAN 0 -#define KERNEL_CHAN 1 - -#define DST_IS_DRAM BIT(0) -#define SRC_IS_DRAM BIT(1) -#define NON_SNOOP BIT(2) - -/* ISH5 and on */ -#define RS0 0x0 -#define RS3 0x3 -#define RS_SRC_OFFSET 3 -#define RS_DST_OFFSET 5 - -#define PAGE_SIZE 4096 - -/** - * SRAM: ISH local static ram - * UMA: Protected system DRAM region dedicated for ISH - * HOST_DRAM: OS owned buffer in system DRAM - */ -enum dma_mode { - SRAM_TO_SRAM = 0, - SRAM_TO_UMA = DST_IS_DRAM | (RS3 << RS_DST_OFFSET), - UMA_TO_SRAM = SRC_IS_DRAM | (RS3 << RS_SRC_OFFSET), - HOST_DRAM_TO_SRAM = SRC_IS_DRAM | (RS0 << RS_SRC_OFFSET), - SRAM_TO_HOST_DRAM = DST_IS_DRAM | (RS0 << RS_DST_OFFSET) -}; - -/* Disable DMA engine */ -void ish_dma_disable(void); -/* Initialize DMA engine */ -void ish_dma_init(void); - -/** - * Main DMA transfer function - * - * @param chan DMA channel - * @param dst Destination address - * @param src Source address - * @param length Transfer size - * @param mode Transfer mode - * @return DMA_RC_OK, or non-zero if error. - */ -int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, - enum dma_mode mode); -/** - * Set upper 32 bits address for DRAM - * - * @param chan DMA channel - * @param dst_msb Destination DRAM upper 32 bits address - * @param src_msb Source DRAM upper 32 bits address - */ -void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb); - -/** - * Wait for DMA transfer finish - * - * @param chan DMA channel - * @return DMA_RC_OK, or non-zero if error. - */ -int ish_wait_for_dma_done(uint32_t ch); - -/* Disable OCP (Open Core Protocol) fabric time out */ -void ish_dma_ocp_timeout_disable(void); -#endif diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h deleted file mode 100644 index c114db3241..0000000000 --- a/chip/ish/ish_fwst.h +++ /dev/null @@ -1,189 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* - * ISH Firmware status register contains currnet ISH FW status. - * Communication protocol for Host(x64), CSME, and PMC uses this register. - */ - -#ifndef __ISH_FWST_H -#define __ISH_FWST_H - -#include "common.h" -#include "registers.h" - -/* - * IPC link is up(ready) - * IPC can be used by other protocols - */ -#define IPC_ISH_FWSTS_ILUP_FIELD 0x01 -#define IPC_ISH_FWSTS_ILUP_SHIFT 0 -#define IPC_ISH_FWSTS_ILUP_MASK \ - (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT) - -/* - * HECI layer is up(ready) - */ -#define IPC_ISH_FWSTS_HUP_FIELD 0x01 -#define IPC_ISH_FWSTS_HUP_SHIFT 1 -#define IPC_ISH_FWSTS_HUP_MASK \ - (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT) - -/* - * ISH FW reason reason - */ -#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F -#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2 -#define IPC_ISH_FWSTS_FAIL_REASON_MASK \ - (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT) - -/* - * ISH FW reset ID - */ -#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F -#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8 -#define IPC_ISH_FWSTS_RESET_ID_MASK \ - (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT) - -/* - * ISH FW status type - */ -enum { - FWSTS_AFTER_RESET = 0, - FWSTS_WAIT_FOR_HOST = 4, - FWSTS_START_KERNEL_DMA = 5, - FWSTS_FW_IS_RUNNING = 7, - FWSTS_SENSOR_APP_LOADED = 8, - FWSTS_SENSOR_APP_RUNNING = 15 -}; - -/* - * General ISH FW status - */ -#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F -#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12 -#define IPC_ISH_FWSTS_FW_STATUS_MASK \ - (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT) - -#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16 -#define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT) - -#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17 -#define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT) - -#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18 -#define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT) - -#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19 -#define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT) - -#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F -#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20 -#define IPC_ISH_FWSTS_POWER_STATE_MASK \ - (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT) - -#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07 -#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24 -#define IPC_ISH_FWSTS_AON_CHECK_MASK \ - (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT) - -/* get ISH FW status register */ -static inline uint32_t ish_fwst_get(void) -{ - return IPC_ISH_FWSTS; -} - -/* set IPC link up */ -static inline void ish_fwst_set_ilup(void) -{ - IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT); -} - -/* clear IPC link up */ -static inline void ish_fwst_clear_ilup(void) -{ - IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_ILUP_MASK; -} - -/* return IPC link up state */ -static inline int ish_fwst_is_ilup_set(void) -{ - return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_ILUP_MASK); -} - -/* set HECI up */ -static inline void ish_fwst_set_hup(void) -{ - IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT); -} - -/* clear HECI up */ -static inline void ish_fwst_clear_hup(void) -{ - IPC_ISH_FWSTS &= ~IPC_ISH_FWSTS_HUP_MASK; -} - -/* get HECI up status */ -static inline int ish_fwst_is_hup_set(void) -{ - return !!(IPC_ISH_FWSTS & IPC_ISH_FWSTS_HUP_MASK); -} - -/* set fw failure reason */ -static inline void ish_fwst_set_fail_reason(uint32_t val) -{ - uint32_t fwst = IPC_ISH_FWSTS; - - IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) | - (val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT); -} - -/* get fw failure reason */ -static inline uint32_t ish_fwst_get_fail_reason(void) -{ - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) - >> IPC_ISH_FWSTS_FAIL_REASON_SHIFT; -} - -/* set reset id */ -static inline void ish_fwst_set_reset_id(uint32_t val) -{ - uint32_t fwst = IPC_ISH_FWSTS; - - IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) | - (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); -} - -/* get reset id */ -static inline uint32_t ish_fwst_get_reset_id(void) -{ - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) - >> IPC_ISH_FWSTS_RESET_ID_SHIFT; -} - -/* set general fw status */ -static inline void ish_fwst_set_fw_status(uint32_t val) -{ - uint32_t fwst = IPC_ISH_FWSTS; - - IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) | - (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); -} - -/* get general fw status */ -static inline uint32_t ish_fwst_get_fw_status(void) -{ - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) - >> IPC_ISH_FWSTS_FW_STATUS_SHIFT; -} - -#endif /* __ISH_FWST_H */ diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h deleted file mode 100644 index 5b30de775c..0000000000 --- a/chip/ish/ish_i2c.h +++ /dev/null @@ -1,205 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ISH_I2C_H -#define __CROS_EC_ISH_I2C_H - -#include <stdint.h> -#include "task.h" - -#define I2C_TSC_TIMEOUT 2000000 -#define I2C_CALIB_ADDRESS 0x3 -#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20) -#define NS_IN_SEC 1000 -#define DEFAULT_SDA_HOLD 240 -#define DEFAULT_SDA_HOLD_STD 2400 -#define DEFAULT_SDA_HOLD_FAST 600 -#define DEFAULT_SDA_HOLD_FAST_PLUS 300 -#define DEFAULT_SDA_HOLD_HIGH 140 -#define NS_2_COUNTERS(ns, clk) ((ns * clk)/NS_IN_SEC) -#define COUNTERS_2_NS(counters, clk) (counters * (NANOSECONDS_IN_SEC / \ - (clk * HZ_IN_MEGAHZ))) -#define I2C_TX_FLUSH_TIMEOUT_USEC 200 - -#define ISH_I2C_FIFO_SIZE 64 - - -enum { - /* freq mode values */ - I2C_FREQ_25 = 0, - I2C_FREQ_50 = 1, - I2C_FREQ_100 = 2, - I2C_FREQ_120 = 3, - I2C_FREQ_40 = 4, - I2C_FREQ_20 = 5, - I2C_FREQ_37 = 6 -}; - -const unsigned int clk_in[] = { - [I2C_FREQ_25] = 25, - [I2C_FREQ_50] = 50, - [I2C_FREQ_100] = 100, - [I2C_FREQ_120] = 120, - [I2C_FREQ_40] = 40, - [I2C_FREQ_20] = 20, - [I2C_FREQ_37] = 37, -}; - -const uint8_t spkln[] = { - [I2C_FREQ_25] = 2, - [I2C_FREQ_50] = 3, - [I2C_FREQ_100] = 5, - [I2C_FREQ_120] = 6, - [I2C_FREQ_40] = 2, - [I2C_FREQ_20] = 1, - [I2C_FREQ_37] = 2, -}; - -enum { - I2C_READ, - I2C_WRITE -}; - -enum { - /* REGISTERS */ - IC_ENABLE = 0x6c, - IC_STATUS = 0x70, - IC_ENABLE_STATUS = 0x9c, - IC_CON = 0x00, - IC_TAR = 0x04, - IC_DATA_CMD = 0x10, - IC_RX_TL = 0x38, - IC_TX_TL = 0x3c, - IC_COMP_PARAM_1 = 0xf4, - IC_INTR_MASK = 0x30, - IC_RAW_INTR_STAT = 0x34, - IC_INTR_STAT = 0x2c, - IC_CLR_TX_ABRT = 0x54, - IC_TX_ABRT_SOURCE = 0x80, - IC_SS_SCL_HCNT = 0x14, - IC_SS_SCL_LCNT = 0x18, - IC_FS_SCL_HCNT = 0x1c, - IC_FS_SCL_LCNT = 0x20, - IC_HS_SCL_HCNT = 0x24, - IC_HS_SCL_LCNT = 0x28, - IC_CLR_STOP_DET = 0x60, - IC_CLR_START_DET = 0x64, - IC_TXFLR = 0x74, - IC_SDA_HOLD = 0x7c, - IC_FS_SPKLEN = 0xA0, - IC_HS_SPKLEN = 0xA4, - /* IC_ENABLE VALUES */ - IC_ENABLE_ENABLE = 1, - IC_ENABLE_DISABLE = 0, - /* IC_STATUS OFFSETS */ - IC_STATUS_MASTER_ACTIVITY = 5, - IC_STATUS_TFE = 2, - /* IC_CON OFFSETS */ - MASTER_MODE_OFFSET = 0, - SPEED_OFFSET = 1, - IC_RESTART_EN_OFFSET = 5, - IC_SLAVE_DISABLE_OFFSET = 6, - /* IC_CON VALUES */ - MASTER_MODE = 1, - STD_SPEED = 1, - FAST_SPEED = 2, - HIGH_SPEED = 3, - IC_RESTART_EN = 1, - IC_SLAVE_DISABLE = 1, - /* IC_CON WRITE VALUES */ - MASTER_MODE_VAL = (MASTER_MODE << MASTER_MODE_OFFSET), - STD_SPEED_VAL = (STD_SPEED << SPEED_OFFSET), - FAST_SPEED_VAL = (FAST_SPEED << SPEED_OFFSET), - HIGH_SPEED_VAL = (HIGH_SPEED << SPEED_OFFSET), - SPEED_MASK = (0x3 << SPEED_OFFSET), - IC_RESTART_EN_VAL = (IC_RESTART_EN << IC_RESTART_EN_OFFSET), - IC_SLAVE_DISABLE_VAL = (IC_SLAVE_DISABLE << IC_SLAVE_DISABLE_OFFSET), - /* IC_TAR OFFSETS */ - IC_TAR_OFFSET = 0, - SPECIAL_OFFSET = 11, - IC_10BITADDR_MASTER_OFFSET = 12, - /* IC_TAR VALUES */ - TAR_SPECIAL = 0, - IC_10BITADDR_MASTER = 0, - /* IC_TAR WRITE VALUES */ - IC_10BITADDR_MASTER_VAL = - (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET), - TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET), - /* IC_DATA_CMD OFFSETS */ - DATA_CMD_DAT_OFFSET = 0, - DATA_CMD_CMD_OFFSET = 8, - DATA_CMD_STOP_OFFSET = 9, - DATA_CMD_RESTART_OFFSET = 10, - /* IC_DATA_CMD VALUES */ - DATA_CMD_READ = 1, - DATA_CMD_WRITE = 0, - DATA_CMD_STOP = 1, - DATA_CMD_RESTART = 1, - /* IC_DATA_CMD WRITE VALUES */ - DATA_CMD_WRITE_VAL = (DATA_CMD_WRITE << DATA_CMD_CMD_OFFSET), - DATA_CMD_READ_VAL = (DATA_CMD_READ << DATA_CMD_CMD_OFFSET), - DATA_CMD_STOP_VAL = (DATA_CMD_STOP << DATA_CMD_STOP_OFFSET), - DATA_CMD_RESTART_VAL = (DATA_CMD_RESTART << DATA_CMD_RESTART_OFFSET), - /* IC_TX_TL */ - IC_TX_TL_VAL = 0, - /* IC_COM_PARAM_OFFSETS */ - TX_BUFFER_DEPTH_OFFSET = 16, - RX_BUFFER_DEPTH_OFFSET = 8, - /* IC_INTR_MASK VALUES */ - M_RX_FULL = BIT(2), - M_TX_EMPTY = BIT(4), - M_TX_ABRT = BIT(6), - M_STOP_DET = BIT(9), - M_START_DET = BIT(10), - IC_INTR_WRITE_MASK_VAL = (M_STOP_DET | M_TX_ABRT), - IC_INTR_READ_MASK_VAL = (M_RX_FULL | M_TX_ABRT), - DISABLE_INT = 0, - ENABLE_WRITE_INT = 1, - ENABLE_READ_INT = 2, - /* IC_ENABLE_STATUS_OFFSETS */ - IC_EN_OFFSET = 0, - /* IC_ENABLE_STATUS_VALUES */ - IC_EN_DISABLED_VAL = 0, - IC_EN_DISABLED = (IC_EN_DISABLED_VAL << IC_EN_OFFSET), - IC_EN_MASK = BIT(IC_EN_OFFSET), - /* IC_TX_ABRT_SOURCE bits */ - ABRT_7B_ADDR_NOACK = 1, -}; - -struct i2c_bus_data { - uint16_t hcnt; - uint16_t lcnt; - uint16_t sda_hold; -}; - -struct i2c_bus_info { - uint8_t bus_id; - struct i2c_bus_data std_speed; - struct i2c_bus_data fast_speed; - struct i2c_bus_data fast_plus_speed; - struct i2c_bus_data high_speed; -} __attribute__ ((__packed__)); - -enum i2c_speed { - I2C_SPEED_100KHZ, /* 100kHz */ - I2C_SPEED_400KHZ, /* 400kHz */ - I2C_SPEED_1MHZ, /* 1MHz */ - I2C_SPEED_3M4HZ, /* 3.4MHz */ -}; - -struct i2c_context { - uint32_t *base; - uint8_t max_rx_depth; - uint8_t max_tx_depth; - uint8_t bus; - enum i2c_speed speed; - uint32_t interrupts; - uint32_t reason; - uint32_t int_pin; - uint8_t error_flag; - task_id_t wait_task_id; -}; - -#endif /* __CROS_EC_ISH_I2C_H */ diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c deleted file mode 100644 index 003f781d5f..0000000000 --- a/chip/ish/ish_persistent_data.c +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "ec_commands.h" -#include "config.h" -#include "hooks.h" -#include "system.h" -#include "ish_persistent_data.h" - -#define PERSISTENT_DATA_MAGIC 0x49534864 /* "ISHd" */ - -struct ish_persistent_data ish_persistent_data = { - .magic = PERSISTENT_DATA_MAGIC, - .reset_flags = EC_RESET_FLAG_POWER_ON, - .watchdog_counter = 0, - .panic_data = {0}, -}; - -/* - * When AON task firmware is not available (perhaps in the early - * stages of bringing up a new board), we have no way to persist data - * across reset. Allocate a memory region for "persistent data" which - * will never persist, this way we can use ish_persistent_data in a - * consistent manner without having to worry if the AON task firmware - * is available. - * - * Otherwise (AON task firmware is available), the - * ish_persistent_data_aon symbol is exported by the linker script. - */ -#ifdef CONFIG_ISH_PM_AONTASK -extern struct ish_persistent_data ish_persistent_data_aon; -#else -static struct ish_persistent_data ish_persistent_data_aon; -#endif - -void ish_persistent_data_init(void) -{ - if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) { - /* Stored data is valid, load a copy */ - memcpy(&ish_persistent_data, - &ish_persistent_data_aon, - sizeof(struct ish_persistent_data)); - - /* Invalidate stored data, in case commit fails to happen */ - ish_persistent_data_aon.magic = 0; - } - - /* Update the system module's copy of the reset flags */ - system_set_reset_flags(chip_read_reset_flags()); -} - -void ish_persistent_data_commit(void) -{ - memcpy(&ish_persistent_data_aon, - &ish_persistent_data, - sizeof(struct ish_persistent_data)); -} diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h deleted file mode 100644 index 0fd973e1bb..0000000000 --- a/chip/ish/ish_persistent_data.h +++ /dev/null @@ -1,53 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_ISH_PERSISTENT_DATA_H -#define __CROS_EC_ISH_PERSISTENT_DATA_H - -#include "panic.h" - -/* - * If you make backwards-incompatible changes to this struct, (that - * is, reading a previous version of the data would be incorrect), - * simply change the magic number in ish_persistent_data.c. This will - * cause the struct to be re-initialized when the firmware loads. - */ -struct ish_persistent_data { - uint32_t magic; - uint32_t reset_flags; - uint32_t watchdog_counter; - struct panic_data panic_data; -}; - -/* - * Local copy of persistent data, which is copied from AON memory only - * if the data in AON memory is valid. - */ -extern struct ish_persistent_data ish_persistent_data; - -/* - * Copy the AON persistent data into the local copy and initialize - * system reset flags, only if magic number is correct. - */ -void ish_persistent_data_init(void); - -/* - * Commit the local copy to the AON memory (to be called at reset). - */ -void ish_persistent_data_commit(void); - -/** - * SNOWBALL - registers about UMA/IMR DDR information and FW location - * in it. ISH Bringup will set these register values at boot - */ -struct snowball_struct { - uint32_t reserved[28]; - uint32_t volatile uma_base_hi; - uint32_t volatile uma_base_lo; - uint32_t volatile uma_limit; - uint32_t volatile fw_offset; -}; - -#endif /* __CROS_EC_ISH_PERSISTENT_DATA_H */ diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c deleted file mode 100644 index f6ef5f8e0b..0000000000 --- a/chip/ish/power_mgt.c +++ /dev/null @@ -1,739 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "aontaskfw/ish_aon_share.h" -#include "console.h" -#include "hwtimer.h" -#include "interrupts.h" -#include "ish_dma.h" -#include "ish_persistent_data.h" -#include "power_mgt.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "watchdog.h" - -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) - -/* defined in link script: core/minute-ia/ec.lds.S */ -extern uint32_t __aon_ro_start; -extern uint32_t __aon_ro_end; -extern uint32_t __aon_rw_start; -extern uint32_t __aon_rw_end; - -/** - * on ISH, uart interrupt can only wakeup ISH from low power state via - * CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin - * exposed, so, we need block ISH enter low power state for a while when - * console is in use. - * fixed amount of time to keep the console in use flag true after boot in - * order to give a permanent window in which the low speed clock is not used. - */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) - -/* power management internal context data structure */ -struct pm_context { - /* aontask image valid flag */ - int aon_valid; - /* point to the aon shared data in aontask */ - struct ish_aon_share *aon_share; - /* TSS segment selector for task switching */ - int aon_tss_selector[2]; - /* console expire time */ - timestamp_t console_expire_time; - /* console in use timeout */ - int console_in_use_timeout_sec; -} __packed; - -static struct pm_context pm_ctx = { - .aon_valid = 0, - /* aon shared data located in the start of aon memory */ - .aon_share = (struct ish_aon_share *)CONFIG_AON_RAM_BASE, - .console_in_use_timeout_sec = 60 -}; - -/* D0ix statistics data, including each state's count and total stay time */ -struct pm_stat { - uint64_t count; - uint64_t total_time_us; -}; - -struct pm_statistics { - struct pm_stat d0i0; - struct pm_stat d0i1; - struct pm_stat d0i2; - struct pm_stat d0i3; -}; - -static struct pm_statistics pm_stats; - -/* - * Log a new statistic - * - * t0: start time, in us - * t1: end time, in us - */ -static void log_pm_stat(struct pm_stat *stat, uint32_t t0, uint32_t t1) -{ - stat->total_time_us += t1 - t0; - stat->count++; -} - -#ifdef CONFIG_ISH_PM_AONTASK - -/* The GDT which initialized in init.S */ -extern struct gdt_entry __gdt[]; -extern struct gdt_header __gdt_ptr[]; - -/* TSS desccriptor for saving main FW's cpu context during aontask switching */ -static struct tss_entry main_tss; - -/** - * add new entry in GDT - * if defined 'CONFIG_ISH_PM_AONTASK', the GDT which defined in init.S will - * have 3 more empty placeholder entries, this function is help to update - * these entries which needed by x86's HW task switching method - * - * @param desc_lo lower DWORD of the entry descriptor - * @param desc_up upper DWORD of the entry descriptor - * - * @return the descriptor selector index of the added entry - */ -static uint32_t add_gdt_entry(uint32_t desc_lo, uint32_t desc_up) -{ - int index; - - /** - * get the first empty entry of GDT which defined in init.S - * each entry has a fixed size of 8 bytes - */ - index = __gdt_ptr[0].limit >> 3; - - /* add the new entry descriptor to the GDT */ - __gdt[index].dword_lo = desc_lo; - __gdt[index].dword_up = desc_up; - - /* update GDT's limit size */ - __gdt_ptr[0].limit += sizeof(struct gdt_entry); - - return __gdt_ptr[0].limit - sizeof(struct gdt_entry); -} - -static void init_aon_task(void) -{ - uint32_t desc_lo, desc_up; - struct ish_aon_share *aon_share = pm_ctx.aon_share; - struct tss_entry *aon_tss = aon_share->aon_tss; - - if (aon_share->magic_id != AON_MAGIC_ID) { - pm_ctx.aon_valid = 0; - return; - } - - pm_ctx.aon_valid = 1; - - pm_ctx.aon_tss_selector[0] = 0; - - /* fill in the 3 placeholder GDT entries */ - - /* TSS's limit specified as 0x67, to allow the task has permission to - * access I/O port using IN/OUT instructions,'iomap_base_addr' field - * must be greater than or equal to TSS' limit - * see 'I/O port permissions' on - * https://en.wikipedia.org/wiki/Task_state_segment - */ - main_tss.iomap_base_addr = GDT_DESC_TSS_LIMIT; - - /* set GDT entry 3 for TSS descriptor of main FW - * limit: 0x67 - * Present = 1, DPL = 0 - */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - add_gdt_entry(desc_lo, desc_up); - - /* set GDT entry 4 for TSS descriptor of aontask - * limit: 0x67 - * Present = 1, DPL = 0, Accessed = 1 - */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up); - - /* set GDT entry 5 for LDT descriptor of aontask - * Present = 1, DPL = 0, Readable = 1 - */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_share->aon_ldt, - aon_share->aon_ldt_size, GDT_DESC_LDT_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)aon_share->aon_ldt, - aon_share->aon_ldt_size, GDT_DESC_LDT_FLAGS); - aon_tss->ldt_seg_selector = add_gdt_entry(desc_lo, desc_up); - - /* update GDT register and set current TSS as main_tss (GDT entry 3) */ - __asm__ volatile("lgdt __gdt_ptr;\n" - "push %eax;\n" - "movw $0x18, %ax;\n" - "ltr %ax;\n" - "pop %eax;"); - - aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start; - aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end - - (uint32_t)&__aon_ro_start; - - aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start; - aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end - - (uint32_t)&__aon_rw_start; - - ish_dma_init(); -} - -static inline void check_aon_task_status(void) -{ - struct ish_aon_share *aon_share = pm_ctx.aon_share; - - if (aon_share->last_error != AON_SUCCESS) { - CPRINTF("aontask has errors:\n"); - CPRINTF(" last error: %d\n", aon_share->last_error); - CPRINTF(" error counts: %d\n", aon_share->error_count); - } -} - -static void switch_to_aontask(void) -{ - interrupt_disable(); - - __sync_synchronize(); - - /* disable cache and flush cache */ - __asm__ volatile("movl %%cr0, %%eax;\n" - "orl $0x60000000, %%eax;\n" - "movl %%eax, %%cr0;\n" - "wbinvd;" - : - : - : "eax"); - - /* switch to aontask through a far call with aontask's TSS selector */ - __asm__ volatile("lcall *%0;" ::"m"(*pm_ctx.aon_tss_selector) :); - - /* clear TS (Task Switched) flag and enable cache */ - __asm__ volatile("clts;\n" - "movl %%cr0, %%eax;\n" - "andl $0x9FFFFFFF, %%eax;\n" - "movl %%eax, %%cr0;" - : - : - : "eax"); - - interrupt_enable(); -} - -__attribute__ ((noreturn)) -static void handle_reset_in_aontask(enum ish_pm_state pm_state) -{ - pm_ctx.aon_share->pm_state = pm_state; - - /* only enable PMU wakeup interrupt */ - disable_all_interrupts(); - task_enable_irq(ISH_PMU_WAKEUP_IRQ); - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) - task_enable_irq(ISH_RESET_PREP_IRQ); - - /* enable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 1; - - /* enable power gating of RF(Cache) and ROMs */ - PMU_RF_ROM_PWR_CTRL = 1; - - switch_to_aontask(); - - __builtin_unreachable(); -} - -#endif - -static void enter_d0i0(void) -{ - uint32_t t0, t1; - - t0 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I0; - - /* halt ISH cpu, will wakeup from any interrupt */ - ish_mia_halt(); - - t1 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; - log_pm_stat(&pm_stats.d0i0, t0, t1); -} - -/** - * ISH PMU does not support both-edge interrupt triggered gpio configuration. - * If both edges are configured, then the ISH can't stay in low poer mode - * because it will exit immediately. - * - * As a workaround, we scan all gpio pins which have been configured as - * both-edge triggered, and then temporarily set each gpio pin to the single - * edge trigger that is opposite of its value, then restore the both-edge - * trigger configuration immediately after exiting low power mode. - */ -static uint32_t convert_both_edge_gpio_to_single_edge(void) -{ - uint32_t both_edge_pins = 0; - int i = 0; - - /** - * scan GPIO GFER, GRER and GIMR registers to find the both edge - * interrupt trigger mode enabled pins. - */ - for (i = 0; i < 32; i++) { - if (ISH_GPIO_GIMR & BIT(i) && - ISH_GPIO_GRER & BIT(i) && - ISH_GPIO_GFER & BIT(i)) { - - /* Record the pin so we can restore it later */ - both_edge_pins |= BIT(i); - - if (ISH_GPIO_GPLR & BIT(i)) { - /* pin is high, just keep falling edge mode */ - ISH_GPIO_GRER &= ~BIT(i); - } else { - /* pin is low, just keep rising edge mode */ - ISH_GPIO_GFER &= ~BIT(i); - } - } - } - - return both_edge_pins; -} - -static void restore_both_edge_gpio_config(uint32_t both_edge_pin_map) -{ - ISH_GPIO_GRER |= both_edge_pin_map; - ISH_GPIO_GFER |= both_edge_pin_map; -} - -static void enter_d0i1(void) -{ - uint64_t current_irq_map; - uint32_t both_edge_gpio_pins; - uint32_t t0, t1; - - /* only enable PMU wakeup interrupt */ - current_irq_map = disable_all_interrupts(); - task_enable_irq(ISH_PMU_WAKEUP_IRQ); - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) - task_enable_irq(ISH_RESET_PREP_IRQ); - - t0 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I1; - - both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge(); - - /* enable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 1; - - /* halt ISH cpu, will wakeup from PMU wakeup interrupt */ - ish_mia_halt(); - - /* disable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 0; - - restore_both_edge_gpio_config(both_edge_gpio_pins); - - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; - t1 = __hw_clock_source_read(); - log_pm_stat(&pm_stats.d0i1, t0, t1); - - /* Reload watchdog before enabling interrupts again */ - watchdog_reload(); - - /* restore interrupts */ - task_disable_irq(ISH_PMU_WAKEUP_IRQ); - restore_interrupts(current_irq_map); -} - -static void enter_d0i2(void) -{ - uint64_t current_irq_map; - uint32_t both_edge_gpio_pins; - uint32_t t0, t1; - - /* only enable PMU wakeup interrupt */ - current_irq_map = disable_all_interrupts(); - task_enable_irq(ISH_PMU_WAKEUP_IRQ); - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) - task_enable_irq(ISH_RESET_PREP_IRQ); - - t0 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I2; - - both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge(); - - /* enable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 1; - - /* enable power gating of RF(Cache) and ROMs */ - PMU_RF_ROM_PWR_CTRL = 1; - - switch_to_aontask(); - - /* returned from aontask */ - - /* disable power gating of RF(Cache) and ROMs */ - PMU_RF_ROM_PWR_CTRL = 0; - - /* disable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 0; - - restore_both_edge_gpio_config(both_edge_gpio_pins); - - t1 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; - log_pm_stat(&pm_stats.d0i2, t0, t1); - - /* Reload watchdog before enabling interrupts again */ - watchdog_reload(); - - /* restore interrupts */ - task_disable_irq(ISH_PMU_WAKEUP_IRQ); - restore_interrupts(current_irq_map); -} - -static void enter_d0i3(void) -{ - uint64_t current_irq_map; - uint32_t both_edge_gpio_pins; - uint32_t t0, t1; - - /* only enable PMU wakeup interrupt */ - current_irq_map = disable_all_interrupts(); - task_enable_irq(ISH_PMU_WAKEUP_IRQ); - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) - task_enable_irq(ISH_RESET_PREP_IRQ); - - t0 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0I3; - - both_edge_gpio_pins = convert_both_edge_gpio_to_single_edge(); - - /* enable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 1; - - /* enable power gating of RF(Cache) and ROMs */ - PMU_RF_ROM_PWR_CTRL = 1; - - switch_to_aontask(); - - /* returned from aontask */ - - /* disable power gating of RF(Cache) and ROMs */ - PMU_RF_ROM_PWR_CTRL = 0; - - /* disable Trunk Clock Gating (TCG) of ISH */ - CCU_TCG_EN = 0; - - restore_both_edge_gpio_config(both_edge_gpio_pins); - - t1 = __hw_clock_source_read(); - pm_ctx.aon_share->pm_state = ISH_PM_STATE_D0; - log_pm_stat(&pm_stats.d0i3, t0, t1); - - /* Reload watchdog before enabling interrupts again */ - watchdog_reload(); - - /* restore interrupts */ - task_disable_irq(ISH_PMU_WAKEUP_IRQ); - restore_interrupts(current_irq_map); -} - -static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us) -{ - int pm_state = ISH_PM_STATE_D0I0; - - if (DEEP_SLEEP_ALLOWED) { - - /* check if the console use has expired. */ - if (sleep_mask & SLEEP_MASK_CONSOLE) { - if (cur_time.val > pm_ctx.console_expire_time.val) { - enable_sleep(SLEEP_MASK_CONSOLE); - ccprints("Disabling console in deep sleep"); - } else { - return pm_state; - } - } - - if (IS_ENABLED(CONFIG_ISH_PM_D0I3) && - idle_us >= CONFIG_ISH_D0I3_MIN_USEC && - pm_ctx.aon_valid) - pm_state = ISH_PM_STATE_D0I3; - - else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) && - idle_us >= CONFIG_ISH_D0I2_MIN_USEC && - pm_ctx.aon_valid) - pm_state = ISH_PM_STATE_D0I2; - - else if (IS_ENABLED(CONFIG_ISH_PM_D0I1)) - pm_state = ISH_PM_STATE_D0I1; - } - - return pm_state; -} - -static void pm_process(timestamp_t cur_time, uint32_t idle_us) -{ - int decide; - - decide = d0ix_decide(cur_time, idle_us); - - switch (decide) { - case ISH_PM_STATE_D0I1: - enter_d0i1(); - break; - case ISH_PM_STATE_D0I2: - enter_d0i2(); - check_aon_task_status(); - break; - case ISH_PM_STATE_D0I3: - enter_d0i3(); - check_aon_task_status(); - break; - default: - enter_d0i0(); - break; - } -} - -void ish_pm_init(void) -{ - /* clear reset bit */ - ISH_RST_REG = 0; - - /* clear reset history register in CCU */ - CCU_RST_HST = CCU_RST_HST; - - /* disable TCG and disable BCG */ - CCU_TCG_EN = 0; - CCU_BCG_EN = 0; - - if (IS_ENABLED(CONFIG_ISH_PM_AONTASK)) - init_aon_task(); - - /* unmask all wake up events */ - PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL; - - if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) { - /* unmask reset prep avail interrupt */ - PMU_RST_PREP = 0; - - task_enable_irq(ISH_RESET_PREP_IRQ); - } - - if (IS_ENABLED(CONFIG_ISH_PM_D3)) { - /* unmask D3 and BME interrupts */ - PMU_D3_STATUS &= (PMU_D3_BIT_SET | PMU_BME_BIT_SET); - - if ((!(PMU_D3_STATUS & PMU_D3_BIT_SET)) && - (PMU_D3_STATUS & PMU_BME_BIT_SET)) - PMU_D3_STATUS = PMU_D3_STATUS; - - task_enable_irq(ISH_D3_RISE_IRQ); - task_enable_irq(ISH_D3_FALL_IRQ); - task_enable_irq(ISH_BME_RISE_IRQ); - task_enable_irq(ISH_BME_FALL_IRQ); - } -} - -__attribute__ ((noreturn)) -void ish_pm_reset(enum ish_pm_state pm_state) -{ - if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && - pm_ctx.aon_valid) { - handle_reset_in_aontask(pm_state); - } else { - ish_mia_reset(); - } - - __builtin_unreachable(); -} - -void __idle(void) -{ - timestamp_t t0; - int next_delay = 0; - - /** - * initialize console in use to true and specify the console expire - * time in order to give a fixed window on boot - */ - disable_sleep(SLEEP_MASK_CONSOLE); - pm_ctx.console_expire_time.val = get_time().val + - CONSOLE_IN_USE_ON_BOOT_TIME; - - while (1) { - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - - /* - * Most of the time, 'next_delay' will be positive. But, due to - * interrupt latency, it's possible that get_time() returns - * the value bigger than the one from __hw_clock_event_get() - * which is supposed to be updated by ISR before control reaches - * to the get_time(). - * - * Here, we handle the delayed update by changing negative to 0. - */ - pm_process(t0, MAX(0, next_delay)); - } -} - -/* - * helper for command_idle_stats - */ -static void print_stats(const char *name, const struct pm_stat *stat) -{ - if (stat->count) - ccprintf(" %s:\n" - " counts: %llu\n" - " time: %.6llus\n", - name, stat->count, stat->total_time_us); -} - -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - struct ish_aon_share *aon_share = pm_ctx.aon_share; - - ccprintf("Aontask exists: %s\n", pm_ctx.aon_valid ? "Yes" : "No"); - ccprintf("Total time on: %.6llus\n", get_time().val); - ccprintf("Idle sleep:\n"); - print_stats("D0i0", &pm_stats.d0i0); - - ccprintf("Deep sleep:\n"); - print_stats("D0i1", &pm_stats.d0i1); - print_stats("D0i2", &pm_stats.d0i2); - print_stats("D0i3", &pm_stats.d0i3); - - if (pm_ctx.aon_valid) { - ccprintf(" Aontask status:\n"); - ccprintf(" last error: %u\n", aon_share->last_error); - ccprintf(" error counts: %u\n", aon_share->error_count); - } - - return EC_SUCCESS; -} - -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", - "Print power management statistics"); - - -/** - * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will - * handle PMU wakeup interrupt for other low power states - */ -__maybe_unused -static void pmu_wakeup_isr(void) -{ - /* at current nothing need to do */ -} - -#ifdef CONFIG_ISH_PM_D0I1 -DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr); -#endif - -/** - * from ISH5.0, when system doing S0->Sx transition, will receive reset prep - * interrupt, will switch to aontask for handling - * - */ - -__maybe_unused __attribute__ ((noreturn)) -static void reset_prep_isr(void) -{ - /* mask reset prep avail interrupt */ - PMU_RST_PREP = PMU_RST_PREP_INT_MASK; - - /* - * Indicate completion of servicing the interrupt to IOAPIC first - * then indicate completion of servicing the interrupt to LAPIC - */ - IOAPIC_EOI_REG = ISH_RESET_PREP_VEC; - LAPIC_EOI_REG = 0x0; - - system_reset(0); - __builtin_unreachable(); -} - -#ifdef CONFIG_ISH_PM_RESET_PREP -DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr); -#endif - -__maybe_unused -static void handle_d3(uint32_t irq_vec) -{ - PMU_D3_STATUS = PMU_D3_STATUS; - - if (PMU_D3_STATUS & (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) { - /* - * Indicate completion of servicing the interrupt to IOAPIC - * first then indicate completion of servicing the interrupt - * to LAPIC - */ - IOAPIC_EOI_REG = irq_vec; - LAPIC_EOI_REG = 0x0; - - ish_persistent_data_commit(); - ish_pm_reset(ISH_PM_STATE_D3); - } -} - -static void d3_rise_isr(void) -{ - handle_d3(ISH_D3_RISE_VEC); -} - -static void d3_fall_isr(void) -{ - handle_d3(ISH_D3_FALL_VEC); -} - -static void bme_rise_isr(void) -{ - handle_d3(ISH_BME_RISE_VEC); -} - -static void bme_fall_isr(void) -{ - handle_d3(ISH_BME_FALL_VEC); -} - -#ifdef CONFIG_ISH_PM_D3 -DECLARE_IRQ(ISH_D3_RISE_IRQ, d3_rise_isr); -DECLARE_IRQ(ISH_D3_FALL_IRQ, d3_fall_isr); -DECLARE_IRQ(ISH_BME_RISE_IRQ, bme_rise_isr); -DECLARE_IRQ(ISH_BME_FALL_IRQ, bme_fall_isr); -#endif - -void ish_pm_refresh_console_in_use(void) -{ - disable_sleep(SLEEP_MASK_CONSOLE); - - /* Set console in use expire time. */ - pm_ctx.console_expire_time = get_time(); - pm_ctx.console_expire_time.val += - pm_ctx.console_in_use_timeout_sec * SECOND; -} diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h deleted file mode 100644 index d66bb96550..0000000000 --- a/chip/ish/power_mgt.h +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_POWER_MGT_H -#define __CROS_EC_POWER_MGT_H - -#include "common.h" -#include "registers.h" - -/* power states for ISH */ -enum ish_pm_state { - /* D0 state: active mode */ - ISH_PM_STATE_D0 = 0, - /* sleep state: cpu halt */ - ISH_PM_STATE_D0I0, - /* deep sleep state 1: Trunk Clock Gating(TCG), cpu halt*/ - ISH_PM_STATE_D0I1, - /* deep sleep state 2: TCG, SRAM retention, cpu halt */ - ISH_PM_STATE_D0I2, - /* deep sleep state 3: TCG, SRAM power off, cpu halt*/ - ISH_PM_STATE_D0I3, - /** - * D3 state: power off state, on ISH5.0, can't do real power off, - * similar to D0I3, but will reset ISH - */ - ISH_PM_STATE_D3, - /** - * reset ISH, main FW received 'reboot' command - */ - ISH_PM_STATE_RESET, - /** - * reset ISH, main FW received reset_prep interrupt during - * S0->Sx transition. - */ - ISH_PM_STATE_RESET_PREP, - ISH_PM_STATE_NUM -}; - -/* halt ISH minute-ia cpu core */ -static inline void ish_mia_halt(void) -{ - /* make sure interrupts are enabled before halting */ - __asm__ volatile("sti;\n" - "hlt;"); -} - -/* reset ISH mintue-ia cpu core */ -__attribute__((noreturn)) -static inline void ish_mia_reset(void) -{ - /** - * ISH HW looks at the rising edge of this bit to - * trigger a MIA reset. - */ - ISH_RST_REG = 0; - ISH_RST_REG = 1; - - __builtin_unreachable(); -} - -/* Initialize power management module. */ -#ifdef CONFIG_LOW_POWER_IDLE -void ish_pm_init(void); -#else -__maybe_unused static void ish_pm_init(void) -{ -} -#endif - -/** - * reset ISH (reset minute-ia cpu core, and power off main SRAM) - */ -void ish_pm_reset(enum ish_pm_state pm_state) __attribute__((noreturn)); - -/** - * notify the power management module that the UART for the console is in use. - */ -void ish_pm_refresh_console_in_use(void); - -#endif /* __CROS_EC_POWER_MGT_H */ diff --git a/chip/ish/registers.h b/chip/ish/registers.h deleted file mode 100644 index d4ac2ea47a..0000000000 --- a/chip/ish/registers.h +++ /dev/null @@ -1,373 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Registers and interrupts for Intel(R) Integrated Sensor Hub - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#ifndef __ASSEMBLER__ -#include "common.h" -#include "compile_time_macros.h" - -/* ISH GPIO has only one port */ -#define DUMMY_GPIO_BANK -1 - -/* - * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port). - */ -enum ish_i2c_port { - ISH_I2C0 = 0, /* Controller 0 */ - ISH_I2C1 = 1, /* Controller 1 */ - ISH_I2C2 = 2, /* Controller 2 */ - I2C_PORT_COUNT, -}; - -#endif - -#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT - -/* In ISH, the devices are mapped to pre-defined addresses in the 32-bit - * linear address space. - */ -#ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_BASE 0x00000000 -#define ISH_I2C1_BASE 0x00002000 -#define ISH_I2C2_BASE 0x00004000 -#define ISH_UART_BASE 0x08100000 -#define ISH_GPIO_BASE 0x00100000 -#define ISH_PMU_BASE 0x04200000 -#define ISH_OCP_BASE 0xFFFFFFFF -#define ISH_MISC_BASE 0xFFFFFFFF -#define ISH_DMA_BASE 0x10100000 -#define ISH_CCU_BASE 0x04300000 -#define ISH_IPC_BASE 0x04100000 -#define ISH_WDT_BASE 0x04900000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0x04700000 -#define ISH_LAPIC_BASE 0xFEE00000 -#else -#define ISH_I2C0_BASE 0x00100000 -#define ISH_I2C1_BASE 0x00102000 -#define ISH_I2C2_BASE 0x00105000 -#define ISH_UART_BASE 0x00103000 -#define ISH_GPIO_BASE 0x001F0000 -#define ISH_PMU_BASE 0x00800000 -#define ISH_OCP_BASE 0x00700000 -#define ISH_MISC_BASE 0x00C00000 -#define ISH_DMA_BASE 0x00400000 -#define ISH_CCU_BASE 0x00900000 -#define ISH_IPC_BASE 0x00B00000 -#define ISH_WDT_BASE 0xFDE00000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0xFED00000 -#define ISH_LAPIC_BASE 0xFEE00000 -#endif - -/* HW interrupt pins mapped to IOAPIC, from I/O sources */ -#ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_IRQ 15 -#define ISH_I2C1_IRQ 16 -#define ISH_FABRIC_IRQ 12 -#define ISH_I2C2_IRQ 17 -#define ISH_WDT_IRQ 26 -#define ISH_GPIO_IRQ 13 -#define ISH_HPET_TIMER1_IRQ 14 -#define ISH_IPC_HOST2ISH_IRQ 0 -#define ISH_PMU_WAKEUP_IRQ 10 -#define ISH_D3_RISE_IRQ 9 -#define ISH_D3_FALL_IRQ 9 -#define ISH_BME_RISE_IRQ 9 -#define ISH_BME_FALL_IRQ 9 -#define ISH_IPC_ISH2HOST_CLR_IRQ 0 -#define ISH_UART0_IRQ 23 -#define ISH_UART1_IRQ 24 -#define ISH_RESET_PREP_IRQ 6 -#else -#define ISH_I2C0_IRQ 0 -#define ISH_I2C1_IRQ 1 -#define ISH_FABRIC_IRQ 5 -#define ISH_I2C2_IRQ 40 -#define ISH_WDT_IRQ 6 -#define ISH_GPIO_IRQ 7 -#define ISH_HPET_TIMER1_IRQ 8 -#define ISH_IPC_HOST2ISH_IRQ 12 -#define ISH_PMU_WAKEUP_IRQ 18 -#define ISH_D3_RISE_IRQ 19 -#define ISH_D3_FALL_IRQ 29 -#define ISH_BME_RISE_IRQ 50 -#define ISH_BME_FALL_IRQ 51 -#define ISH_IPC_ISH2HOST_CLR_IRQ 24 -#define ISH_UART0_IRQ 34 -#define ISH_UART1_IRQ 35 -#define ISH_RESET_PREP_IRQ 62 -#endif - -/* Interrupt vectors 0-31 are architecture reserved. - * Vectors 32-255 are user-defined. - */ -#define USER_VEC_START 32 -/* Map IRQs to vectors after offset 10 for certain APIC interrupts */ -#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) -#define VEC_TO_IRQ(vec) ((vec) - USER_VEC_START - 10) - -/* ISH GPIO Registers */ -#define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */ -#define ISH_GPIO_GPLR REG32(ISH_GPIO_BASE + 0x004) /* Pin level */ -#define ISH_GPIO_GPDR REG32(ISH_GPIO_BASE + 0x01C) /* Pin direction */ -#define ISH_GPIO_GPSR REG32(ISH_GPIO_BASE + 0x034) /* Output set */ -#define ISH_GPIO_GPCR REG32(ISH_GPIO_BASE + 0x04C) /* Output clear */ -#define ISH_GPIO_GRER REG32(ISH_GPIO_BASE + 0x064) /* Rising edge detect */ -#define ISH_GPIO_GFER REG32(ISH_GPIO_BASE + 0x07C) /* Falling edge detect */ -#define ISH_GPIO_GFBR REG32(ISH_GPIO_BASE + 0x094) /* Glitch Filter disable */ -#define ISH_GPIO_GIMR REG32(ISH_GPIO_BASE + 0x0AC) /* Interrupt Enable */ -#define ISH_GPIO_GISR REG32(ISH_GPIO_BASE + 0x0C4) /* Interrupt Source */ -#define ISH_GPIO_GWMR REG32(ISH_GPIO_BASE + 0x100) /* Wake Enable */ -#define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */ -#define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */ - -/* APIC interrupt vectors */ -#define ISH_TS_VECTOR 0x20 /* Task switch vector */ -#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ -#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */ -#define LAPIC_SPURIOUS_INT_VECTOR 0xff - -/* Interrupt to vector mapping. To be programmed into IOAPIC */ -#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ) -#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ) -#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ) -#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ) -#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ) -#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ) -#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ) -#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) -#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) -#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) -#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) -#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ) -#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ) -#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ) -#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ) -#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ) -#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ) - -#define ISH_DEBUG_UART UART_PORT_0 -#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ -#define ISH_DEBUG_UART_VEC ISH_UART0_VEC - -/* IPC_Registers */ -#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) -#define IPC_PISR_HOST2ISH_BIT BIT(0) - -#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) -#define IPC_PIMR_HOST2ISH_BIT BIT(0) -#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) -#define IPC_PIMR_CSME_CSR_BIT BIT(23) -#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) -#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) -#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) -#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) -#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) -#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) -#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) -#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) -#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) -#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) -#define DMA_ENABLED_MASK BIT(0) -#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) -#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) - -#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) -#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) -#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) -#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) - -/* PMU Registers */ -#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) -#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) -#define PMU_D3_BIT_SET BIT(0) -#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) -#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2) -#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3) -#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4) -#define PMU_BME_BIT_SET BIT(5) -#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6) -#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7) -#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) -#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) -#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) -#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ - -#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) -#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ - -#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) -#define PMU_RST_PREP_GET BIT(0) -#define PMU_RST_PREP_AVAIL BIT(1) -#define PMU_RST_PREP_INT_MASK BIT(31) - -#define VNN_ID_DMA0 4 -#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) - -/* OCP registers */ -#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) -#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20) -#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF - -/* MISC registers */ -#define MISC_REG_BASE ISH_MISC_BASE -#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) -#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) -#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) -#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) -#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) - -/* DMA registers */ -#define DMA_REG_BASE ISH_DMA_BASE -#define DMA_CH_REGS_SIZE 0x58 -#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) -#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) -#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0) -#define DMA_EN_REG REG32(DMA_EN_REG_ADDR) -#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398) -#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400) -#define DMA_PSIZE_CHAN0_SIZE 512 -#define DMA_PSIZE_CHAN0_OFFSET 0 -#define DMA_PSIZE_CHAN1_SIZE 128 -#define DMA_PSIZE_CHAN1_OFFSET 13 -#define DMA_PSIZE_UPDATE BIT(26) -#define DMA_MAX_CHANNEL 4 -#define DMA_SAR(chan) REG32(chan + 0x000) -#define DMA_DAR(chan) REG32(chan + 0x008) -#define DMA_LLP(chan) REG32(chan + 0x010) -#define DMA_CTL_LOW(chan) REG32(chan + 0x018) -#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4) -#define DMA_CTL_INT_ENABLE BIT(0) -#define DMA_CTL_DST_TR_WIDTH_SHIFT 1 -#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4 -#define DMA_CTL_DINC_SHIFT 7 -#define DMA_CTL_SINC_SHIFT 9 -#define DMA_CTL_ADDR_INC 0 -#define DMA_CTL_DEST_MSIZE_SHIFT 11 -#define DMA_CTL_SRC_MSIZE_SHIFT 14 -#define DMA_CTL_TT_FC_SHIFT 20 -#define DMA_CTL_TT_FC_M2M_DMAC 0 -#define DMA_ENABLE BIT(0) -#define DMA_CH_EN_BIT(n) BIT(n) -#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n)) -#define DMA_MAX_BLOCK_SIZE (4096) -#define SRC_TR_WIDTH 2 -#define SRC_BURST_SIZE 3 -#define DEST_TR_WIDTH 2 -#define DEST_BURST_SIZE 3 - -#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) -#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) -#define PMU_MASK_EVENT_BIT_HPET BIT(16) -#define PMU_MASK_EVENT_BIT_IPC BIT(17) -#define PMU_MASK_EVENT_BIT_D3 BIT(18) -#define PMU_MASK_EVENT_BIT_DMA BIT(19) -#define PMU_MASK_EVENT_BIT_I2C0 BIT(20) -#define PMU_MASK_EVENT_BIT_I2C1 BIT(21) -#define PMU_MASK_EVENT_BIT_SPI BIT(22) -#define PMU_MASK_EVENT_BIT_UART BIT(23) -#define PMU_MASK_EVENT_BIT_ALL (0xffffffff) - -#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) - -#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44) -#define PMU_LDO_ENABLE_BIT BIT(0) -#define PMU_LDO_RETENTION_BIT BIT(1) -#define PMU_LDO_CALIBRATION_BIT BIT(2) -#define PMU_LDO_READY_BIT BIT(3) - -/* CCU Registers */ -#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) -#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) -#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) -#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ -#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) -#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) -#define CCU_BCG_BIT_MIA BIT(0) -#define CCU_BCG_BIT_DMA BIT(1) -#define CCU_BCG_BIT_I2C0 BIT(2) -#define CCU_BCG_BIT_I2C1 BIT(3) -#define CCU_BCG_BIT_SPI BIT(4) -#define CCU_BCG_BIT_SRAM BIT(5) -#define CCU_BCG_BIT_HPET BIT(6) -#define CCU_BCG_BIT_UART BIT(7) -#define CCU_BCG_BIT_GPIO BIT(8) -#define CCU_BCG_BIT_I2C2 BIT(9) -#define CCU_BCG_BIT_SPI2 BIT(10) -#define CCU_BCG_BIT_ALL (0x7ff) - -/* Bitmasks for CCU_RST_HST */ -#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */ -#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */ -#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */ -#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ - -/* Fabric Agent Status register */ -#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) -#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) -#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) -#define FABRIC_M_ERR_BIT BIT(24) -#define FABRIC_MIA_STATUS_BIT_ERR (FABRIC_INBAND_ERR_SECONDARY_BIT | \ - FABRIC_INBAND_ERR_PRIMARY_BIT | \ - FABRIC_M_ERR_BIT) - -/* CSME Registers */ -#ifdef CHIP_VARIANT_ISH5P4 -#define SEC_OFFSET 0x10000 -#else -#define SEC_OFFSET 0x0 -#endif -#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) - -/* IOAPIC registers */ -#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) -#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) -/* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */ -#define IOAPIC_EOI_REG_ADDR 0xFEC00040 -#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) - -#define IOAPIC_VERSION (0x1) -#define IOAPIC_IOREDTBL (0x10) -#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) -#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) -#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) -#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) -#define IOAPIC_REDTBL_IRR (0x00004000) -#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) -#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) -#define IOAPIC_REDTBL_MASK (0x00010000) - -/* WDT (Watchdog Timer) Registers */ -#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) -#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) -#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) -#define WDT_CONTROL_ENABLE_BIT BIT(17) - -/* LAPIC registers */ -/* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ -#define LAPIC_EOI_REG_ADDR 0xFEE000B0 -#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) -#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) -#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) -#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) -#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL BIT(6) -#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) - -/* SRAM control registers */ -#define ISH_SRAM_CTRL_BASE 0x00500000 -#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) -#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) -#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) -#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) -#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) -#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/ish/reset_prep_wr.c b/chip/ish/reset_prep_wr.c deleted file mode 100644 index c192fb3723..0000000000 --- a/chip/ish/reset_prep_wr.c +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Workaround for ISH5.4 reset prep handling before full PM is enabled */ -#include "common.h" -#include "hooks.h" -#include "interrupts.h" -#include "registers.h" -#include "system.h" -#include "task.h" - -/* - * IRQ fires when we receive a RESET_PREP message from AP. This happens at S0 - * entry. - */ -static void reset_prep_wr_isr(void) -{ - system_reset(SYSTEM_RESET_HARD); -} -DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_wr_isr); - -void reset_prep_init(void) -{ - /* Clear reset bit */ - ISH_RST_REG = 0; - - /* Clear reset history register from previous boot. */ - CCU_RST_HST = CCU_RST_HST; - /* Unmask reset prep avail interrupt mask */ - PMU_RST_PREP = 0; - /* Clear TCG Enable, no trunk level clock gating*/ - CCU_TCG_ENABLE = 0; - /* Clear BCG Enable, no block level clock gating*/ - CCU_BCG_ENABLE = 0; - - task_enable_irq(ISH_RESET_PREP_IRQ); -} -DECLARE_HOOK(HOOK_INIT, reset_prep_init, HOOK_PRIO_DEFAULT); diff --git a/chip/ish/system.c b/chip/ish/system.c deleted file mode 100644 index 280bf57fa4..0000000000 --- a/chip/ish/system.c +++ /dev/null @@ -1,190 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "interrupts.h" -#include "ish_fwst.h" -#include "ish_persistent_data.h" -#include "power_mgt.h" -#include "registers.h" -#include "shared_mem.h" -#include "spi.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -int system_is_reboot_warm(void) -{ - return !(system_get_reset_flags() & - (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_HARD)); -} - -void system_pre_init(void) -{ - ish_fwst_set_fw_status(FWSTS_FW_IS_RUNNING); - if (IS_ENABLED(CONFIG_ISH_CLEAR_FABRIC_ERRORS)) - task_enable_irq(ISH_FABRIC_IRQ); - ish_pm_init(); - ish_persistent_data_init(); -} - -void chip_save_reset_flags(uint32_t flags) -{ - ish_persistent_data.reset_flags = flags; -} - -uint32_t chip_read_reset_flags(void) -{ - return ish_persistent_data.reset_flags; -} - -/* - * Kill the Minute-IA core and don't come back alive. - * - * Used when the watchdog timer exceeds max retries and we want to - * disable ISH completely. - */ -__attribute__((noreturn)) -static void system_halt(void) -{ - cflush(); - - while (1) { - disable_all_interrupts(); - WDT_CONTROL = 0; - CCU_TCG_EN = 1; - __asm__ volatile ( - "cli\n" - "hlt\n"); - } -} - -void system_reset(int flags) -{ - uint32_t save_flags; - - /* - * We can't save any data when we do an ish_mia_reset(). Take - * the quick path out. - */ - if (!IS_ENABLED(CONFIG_ISH_PM_AONTASK) || flags & SYSTEM_RESET_HARD) { - ish_mia_reset(); - __builtin_unreachable(); - } - - system_encode_save_flags(flags, &save_flags); - - if (flags & SYSTEM_RESET_AP_WATCHDOG) { - save_flags |= EC_RESET_FLAG_WATCHDOG; - ish_persistent_data.watchdog_counter += 1; - if (ish_persistent_data.watchdog_counter - >= CONFIG_WATCHDOG_MAX_RETRIES) { - CPRINTS("Halting ISH due to max watchdog resets"); - system_halt(); - } - } - - chip_save_reset_flags(save_flags); - - ish_persistent_data_commit(); - ish_pm_reset(ISH_PM_STATE_RESET); - __builtin_unreachable(); -} - -const char *system_get_chip_vendor(void) -{ - return "intel"; -} - -const char *system_get_chip_name(void) -{ - return "intel"; -} - -static char to_hex(int x) -{ - if (x >= 0 && x <= 9) - return '0' + x; - return 'a' + x - 10; -} - -const char *system_get_chip_revision(void) -{ - static char buf[3]; - uint8_t rev = 0x86; - - buf[0] = to_hex(rev / 16); - buf[1] = to_hex(rev & 0xf); - buf[2] = '\0'; - return buf; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - return EC_ERROR_UNIMPLEMENTED; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - return EC_ERROR_UNIMPLEMENTED; -} - -int system_set_scratchpad(uint32_t value) -{ - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - return 0; -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ -} - -void htimer_interrupt(void) -{ - /* Time to wake up */ -} - -enum system_image_copy_t system_get_shrspi_image_copy(void) -{ - return 0; -} - -uint32_t system_get_lfw_address(void) -{ - return 0; -} - -void system_set_image_copy(enum system_image_copy_t copy) -{ -} - -static __maybe_unused void fabric_isr(void) -{ - /** - * clear fabric error status, otherwise it will wakeup ISH immediately - * when entered low power mode. - * TODO(b:130740646): figure out why this issue happens. - */ - if (FABRIC_AGENT_STATUS & FABRIC_MIA_STATUS_BIT_ERR) - FABRIC_AGENT_STATUS = FABRIC_AGENT_STATUS; -} -#ifdef CONFIG_ISH_CLEAR_FABRIC_ERRORS -DECLARE_IRQ(ISH_FABRIC_IRQ, fabric_isr); -#endif diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h deleted file mode 100644 index 20de1aaf4b..0000000000 --- a/chip/ish/system_state.h +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __SYSTEM_STATE_H -#define __SYSTEM_STATE_H - -#define HECI_FIXED_SYSTEM_STATE_ADDR 13 - -struct ss_subsys_device; - -struct system_state_callbacks { - int (*resume)(struct ss_subsys_device *ss_device); - int (*suspend)(struct ss_subsys_device *ss_device); -}; - -struct ss_subsys_device { - struct system_state_callbacks *cbs; -}; - -/* register system state client */ -int ss_subsys_register_client(struct ss_subsys_device *ss_device); - -/* - * this function is called by HECI layer when there's a message for - * system state subsystem - */ -void heci_handle_system_state_msg(uint8_t *msg, const size_t length); - -#endif /* __SYSTEM_STATE_H */ diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c deleted file mode 100644 index 36b79c747a..0000000000 --- a/chip/ish/system_state_subsys.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "heci_client.h" -#include "registers.h" -#include "system_state.h" -#include "console.h" - -#ifdef SS_SUBSYSTEM_DEBUG -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) -#else -#define CPUTS(outstr) -#define CPRINTS(format, args...) -#define CPRINTF(format, args...) -#endif - - -/* the following "define"s and structures are from host driver - * and they are slightly modified for look&feel purpose. - */ -#define SYSTEM_STATE_SUBSCRIBE 0x1 -#define SYSTEM_STATE_STATUS 0x2 -#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3 -#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4 - -#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ - -/* Cached state of ISH's requested power rails when AP suspends */ -static uint32_t cached_vnn_request; - -struct ss_header { - uint32_t cmd; - uint32_t cmd_status; -} __packed; - -struct ss_query_subscribers { - struct ss_header hdr; -} __packed; - -struct ss_subscribe { - struct ss_header hdr; - uint32_t states; -} __packed; - -struct ss_status { - struct ss_header hdr; - uint32_t supported_states; - uint32_t states_status; -} __packed; - -/* change request from device but host doesn't support it */ -struct ss_state_change_req { - struct ss_header hdr; - uint32_t requested_states; - uint32_t states_status; -} __packed; - -/* - * TODO: For now, every HECI client with valid .suspend or .resume callback is - * automatically registered as client of system state subsystem. - * so MAX_SS_CLIENTS should be HECI_MAX_NUM_OF_CLIENTS. - * if an object wants to get system state event then it can embeds - * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like - * HECI client. - */ -#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS - -struct ss_subsystem_context { - uint32_t registered_state; - - int num_of_ss_client; - struct ss_subsys_device *clients[MAX_SS_CLIENTS]; -}; - -static struct ss_subsystem_context ss_subsys_ctx; - -int ss_subsys_register_client(struct ss_subsys_device *ss_device) -{ - int handle; - - if (ss_subsys_ctx.num_of_ss_client == MAX_SS_CLIENTS) - return -1; - - if (ss_device->cbs->resume || ss_device->cbs->suspend) { - handle = ss_subsys_ctx.num_of_ss_client++; - ss_subsys_ctx.registered_state |= SUSPEND_STATE_BIT; - ss_subsys_ctx.clients[handle] = ss_device; - } else { - return -1; - } - - return handle; -} - -static int ss_subsys_suspend(void) -{ - int i; - - for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) { - if (ss_subsys_ctx.clients[i]->cbs->suspend) - ss_subsys_ctx.clients[i]->cbs->suspend( - ss_subsys_ctx.clients[i]); - } - - /* - * PMU_VNN_REQ is used by ISH FW to assert power requirements of ISH to - * PMC. The system won't enter S0ix if ISH is requesting any power - * rails. Setting a bit to 1 both sets and clears a requested value. - * Cache the value of request power so we can restore it on resume. - */ - if (IS_ENABLED(CHIP_FAMILY_ISH5)) { - cached_vnn_request = PMU_VNN_REQ; - PMU_VNN_REQ = cached_vnn_request; - } - return EC_SUCCESS; -} - -static int ss_subsys_resume(void) -{ - int i; - - /* - * Restore VNN power request from before suspend. - */ - if (IS_ENABLED(CHIP_FAMILY_ISH5) && - cached_vnn_request) { - /* Request all cached power rails that are not already on. */ - PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ; - /* Wait for power request to get acknowledged */ - while (!(PMU_VNN_REQ_ACK & PMU_VNN_REQ_ACK_STATUS)) - continue; - } - - for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) { - if (ss_subsys_ctx.clients[i]->cbs->resume) - ss_subsys_ctx.clients[i]->cbs->resume( - ss_subsys_ctx.clients[i]); - } - - return EC_SUCCESS; -} - -void heci_handle_system_state_msg(uint8_t *msg, const size_t length) -{ - struct ss_header *hdr = (struct ss_header *)msg; - struct ss_subscribe subscribe; - struct ss_status *status; - - switch (hdr->cmd) { - case SYSTEM_STATE_QUERY_SUBSCRIBERS: - subscribe.hdr.cmd = SYSTEM_STATE_SUBSCRIBE; - subscribe.hdr.cmd_status = 0; - subscribe.states = ss_subsys_ctx.registered_state; - - heci_send_fixed_client_msg(HECI_FIXED_SYSTEM_STATE_ADDR, - (uint8_t *)&subscribe, - sizeof(subscribe)); - - break; - case SYSTEM_STATE_STATUS: - status = (struct ss_status *)msg; - if (status->supported_states & SUSPEND_STATE_BIT) { - if (status->states_status & SUSPEND_STATE_BIT) - ss_subsys_suspend(); - else - ss_subsys_resume(); - } - - break; - } -} diff --git a/chip/ish/uart.c b/chip/ish/uart.c deleted file mode 100644 index 93df2c6504..0000000000 --- a/chip/ish/uart.c +++ /dev/null @@ -1,279 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for ISH */ -#include "common.h" -#include "math_util.h" -#include "console.h" -#include "uart_defs.h" -#include "atomic.h" -#include "task.h" -#include "registers.h" -#include "uart.h" -#include "uart_defs.h" -#include "interrupts.h" -#include "system.h" - -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -static const uint32_t baud_conf[][BAUD_TABLE_MAX] = { - {B9600, 9600}, - {B57600, 57600}, - {B115200, 115200}, - {B921600, 921600}, - {B2000000, 2000000}, - {B3000000, 3000000}, - {B3250000, 3250000}, - {B3500000, 3500000}, - {B4000000, 4000000}, - {B19200, 19200}, -}; - -static struct uart_ctx uart_ctx[UART_DEVICES] = { - { - .id = 0, - .base = UART0_BASE, - .input_freq = UART_ISH_INPUT_FREQ, - .addr_interval = UART_ISH_ADDR_INTERVAL, - .uart_state = UART_STATE_CG, - }, - { - .id = 1, - .base = UART1_BASE, - .input_freq = UART_ISH_INPUT_FREQ, - .addr_interval = UART_ISH_ADDR_INTERVAL, - .uart_state = UART_STATE_CG, - }, - { - .id = 2, - .base = UART2_BASE, - .input_freq = UART_ISH_INPUT_FREQ, - .addr_interval = UART_ISH_ADDR_INTERVAL, - .uart_state = UART_STATE_CG, - } -}; - -static int init_done; - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - if (!IS_ENABLED(CONFIG_POLLING_UART)) { - if (IER(ISH_DEBUG_UART) & IER_TDRQ) - return; - - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - - IER(ISH_DEBUG_UART) |= IER_TDRQ; - } -} - -void uart_tx_stop(void) -{ - if (!IS_ENABLED(CONFIG_POLLING_UART)) { - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); - - IER(ISH_DEBUG_UART) &= ~IER_TDRQ; - } -} - -void uart_tx_flush(void) -{ - if (!IS_ENABLED(CONFIG_POLLING_UART)) { - while (!(LSR(ISH_DEBUG_UART) & LSR_TEMT)) - continue; - } -} - -int uart_tx_ready(void) -{ - return LSR(ISH_DEBUG_UART) & LSR_TEMT; -} - -int uart_rx_available(void) -{ - if (IS_ENABLED(CONFIG_POLLING_UART)) - return 0; - - return LSR(ISH_DEBUG_UART) & LSR_DR; -} - -void uart_write_char(char c) -{ - /* Wait till receiver is ready */ - while (!uart_tx_ready()) - continue; - - THR(ISH_DEBUG_UART) = c; -} - -int uart_read_char(void) -{ - return RBR(ISH_DEBUG_UART); -} - -void uart_ec_interrupt(void) -{ - /* Read input FIFO until empty, then fill output FIFO */ - uart_process_input(); - uart_process_output(); -} -#ifndef CONFIG_POLLING_UART -DECLARE_IRQ(ISH_DEBUG_UART_IRQ, uart_ec_interrupt); -#endif - -static int uart_return_baud_rate_by_id(int baud_rate_id) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(baud_conf); i++) { - if (baud_conf[i][BAUD_IDX] == baud_rate_id) - return baud_conf[i][BAUD_SPEED]; - } - - return -1; -} - -static void uart_hw_init(enum UART_PORT id) -{ - uint32_t divisor; /* baud rate divisor */ - uint8_t mcr = 0; - uint8_t fcr = 0; - struct uart_ctx *ctx = &uart_ctx[id]; - uint8_t fraction; - - /* Calculate baud rate divisor */ - divisor = (ctx->input_freq / ctx->baud_rate) >> 4; - if (IS_ENABLED(CONFIG_ISH_DW_UART)) { - /* calculate the fractional part */ - fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4); - } else { - MUL(ctx->id) = (divisor * ctx->baud_rate); - DIV(ctx->id) = (ctx->input_freq / 16); - PS(ctx->id) = 16; - } - - /* Set the DLAB to access the baud rate divisor registers */ - LCR(ctx->id) = LCR_DLAB; - DLL(ctx->id) = (divisor & 0xff); - DLH(ctx->id) = ((divisor >> 8) & 0xff); - if (IS_ENABLED(CONFIG_ISH_DW_UART)) - DLF(ctx->id) = fraction; - - /* 8 data bits, 1 stop bit, no parity, clear DLAB */ - LCR(ctx->id) = LCR_8BIT_CHR; - - if (ctx->client_flags & UART_CONFIG_HW_FLOW_CONTROL) - mcr = MCR_AUTO_FLOW_EN; - - /* needs to be set regardless of flow control */ - if (!IS_ENABLED(CONFIG_ISH_DW_UART)) - mcr |= MCR_INTR_ENABLE; - - mcr |= (MCR_RTS | MCR_DTR); - MCR(ctx->id) = mcr; - - if (IS_ENABLED(CONFIG_ISH_DW_UART)) - fcr = FCR_TET_EMPTY | FCR_RT_1CHAR; - else - fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1; - - /* configure FIFOs */ - FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE - | FCR_RESET_RX | FCR_RESET_TX); - - if (!IS_ENABLED(CONFIG_ISH_DW_UART)) - /* enable UART unit */ - ABR(ctx->id) = ABR_UUE; - - /* clear the port */ - RBR(ctx->id); - - if (IS_ENABLED(CONFIG_POLLING_UART)) - IER(ctx->id) = 0x00; - else - IER(ctx->id) = IER_RECV; -} - -static void uart_stop_hw(enum UART_PORT id) -{ - int i; - uint32_t fifo_len; - - if (!IS_ENABLED(CONFIG_ISH_DW_UART)) { - /* Manually clearing the fifo from possible noise. - * Entering D0i3 when fifo is not cleared may result in a hang. - */ - fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS; - - for (i = 0; i < fifo_len; i++) - (void)RBR(id); - } - - /* No interrupts are enabled */ - IER(id) = 0; - MCR(id) = 0; - - /* Clear and disable FIFOs */ - FCR(id) = (FCR_RESET_RX | FCR_RESET_TX); - - if (!IS_ENABLED(CONFIG_ISH_DW_UART)) - /* Disable uart unit */ - ABR(id) = 0; -} - -static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags) -{ - if ((uart_ctx[id].base == 0) || (id >= UART_DEVICES)) - return UART_ERROR; - - if (!bool_compare_and_swap_u32(&uart_ctx[id].is_open, 0, 1)) - return UART_BUSY; - - uart_ctx[id].baud_rate = uart_return_baud_rate_by_id(baud_rate_id); - - if ((uart_ctx[id].baud_rate == -1) || (uart_ctx[id].baud_rate == 0)) - uart_ctx[id].baud_rate = UART_DEFAULT_BAUD_RATE; - - uart_ctx[id].client_flags = flags; - - atomic_and(&uart_ctx[id].uart_state, ~UART_STATE_CG); - uart_hw_init(id); - - return EC_SUCCESS; -} - -static void uart_drv_init(void) -{ - int i; - - /* Disable UART */ - for (i = 0; i < UART_DEVICES; i++) - uart_stop_hw(i); - - if (!IS_ENABLED(CONFIG_ISH_DW_UART)) - /* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit - * to allow PMU to clock gate ISH - */ - HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN - | GIEN_UART1_EN | GIEN_PWR_MGMT); - - task_enable_irq(ISH_DEBUG_UART_IRQ); -} - -void uart_init(void) -{ - uart_drv_init(); - uart_client_init(ISH_DEBUG_UART, B115200, 0); - init_done = 1; -} diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h deleted file mode 100644 index b573ef7710..0000000000 --- a/chip/ish/uart_defs.h +++ /dev/null @@ -1,364 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for ISH */ - -#ifndef __CROS_EC_UART_DEFS_H_ -#define __CROS_EC_UART_DEFS_H_ - -#include <stdint.h> -#include <stddef.h> - -#define UART_ERROR -1 -#define UART_BUSY -2 -#ifdef CHIP_VARIANT_ISH5P4 -#define UART0_OFFS (0x00) -#define UART1_OFFS (0x2000) -#define UART2_OFFS (0x4000) -#else -#define UART0_OFFS (0x80) -#define UART1_OFFS (0x100) -#define UART2_OFFS (0x180) -#endif - -#define HSU_BASE ISH_UART_BASE -#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) -#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) -#define UART2_BASE (ISH_UART_BASE + UART2_OFFS) - -#define UART_REG(size, name, n) \ - REG##size(uart_ctx[n].base + \ - UART_OFFSET_##name * uart_ctx[n].addr_interval) - -/* Register accesses */ -#define LSR(n) UART_REG(8, LSR, n) -#define THR(n) UART_REG(8, THR, n) -#define RBR(n) UART_REG(8, RBR, n) -#define DLL(n) UART_REG(8, DLL, n) -#define DLH(n) UART_REG(8, DLH, n) -#define IER(n) UART_REG(8, IER, n) -#define IIR(n) UART_REG(8, IIR, n) -#define FCR(n) UART_REG(8, FCR, n) -#define LCR(n) UART_REG(8, LCR, n) -#define MCR(n) UART_REG(8, MCR, n) -#define MSR(n) UART_REG(8, MSR, n) -#define DLF(n) UART_REG(8, DLF, n) -#define FOR(n) UART_REG(32, FOR, n) -#define ABR(n) UART_REG(32, ABR, n) -#define PS(n) UART_REG(32, PS, n) -#define MUL(n) UART_REG(32, MUL, n) -#define DIV(n) UART_REG(32, DIV, n) - -#ifdef CONFIG_ISH_DW_UART -/* - * RBR: Receive Buffer register (BLAB bit = 0) - */ -#define UART_OFFSET_RBR (0x00) - -/* - * THR: Transmit Holding register (BLAB bit = 0) - */ -#define UART_OFFSET_THR (0x00) - -/* - * DLL: Divisor Latch Reg. low byte (BLAB bit = 1) - * baud rate = (serial clock freq) / (16 * divisor) - */ -#define UART_OFFSET_DLL (0x00) - -/* - * DLH: Divisor Latch Reg. high byte (BLAB bit = 1) - */ -#define UART_OFFSET_DLH (0x04) - -/* - * IER: Interrupt Enable register (BLAB bit = 0) - */ -#define UART_OFFSET_IER (0x04) - -#define IER_RECV (0x01) /* Receive Data Available */ -#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ -#define IER_LINE_STAT (0x04) /* Receiver Line Status */ -#define IER_MODEM (0x08) /* Modem Status */ -#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ - -/* - * IIR: Interrupt ID register - */ -#define UART_OFFSET_IIR (0x08) - -#define IIR_MODEM (0x00) /* Prio: 4 */ -#define IIR_NO_INTR (0x01) -#define IIR_THRE (0x02) /* Prio: 3 */ -#define IIR_RECV_DATA (0x04) /* Prio: 2 */ -#define IIR_LINE_STAT (0x06) /* Prio: 1 */ -#define IIR_BUSY (0x07) /* Prio: 5 */ -#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ -#define IIR_SOURCE (0x0F) - - -/* - * FCR: FIFO Control register (FIFO_MODE != NONE) - */ -#define UART_OFFSET_FCR (0x08) - -#define FIFO_SIZE 64 -#define FCR_FIFO_ENABLE (0x01) -#define FCR_RESET_RX (0x02) -#define FCR_RESET_TX (0x04) -#define FCR_DMA_MODE (0x08) - -/* - * LCR: Line Control register - */ -#define UART_OFFSET_LCR (0x0c) - -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) - -#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ -#define LCR_PEN BIT(3) /* Parity Enable */ -#define LCR_EPS BIT(4) /* Even Parity Select */ -#define LCR_SP BIT(5) /* Stick Parity */ -#define LCR_BC BIT(6) /* Break Control */ -#define LCR_DLAB BIT(7) /* Divisor Latch Access */ - -/* - * MCR: Modem Control register - */ -#define UART_OFFSET_MCR (0x10) -#define MCR_DTR (0x1) /* Data terminal ready */ -#define MCR_RTS (0x2) /* Request to send */ -#define MCR_LOOP (0x10) /* LoopBack bit*/ - -#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ -#define MCR_AUTO_FLOW_EN (0x20) - -/* - * LSR: Line Status register - */ -#define UART_OFFSET_LSR (0x14) - -#define LSR_DR (0x01) /* Data Ready */ -#define LSR_OE (0x02) /* Overrun error */ -#define LSR_PE (0x04) /* Parity error */ -#define LSR_FE (0x08) /* Framing error */ -#define LSR_BI (0x10) /* Breaking interrupt */ -#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ -#define LSR_TEMT (0x40) /* Transmitter empty */ - -/* - * MSR: Modem Status register - */ -#define UART_OFFSET_MSR (0x18) - -#define MSR_CTS BIT(4) /* Clear To Send signal */ - -/* - * TFL: Transmit FIFO Level - */ -#define UART_OFFSET_TFL (0x80) - -/* - * RFL: Receive FIFO Level - */ -#define UART_OFFSET_RFL (0x84) -#else -/* RBR: Receive Buffer register (BLAB bit = 0) */ -#define UART_OFFSET_RBR (0) -/* THR: Transmit Holding register (BLAB bit = 0) */ -#define UART_OFFSET_THR (0) -/* IER: Interrupt Enable register (BLAB bit = 0) */ -#define UART_OFFSET_IER (1) - -/* FCR: FIFO Control register */ -#define UART_OFFSET_FCR (2) -#define FCR_FIFO_ENABLE BIT(0) -#define FCR_RESET_RX BIT(1) -#define FCR_RESET_TX BIT(2) - -/* LCR: Line Control register */ -#define UART_OFFSET_LCR (3) -#define LCR_DLAB (0x80) -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) -#define LCR_SB (0x40) /* Set Break */ - -/* MCR: Modem Control register */ -#define UART_OFFSET_MCR (4) -#define MCR_DTR BIT(0) -#define MCR_RTS BIT(1) -#define MCR_LOO BIT(4) -#define MCR_INTR_ENABLE BIT(3) -#define MCR_AUTO_FLOW_EN BIT(5) - -/* LSR: Line Status register */ -#define UART_OFFSET_LSR (5) -#define LSR_DR BIT(0) /* Data Ready */ -#define LSR_OE BIT(1) /* Overrun error */ -#define LSR_PE BIT(2) /* Parity error */ -#define LSR_FE BIT(3) /* Framing error */ -#define LSR_BI BIT(4) /* Breaking interrupt */ -#define LSR_THR_EMPTY BIT(5) /* Non FIFO mode: Transmit holding - * register empty - */ -#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */ -#define LSR_TEMT BIT(6) /* Transmitter empty */ - -#define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7)) - -#define IER_RECV BIT(0) -#define IER_TDRQ BIT(1) -#define IER_LINE_STAT BIT(2) - -#define UART_OFFSET_IIR (2) -/* MSR: Modem Status register */ -#define UART_OFFSET_MSR (6) - -/* DLL: Divisor Latch Reg. low byte (BLAB bit = 1) */ -#define UART_OFFSET_DLL (0) - -/* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ -#define UART_OFFSET_DLH (1) -#endif - -/* - * DLF: Divisor Latch Fraction Register - */ -#define UART_OFFSET_DLF (0xC0) - -/* FOR: Fifo O Register (ISH only) */ -#define UART_OFFSET_FOR (0x20) -#define FOR_OCCUPANCY_OFFS 0 -#define FOR_OCCUPANCY_MASK 0x7F - -/* ABR: Auto-Baud Control Register (ISH only) */ -#define UART_OFFSET_ABR (0x24) -#define ABR_UUE BIT(4) - -/* Pre-Scalar Register (ISH only) */ -#define UART_OFFSET_PS (0x30) - -/* DDS registers (ISH only) */ -#define UART_OFFSET_MUL (0x34) -#define UART_OFFSET_DIV (0x38) - -#define FCR_FIFO_SIZE_16 (0x00) -#define FCR_FIFO_SIZE_64 (0x20) -#define FCR_ITL_FIFO_64_BYTES_1 (0x00) - -/* tx empty trigger(TET) */ -#define FCR_TET_EMPTY (0x00) -#define FCR_TET_2CHAR (0x10) -#define FCR_TET_QTR_FULL (0x20) -#define FCR_TET_HALF_FULL (0x30) - -/* receive trigger(RT) */ -#define FCR_RT_1CHAR (0x00) -#define FCR_RT_QTR_FULL (0x40) -#define FCR_RT_HALF_FULL (0x80) -#define FCR_RT_2LESS_FULL (0xc0) - -/* G_IEN: Global Interrupt Enable (ISH only) */ -#define HSU_REG_GIEN REG32(HSU_BASE + 0x0) -#define HSU_REG_GIST REG32(HSU_BASE + 0x4) - -#define GIEN_PWR_MGMT BIT(24) -#define GIEN_DMA_EN BIT(5) -#define GIEN_UART2_EN BIT(2) -#define GIEN_UART1_EN BIT(1) -#define GIEN_UART0_EN BIT(0) -#define GIST_DMA_EN BIT(5) -#define GIST_UART2_EN BIT(2) -#define GIST_UART1_EN BIT(1) -#define GIST_UART0_EN BIT(0) -#define GIST_UARTx_EN (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN) - -/* UART config flag, send to sc_io_control if the current UART line has HW - * flow control lines connected. - */ -#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) - -/* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is - * raised only when the rx buffer is completely full. Otherwise, the event - * is raised after a timeout is received on the UART line, - * and all data received until now is provided. - */ -#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) - -/* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted - * is raised when all rx buffers that were added are full. Otherwise, no - * event is raised. - */ -#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) - -#define UART_INT_DEVICES 3 -#define UART_EXT_DEVICES 8 -#define UART_DEVICES UART_INT_DEVICES -#define UART_ISH_ADDR_INTERVAL 1 - -#define B9600 0x0000d -#define B57600 0x00000018 -#define B115200 0x00000011 -#define B921600 0x00000012 -#define B2000000 0x00000013 -#define B3000000 0x00000014 -#define B3250000 0x00000015 -#define B3500000 0x00000016 -#define B4000000 0x00000017 -#define B19200 0x0000e -#define B38400 0x0000f - -/* KHZ, MHZ */ -#define KHZ(x) ((x) * 1000) -#define MHZ(x) (KHZ(x) * 1000) -#if defined(CHIP_VARIANT_ISH5P4) -/* Change to 100MHZ in real silicon platform */ -#define UART_ISH_INPUT_FREQ MHZ(100) -#elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define UART_ISH_INPUT_FREQ MHZ(120) -#elif defined(CHIP_FAMILY_ISH4) -#define UART_ISH_INPUT_FREQ MHZ(100) -#endif -#define UART_DEFAULT_BAUD_RATE 115200 -#define UART_STATE_CG BIT(UART_OP_CG) - -enum UART_PORT { - UART_PORT_0, - UART_PORT_1, - UART_PORT_MAX -}; - -enum UART_OP { - UART_OP_READ, - UART_OP_WRITE, - UART_OP_CG, - UART_OP_MAX -}; - -enum { - BAUD_IDX, - BAUD_SPEED, - BAUD_TABLE_MAX -}; - -struct uart_ctx { - uint32_t id; - uint32_t base; - uint32_t addr_interval; - uint32_t uart_state; - uint32_t is_open; - uint32_t baud_rate; - uint32_t input_freq; - uint32_t client_flags; -}; - -#endif /* _CROS_EC_UART_DEFS_H_ */ diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py deleted file mode 100755 index 71a63dd42f..0000000000 --- a/chip/ish/util/pack_ec.py +++ /dev/null @@ -1,109 +0,0 @@ -#!/usr/bin/env python2 -# -*- coding: utf-8 -*-" - -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# A script to pack EC binary with manifest header according to -# Based on 607297_Host_ISH_Firmware_Load_Chrome_OS_SAS_Rev0p5.pdf, -# https://chrome-internal.googlesource.com/chromeos/intel-ish/+/refs/heads/upstream/master/modules/api/ish_api/include/loader_common.h#211, -# and b/124788278#comment10 - -"""Script to pack EC binary with manifest header. - -Package ecos main FW binary (kernel) and AON task binary into final EC binary -image with a manifest header, ISH shim loader will parse this header and load -each binaries into right memory location. -""" - -from __future__ import print_function -import argparse -import struct - -MANIFEST_ENTRY_SIZE = 0x80 -HEADER_SIZE = 0x1000 -PAGE_SIZE = 0x1000 - -def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument("-k", "--kernel", - help="EC kernel binary to pack, \ - usually ec.RW.bin or ec.RW.flat.", - required=True) - parser.add_argument("--kernel-size", type=int, - help="Size of EC kernel image", - required=True) - parser.add_argument("-a", "--aon", - help="EC aontask binary to pack, \ - usually ish_aontask.bin.", - required=False) - parser.add_argument("--aon-size", type=int, - help="Size of EC aontask image", - required=False) - parser.add_argument("-o", "--output", - help="Output flash binary file") - - return parser.parse_args() - -def gen_manifest(ext_id, comp_app_name, code_offset, module_size): - """Returns a binary blob that represents a manifest entry""" - m = bytearray(MANIFEST_ENTRY_SIZE) - - # 4 bytes of ASCII encode ID (little endian) - struct.pack_into('<4s', m, 0, ext_id) - # 8 bytes of ASCII encode ID (little endian) - struct.pack_into('<8s', m, 32, comp_app_name) - # 4 bytes of code offset (little endian) - struct.pack_into('<I', m, 96, code_offset) - # 2 bytes of module in page size increments (little endian) - struct.pack_into('<H', m, 100, module_size) - - return m - -def roundup_page(size): - """Returns roundup-ed page size from size of bytes""" - return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0) - -def main(): - args = parseargs() - print(" Packing EC image file for ISH") - - with open(args.output, 'wb') as f: - print(" kernel binary size: %i" % args.kernel_size) - kern_rdup_pg_size = roundup_page(args.kernel_size) - # Add manifest for main ISH binary - f.write(gen_manifest('ISHM', 'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size)) - - if args.aon is not None: - print(" AON binary size: %i" % args.aon_size) - aon_rdup_pg_size = roundup_page(args.aon_size) - # Add manifest for aontask binary - f.write(gen_manifest('ISHM', 'AON_TASK', - (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE - - MANIFEST_ENTRY_SIZE), aon_rdup_pg_size)) - - # Add manifest that signals end of manifests - f.write(gen_manifest('ISHE', '', 0, 0)) - - # Pad the remaining HEADER with 0s - if args.aon is not None: - f.write('\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3))) - else: - f.write('\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2))) - - # Append original kernel image - with open(args.kernel, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write('\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size)) - - if args.aon is not None: - # Append original aon image - with open(args.aon, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write('\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size)) - -if __name__ == '__main__': - main() diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c deleted file mode 100644 index bf78f49312..0000000000 --- a/chip/ish/watchdog.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Watchdog Timer - * - * In ISH, there is a watchdog timer available from the hardware. It is - * controlled by a few registers: - * - * - WDT_CONTROL (consists of enable bit, T1, and T2 values): When T1 - * reaches 0, a warning is fired. After T2 then reaches 0, the system - * will reset. - * - WDT_RELOAD: Pet the watchdog by setting to 1 - * - WDT_VALUES: Gives software access to T1 and T2 if needed - * - * For ISH implementation, we wish to reset only the ISH. Waiting until - * T2 expires will kill the whole system. The functionality of T2 is - * ignored, and we simply call system_reset when T1 expires. T2 will - * only be used if the system cannot reset when T1 expires. - */ - -#include "common.h" -#include "ec_commands.h" -#include "hooks.h" -#include "ish_persistent_data.h" -#include "task.h" -#include "registers.h" -#include "system.h" -#include "watchdog.h" - -/* Units are hundreds of milliseconds */ -#define WDT_T1_PERIOD (100) /* 10 seconds */ -#define WDT_T2_PERIOD (10) /* 1 second */ - -int watchdog_init(void) -{ - /* - * Put reset counter back at zero if last reset was not caused - * by watchdog - */ - if ((system_get_reset_flags() & EC_RESET_FLAG_WATCHDOG) == 0) - ish_persistent_data.watchdog_counter = 0; - - /* Initialize WDT clock divider */ - CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */ - - /* Enable the watchdog timer and set initial T1/T2 values */ - WDT_CONTROL = WDT_CONTROL_ENABLE_BIT - | (WDT_T2_PERIOD << 8) - | WDT_T1_PERIOD; - - task_enable_irq(ISH_WDT_IRQ); - - return EC_SUCCESS; -} - -void watchdog_reload(void) -{ - /* - * ISH Supplemental Registers Info, 1.2.6.2: - * "When firmware writes a 1 to this bit, hardware reloads - * the values in WDT_T1 and WDT_T2..." - */ - WDT_RELOAD = 1; -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c deleted file mode 100644 index 287a3bd5ba..0000000000 --- a/chip/it83xx/adc.c +++ /dev/null @@ -1,235 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* IT83xx ADC module for Chrome EC */ - -#include "adc.h" -#include "adc_chip.h" -#include "clock.h" -#include "console.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Global variables */ -static struct mutex adc_lock; -static int adc_init_done; -static volatile task_id_t task_waiting; - -/* Data structure of ADC channel control registers. */ -const struct adc_ctrl_t adc_ctrl_regs[] = { - {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL, - &IT83XX_GPIO_GPCRI0}, - {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL, - &IT83XX_GPIO_GPCRI1}, - {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL, - &IT83XX_GPIO_GPCRI2}, - {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL, - &IT83XX_GPIO_GPCRI3}, - {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL, - &IT83XX_GPIO_GPCRI4}, - {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL, - &IT83XX_GPIO_GPCRI5}, - {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL, - &IT83XX_GPIO_GPCRI6}, - {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL, - &IT83XX_GPIO_GPCRI7}, - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, - &IT83XX_GPIO_GPCRL0}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, - &IT83XX_GPIO_GPCRL1}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, - &IT83XX_GPIO_GPCRL2}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, - &IT83XX_GPIO_GPCRL3}, -}; -BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); - -static void adc_enable_channel(int ch) -{ - if (ch < CHIP_ADC_CH4) - /* - * for channel 0, 1, 2, and 3 - * bit4 ~ bit0 : indicates voltage channel[x] - * input is selected for measurement (enable) - * bit5 : data valid interrupt of adc. - * bit7 : W/C data valid flag - */ - *adc_ctrl_regs[ch].adc_ctrl = 0xa0 + ch; - else - /* - * for channel 4 ~ 7 and 13 ~ 16. - * bit4 : voltage channel enable (ch 4~7 and 13 ~ 16) - * bit5 : data valid interrupt of adc. - * bit7 : W/C data valid flag - */ - *adc_ctrl_regs[ch].adc_ctrl = 0xb0; - - task_clear_pending_irq(IT83XX_IRQ_ADC); - task_enable_irq(IT83XX_IRQ_ADC); - - /* bit 0 : adc module enable */ - IT83XX_ADC_ADCCFG |= 0x01; -} - -static void adc_disable_channel(int ch) -{ - if (ch < CHIP_ADC_CH4) - /* - * for channel 0, 1, 2, and 3 - * bit4 ~ bit0 : indicates voltage channel[x] - * input is selected for measurement (disable) - * bit 7 : W/C data valid flag - */ - *adc_ctrl_regs[ch].adc_ctrl = 0x9F; - else - /* - * for channel 4 ~ 7 and 13 ~ 16. - * bit4 : voltage channel disable (ch 4~7 and 13 ~ 16) - * bit7 : W/C data valid flag - */ - *adc_ctrl_regs[ch].adc_ctrl = 0x80; - - /* bit 0 : adc module disable */ - IT83XX_ADC_ADCCFG &= ~0x01; - - task_disable_irq(IT83XX_IRQ_ADC); -} - -static int adc_data_valid(enum chip_adc_channel adc_ch) -{ - return (adc_ch <= CHIP_ADC_CH7) ? - (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) : - (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13))); -} - -int adc_read_channel(enum adc_channel ch) -{ - uint32_t events; - /* voltage 0 ~ 3v = adc data register raw data 0 ~ 3FFh (10-bit ) */ - uint16_t adc_raw_data; - int valid = 0; - int adc_ch, mv; - - if (!adc_init_done) - return ADC_READ_ERROR; - - mutex_lock(&adc_lock); - - task_waiting = task_get_current(); - adc_ch = adc_channels[ch].channel; - adc_enable_channel(adc_ch); - /* Wait for interrupt */ - events = task_wait_event_mask(TASK_EVENT_ADC_DONE, ADC_TIMEOUT_US); - task_waiting = TASK_ID_INVALID; - - if (events & TASK_EVENT_ADC_DONE) { - /* data valid of adc channel[x] */ - if (adc_data_valid(adc_ch)) { - /* read adc raw data msb and lsb */ - adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) + - *adc_ctrl_regs[adc_ch].adc_datl; - - /* W/C data valid flag */ - if (adc_ch <= CHIP_ADC_CH7) - IT83XX_ADC_ADCDVSTS = BIT(adc_ch); - else - IT83XX_ADC_ADCDVSTS2 = - (1 << (adc_ch - CHIP_ADC_CH13)); - - mv = adc_raw_data * adc_channels[ch].factor_mul / - adc_channels[ch].factor_div + - adc_channels[ch].shift; - valid = 1; - } - } - adc_disable_channel(adc_ch); - - mutex_unlock(&adc_lock); - - return valid ? mv : ADC_READ_ERROR; -} - -void adc_interrupt(void) -{ - /* - * Clear the interrupt status. - * - * NOTE: - * The ADC interrupt pending flag won't be cleared unless - * we W/C data valid flag of ADC module as well. - * (If interrupt type setting is high-level triggered) - */ - task_clear_pending_irq(IT83XX_IRQ_ADC); - /* - * We disable ADC interrupt here, because current setting of - * interrupt type is high-level triggered. - * The interrupt will be triggered again and again until - * we W/C data valid flag if we don't disable it. - */ - task_disable_irq(IT83XX_IRQ_ADC); - /* Wake up the task which was waiting for the interrupt */ - if (task_waiting != TASK_ID_INVALID) - task_set_event(task_waiting, TASK_EVENT_ADC_DONE, 0); -} - -/* - * ADC analog accuracy initialization (only once after VSTBY power on) - * - * Write 1 to this bit and write 0 to this bit immediately once and - * only once during the firmware initialization and do not write 1 again - * after initialization since IT83xx takes much power consumption - * if this bit is set as 1 - */ -static void adc_accuracy_initialization(void) -{ - /* bit3 : start adc accuracy initialization */ - IT83XX_ADC_ADCSTS |= 0x08; - /* short delay for adc accuracy initialization */ - IT83XX_GCTRL_WNCKR = 0; - /* bit3 : stop adc accuracy initialization */ - IT83XX_ADC_ADCSTS &= ~0x08; -} - -/* ADC module Initialization */ -static void adc_init(void) -{ - int index; - int ch; - - /* ADC analog accuracy initialization */ - adc_accuracy_initialization(); - - for (index = 0; index < ADC_CH_COUNT; index++) { - ch = adc_channels[index].channel; - - /* enable adc channel[x] function pin */ - *adc_ctrl_regs[ch].adc_pin_ctrl = 0x00; - } - /* - * bit7@ADCSTS : ADCCTS1 = 0 - * bit5@ADCCFG : ADCCTS0 = 0 - * bit[5-0]@ADCCTL : SCLKDIV - * The ADC channel conversion time is 30.8*(SCLKDIV+1) us. - * (Current setting is 61.6us) - * - * NOTE: A sample time delay (60us) also need to be included in - * conversion time, so the final result is ~= 121.6us. - */ - IT83XX_ADC_ADCSTS &= ~BIT(7); - IT83XX_ADC_ADCCFG &= ~BIT(5); - IT83XX_ADC_ADCCTL = 1; - - task_waiting = TASK_ID_INVALID; - /* disable adc interrupt */ - task_disable_irq(IT83XX_IRQ_ADC); - - adc_init_done = 1; -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h deleted file mode 100644 index c43a64c132..0000000000 --- a/chip/it83xx/adc_chip.h +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* IT83xx ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -#include "common.h" - -/* - * Maximum time we allow for an ADC conversion. - * NOTE: - * This setting must be less than "SLEEP_SET_HTIMER_DELAY_USEC" in clock.c - * or adding a sleep mask to prevent going in to deep sleep while ADC - * converting. - */ -#define ADC_TIMEOUT_US 248 - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 1023 -#define ADC_MAX_MVOLT 3000 - -/* List of ADC channels. */ -enum chip_adc_channel { - CHIP_ADC_CH0 = 0, - CHIP_ADC_CH1, - CHIP_ADC_CH2, - CHIP_ADC_CH3, - CHIP_ADC_CH4, - CHIP_ADC_CH5, - CHIP_ADC_CH6, - CHIP_ADC_CH7, - CHIP_ADC_CH13, - CHIP_ADC_CH14, - CHIP_ADC_CH15, - CHIP_ADC_CH16, - CHIP_ADC_COUNT, -}; - -/* Data structure to define ADC channel control registers. */ -struct adc_ctrl_t { - volatile uint8_t *adc_ctrl; - volatile uint8_t *adc_datm; - volatile uint8_t *adc_datl; - volatile uint8_t *adc_pin_ctrl; -}; - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - enum chip_adc_channel channel; -}; - -/* - * Boards must provide this list of ADC channel definitions. This must match - * the enum adc_channel list provided by the board. - */ -extern const struct adc_t adc_channels[]; - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk deleted file mode 100644 index 657dedf97b..0000000000 --- a/chip/it83xx/build.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# IT83xx chip specific files build -# - -# IT8xxx1 and IT83xx are Andes N8 core. -# IT8xxx2 is RISC-V core. -ifeq ($(CHIP_FAMILY), it8xxx2) -CORE:=riscv-rv32i -else -CORE:=nds32 -endif - -# Required chip modules -chip-y=hwtimer.o uart.o gpio.o system.o clock.o irq.o intc.o - -# Optional chip modules -chip-$(CONFIG_WATCHDOG)+=watchdog.o -chip-$(CONFIG_FANS)+=fan.o pwm.o -chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o -# IT8xxx2 series use the FPU instruction set of RISC-V (single-precision only). -ifneq ($(CHIP_FAMILY), it8xxx2) -chip-$(CONFIG_FPU)+=it83xx_fpu.o -endif -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_ADC)+=adc.o -chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o -chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o -chip-$(CONFIG_SPI_MASTER)+=spi_master.o -chip-$(CONFIG_PECI)+=peci.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif -chip-$(CONFIG_I2C_MASTER)+=i2c.o -chip-$(CONFIG_I2C_SLAVE)+=i2c_slave.o diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c deleted file mode 100644 index 468037f0e9..0000000000 --- a/chip/it83xx/clock.c +++ /dev/null @@ -1,610 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "adc_chip.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "hwtimer.h" -#include "hwtimer_chip.h" -#include "intc.h" -#include "irq_chip.h" -#include "it83xx_pd.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" - -/* Console output macros. */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -#ifdef CONFIG_LOW_POWER_IDLE -#define SLEEP_SET_HTIMER_DELAY_USEC 250 -#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2) - -#ifdef CONFIG_ADC -BUILD_ASSERT(ADC_TIMEOUT_US < SLEEP_SET_HTIMER_DELAY_USEC); -#endif - -static timestamp_t sleep_mode_t0; -static timestamp_t sleep_mode_t1; -static int idle_doze_cnt; -static int idle_sleep_cnt; -static uint64_t total_idle_sleep_time_us; -static uint32_t ec_sleep; -/* - * Fixed amount of time to keep the console in use flag true after boot in - * order to give a permanent window in which the heavy sleep mode is not used. - */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) -static int console_in_use_timeout_sec = 5; -static timestamp_t console_expire_time; - -/* clock source is 32.768KHz */ -#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768) -#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1) -#endif /*CONFIG_LOW_POWER_IDLE */ - -static int freq; - -struct clock_gate_ctrl { - volatile uint8_t *reg; - uint8_t mask; -}; - -static void clock_module_disable(void) -{ - /* bit0: FSPI interface tri-state */ - IT83XX_SMFI_FLHCTRL3R |= BIT(0); - /* bit7: USB pad power-on disable */ - IT83XX_GCTRL_PMER2 &= ~BIT(7); - /* bit7: USB debug disable */ - IT83XX_GCTRL_MCCR &= ~BIT(7); - clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0); - clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB | - CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE | - CGC_OFFSET_SMBF), 0, 0); - clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI | - CGC_OFFSET_USB), 0, 0); -} - -enum pll_freq_idx { - PLL_24_MHZ = 1, - PLL_48_MHZ = 2, - PLL_96_MHZ = 4, -}; - -static const uint8_t pll_to_idx[8] = { - 0, - 0, - PLL_24_MHZ, - 0, - PLL_48_MHZ, - 0, - 0, - PLL_96_MHZ -}; - -struct clock_pll_t { - int pll_freq; - uint8_t pll_setting; - uint8_t div_fnd; - uint8_t div_uart; - uint8_t div_usb; - uint8_t div_smb; - uint8_t div_sspi; - uint8_t div_ec; - uint8_t div_jtag; - uint8_t div_pwm; - uint8_t div_usbpd; -}; - -const struct clock_pll_t clock_pll_ctrl[] = { - /* - * UART: 24MHz - * SMB: 24MHz - * EC: 8MHz - * JTAG: 24MHz - * USBPD: 8MHz - * USB: 48MHz(no support if PLL=24MHz) - * SSPI: 48MHz(24MHz if PLL=24MHz) - */ - /* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */ - [PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2}, -#ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ - /* PLL:48MHz, MCU:48MHz, Fnd:48MHz */ - [PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5}, - /* PLL:96MHz, MCU:96MHz, Fnd:48MHz */ - [PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb}, -#else - /* PLL:48MHz, MCU:48MHz, Fnd:24MHz */ - [PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5}, - /* PLL:96MHz, MCU:96MHz, Fnd:32MHz */ - [PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb}, -#endif -}; - -static uint8_t pll_div_fnd; -static uint8_t pll_div_ec; -static uint8_t pll_div_jtag; -static uint8_t pll_setting; - -void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode) -{ - IT83XX_ECPM_PLLCTRL = mode; - /* for deep doze / sleep mode */ - IT83XX_ECPM_PLLCTRL = mode; - /* - * barrier: ensure low power mode setting is taken into control - * register before standby instruction. - */ - data_serialization_barrier(); -} - -void __ram_code clock_pll_changed(void) -{ - IT83XX_GCTRL_SSCR &= ~BIT(0); - /* - * Update PLL settings. - * Writing data to this register doesn't change the - * PLL frequency immediately until the status is changed - * into wakeup from the sleep mode. - * The following code is intended to make the system - * enter sleep mode, and set up a HW timer to wakeup EC to - * complete PLL update. - */ - IT83XX_ECPM_PLLFREQR = pll_setting; - /* Pre-set FND clock frequency = PLL / 3 */ - IT83XX_ECPM_SCDCR0 = (2 << 4); - /* JTAG and EC */ - IT83XX_ECPM_SCDCR3 = (pll_div_jtag << 4) | pll_div_ec; - /* EC sleep after standby instruction */ - clock_ec_pll_ctrl(EC_PLL_SLEEP); - if (IS_ENABLED(CHIP_CORE_NDS32)) { - /* Global interrupt enable */ - asm volatile ("setgie.e"); - /* EC sleep */ - asm("standby wake_grant"); - /* Global interrupt disable */ - asm volatile ("setgie.d"); - } else if (IS_ENABLED(CHIP_CORE_RISCV)) { - /* Global interrupt enable */ - asm volatile ("csrsi mstatus, 0x8"); - /* EC sleep */ - asm("wfi"); - /* Global interrupt disable */ - asm volatile ("csrci mstatus, 0x8"); - } - /* New FND clock frequency */ - IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4); - /* EC doze after standby instruction */ - clock_ec_pll_ctrl(EC_PLL_DOZE); -} - -/* NOTE: Don't use this function in other place. */ -static void clock_set_pll(enum pll_freq_idx idx) -{ - int pll; - - pll_div_fnd = clock_pll_ctrl[idx].div_fnd; - pll_div_ec = clock_pll_ctrl[idx].div_ec; - pll_div_jtag = clock_pll_ctrl[idx].div_jtag; - pll_setting = clock_pll_ctrl[idx].pll_setting; - - /* Update PLL settings or not */ - if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) || - ((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) || - ((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) { - /* Enable hw timer to wakeup EC from the sleep mode */ - ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, - 1, 1, 5, 1, 0); - task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq); -#ifdef CONFIG_HOSTCMD_ESPI - /* - * Workaround for (b:70537592): - * We have to set chip select pin as input mode in order to - * change PLL. - */ - IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7); -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* - * On DX version, we have to disable eSPI pad before changing - * PLL sequence or sequence will fail if CS# pin is low. - */ - espi_enable_pad(0); -#endif -#endif - /* Update PLL settings. */ - clock_pll_changed(); -#ifdef CONFIG_HOSTCMD_ESPI -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED - /* Enable eSPI pad after changing PLL sequence. */ - espi_enable_pad(1); -#endif - /* (b:70537592) Change back to ESPI CS# function. */ - IT83XX_GPIO_GPCRM5 &= ~0xc0; -#endif - } - - /* Get new/current setting of PLL frequency */ - pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf]; - /* USB and UART */ - IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) | - clock_pll_ctrl[pll].div_uart; - /* SSPI and SMB */ - IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) | - clock_pll_ctrl[pll].div_smb; - /* USBPD and PWM */ - IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) | - clock_pll_ctrl[pll].div_pwm; - /* Current PLL frequency */ - freq = clock_pll_ctrl[pll].pll_freq; -} - -void clock_init(void) -{ - uint32_t image_type = (uint32_t)clock_init; - - /* To change interrupt vector base if at RW image */ - if (image_type > CONFIG_RW_MEM_OFF) - /* Interrupt Vector Table Base Address, in 64k Byte unit */ - IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF; - -#if (PLL_CLOCK == 24000000) || \ - (PLL_CLOCK == 48000000) || \ - (PLL_CLOCK == 96000000) - /* Set PLL frequency */ - clock_set_pll(PLL_CLOCK / 24000000); -#else -#error "Support only for PLL clock speed of 24/48/96MHz." -#endif - /* - * The VCC power status is treated as power-on. - * The VCC supply of LPC and related functions (EC2I, - * KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI). - * It means VCC (pin 11) should be logic high before using - * these functions, or firmware treats VCC logic high - * as following setting. - */ - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40; - -#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI) - /* - * Because we don't support eSPI HW reset function (b/111480168) on DX - * version, so we have to reset eSPI configurations during init to - * ensure Host and EC are synchronized (especially for the field of - * I/O mode) - */ - if (!system_jumped_to_this_image()) - espi_fw_reset_module(); -#endif - /* Turn off auto clock gating. */ - IT83XX_ECPM_AUTOCG = 0x00; - - /* Default doze mode */ - clock_ec_pll_ctrl(EC_PLL_DOZE); - - clock_module_disable(); - -#ifdef CONFIG_HOSTCMD_X86 - IT83XX_WUC_WUESR4 = BIT(2); - task_clear_pending_irq(IT83XX_IRQ_WKINTAD); - /* bit2, wake-up enable for LPC access */ - IT83XX_WUC_WUENR4 |= BIT(2); -#endif -} - -int clock_get_freq(void) -{ - return freq; -} - -/** - * Enable clock to specified peripheral - * - * @param offset Should be element of clock_gate_offsets enum. - * Bits 8-15 specify the ECPM offset of the specific clock reg. - * Bits 0-7 specify the mask for the clock register. - * @param mask Unused - * @param mode Unused - */ -void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) -{ - volatile uint8_t *reg = (volatile uint8_t *) - (IT83XX_ECPM_BASE + (offset >> 8)); - uint8_t reg_mask = offset & 0xff; - - /* - * Note: CGCTRL3R, bit 6, must always write 1, but since there is no - * offset argument that addresses this bit, then we are guaranteed - * that this line will write a 1 to that bit. - */ - *reg &= ~reg_mask; -} - -/** - * Disable clock to specified peripheral - * - * @param offset Should be element of clock_gate_offsets enum. - * Bits 8-15 specify the ECPM offset of the specific clock reg. - * Bits 0-7 specify the mask for the clock register. - * @param mask Unused - * @param mode Unused - */ -void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) -{ - volatile uint8_t *reg = (volatile uint8_t *) - (IT83XX_ECPM_BASE + (offset >> 8)); - uint8_t reg_mask = offset & 0xff; - uint8_t tmp_mask = 0; - - /* CGCTRL3R, bit 6, must always write a 1. */ - tmp_mask |= ((offset >> 8) == IT83XX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00; - - *reg |= reg_mask | tmp_mask; -} - -#ifdef CONFIG_LOW_POWER_IDLE -void clock_refresh_console_in_use(void) -{ - /* Set console in use expire time. */ - console_expire_time = get_time(); - console_expire_time.val += console_in_use_timeout_sec * SECOND; -} - -static void clock_event_timer_clock_change(enum ext_timer_clock_source clock, - uint32_t count) -{ - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); - IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock; - IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count; - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3; -} - -static void clock_htimer_enable(void) -{ - uint32_t c; - - /* change event timer clock source to 32.768 KHz */ -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES - c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER)); -#else - c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)); -#endif - clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c); -} - -static int clock_allow_low_power_idle(void) -{ - if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0))) - return 0; - - if (*et_ctrl_regs[EVENT_EXT_TIMER].isr & - et_ctrl_regs[EVENT_EXT_TIMER].mask) - return 0; - -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES - if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) < -#else - if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) < -#endif - SLEEP_SET_HTIMER_DELAY_USEC) - return 0; - - sleep_mode_t0 = get_time(); - if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) || - (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC)) - return 0; - - if (sleep_mode_t0.val < console_expire_time.val) - return 0; - - return 1; -} - -int clock_ec_wake_from_sleep(void) -{ - return ec_sleep; -} - -void clock_cpu_standby(void) -{ - /* standby instruction */ - if (IS_ENABLED(CHIP_CORE_NDS32)) { - asm("standby wake_grant"); - } else if (IS_ENABLED(CHIP_CORE_RISCV)) { - /* - * TODO(b:142029177): we have to enable interrupts before - * standby instruction on IT8xxx2 series. - */ - interrupt_enable(); - asm("wfi"); - } -} - -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - - /* disable all interrupts */ - interrupt_disable(); - for (i = 0; i < IT83XX_IRQ_COUNT; i++) { - chip_disable_irq(i); - chip_clear_pending_irq(i); - } - /* bit5: watchdog is disabled. */ - IT83XX_ETWD_ETWCTRL |= BIT(5); - /* Setup GPIOs for hibernate */ - if (board_hibernate_late) - board_hibernate_late(); - - if (seconds || microseconds) { - /* At least 1 ms for hibernate. */ - uint64_t c = (seconds * 1000 + microseconds / 1000 + 1) * 1024; - - uint64divmod(&c, 1000); - /* enable a 56-bit timer and clock source is 1.024 KHz */ - ext_timer_stop(FREE_EXT_TIMER_L, 1); - ext_timer_stop(FREE_EXT_TIMER_H, 1); - IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_L) = EXT_PSR_1P024K_HZ; - IT83XX_ETWD_ETXPSR(FREE_EXT_TIMER_H) = EXT_PSR_1P024K_HZ; - IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_L) = c & 0xffffff; - IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = (c >> 24) & 0xffffffff; - ext_timer_start(FREE_EXT_TIMER_H, 1); - ext_timer_start(FREE_EXT_TIMER_L, 0); - } - -#ifdef CONFIG_USB_PD_TCPM_ITE83XX - /* - * Disable integrated pd modules in hibernate for - * better power consumption. - */ - for (i = 0; i < USBPD_PORT_COUNT; i++) - it83xx_disable_pd_module(i); -#endif - - for (i = 0; i < hibernate_wake_pins_used; ++i) - gpio_enable_interrupt(hibernate_wake_pins[i]); - - /* EC sleep */ - ec_sleep = 1; -#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOSTCMD_ESPI) - /* Disable eSPI pad. */ - espi_enable_pad(0); -#endif - clock_ec_pll_ctrl(EC_PLL_SLEEP); - interrupt_enable(); - /* standby instruction */ - clock_cpu_standby(); - - /* we should never reach that point */ - __builtin_unreachable(); -} - -void clock_sleep_mode_wakeup_isr(void) -{ - uint32_t st_us, c; - - /* trigger a reboot if wake up EC from sleep mode (system hibernate) */ - if (clock_ec_wake_from_sleep()) { -#if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOSTCMD_ESPI) - /* - * Enable eSPI pad. - * We will not need to enable eSPI pad here if Dx is able to - * enable watchdog hardware reset function. But the function is - * failed (b:111264984), so the following system reset is - * software reset (PLL setting is not reset). - * We will not go into the change PLL sequence on reboot if PLL - * setting is the same, so the operation of enabling eSPI pad we - * added in clock_set_pll() will not be applied. - */ - espi_enable_pad(1); -#endif - system_reset(SYSTEM_RESET_HARD); - } - - if (IT83XX_ECPM_PLLCTRL == EC_PLL_DEEP_DOZE) { - clock_ec_pll_ctrl(EC_PLL_DOZE); - - /* update free running timer */ - c = 0xffffffff - IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER); - st_us = TIMER_32P768K_CNT_TO_US(c); - sleep_mode_t1.val = sleep_mode_t0.val + st_us; - __hw_clock_source_set(sleep_mode_t1.le.lo); - - /* reset event timer and clock source is 8 MHz */ - clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff); - task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq); - process_timers(0); -#ifdef CONFIG_HOSTCMD_X86 - /* disable lpc access wui */ - task_disable_irq(IT83XX_IRQ_WKINTAD); - IT83XX_WUC_WUESR4 = BIT(2); - task_clear_pending_irq(IT83XX_IRQ_WKINTAD); -#endif - /* disable uart wui */ - uart_exit_dsleep(); - /* Record time spent in sleep. */ - total_idle_sleep_time_us += st_us; - } -} - -/** - * Low power idle task. Executed when no tasks are ready to be scheduled. - */ -void __idle(void) -{ - console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; - /* init hw timer and clock source is 32.768 KHz */ - ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0, - 0xffffffff, 1, 1); - - /* - * Print when the idle task starts. This is the lowest priority task, - * so this only starts once all other tasks have gotten a chance to do - * their task inits and have gone to sleep. - */ - CPRINTS("low power idle task started"); - - while (1) { - /* Disable interrupts */ - interrupt_disable(); - /* Check if the EC can enter deep doze mode or not */ - if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) { - /* reset low power mode hw timer */ - IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1); - sleep_mode_t0 = get_time(); -#ifdef CONFIG_HOSTCMD_X86 - /* enable lpc access wui */ - task_enable_irq(IT83XX_IRQ_WKINTAD); -#endif - /* enable uart wui */ - uart_enter_dsleep(); - /* enable hw timer for deep doze / sleep mode wake-up */ - clock_htimer_enable(); - /* deep doze mode */ - clock_ec_pll_ctrl(EC_PLL_DEEP_DOZE); - idle_sleep_cnt++; - } else { - /* doze mode */ - clock_ec_pll_ctrl(EC_PLL_DOZE); - idle_doze_cnt++; - } - clock_cpu_standby(); - interrupt_enable(); - } -} -#endif /* CONFIG_LOW_POWER_IDLE */ - -#ifdef CONFIG_LOW_POWER_IDLE -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that doze: %d\n", idle_doze_cnt); - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - - ccprintf("Total Time spent in sleep(sec): %.6lld(s)\n", - total_idle_sleep_time_us); - ccprintf("Total time on: %.6llds\n\n", ts.val); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); - -#endif /* CONFIG_CMD_IDLE_STATS */ -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h deleted file mode 100644 index 1eb0c0f05a..0000000000 --- a/chip/it83xx/config_chip.h +++ /dev/null @@ -1,122 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#if defined(CHIP_FAMILY_IT8320) /* N8 core */ -#include "config_chip_it8320.h" -#elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */ -#include "config_chip_it8xxx2.h" -#else -#error "Unsupported chip family!" -#endif - -/* Number of IRQ vectors on the IVIC */ -#define CONFIG_IRQ_COUNT IT83XX_IRQ_COUNT - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Default PLL frequency. */ -#define PLL_CLOCK 48000000 - -/* Number of I2C ports */ -#define I2C_PORT_COUNT 6 - -/* I2C ports on chip - * IT83xx - There are three i2c standard ports. - * There are three i2c enhanced ports. - */ -#define I2C_STANDARD_PORT_COUNT 3 -#define I2C_ENHANCED_PORT_COUNT 3 - -/* System stack size */ -#define CONFIG_STACK_SIZE 1024 - -/* non-standard task stack sizes */ -#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE) -#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) -#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE) -#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE) - -/* Default task stack size */ -#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) - -#ifdef IT83XX_CHIP_FLASH_IS_KGD -#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* erase bank size */ -#else -#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */ -#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */ -#endif -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */ - -/* - * This is the block size of the ILM on the it83xx chip. - * The ILM for static code cache, CPU fetch instruction from - * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled. - */ -#define IT83XX_ILM_BLOCK_SIZE 0x00001000 - -#ifdef IT83XX_CHIP_FLASH_IS_KGD -/* - * One page program instruction allows maximum 256 bytes (a page) of data - * to be programmed. - */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 -#else -/* - * The AAI program instruction allows continue write flash - * until write disable instruction. - */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE -#endif - -/****************************************************************************/ -/* Define our flash layout. */ - -/* Memory-mapped internal flash */ -#define CONFIG_INTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE - -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE - -/* Compute the rest of the flash params from these */ -#include "config_std_internal_flash.h" - -/****************************************************************************/ -/* H2RAM memory mapping */ - -/* - * Only it839x series and IT838x DX support mapping LPC I/O cycle 800h ~ 9FFh - * to 0x8D800h ~ 0x8D9FFh of DLM13. - * - * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh - * to 0x80081800 ~ 0x800819FF of DLM1. - */ -#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE) -#define CONFIG_H2RAM_SIZE 0x00001000 -#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800 - -/****************************************************************************/ -/* Customize the build */ - -#define CONFIG_FW_RESET_VECTOR - -/* Optional features present on this chip */ -#define CHIP_FAMILY_IT83XX -#define CONFIG_ADC -#define CONFIG_SWITCH - -/* Chip needs to do custom pre-init */ -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_PIN(port, index) GPIO_##port, BIT(index) -#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h deleted file mode 100644 index 3bbb2060ea..0000000000 --- a/chip/it83xx/config_chip_it8320.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_IT8320_H -#define __CROS_EC_CONFIG_CHIP_IT8320_H - -/* CPU core BFD configuration */ -#include "core/nds32/config_core.h" - -/* N8 core */ -#define CHIP_CORE_NDS32 -/* The base address of EC interrupt controller registers. */ -#define CHIP_EC_INTC_BASE 0x00F01100 - -/****************************************************************************/ -/* Memory mapping */ - -#define CHIP_H2RAM_BASE 0x0008D000 /* 0x0008D000~0x0008DFFF */ -#define CHIP_RAMCODE_BASE 0x0008E000 /* 0x0008E000~0x0008EFFF */ -#define CHIP_EXTRA_STACK_SPACE 0 - -#define CONFIG_RAM_BASE 0x00080000 -#define CONFIG_RAM_SIZE 0x0000C000 - -#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 - -#if defined(CHIP_VARIANT_IT8320BX) -/* This is the physical size of the flash on the chip. We'll reserve one bank - * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware - * doesn't support a write-protect pin, and if we make the write-protection - * permanent, it can't be undone easily enough to support RMA. - */ -#define CONFIG_FLASH_SIZE 0x00040000 -/* For IT8320BX, we have to reload cc parameters after ec softreset. */ -#define IT83XX_USBPD_CC_PARAMETER_RELOAD -/* - * The voltage detector of CC1 and CC2 is enabled/disabled by different bit - * of the control register (bit1 and bit5 at register IT83XX_USBPD_CCCSR). - */ -#define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT -/* For IT8320BX, we have to write 0xff to clear pending bit.*/ -#define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR -/* For IT8320BX, we have to read observation register of external timer two - * times to get correct time. - */ -#define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES -#elif defined(CHIP_VARIANT_IT8320DX) -#define CONFIG_FLASH_SIZE 0x00080000 -/* - * Disable eSPI pad, then PLL change - * (include EC clock frequency) is succeed even CS# is low. - */ -#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED -/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */ -#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE -/* - * TODO(b/111480168): eSPI HW reset can't be used because the DMA address - * gets set incorrectly resulting in a memory access exception. - */ -#define IT83XX_ESPI_RESET_MODULE_BY_FW -/* Watchdog reset supports hardware reset. */ -/* TODO(b/111264984): watchdog hardware reset function failed. */ -#undef IT83XX_ETWD_HW_RESET_SUPPORT -/* - * (b/112452221): - * Floating-point multiplication single-precision is failed on DX version, - * so we use the formula "A/(1/B)" to replace a multiplication operation - * (A*B = A/(1/B)). - */ -#define IT83XX_FPU_MUL_BY_DIV -/* - * More GPIOs can be set as 1.8v input. - * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs. - */ -#define IT83XX_GPIO_1P8V_PIN_EXTENDED -/* All GPIOs support interrupt on rising, falling, and either edge. */ -#define IT83XX_GPIO_INT_FLEXIBLE -/* Enable interrupts of group 21 and 22. */ -#define IT83XX_INTC_GROUP_21_22_SUPPORT -/* Enable detect type-c plug in interrupt. */ -#define IT83XX_INTC_PLUG_IN_SUPPORT -/* Chip Dx transmit status bit of PD register is different from Bx. */ -#define IT83XX_PD_TX_ERROR_STATUS_BIT5 -#else -#error "Unsupported chip variant!" -#endif - -#endif /* __CROS_EC_CONFIG_CHIP_IT8320_H */ diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h deleted file mode 100644 index 88a1ee4960..0000000000 --- a/chip/it83xx/config_chip_it8xxx2.h +++ /dev/null @@ -1,62 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H -#define __CROS_EC_CONFIG_CHIP_IT8XXX2_H - -/* CPU core BFD configuration */ -#include "core/riscv-rv32i/config_core.h" - - /* RISCV core */ -#define CHIP_CORE_RISCV -#define CHIP_ILM_DLM_ORDER -/* The base address of EC interrupt controller registers. */ -#define CHIP_EC_INTC_BASE 0x00F03F00 - -/****************************************************************************/ -/* Memory mapping */ - -#define CHIP_ILM_BASE 0x80000000 -#define CHIP_H2RAM_BASE 0x80081000 /* 0x80081000~0x80081FFF */ -#define CHIP_RAMCODE_BASE 0x80082000 /* 0x80082000~0x80082FFF */ -#define CHIP_EXTRA_STACK_SPACE 128 -/* We reserve 12KB space for ramcode, h2ram, and immu sections. */ -#define CHIP_RAM_SPACE_RESERVED 0x3000 - -#define CONFIG_RAM_BASE 0x80080000 -#define CONFIG_RAM_SIZE 0x00010000 - -#define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE) - -#if defined(CHIP_VARIANT_IT83202BX) -/* TODO(b/133460224): enable properly chip config option. */ -#define CONFIG_FLASH_SIZE 0x00080000 -/* Embedded flash is KGD */ -#define IT83XX_CHIP_FLASH_IS_KGD -/* chip id is 3 bytes */ -#define IT83XX_CHIP_ID_3BYTES -/* - * Disable eSPI pad, then PLL change - * (include EC clock frequency) is succeed even CS# is low. - */ -#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED -/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */ -#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE -/* Watchdog reset supports hardware reset. */ -#define IT83XX_ETWD_HW_RESET_SUPPORT -/* - * More GPIOs can be set as 1.8v input. - * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs. - */ -#define IT83XX_GPIO_1P8V_PIN_EXTENDED -/* All GPIOs support interrupt on rising, falling, and either edge. */ -#define IT83XX_GPIO_INT_FLEXIBLE -/* Enable detect type-c plug in interrupt. */ -#define IT83XX_INTC_PLUG_IN_SUPPORT -#else -#error "Unsupported chip variant!" -#endif - -#endif /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */ diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c deleted file mode 100644 index fe657438c4..0000000000 --- a/chip/it83xx/ec2i.c +++ /dev/null @@ -1,314 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* EC2I control module for IT83xx. */ - -#include "common.h" -#include "console.h" -#include "ec2i_chip.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -static const struct ec2i_t keyboard_settings[] = { - /* Select logical device 06h(keyboard) */ - {HOST_INDEX_LDN, LDN_KBC_KEYBOARD}, - /* Set IRQ=01h for logical device */ - {HOST_INDEX_IRQNUMX, 0x01}, - /* Configure IRQTP for KBC. */ -#ifdef CONFIG_HOSTCMD_ESPI - /* - * Interrupt request type select (IRQTP) for KBC. - * bit 1, 0: IRQ request is buffered and applied to SERIRQ - * 1: IRQ request is inverted before being applied to SERIRQ - * bit 0, 0: Edge triggered mode - * 1: Level triggered mode - * - * SERIRQ# is by default deasserted level high. However, when using - * eSPI, SERIRQ# is routed over virtual wire as interrupt event. As - * per eSPI base spec (doc#327432), all virtual wire interrupt events - * are deasserted level low. Thus, it is necessary to configure this - * interrupt as inverted. ITE hardware takes care of routing the SERIRQ# - * signal appropriately over eSPI / LPC depending upon the selected - * mode. - * - * Additionally, this interrupt is configured as edge-triggered on the - * host side. So, match the trigger mode on the EC side as well. - */ - {HOST_INDEX_IRQTP, 0x02}, -#endif - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; - -#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE -static const struct ec2i_t mouse_settings[] = { - /* Select logical device 05h(mouse) */ - {HOST_INDEX_LDN, LDN_KBC_MOUSE}, - /* Set IRQ=0Ch for logical device */ - {HOST_INDEX_IRQNUMX, 0x0C}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; -#endif - -static const struct ec2i_t pm1_settings[] = { - /* Select logical device 11h(PM1 ACPI) */ - {HOST_INDEX_LDN, LDN_PMC1}, - /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; - -static const struct ec2i_t pm2_settings[] = { - /* Select logical device 12h(PM2) */ - {HOST_INDEX_LDN, LDN_PMC2}, - /* I/O Port Base Address 200h/204h */ - {HOST_INDEX_IOBAD0_MSB, 0x02}, - {HOST_INDEX_IOBAD0_LSB, 0x00}, - {HOST_INDEX_IOBAD1_MSB, 0x02}, - {HOST_INDEX_IOBAD1_LSB, 0x04}, - /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; - -static const struct ec2i_t smfi_settings[] = { - /* Select logical device 0Fh(SMFI) */ - {HOST_INDEX_LDN, LDN_SMFI}, - /* H2RAM LPC I/O cycle Dxxx */ - {HOST_INDEX_DSLDC6, 0x00}, - /* Enable H2RAM LPC I/O cycle */ - {HOST_INDEX_DSLDC7, 0x01}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; - -/* - * PM3 is enabled and base address is set to 80h so that we are able to get an - * interrupt when host outputs data to port 80. - */ -static const struct ec2i_t pm3_settings[] = { - /* Select logical device 17h(PM3) */ - {HOST_INDEX_LDN, LDN_PMC3}, - /* I/O Port Base Address 80h */ - {HOST_INDEX_IOBAD0_MSB, 0x00}, - {HOST_INDEX_IOBAD0_LSB, 0x80}, - {HOST_INDEX_IOBAD1_MSB, 0x00}, - {HOST_INDEX_IOBAD1_LSB, 0x00}, - /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; - -/* - * This logical device is not enabled, however P80L* settings need to be - * performed on this logical device to ensure that port80 BRAM index is - * initialized correctly. - */ -static const struct ec2i_t rtct_settings[] = { - /* Select logical device 10h(RTCT) */ - {HOST_INDEX_LDN, LDN_RTCT}, - /* P80L Begin Index */ - {HOST_INDEX_DSLDC4, P80L_P80LB}, - /* P80L End Index */ - {HOST_INDEX_DSLDC5, P80L_P80LE}, - /* P80L Current Index */ - {HOST_INDEX_DSLDC6, P80L_P80LC}, -}; - -#ifdef CONFIG_UART_HOST -static const struct ec2i_t uart2_settings[] = { - /* Select logical device 2h(UART2) */ - {HOST_INDEX_LDN, LDN_UART2}, - /* - * I/O port base address is 2F8h. - * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2. - * See specification 7.24.4 for more detial. - */ - {HOST_INDEX_IOBAD0_MSB, 0x02}, - {HOST_INDEX_IOBAD0_LSB, 0xF8}, - /* IRQ number is 3 */ - {HOST_INDEX_IRQNUMX, 0x03}, - /* - * Interrupt Request Type Select - * bit1, 0: IRQ request is buffered and applied to SERIRQ. - * 1: IRQ request is inverted before being applied to SERIRQ. - * bit0, 0: Edge triggered mode. - * 1: Level triggered mode. - */ - {HOST_INDEX_IRQTP, 0x02}, - /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, -}; -#endif - -/* EC2I access index/data port */ -enum ec2i_access { - /* index port */ - EC2I_ACCESS_INDEX = 0, - /* data port */ - EC2I_ACCESS_DATA = 1, -}; - -enum ec2i_status_mask { - /* 1: EC read-access is still processing. */ - EC2I_STATUS_CRIB = BIT(1), - /* 1: EC write-access is still processing with IHD register. */ - EC2I_STATUS_CWIB = BIT(2), - EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB), -}; - -static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask) -{ - /* delay ~15.25us */ - IT83XX_GCTRL_WNCKR = 0; - - return (IT83XX_EC2I_IBCTL & mask); -} - -static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data) -{ - int rv = EC_ERROR_UNKNOWN; - - /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & BIT(1)) { - /* - * Wait that both CRIB and CWIB bits in IBCTL register - * are cleared. - */ - rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL); - if (!rv) { - /* Set indirect host I/O offset. */ - IT83XX_EC2I_IHIOA = sel; - /* Write the data to IHD register */ - IT83XX_EC2I_IHD = data; - /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= BIT(0); - /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= BIT(0); - /* Wait the CWIB bit in IBCTL cleared. */ - rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB); - /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~BIT(0); - /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~BIT(0); - } - } - - return rv ? EC2I_WRITE_ERROR : EC2I_WRITE_SUCCESS; -} - -static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel) -{ - int rv = EC_ERROR_UNKNOWN; - uint8_t ihd = 0; - - /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & BIT(1)) { - /* - * Wait that both CRIB and CWIB bits in IBCTL register - * are cleared. - */ - rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_ALL); - if (!rv) { - /* Set indirect host I/O offset. */ - IT83XX_EC2I_IHIOA = sel; - /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= BIT(0); - /* bit1: a read-action */ - IT83XX_EC2I_IBCTL |= BIT(1); - /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= BIT(0); - /* Wait the CRIB bit in IBCTL cleared. */ - rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB); - /* Read the data from IHD register */ - ihd = IT83XX_EC2I_IHD; - /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~BIT(0); - /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~BIT(0); - } - } - - return rv ? EC2I_READ_ERROR : (EC2I_READ_SUCCESS + ihd); -} - -/* EC2I read */ -enum ec2i_message ec2i_read(enum host_pnpcfg_index index) -{ - enum ec2i_message ret = EC2I_READ_ERROR; - uint32_t int_mask = get_int_mask(); - - /* critical section with interrupts off */ - interrupt_disable(); - /* Set index */ - if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS) - /* read data port */ - ret = ec2i_read_pnpcfg(EC2I_ACCESS_DATA); - /* restore interrupts */ - set_int_mask(int_mask); - - return ret; -} - -/* EC2I write */ -enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data) -{ - enum ec2i_message ret = EC2I_WRITE_ERROR; - uint32_t int_mask = get_int_mask(); - - /* critical section with interrupts off */ - interrupt_disable(); - /* Set index */ - if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS) - /* Set data */ - ret = ec2i_write_pnpcfg(EC2I_ACCESS_DATA, data); - /* restore interrupts */ - set_int_mask(int_mask); - - return ret; -} - -static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries) -{ - size_t i; - - for (i = 0; i < entries; i++) { - if (ec2i_write(settings[i].index_port, settings[i].data_port) == - EC2I_WRITE_ERROR) { - ccprints("Failed to apply %zd", i); - break; - } - } -} - -#define PNPCFG(_s) \ - pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings)) - -static void pnpcfg_init(void) -{ - /* Host access is disabled */ - IT83XX_EC2I_LSIOHA |= 0x3; - - PNPCFG(keyboard); -#ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE - PNPCFG(mouse); -#endif - PNPCFG(pm1); - PNPCFG(pm2); - PNPCFG(smfi); - PNPCFG(pm3); - PNPCFG(rtct); -#ifdef CONFIG_UART_HOST - PNPCFG(uart2); -#endif -} -DECLARE_HOOK(HOOK_INIT, pnpcfg_init, HOOK_PRIO_DEFAULT); diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h deleted file mode 100644 index c8069f4ff5..0000000000 --- a/chip/it83xx/ec2i_chip.h +++ /dev/null @@ -1,129 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* EC2I control module for IT83xx. */ - -#ifndef __CROS_EC_EC2I_CHIP_H -#define __CROS_EC_EC2I_CHIP_H - -#define P80L_P80LB 0 -#define P80L_P80LE 0x3F -#define P80L_P80LC 0 -#define P80L_BRAM_BANK1_SIZE_MASK 0x3F - -/* Index list of the host interface registers of PNPCFG */ -enum host_pnpcfg_index { - /* Logical Device Number */ - HOST_INDEX_LDN = 0x07, - /* Chip ID Byte 1 */ - HOST_INDEX_CHIPID1 = 0x20, - /* Chip ID Byte 2 */ - HOST_INDEX_CHIPID2 = 0x21, - /* Chip Version */ - HOST_INDEX_CHIPVER = 0x22, - /* Super I/O Control */ - HOST_INDEX_SIOCTRL = 0x23, - /* Super I/O IRQ Configuration */ - HOST_INDEX_SIOIRQ = 0x25, - /* Super I/O General Purpose */ - HOST_INDEX_SIOGP = 0x26, - /* Super I/O Power Mode */ - HOST_INDEX_SIOPWR = 0x2D, - /* Depth 2 I/O Address */ - HOST_INDEX_D2ADR = 0x2E, - /* Depth 2 I/O Data */ - HOST_INDEX_D2DAT = 0x2F, - /* Logical Device Activate Register */ - HOST_INDEX_LDA = 0x30, - /* I/O Port Base Address Bits [15:8] for Descriptor 0 */ - HOST_INDEX_IOBAD0_MSB = 0x60, - /* I/O Port Base Address Bits [7:0] for Descriptor 0 */ - HOST_INDEX_IOBAD0_LSB = 0x61, - /* I/O Port Base Address Bits [15:8] for Descriptor 1 */ - HOST_INDEX_IOBAD1_MSB = 0x62, - /* I/O Port Base Address Bits [7:0] for Descriptor 1 */ - HOST_INDEX_IOBAD1_LSB = 0x63, - /* Interrupt Request Number and Wake-Up on IRQ Enabled */ - HOST_INDEX_IRQNUMX = 0x70, - /* Interrupt Request Type Select */ - HOST_INDEX_IRQTP = 0x71, - /* DMA Channel Select 0 */ - HOST_INDEX_DMAS0 = 0x74, - /* DMA Channel Select 1 */ - HOST_INDEX_DMAS1 = 0x75, - /* Device Specific Logical Device Configuration 1 to 10 */ - HOST_INDEX_DSLDC1 = 0xF0, - HOST_INDEX_DSLDC2 = 0xF1, - HOST_INDEX_DSLDC3 = 0xF2, - HOST_INDEX_DSLDC4 = 0xF3, - HOST_INDEX_DSLDC5 = 0xF4, - HOST_INDEX_DSLDC6 = 0xF5, - HOST_INDEX_DSLDC7 = 0xF6, - HOST_INDEX_DSLDC8 = 0xF7, - HOST_INDEX_DSLDC9 = 0xF8, - HOST_INDEX_DSLDC10 = 0xF9, -}; - -/* List of logical device number (LDN) assignments */ -enum logical_device_number { - /* Serial Port 1 */ - LDN_UART1 = 0x01, - /* Serial Port 2 */ - LDN_UART2 = 0x02, - /* System Wake-Up Control */ - LDN_SWUC = 0x04, - /* KBC/Mouse Interface */ - LDN_KBC_MOUSE = 0x05, - /* KBC/Keyboard Interface */ - LDN_KBC_KEYBOARD = 0x06, - /* Consumer IR */ - LDN_CIR = 0x0A, - /* Shared Memory/Flash Interface */ - LDN_SMFI = 0x0F, - /* RTC-like Timer */ - LDN_RTCT = 0x10, - /* Power Management I/F Channel 1 */ - LDN_PMC1 = 0x11, - /* Power Management I/F Channel 2 */ - LDN_PMC2 = 0x12, - /* Serial Peripheral Interface */ - LDN_SSPI = 0x13, - /* Platform Environment Control Interface */ - LDN_PECI = 0x14, - /* Power Management I/F Channel 3 */ - LDN_PMC3 = 0x17, - /* Power Management I/F Channel 4 */ - LDN_PMC4 = 0x18, - /* Power Management I/F Channel 5 */ - LDN_PMC5 = 0x19, -}; - -/* EC2I read/write message */ -enum ec2i_message { - /* EC2I write success */ - EC2I_WRITE_SUCCESS = 0x00, - /* EC2I write error */ - EC2I_WRITE_ERROR = 0x01, - /* EC2I read success */ - EC2I_READ_SUCCESS = 0x8000, - /* EC2I read error */ - EC2I_READ_ERROR = 0x8100, -}; - -/* Data structure for initializing PNPCFG via ec2i. */ -struct ec2i_t { - /* index port */ - enum host_pnpcfg_index index_port; - /* data port */ - uint8_t data_port; -}; - -/* EC2I write */ -enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data); - -/* EC2I read */ -enum ec2i_message ec2i_read(enum host_pnpcfg_index index); - -#endif /* __CROS_EC_EC2I_CHIP_H */ diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c deleted file mode 100644 index c731a7ad7e..0000000000 --- a/chip/it83xx/espi.c +++ /dev/null @@ -1,618 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* ESPI module for Chrome EC */ - -#include "console.h" -#include "espi.h" -#include "hooks.h" -#include "port80.h" -#include "power.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - -struct vw_channel_t { - uint8_t index; /* VW index of signal */ - uint8_t level_mask; /* level bit of signal */ - uint8_t valid_mask; /* valid bit of signal */ -}; - -/* VW settings after the master enables the VW channel. */ -static const struct vw_channel_t en_vw_setting[] = { - /* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */ -#ifndef CONFIG_CHIPSET_GEMINILAKE - {ESPI_SYSTEM_EVENT_VW_IDX_40, - VW_LEVEL_FIELD(0), - VW_VALID_FIELD(VW_IDX_40_SUS_ACK)}, -#endif -}; - -/* VW settings after the master enables the OOB channel. */ -static const struct vw_channel_t en_oob_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(0), - VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)}, -}; - -/* VW settings after the master enables the flash channel. */ -static const struct vw_channel_t en_flash_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE), - VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)}, -}; - -/* VW settings at host startup */ -static const struct vw_channel_t vw_host_startup_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | - VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK), - VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | - VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)}, -}; - -#define VW_CHAN(name, idx, level, valid) \ - [(name - VW_SIGNAL_START)] = {idx, level, valid} - -/* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */ -static const struct vw_channel_t vw_channel_list[] = { - /* index 02h: master to slave. */ - VW_CHAN(VW_SLP_S3_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, - VW_LEVEL_FIELD(VW_IDX_2_SLP_S3), - VW_VALID_FIELD(VW_IDX_2_SLP_S3)), - VW_CHAN(VW_SLP_S4_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, - VW_LEVEL_FIELD(VW_IDX_2_SLP_S4), - VW_VALID_FIELD(VW_IDX_2_SLP_S4)), - VW_CHAN(VW_SLP_S5_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, - VW_LEVEL_FIELD(VW_IDX_2_SLP_S5), - VW_VALID_FIELD(VW_IDX_2_SLP_S5)), - /* index 03h: master to slave. */ - VW_CHAN(VW_SUS_STAT_L, - ESPI_SYSTEM_EVENT_VW_IDX_3, - VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT), - VW_VALID_FIELD(VW_IDX_3_SUS_STAT)), - VW_CHAN(VW_PLTRST_L, - ESPI_SYSTEM_EVENT_VW_IDX_3, - VW_LEVEL_FIELD(VW_IDX_3_PLTRST), - VW_VALID_FIELD(VW_IDX_3_PLTRST)), - VW_CHAN(VW_OOB_RST_WARN, - ESPI_SYSTEM_EVENT_VW_IDX_3, - VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN), - VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)), - /* index 04h: slave to master. */ - VW_CHAN(VW_OOB_RST_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK), - VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)), - VW_CHAN(VW_WAKE_L, - ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(VW_IDX_4_WAKE), - VW_VALID_FIELD(VW_IDX_4_WAKE)), - VW_CHAN(VW_PME_L, - ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(VW_IDX_4_PME), - VW_VALID_FIELD(VW_IDX_4_PME)), - /* index 05h: slave to master. */ - VW_CHAN(VW_ERROR_FATAL, - ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_FATAL), - VW_VALID_FIELD(VW_IDX_5_FATAL)), - VW_CHAN(VW_ERROR_NON_FATAL, - ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL), - VW_VALID_FIELD(VW_IDX_5_NON_FATAL)), - VW_CHAN(VW_SLAVE_BTLD_STATUS_DONE, - ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE), - VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)), - /* index 06h: slave to master. */ - VW_CHAN(VW_SCI_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SCI), - VW_VALID_FIELD(VW_IDX_6_SCI)), - VW_CHAN(VW_SMI_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SMI), - VW_VALID_FIELD(VW_IDX_6_SMI)), - VW_CHAN(VW_RCIN_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_RCIN), - VW_VALID_FIELD(VW_IDX_6_RCIN)), - VW_CHAN(VW_HOST_RST_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK), - VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)), - /* index 07h: master to slave. */ - VW_CHAN(VW_HOST_RST_WARN, - ESPI_SYSTEM_EVENT_VW_IDX_7, - VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN), - VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)), - /* index 40h: slave to master. */ - VW_CHAN(VW_SUS_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_40, - VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK), - VW_VALID_FIELD(VW_IDX_40_SUS_ACK)), - /* index 41h: master to slave. */ - VW_CHAN(VW_SUS_WARN_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, - VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN), - VW_VALID_FIELD(VW_IDX_41_SUS_WARN)), - VW_CHAN(VW_SUS_PWRDN_ACK_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, - VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK), - VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)), - VW_CHAN(VW_SLP_A_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, - VW_LEVEL_FIELD(VW_IDX_41_SLP_A), - VW_VALID_FIELD(VW_IDX_41_SLP_A)), - /* index 42h: master to slave. */ - VW_CHAN(VW_SLP_LAN, - ESPI_SYSTEM_EVENT_VW_IDX_42, - VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN), - VW_VALID_FIELD(VW_IDX_42_SLP_LAN)), - VW_CHAN(VW_SLP_WLAN, - ESPI_SYSTEM_EVENT_VW_IDX_42, - VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN), - VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)), -}; -BUILD_ASSERT(ARRAY_SIZE(vw_channel_list) == VW_SIGNAL_COUNT); - -/* Get vw index & value information by signal */ -static int espi_vw_get_signal_index(enum espi_vw_signal event) -{ - uint32_t i = event - VW_SIGNAL_START; - - return (i < ARRAY_SIZE(vw_channel_list)) ? i : -1; -} - -/** - * Set eSPI Virtual-Wire signal to Host - * - * @param signal vw signal needs to set - * @param level level of vw signal - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level) -{ - /* Get index of vw signal list by signale name */ - int i = espi_vw_get_signal_index(signal); - - if (i < 0) - return EC_ERROR_PARAM1; - - /* critical section with interrupts off */ - interrupt_disable(); - if (level) - IT83XX_ESPI_VWIDX(vw_channel_list[i].index) |= - vw_channel_list[i].level_mask; - else - IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &= - ~vw_channel_list[i].level_mask; - /* restore interrupts */ - interrupt_enable(); - - return EC_SUCCESS; -} - -/** - * Get eSPI Virtual-Wire signal from host - * - * @param signal vw signal needs to get - * @return 1: set by host, otherwise: no signal - */ -int espi_vw_get_wire(enum espi_vw_signal signal) -{ - /* Get index of vw signal list by signale name */ - int i = espi_vw_get_signal_index(signal); - - if (i < 0) - return 0; - - /* Not valid */ - if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) & - vw_channel_list[i].valid_mask)) - return 0; - - return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) & - vw_channel_list[i].level_mask); -} - -/** - * Enable VW interrupt of power sequence signal - * - * @param signal vw signal needs to enable interrupt - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_enable_wire_int(enum espi_vw_signal signal) -{ - /* - * Common code calls this function to enable VW interrupt of power - * sequence signal. - * IT83xx only use a bit (bit7@IT83XX_ESPI_VWCTRL0) to enable VW - * interrupt. - * VW interrupt will be triggerd with any updated VW index flag - * if this control bit is set. - * So we will always return success here. - */ - return EC_SUCCESS; -} - -/** - * Disable VW interrupt of power sequence signal - * - * @param signal vw signal needs to disable interrupt - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_disable_wire_int(enum espi_vw_signal signal) -{ - /* - * We can't disable VW interrupt of power sequence signal - * individually. - */ - return EC_ERROR_UNIMPLEMENTED; -} - -/* Configure virtual wire outputs */ -static void espi_configure_vw(const struct vw_channel_t *settings, - size_t entries) -{ - size_t i; - - for (i = 0; i < entries; i++) - IT83XX_ESPI_VWIDX(settings[i].index) |= - (settings[i].level_mask | settings[i].valid_mask); -} - -static void espi_vw_host_startup(void) -{ - espi_configure_vw(vw_host_startup_setting, - ARRAY_SIZE(vw_host_startup_setting)); -} - -static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt) -{ - CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)", - vw_evt); -} - -#ifndef CONFIG_CHIPSET_GEMINILAKE -static void espi_vw_idx41_isr(uint8_t flag_changed, uint8_t vw_evt) -{ - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN)) - espi_vw_set_wire(VW_SUS_ACK, espi_vw_get_wire(VW_SUS_WARN_L)); -} -#endif - -static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt) -{ - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN)) - espi_vw_set_wire(VW_HOST_RST_ACK, - espi_vw_get_wire(VW_HOST_RST_WARN)); -} - -#ifdef CONFIG_CHIPSET_RESET_HOOK -static void espi_chipset_reset(void) -{ - hook_notify(HOOK_CHIPSET_RESET); -} -DECLARE_DEFERRED(espi_chipset_reset); -#endif - -static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt) -{ - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_PLTRST)) { - int pltrst = espi_vw_get_wire(VW_PLTRST_L); - - if (pltrst) { - espi_vw_host_startup(); - } else { -#ifdef CONFIG_CHIPSET_RESET_HOOK - hook_call_deferred(&espi_chipset_reset_data, MSEC); -#endif - /* Store port 80 reset event */ - port_80_write(PORT_80_EVENT_RESET); - } - - CPRINTS("VW PLTRST_L %sasserted", pltrst ? "de" : ""); - } - - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN)) - espi_vw_set_wire(VW_OOB_RST_ACK, - espi_vw_get_wire(VW_OOB_RST_WARN)); -} - -static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt) -{ - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S3)) - power_signal_interrupt(VW_SLP_S3_L); - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S4)) - power_signal_interrupt(VW_SLP_S4_L); - if (flag_changed & VW_LEVEL_FIELD(VW_IDX_2_SLP_S5)) - power_signal_interrupt(VW_SLP_S5_L); -} - -struct vw_interrupt_t { - void (*vw_isr)(uint8_t flag_changed, uint8_t vw_evt); - uint8_t vw_index; -}; - -/* - * The ISR of espi VW interrupt in array needs to match bit order in - * IT83XX_ESPI_VWCTRL1 register. - */ -#ifdef CONFIG_CHIPSET_GEMINILAKE -static const struct vw_interrupt_t vw_isr_list[] = { - [0] = {espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2}, - [1] = {espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3}, - [2] = {espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7}, - [3] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_41}, - [4] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42}, - [5] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43}, - [6] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44}, - [7] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47}, -}; -#else -static const struct vw_interrupt_t vw_isr_list[] = { - [0] = {espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2}, - [1] = {espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3}, - [2] = {espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7}, - [3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41}, - [4] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42}, - [5] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43}, - [6] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44}, - [7] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47}, -}; -#endif - -/* - * This is used to record the previous VW valid / level field state to discover - * changes. Then do following sequence only when state is changed. - */ -static uint8_t vw_index_flag[ARRAY_SIZE(vw_isr_list)]; - -void espi_vw_interrupt(void) -{ - int i; - uint8_t vwidx_updated = IT83XX_ESPI_VWCTRL1; - -#ifdef IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR - /* For IT8320BX, we have to write 0xff to clear pending bit.*/ - IT83XX_ESPI_VWCTRL1 = 0xff; -#else - /* write-1 to clear */ - IT83XX_ESPI_VWCTRL1 = vwidx_updated; -#endif - task_clear_pending_irq(IT83XX_IRQ_ESPI_VW); - - for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++) { - if (vwidx_updated & BIT(i)) { - uint8_t idx_flag; - - idx_flag = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index); - vw_isr_list[i].vw_isr(vw_index_flag[i] ^ idx_flag, i); - vw_index_flag[i] = idx_flag; - } - } -} - -static void espi_reset_vw_index_flags(void) -{ - int i; - - /* reset vw_index_flag */ - for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++) - vw_index_flag[i] = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index); -} - -#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW -void __ram_code espi_fw_reset_module(void) -{ - /* - * (b/111480168): Force a reset of logic VCC domain in EC. This will - * reset both LPC and eSPI blocks. The IT8320DX spec describes the - * purpose of these bits as deciding whether VCC power status is used as - * an internal "power good" signal. However, toggling this field while - * VCC is applied results in resettig VCC domain logic in EC. This code - * must reside in SRAM to prevent DMA address corruption. - * - * bit[7-6]: - * 00b: The VCC power status is treated as power-off. - * 01b: The VCC power status is treated as power-on. - */ - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0); - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6); -} -#endif - -void espi_reset_pin_asserted_interrupt(enum gpio_signal signal) -{ -#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW - espi_fw_reset_module(); -#endif - /* reset vw_index_flag when espi_reset# asserted. */ - espi_reset_vw_index_flags(); -} - -static int espi_get_reset_enable_config(void) -{ - uint8_t config; - const struct gpio_info *espi_rst = gpio_list + GPIO_ESPI_RESET_L; - - /* - * Determine if eSPI HW reset is connected to eiter B7 or D2. - * bit[2-1]: - * 00b: reserved. - * 01b: espi_reset# is enabled on GPB7. - * 10b: espi_reset# is enabled on GPD2. - * 11b: reset is disabled. - */ - if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) { - config = IT83XX_GPIO_GCR_LPC_RST_D2; - } else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) { - config = IT83XX_GPIO_GCR_LPC_RST_B7; - } else { - config = IT83XX_GPIO_GCR_LPC_RST_DISABLE; - CPRINTS("EC's espi_reset pin is not enabled correctly"); - } - - return config; -} - -static void espi_enable_reset(void) -{ - int config = espi_get_reset_enable_config(); - -#ifdef IT83XX_ESPI_RESET_MODULE_BY_FW - /* - * Need to overwrite the config to ensure that eSPI HW reset is - * disabled. The reset function is instead handled by FW in the - * interrupt handler. - */ - config = IT83XX_GPIO_GCR_LPC_RST_DISABLE; - CPRINTS("EC's espi_reset pin hw auto reset is disabled"); - -#endif - IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) | - (config << IT83XX_GPIO_GCR_LPC_RST_POS); - - /* enable interrupt of EC's espi_reset pin */ - gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L); - gpio_enable_interrupt(GPIO_ESPI_RESET_L); -} - -/* Interrupt event of master enables the VW channel. */ -static void espi_vw_en_asserted(uint8_t evt) -{ - /* - * Configure slave to master virtual wire outputs after receiving - * the event of master enables the VW channel. - */ - espi_configure_vw(en_vw_setting, ARRAY_SIZE(en_vw_setting)); -} - -/* Interrupt event of master enables the OOB channel. */ -static void espi_oob_en_asserted(uint8_t evt) -{ - /* - * Configure slave to master virtual wire outputs after receiving - * the event of master enables the OOB channel. - */ - espi_configure_vw(en_oob_setting, ARRAY_SIZE(en_oob_setting)); -} - -/* Interrupt event of master enables the flash channel. */ -static void espi_flash_en_asserted(uint8_t evt) -{ - /* - * Configure slave to master virtual wire outputs after receiving - * the event of master enables the flash channel. - */ - espi_configure_vw(en_flash_setting, ARRAY_SIZE(en_flash_setting)); -} - -static void espi_no_isr(uint8_t evt) -{ - CPRINTS("espi interrupt event is ignored! (bit%d at ESGCTRL0)", evt); -} - -/* - * The ISR of espi interrupt event in array need to be matched bit order in - * IT83XX_ESPI_ESGCTRL0 register. - */ -static void (*espi_isr[])(uint8_t evt) = { - [0] = espi_no_isr, - [1] = espi_vw_en_asserted, - [2] = espi_oob_en_asserted, - [3] = espi_flash_en_asserted, - [4] = espi_no_isr, - [5] = espi_no_isr, - [6] = espi_no_isr, - [7] = espi_no_isr, -}; - -void espi_interrupt(void) -{ - int i; - /* get espi interrupt events */ - uint8_t espi_event = IT83XX_ESPI_ESGCTRL0; - - /* write-1 to clear */ - IT83XX_ESPI_ESGCTRL0 = espi_event; - /* process espi interrupt events */ - for (i = 0; i < ARRAY_SIZE(espi_isr); i++) { - if (espi_event & BIT(i)) - espi_isr[i](i); - } - /* - * bit7: the slave has received a peripheral posted/completion. - * This bit indicates the slave has received a packet from eSPI - * peripheral channel. We can check cycle type (bit[3-0] at ESPCTRL0) - * and make corresponding modification if needed. - */ - if (IT83XX_ESPI_ESPCTRL0 & ESPI_INTERRUPT_EVENT_PUT_PC) { - /* write-1-clear to release PC_FREE */ - IT83XX_ESPI_ESPCTRL0 = ESPI_INTERRUPT_EVENT_PUT_PC; - CPRINTS("A packet from peripheral channel is ignored!"); - } - - task_clear_pending_irq(IT83XX_IRQ_ESPI); -} - -#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED -/* Enable/Disable eSPI pad */ -void espi_enable_pad(int enable) -{ - if (enable) - /* Enable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 &= ~BIT(6); - else - /* Disable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 |= BIT(6); -} -#endif - -void espi_init(void) -{ - /* - * bit[2-0], the maximum frequency of operation supported by slave: - * 000b: 20MHz - * 001b: 25MHz - * 010b: 33MHz - * 011b: 50MHz - * 100b: 66MHz - */ -#ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE - IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2); -#endif - /* reset vw_index_flag at initialization */ - espi_reset_vw_index_flags(); - - /* - * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH - * register and WRST#. - */ - IT83XX_GCTRL_RSTS &= ~BIT(3); - task_clear_pending_irq(IT83XX_IRQ_ESPI_VW); - /* bit7: VW interrupt enable */ - IT83XX_ESPI_VWCTRL0 |= BIT(7); - task_enable_irq(IT83XX_IRQ_ESPI_VW); - - /* bit7: eSPI interrupt enable */ - IT83XX_ESPI_ESGCTRL1 |= BIT(7); - /* bit4: eSPI to WUC enable */ - IT83XX_ESPI_ESGCTRL2 |= BIT(4); - task_enable_irq(IT83XX_IRQ_ESPI); - - /* enable interrupt and reset from eSPI_reset# */ - espi_enable_reset(); -} diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c deleted file mode 100644 index adb3985025..0000000000 --- a/chip/it83xx/fan.c +++ /dev/null @@ -1,478 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Fan control module. */ - -#include "clock.h" -#include "fan.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer_chip.h" -#include "math_util.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -#define TACH_EC_FREQ 8000000 -#define FAN_CTRL_BASED_MS 10 -#define FAN_CTRL_INTERVAL_MAX_MS 60 - -/* The sampling rate (fs) is FreqEC / 128 */ -#define TACH_DATA_VALID_TIMEOUT_MS (0xFFFF * 128 / (TACH_EC_FREQ / 1000)) - -/* - * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P) - * n denotes 1 or 2. - * P denotes the numbers of square pulses per revolution. - * And {FnTMRR, FnTLRR} = 0000h denotes Fan Speed is zero. - * The sampling rate (fs) is FreqEC / 128. - */ -/* pulse, the numbers of square pulses per revolution. */ -#define TACH0_TO_RPM(pulse, raw) (60 * TACH_EC_FREQ / 128 / pulse / raw) -#define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2)) - -enum fan_output_s { - FAN_DUTY_I = 0x01, - FAN_DUTY_R = 0x02, - FAN_DUTY_OV = 0x03, - FAN_DUTY_DONE = 0x04, -}; - -struct fan_info { - unsigned int flags; - int fan_mode; - int fan_p; - int rpm_target; - int rpm_actual; - int tach_valid_ms; - int rpm_re; - int fan_ms; - int fan_ms_idx; - int startup_duty; - enum fan_status fan_sts; - int enabled; -}; -static struct fan_info fan_info_data[TACH_CH_COUNT]; - -static enum tach_ch_sel tach_bind(int ch) -{ - return fan_tach[pwm_channels[ch].channel].ch_tach; -} - -static void fan_set_interval(int ch) -{ - int diff, fan_ms; - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - diff = ABS(fan_info_data[tach_ch].rpm_target - - fan_info_data[tach_ch].rpm_actual) / 100; - - fan_ms = FAN_CTRL_INTERVAL_MAX_MS; - - fan_ms -= diff; - if (fan_ms < FAN_CTRL_BASED_MS) - fan_ms = FAN_CTRL_BASED_MS; - - fan_info_data[tach_ch].fan_ms = fan_ms; -} - -static void fan_init_start(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - fan_set_duty(ch, fan_info_data[tach_ch].startup_duty); -} - -static int fan_all_disabled(void) -{ - int fan, all_disabled = 0; - - for (fan = 0; fan < fan_get_count(); fan++) { - if (!fan_get_enabled(FAN_CH(fan))) - all_disabled++; - } - - if (all_disabled >= fan_get_count()) - return 1; - - return 0; -} - -void fan_set_enabled(int ch, int enabled) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - /* enable */ - if (enabled) { - if (tach_ch < TACH_CH_COUNT) - fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING; - - disable_sleep(SLEEP_MASK_FAN); - /* enable timer interrupt for fan control */ - ext_timer_start(FAN_CTRL_EXT_TIMER, 1); - /* disable */ - } else { - fan_set_duty(ch, 0); - - if (tach_ch < TACH_CH_COUNT) { - fan_info_data[tach_ch].rpm_actual = 0; - fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED; - } - } - - /* on/off */ - if (tach_ch < TACH_CH_COUNT) { - fan_info_data[tach_ch].enabled = enabled; - fan_info_data[tach_ch].tach_valid_ms = 0; - } - - pwm_enable(ch, enabled); - - if (!enabled) { - /* disable timer interrupt if all fan off. */ - if (fan_all_disabled()) { - ext_timer_stop(FAN_CTRL_EXT_TIMER, 1); - enable_sleep(SLEEP_MASK_FAN); - } - } -} - -int fan_get_enabled(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - return pwm_get_enabled(ch) && fan_info_data[tach_ch].enabled; - else - return 0; -} - -void fan_set_duty(int ch, int percent) -{ - pwm_set_duty(ch, percent); -} - -int fan_get_duty(int ch) -{ - return pwm_get_duty(ch); -} - -int fan_get_rpm_mode(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - return fan_info_data[tach_ch].fan_mode; - else - return EC_ERROR_UNKNOWN; -} - -void fan_set_rpm_mode(int ch, int rpm_mode) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - fan_info_data[tach_ch].fan_mode = rpm_mode; -} - -int fan_get_rpm_actual(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - return fan_info_data[tach_ch].rpm_actual; - else - return EC_ERROR_UNKNOWN; -} - -int fan_get_rpm_target(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - return fan_info_data[tach_ch].rpm_target; - else - return EC_ERROR_UNKNOWN; -} - -test_mockable void fan_set_rpm_target(int ch, int rpm) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - fan_info_data[tach_ch].rpm_target = rpm; -} - -enum fan_status fan_get_status(int ch) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - return fan_info_data[tach_ch].fan_sts; - else - return FAN_STATUS_STOPPED; -} - -/** - * Return non-zero if fan is enabled but stalled. - */ -int fan_is_stalled(int ch) -{ - /* Must be enabled with non-zero target to stall */ - if (!fan_get_enabled(ch) || - fan_get_rpm_target(ch) == 0 || - !fan_get_duty(ch)) - return 0; - - /* Check for stall condition */ - return fan_get_status(ch) == FAN_STATUS_STOPPED; -} - -void fan_channel_setup(int ch, unsigned int flags) -{ - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - if (tach_ch < TACH_CH_COUNT) - fan_info_data[tach_ch].flags = flags; -} - -static void fan_ctrl(int ch) -{ - int status = -1, adjust = 0; - int rpm_actual, rpm_target, rpm_re, duty; - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS; - if (fan_info_data[tach_ch].fan_ms_idx > - fan_info_data[tach_ch].fan_ms) { - fan_info_data[tach_ch].fan_ms_idx = 0x00; - adjust = 1; - } - - if (adjust) { - /* get current pwm output duty */ - duty = fan_get_duty(ch); - - /* rpm mode */ - if (fan_info_data[tach_ch].fan_mode) { - rpm_actual = fan_info_data[tach_ch].rpm_actual; - rpm_target = fan_info_data[tach_ch].rpm_target; - rpm_re = fan_info_data[tach_ch].rpm_re; - - if (rpm_actual < (rpm_target - rpm_re)) { - if (duty == 100) { - status = FAN_DUTY_OV; - } else { - if (duty == 0) - fan_init_start(ch); - - pwm_duty_inc(ch); - status = FAN_DUTY_I; - } - } else if (rpm_actual > (rpm_target + rpm_re)) { - if (duty == 0) { - status = FAN_DUTY_OV; - } else { - pwm_duty_reduce(ch); - status = FAN_DUTY_R; - } - } else { - status = FAN_DUTY_DONE; - } - } else { - fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED; - } - - if (status == FAN_DUTY_DONE) { - fan_info_data[tach_ch].fan_sts = FAN_STATUS_LOCKED; - } else if ((status == FAN_DUTY_I) || (status == FAN_DUTY_R)) { - fan_info_data[tach_ch].fan_sts = FAN_STATUS_CHANGING; - } else if (status == FAN_DUTY_OV) { - fan_info_data[tach_ch].fan_sts = FAN_STATUS_FRUSTRATED; - - if (!fan_info_data[tach_ch].rpm_actual && duty) - fan_info_data[tach_ch].fan_sts = - FAN_STATUS_STOPPED; - } - } -} - -static int tach_ch_valid(enum tach_ch_sel tach_ch) -{ - int valid = 0; - - switch (tach_ch) { - case TACH_CH_TACH0A: - if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x08) - valid = 1; - break; - case TACH_CH_TACH1A: - if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x02) - valid = 1; - break; - case TACH_CH_TACH0B: - if ((IT83XX_PWM_TSWCTRL & 0x0C) == 0x0C) - valid = 1; - break; - case TACH_CH_TACH1B: - if ((IT83XX_PWM_TSWCTRL & 0x03) == 0x03) - valid = 1; - break; - default: - break; - } - - return valid; -} - -static int get_tach0_rpm(int fan_p) -{ - uint16_t rpm; - - /* TACH0A / TACH0B data is valid */ - if (IT83XX_PWM_TSWCTRL & 0x08) { - rpm = (IT83XX_PWM_F1TMRR << 8) | IT83XX_PWM_F1TLRR; - - if (rpm) - rpm = TACH0_TO_RPM(fan_p, rpm); - - /* W/C */ - IT83XX_PWM_TSWCTRL |= 0x08; - return rpm; - } - return -1; -} - -static int get_tach1_rpm(int fan_p) -{ - uint16_t rpm; - - /* TACH1A / TACH1B data is valid */ - if (IT83XX_PWM_TSWCTRL & 0x02) { - rpm = (IT83XX_PWM_F2TMRR << 8) | IT83XX_PWM_F2TLRR; - - if (rpm) - rpm = TACH1_TO_RPM(fan_p, rpm); - - /* W/C */ - IT83XX_PWM_TSWCTRL |= 0x02; - return rpm; - } - return -1; -} - -static void proc_tach(int ch) -{ - int t_rpm; - enum tach_ch_sel tach_ch; - - tach_ch = tach_bind(ch); - - /* tachometer data valid */ - if (tach_ch_valid(tach_ch)) { - if ((tach_ch == TACH_CH_TACH0A) || (tach_ch == TACH_CH_TACH0B)) - t_rpm = get_tach0_rpm(fan_info_data[tach_ch].fan_p); - else - t_rpm = get_tach1_rpm(fan_info_data[tach_ch].fan_p); - - fan_info_data[tach_ch].rpm_actual = t_rpm; - fan_set_interval(ch); - fan_info_data[tach_ch].tach_valid_ms = 0; - } else { - fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS; - if (fan_info_data[tach_ch].tach_valid_ms > - TACH_DATA_VALID_TIMEOUT_MS) - fan_info_data[tach_ch].rpm_actual = 0; - } -} - -void fan_ext_timer_interrupt(void) -{ - int fan; - - task_clear_pending_irq(et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq); - - for (fan = 0; fan < fan_get_count(); fan++) { - if (fan_get_enabled(FAN_CH(fan))) { - proc_tach(FAN_CH(fan)); - fan_ctrl(FAN_CH(fan)); - } - } -} - -static void fan_init(void) -{ - int ch, rpm_re, fan_p, s_duty; - enum tach_ch_sel tach_ch; - - for (ch = 0; ch < fan_get_count(); ch++) { - - rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re; - fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p; - s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty; - tach_ch = tach_bind(FAN_CH(ch)); - - if (tach_ch < TACH_CH_COUNT) { - - if (tach_ch == TACH_CH_TACH0B) { - /* GPJ2 will select TACH0B as its alt. */ - IT83XX_GPIO_GRC5 |= 0x01; - /* bit2, to select TACH0B */ - IT83XX_PWM_TSWCTRL |= 0x04; - } else if (tach_ch == TACH_CH_TACH1B) { - /* GPJ3 will select TACH1B as its alt. */ - IT83XX_GPIO_GRC5 |= 0x02; - /* bit0, to select TACH1B */ - IT83XX_PWM_TSWCTRL |= 0x01; - } - - fan_info_data[tach_ch].flags = 0; - fan_info_data[tach_ch].fan_mode = 0; - fan_info_data[tach_ch].rpm_target = 0; - fan_info_data[tach_ch].rpm_actual = 0; - fan_info_data[tach_ch].tach_valid_ms = 0; - fan_info_data[tach_ch].fan_ms_idx = 0; - fan_info_data[tach_ch].enabled = 0; - fan_info_data[tach_ch].fan_p = fan_p; - fan_info_data[tach_ch].rpm_re = rpm_re; - fan_info_data[tach_ch].fan_ms = FAN_CTRL_BASED_MS; - fan_info_data[tach_ch].fan_sts = FAN_STATUS_STOPPED; - fan_info_data[tach_ch].startup_duty = s_duty; - } - } - - /* init external timer for fan control */ - ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0, - FAN_CTRL_BASED_MS, 1, 0); -} -DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN); diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c deleted file mode 100644 index 40f16ac08e..0000000000 --- a/chip/it83xx/flash.c +++ /dev/null @@ -1,725 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "flash_chip.h" -#include "host_command.h" -#include "intc.h" -#include "system.h" -#include "util.h" -#include "watchdog.h" -#include "registers.h" -#include "task.h" -#include "shared_mem.h" -#include "uart.h" - -#define FLASH_DMA_START ((uint32_t) &__flash_dma_start) -#define FLASH_DMA_CODE __attribute__((section(".flash_direct_map"))) - -/* erase size of sector is 1KB or 4KB */ -#define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE - -#ifdef IT83XX_CHIP_FLASH_IS_KGD -/* page program command */ -#define FLASH_CMD_PAGE_WRITE 0x2 -/* ector erase command (erase size is 4KB) */ -#define FLASH_CMD_SECTOR_ERASE 0x20 -/* command for flash write */ -#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE -#else -/* Auto address increment programming */ -#define FLASH_CMD_AAI_WORD 0xAD -/* Flash sector erase (1K bytes) command */ -#define FLASH_CMD_SECTOR_ERASE 0xD7 -/* command for flash write */ -#define FLASH_CMD_WRITE FLASH_CMD_AAI_WORD -#endif -/* Write status register */ -#define FLASH_CMD_WRSR 0x01 -/* Write disable */ -#define FLASH_CMD_WRDI 0x04 -/* Write enable */ -#define FLASH_CMD_WREN 0x06 -/* Read status register */ -#define FLASH_CMD_RS 0x05 - -#define FLASH_TEXT_START ((uint32_t) &__flash_text_start) -/* The default tag index of immu. */ -#define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000 -/* immu cache size is 8K bytes. */ -#define IMMU_SIZE 0x2000 - -#if CONFIG_FLASH_SIZE == 0x80000 -/* Apply workaround of the issue (b:111808417) */ -#define IMMU_CACHE_TAG_INVALID -#endif - -static int stuck_locked; -static int inconsistent_locked; -static int all_protected; -static int flash_dma_code_enabled; - -#define FWP_REG(bank) (bank / 8) -#define FWP_MASK(bank) (1 << (bank % 8)) - -enum flash_wp_interface { - FLASH_WP_HOST = 0x01, - FLASH_WP_DBGR = 0x02, - FLASH_WP_EC = 0x04, -}; - -enum flash_wp_status { - FLASH_WP_STATUS_PROTECT_RO = EC_FLASH_PROTECT_RO_NOW, - FLASH_WP_STATUS_PROTECT_ALL = EC_FLASH_PROTECT_ALL_NOW, -}; - -enum flash_status_mask { - FLASH_SR_NO_BUSY = 0, - /* Internal write operation is in progress */ - FLASH_SR_BUSY = 0x01, - /* Device is memory Write enabled */ - FLASH_SR_WEL = 0x02, - - FLASH_SR_ALL = (FLASH_SR_BUSY | FLASH_SR_WEL), -}; - -enum dlm_address_view { - SCAR0_ILM0_DLM13 = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */ - SCAR1_ILM1_DLM11 = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */ - SCAR2_ILM2_DLM14 = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */ - SCAR3_ILM3_DLM6 = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */ - SCAR4_ILM4_DLM7 = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */ - SCAR5_ILM5_DLM8 = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */ - SCAR6_ILM6_DLM9 = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */ - SCAR7_ILM7_DLM10 = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */ - SCAR8_ILM8_DLM4 = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */ - SCAR9_ILM9_DLM5 = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */ - SCAR10_ILM10_DLM2 = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */ - SCAR11_ILM11_DLM3 = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */ - SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */ -}; - -void FLASH_DMA_CODE dma_reset_immu(int fill_immu) -{ - /* Immu tag sram reset */ - IT83XX_GCTRL_MCCR |= 0x10; - /* Make sure the immu(dynamic cache) is reset */ - data_serialization_barrier(); - - IT83XX_GCTRL_MCCR &= ~0x10; - data_serialization_barrier(); - -#ifdef IMMU_CACHE_TAG_INVALID - /* - * Workaround for (b:111808417): - * After immu reset, we will fill the immu cache with 8KB data - * that are outside address 0x7e000 ~ 0x7ffff. - * When CPU tries to fetch contents from address 0x7e000 ~ 0x7ffff, - * immu will re-fetch the missing contents inside 0x7e000 ~ 0x7ffff. - */ - if (fill_immu) { - volatile int immu __unused; - const uint32_t *ptr = (uint32_t *)FLASH_TEXT_START; - int i = 0; - - while (i < IMMU_SIZE) { - immu = *ptr++; - i += sizeof(*ptr); - } - } -#endif -} - -void FLASH_DMA_CODE dma_flash_follow_mode(void) -{ - /* - * ECINDAR3-0 are EC-indirect memory address registers. - * - * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register, - * and set high nibble as 0x4 to select internal flash. - */ - IT83XX_SMFI_ECINDAR3 = (EC_INDIRECT_READ_INTERNAL_FLASH | 0xf); - /* Set FSCE# as high level by writing 0 to address xfff_fe00h */ - IT83XX_SMFI_ECINDAR2 = 0xFF; - IT83XX_SMFI_ECINDAR1 = 0xFE; - IT83XX_SMFI_ECINDAR0 = 0x00; - /* EC-indirect memory data register */ - IT83XX_SMFI_ECINDDR = 0x00; -} - -void FLASH_DMA_CODE dma_flash_follow_mode_exit(void) -{ - /* Exit follow mode, and keep the setting of selecting internal flash */ - IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH; - IT83XX_SMFI_ECINDAR2 = 0x00; -} - -void FLASH_DMA_CODE dma_flash_fsce_high(void) -{ - /* FSCE# high level */ - IT83XX_SMFI_ECINDAR1 = 0xFE; - IT83XX_SMFI_ECINDDR = 0x00; -} - -uint8_t FLASH_DMA_CODE dma_flash_read_dat(void) -{ - /* Read data from FMISO */ - return IT83XX_SMFI_ECINDDR; -} - -void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata) -{ - /* Write data to FMOSI */ - IT83XX_SMFI_ECINDDR = wdata; -} - -void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, - int rlen, uint8_t *rbuf, int cmd_end) -{ - int i; - - /* FSCE# with low level */ - IT83XX_SMFI_ECINDAR1 = 0xFD; - /* Write data to FMOSI */ - for (i = 0; i < wlen; i++) - IT83XX_SMFI_ECINDDR = wbuf[i]; - /* Read data from FMISO */ - for (i = 0; i < rlen; i++) - rbuf[i] = IT83XX_SMFI_ECINDDR; - - /* FSCE# high level if transaction done */ - if (cmd_end) - dma_flash_fsce_high(); -} - -void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask, - enum flash_status_mask target) -{ - uint8_t status[1]; - uint8_t cmd_rs[] = {FLASH_CMD_RS}; - - /* - * We prefer no timeout here. We can always get the status - * we want, or wait for watchdog triggered to check - * e-flash's status instead of breaking loop. - * This will avoid fetching unknown instruction from e-flash - * and causing exception. - */ - while (1) { - /* read status */ - dma_flash_transaction(sizeof(cmd_rs), cmd_rs, 1, status, 1); - /* only bit[1:0] valid */ - if ((status[0] & mask) == target) - break; - } -} - -void FLASH_DMA_CODE dma_flash_cmd_write_enable(void) -{ - uint8_t cmd_we[] = {FLASH_CMD_WREN}; - - /* enter EC-indirect follow mode */ - dma_flash_follow_mode(); - /* send write enable command */ - dma_flash_transaction(sizeof(cmd_we), cmd_we, 0, NULL, 1); - /* read status and make sure busy bit cleared and write enabled. */ - dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL); - /* exit EC-indirect follow mode */ - dma_flash_follow_mode_exit(); -} - -void FLASH_DMA_CODE dma_flash_cmd_write_disable(void) -{ - uint8_t cmd_wd[] = {FLASH_CMD_WRDI}; - - /* enter EC-indirect follow mode */ - dma_flash_follow_mode(); - /* send write disable command */ - dma_flash_transaction(sizeof(cmd_wd), cmd_wd, 0, NULL, 1); - /* make sure busy bit cleared. */ - dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_NO_BUSY); - /* exit EC-indirect follow mode */ - dma_flash_follow_mode_exit(); -} - -void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd) -{ - uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF), - ((addr >> 8) & 0xFF), (addr & 0xFF)}; - - /* enter EC-indirect follow mode */ - dma_flash_follow_mode(); - /* send erase command */ - dma_flash_transaction(sizeof(cmd_erase), cmd_erase, 0, NULL, 1); - /* make sure busy bit cleared. */ - dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY); - /* exit EC-indirect follow mode */ - dma_flash_follow_mode_exit(); -} - -void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf) -{ - int i; - uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF), - ((addr >> 8) & 0xFF), (addr & 0xFF)}; - - /* enter EC-indirect follow mode */ - dma_flash_follow_mode(); - /* send flash write command (aai word or page program) */ - dma_flash_transaction(sizeof(flash_write), flash_write, 0, NULL, 0); -#ifdef IT83XX_CHIP_FLASH_IS_KGD - for (i = 0; i < wlen; i++) { - /* send data byte */ - dma_flash_write_dat(wbuf[i]); - - /* - * we want to restart the write sequence every IDEAL_SIZE - * chunk worth of data. - */ - if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) { - uint8_t w_en[] = {FLASH_CMD_WREN}; - - dma_flash_fsce_high(); - /* make sure busy bit cleared. */ - dma_flash_cmd_read_status(FLASH_SR_BUSY, - FLASH_SR_NO_BUSY); - /* send write enable command */ - dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1); - /* make sure busy bit cleared and write enabled. */ - dma_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL); - /* re-send write command */ - flash_write[1] = (addr >> 16) & 0xff; - flash_write[2] = (addr >> 8) & 0xff; - flash_write[3] = addr & 0xff; - dma_flash_transaction(sizeof(flash_write), flash_write, - 0, NULL, 0); - } - } - dma_flash_fsce_high(); - /* make sure busy bit cleared. */ - dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY); -#else - for (i = 0; i < wlen; i += 2) { - dma_flash_write_dat(wbuf[i]); - dma_flash_write_dat(wbuf[i + 1]); - dma_flash_fsce_high(); - /* make sure busy bit cleared. */ - dma_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY); - /* resend aai word command without address field */ - if ((i + 2) < wlen) - dma_flash_transaction(1, flash_write, 0, NULL, 0); - } -#endif - /* exit EC-indirect follow mode */ - dma_flash_follow_mode_exit(); -} - -uint8_t FLASH_DMA_CODE dma_flash_indirect_fast_read(int addr) -{ - IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH; - IT83XX_SMFI_ECINDAR2 = (addr >> 16) & 0xFF; - IT83XX_SMFI_ECINDAR1 = (addr >> 8) & 0xFF; - IT83XX_SMFI_ECINDAR0 = (addr & 0xFF); - - return IT83XX_SMFI_ECINDDR; -} - -int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data) -{ - int i; - uint8_t *wbuf = (uint8_t *)data; - uint8_t *flash = (uint8_t *)addr; - - /* verify for erase */ - if (data == NULL) { - for (i = 0; i < size; i++) { - if (flash[i] != 0xFF) - return EC_ERROR_UNKNOWN; - } - /* verify for write */ - } else { - for (i = 0; i < size; i++) { - if (flash[i] != wbuf[i]) - return EC_ERROR_UNKNOWN; - } - } - - return EC_SUCCESS; -} - -void FLASH_DMA_CODE dma_flash_write(int addr, int wlen, const char *wbuf) -{ - dma_flash_cmd_write_enable(); - dma_flash_cmd_write(addr, wlen, (uint8_t *)wbuf); - dma_flash_cmd_write_disable(); -} - -void FLASH_DMA_CODE dma_flash_erase(int addr, int cmd) -{ - dma_flash_cmd_write_enable(); - dma_flash_cmd_erase(addr, cmd); - dma_flash_cmd_write_disable(); -} - -static enum flash_wp_status flash_check_wp(void) -{ - enum flash_wp_status wp_status; - int all_bank_count, bank; - - all_bank_count = CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE; - - for (bank = 0; bank < all_bank_count; bank++) { - if (!(IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank))) - break; - } - - if (bank == WP_BANK_COUNT) - wp_status = FLASH_WP_STATUS_PROTECT_RO; - else if (bank == (WP_BANK_COUNT + PSTATE_BANK_COUNT)) - wp_status = FLASH_WP_STATUS_PROTECT_RO; - else if (bank == all_bank_count) - wp_status = FLASH_WP_STATUS_PROTECT_ALL; - else - wp_status = 0; - - return wp_status; -} - -/** - * Protect flash banks until reboot. - * - * @param start_bank Start bank to protect - * @param bank_count Number of banks to protect - */ -static void flash_protect_banks(int start_bank, - int bank_count, - enum flash_wp_interface wp_if) -{ - int bank; - - for (bank = start_bank; bank < start_bank + bank_count; bank++) { - if (wp_if & FLASH_WP_EC) - IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank); - if (wp_if & FLASH_WP_HOST) - IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank); - if (wp_if & FLASH_WP_DBGR) - IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank); - } -} - -int FLASH_DMA_CODE flash_physical_read(int offset, int size, char *data) -{ - int i; - - for (i = 0; i < size; i++) { - data[i] = dma_flash_indirect_fast_read(offset); - offset++; - } - - return EC_SUCCESS; -} - -/** - * Write to physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Data to write to flash. Must be 32-bit aligned. - */ -int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data) -{ - int ret = EC_ERROR_UNKNOWN; - - if (flash_dma_code_enabled == 0) - return EC_ERROR_ACCESS_DENIED; - - if (all_protected) - return EC_ERROR_ACCESS_DENIED; - - watchdog_reload(); - - /* - * CPU can't fetch instruction from flash while use - * EC-indirect follow mode to access flash, interrupts need to be - * disabled. - */ - interrupt_disable(); - - dma_flash_write(offset, size, data); - dma_reset_immu((offset + size) >= IMMU_TAG_INDEX_BY_DEFAULT); - ret = dma_flash_verify(offset, size, data); - - interrupt_enable(); - - return ret; -} - -/** - * Erase physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE. - * - * @param offset Flash offset to erase. - * @param size Number of bytes to erase. - */ -int FLASH_DMA_CODE flash_physical_erase(int offset, int size) -{ - int v_size = size, v_addr = offset, ret = EC_ERROR_UNKNOWN; - - if (flash_dma_code_enabled == 0) - return EC_ERROR_ACCESS_DENIED; - - if (all_protected) - return EC_ERROR_ACCESS_DENIED; - - /* - * CPU can't fetch instruction from flash while use - * EC-indirect follow mode to access flash, interrupts need to be - * disabled. - */ - interrupt_disable(); - - /* Always use sector erase command (1K or 4K bytes) */ - for (; size > 0; size -= FLASH_SECTOR_ERASE_SIZE) { - dma_flash_erase(offset, FLASH_CMD_SECTOR_ERASE); - offset += FLASH_SECTOR_ERASE_SIZE; - } - dma_reset_immu((v_addr + v_size) >= IMMU_TAG_INDEX_BY_DEFAULT); - ret = dma_flash_verify(v_addr, v_size, NULL); - - interrupt_enable(); - - return ret; -} - -/** - * Read physical write protect setting for a flash bank. - * - * @param bank Bank index to check. - * @return non-zero if bank is protected until reboot. - */ -int flash_physical_get_protect(int bank) -{ - return IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) & FWP_MASK(bank); -} - -/** - * Protect flash now. - * - * @param all Protect all (=1) or just read-only and pstate (=0). - * @return non-zero if error. - */ -int flash_physical_protect_now(int all) -{ - if (all) { - /* Protect the entire flash */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, - FLASH_WP_EC); - all_protected = 1; - } else { - /* Protect the read-only section and persistent state */ - flash_protect_banks(WP_BANK_OFFSET, - WP_BANK_COUNT, FLASH_WP_EC); -#ifdef PSTATE_BANK - flash_protect_banks(PSTATE_BANK, - PSTATE_BANK_COUNT, FLASH_WP_EC); -#endif - } - - /* - * bit[0], eflash protect lock register which can only be write 1 and - * only be cleared by power-on reset. - */ - IT83XX_GCTRL_EPLR |= 0x01; - - return EC_SUCCESS; -} - -/** - * Return flash protect state flags from the physical layer. - * - * This should only be called by flash_get_protect(). - * - * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - flags |= flash_check_wp(); - - if (all_protected) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - /* Check if blocks were stuck locked at pre-init */ - if (stuck_locked) - flags |= EC_FLASH_PROTECT_ERROR_STUCK; - - /* Check if flash protection is in inconsistent state at pre-init */ - if (inconsistent_locked) - flags |= EC_FLASH_PROTECT_ERROR_INCONSISTENT; - - return flags; -} - -/** - * Return the valid flash protect flags. - * - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -/** - * Return the writable flash protect flags. - * - * @param cur_flags The current flash protect flags. - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -static void flash_code_static_dma(void) -{ - - /* Make sure no interrupt while enable static DMA */ - interrupt_disable(); - - /* invalid static DMA first */ - if (IS_ENABLED(CHIP_CORE_RISCV)) - IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM2_ENABLE; - IT83XX_SMFI_SCAR2H = 0x08; - - /* Copy to DLM */ - IT83XX_GCTRL_MCCR2 |= 0x20; - memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START, - IT83XX_ILM_BLOCK_SIZE); - if (IS_ENABLED(CHIP_CORE_RISCV)) - IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE; - IT83XX_GCTRL_MCCR2 &= ~0x20; - - /* - * Enable ILM - * Set the logic memory address(flash code of RO/RW) in eflash - * by programming the register SCARx bit19-bit0. - */ - IT83XX_SMFI_SCAR2L = FLASH_DMA_START & 0xFF; - IT83XX_SMFI_SCAR2M = (FLASH_DMA_START >> 8) & 0xFF; - IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x0F; - /* - * Validate Direct-map SRAM function by programming - * register SCARx bit20=0 - */ - IT83XX_SMFI_SCAR2H &= ~0x10; - - flash_dma_code_enabled = 0x01; - - interrupt_enable(); -} - -/** - * Initialize the module. - * - * Applies at-boot protection settings if necessary. - */ -int flash_pre_init(void) -{ - int32_t reset_flags, prot_flags, unwanted_prot_flags; - - /* By default, select internal flash for indirect fast read. */ - IT83XX_SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH; - if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD)) - IT83XX_SMFI_FLHCTRL6R |= IT83XX_SMFI_MASK_ECINDPP; - flash_code_static_dma(); - - reset_flags = system_get_reset_flags(); - prot_flags = flash_get_protect(); - unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - /* Protect the entire flash of host interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, - FLASH_WP_HOST); - /* Protect the entire flash of DBGR interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE, - FLASH_WP_DBGR); - /* - * Write protect is asserted. If we want RO flash protected, - * protect it now. - */ - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); - if (rv) - return rv; - - /* Re-read flags */ - prot_flags = flash_get_protect(); - } - } else { - /* Don't want RO flash protected */ - unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW; - } - - /* If there are no unwanted flags, done */ - if (!(prot_flags & unwanted_prot_flags)) - return EC_SUCCESS; - - /* - * If the last reboot was a power-on reset, it should have cleared - * write-protect. If it didn't, then the flash write protect registers - * have been permanently committed and we can't fix that. - */ - if (reset_flags & EC_RESET_FLAG_POWER_ON) { - stuck_locked = 1; - return EC_ERROR_ACCESS_DENIED; - } else { - /* - * Set inconsistent flag, because there is no software - * reset can clear write-protect. - */ - inconsistent_locked = 1; - return EC_ERROR_ACCESS_DENIED; - } - - /* That doesn't return, so if we're still here that's an error */ - return EC_ERROR_UNKNOWN; -} diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h deleted file mode 100644 index 4a604ed7f7..0000000000 --- a/chip/it83xx/flash_chip.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_FLASH_CHIP_H -#define __CROS_EC_FLASH_CHIP_H - -/* - * This symbol is defined in linker script and used to provide the begin - * address of the ram code section. With this address, we can enable a ILM - * (4K bytes static code cache) for ram code section. - */ -extern const char __flash_dma_start; - -/* This symbol is the begin address of the text section. */ -extern const char __flash_text_start; - -#endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c deleted file mode 100644 index 24947cca59..0000000000 --- a/chip/it83xx/gpio.c +++ /dev/null @@ -1,766 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "intc.h" -#include "kmsc_chip.h" -#include "registers.h" -#include "switch.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/** - * Convert wake-up controller (WUC) group to the corresponding wake-up edge - * sense register (WUESR). Return pointer to the register. - * - * @param grp WUC group. - * - * @return Pointer to corresponding WUESR register. - */ -static volatile uint8_t *wuesr(uint8_t grp) -{ - /* - * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on - * the address increases by fours. - */ - return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5)); -} - -/** - * Convert wake-up controller (WUC) group to the corresponding wake-up edge - * mode register (WUEMR). Return pointer to the register. - * - * @param grp WUC group. - * - * @return Pointer to corresponding WUEMR register. - */ -static volatile uint8_t *wuemr(uint8_t grp) -{ - /* - * From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on - * the address increases by fours. - */ - return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5)); -} - -/** - * Convert wake-up controller (WUC) group to the corresponding wake-up both edge - * mode register (WUBEMR). Return pointer to the register. - * - * @param grp WUC group. - * - * @return Pointer to corresponding WUBEMR register. - */ -#ifdef IT83XX_GPIO_INT_FLEXIBLE -static volatile uint8_t *wubemr(uint8_t grp) -{ - /* - * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on - * the address increases by fours. - */ - return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5)); -} -#endif - -/* - * Array to store the corresponding GPIO port and mask, and WUC group and mask - * for each WKO interrupt. This allows GPIO interrupts coming in through WKO - * to easily identify which pin caused the interrupt. - * Note: Using designated initializers here in addition to using the array size - * assert because many rows are purposely skipped. Not all IRQs are WKO IRQs, - * so the IRQ index skips around. But, we still want the entire array to take - * up the size of the total number of IRQs because the index to the array could - * be any IRQ number. - */ -static const struct { - uint8_t gpio_port; - uint8_t gpio_mask; - uint8_t wuc_group; - uint8_t wuc_mask; -} gpio_irqs[] = { - /* irq gpio_port,gpio_mask,wuc_group,wuc_mask */ - [IT83XX_IRQ_WKO20] = {GPIO_D, BIT(0), 2, BIT(0)}, - [IT83XX_IRQ_WKO21] = {GPIO_D, BIT(1), 2, BIT(1)}, - [IT83XX_IRQ_WKO22] = {GPIO_C, BIT(4), 2, BIT(2)}, - [IT83XX_IRQ_WKO23] = {GPIO_C, BIT(6), 2, BIT(3)}, - [IT83XX_IRQ_WKO24] = {GPIO_D, BIT(2), 2, BIT(4)}, -#ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO40] = {GPIO_E, BIT(5), 4, BIT(0)}, - [IT83XX_IRQ_WKO45] = {GPIO_E, BIT(6), 4, BIT(5)}, - [IT83XX_IRQ_WKO46] = {GPIO_E, BIT(7), 4, BIT(6)}, -#endif - [IT83XX_IRQ_WKO50] = {GPIO_K, BIT(0), 5, BIT(0)}, - [IT83XX_IRQ_WKO51] = {GPIO_K, BIT(1), 5, BIT(1)}, - [IT83XX_IRQ_WKO52] = {GPIO_K, BIT(2), 5, BIT(2)}, - [IT83XX_IRQ_WKO53] = {GPIO_K, BIT(3), 5, BIT(3)}, - [IT83XX_IRQ_WKO54] = {GPIO_K, BIT(4), 5, BIT(4)}, - [IT83XX_IRQ_WKO55] = {GPIO_K, BIT(5), 5, BIT(5)}, - [IT83XX_IRQ_WKO56] = {GPIO_K, BIT(6), 5, BIT(6)}, - [IT83XX_IRQ_WKO57] = {GPIO_K, BIT(7), 5, BIT(7)}, - [IT83XX_IRQ_WKO60] = {GPIO_H, BIT(0), 6, BIT(0)}, - [IT83XX_IRQ_WKO61] = {GPIO_H, BIT(1), 6, BIT(1)}, - [IT83XX_IRQ_WKO62] = {GPIO_H, BIT(2), 6, BIT(2)}, - [IT83XX_IRQ_WKO63] = {GPIO_H, BIT(3), 6, BIT(3)}, - [IT83XX_IRQ_WKO64] = {GPIO_F, BIT(4), 6, BIT(4)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(5), 6, BIT(5)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(6), 6, BIT(6)}, - [IT83XX_IRQ_WKO67] = {GPIO_F, BIT(7), 6, BIT(7)}, - [IT83XX_IRQ_WKO70] = {GPIO_E, BIT(0), 7, BIT(0)}, - [IT83XX_IRQ_WKO71] = {GPIO_E, BIT(1), 7, BIT(1)}, - [IT83XX_IRQ_WKO72] = {GPIO_E, BIT(2), 7, BIT(2)}, - [IT83XX_IRQ_WKO73] = {GPIO_E, BIT(3), 7, BIT(3)}, - [IT83XX_IRQ_WKO74] = {GPIO_I, BIT(4), 7, BIT(4)}, - [IT83XX_IRQ_WKO75] = {GPIO_I, BIT(5), 7, BIT(5)}, - [IT83XX_IRQ_WKO76] = {GPIO_I, BIT(6), 7, BIT(6)}, - [IT83XX_IRQ_WKO77] = {GPIO_I, BIT(7), 7, BIT(7)}, - [IT83XX_IRQ_WKO80] = {GPIO_A, BIT(3), 8, BIT(0)}, - [IT83XX_IRQ_WKO81] = {GPIO_A, BIT(4), 8, BIT(1)}, - [IT83XX_IRQ_WKO82] = {GPIO_A, BIT(5), 8, BIT(2)}, - [IT83XX_IRQ_WKO83] = {GPIO_A, BIT(6), 8, BIT(3)}, - [IT83XX_IRQ_WKO84] = {GPIO_B, BIT(2), 8, BIT(4)}, - [IT83XX_IRQ_WKO85] = {GPIO_C, BIT(0), 8, BIT(5)}, - [IT83XX_IRQ_WKO86] = {GPIO_C, BIT(7), 8, BIT(6)}, - [IT83XX_IRQ_WKO87] = {GPIO_D, BIT(7), 8, BIT(7)}, - [IT83XX_IRQ_WKO88] = {GPIO_H, BIT(4), 9, BIT(0)}, - [IT83XX_IRQ_WKO89] = {GPIO_H, BIT(5), 9, BIT(1)}, - [IT83XX_IRQ_WKO90] = {GPIO_H, BIT(6), 9, BIT(2)}, - [IT83XX_IRQ_WKO91] = {GPIO_A, BIT(0), 9, BIT(3)}, - [IT83XX_IRQ_WKO92] = {GPIO_A, BIT(1), 9, BIT(4)}, - [IT83XX_IRQ_WKO93] = {GPIO_A, BIT(2), 9, BIT(5)}, - [IT83XX_IRQ_WKO94] = {GPIO_B, BIT(4), 9, BIT(6)}, - [IT83XX_IRQ_WKO95] = {GPIO_C, BIT(2), 9, BIT(7)}, - [IT83XX_IRQ_WKO96] = {GPIO_F, BIT(0), 10, BIT(0)}, - [IT83XX_IRQ_WKO97] = {GPIO_F, BIT(1), 10, BIT(1)}, - [IT83XX_IRQ_WKO98] = {GPIO_F, BIT(2), 10, BIT(2)}, - [IT83XX_IRQ_WKO99] = {GPIO_F, BIT(3), 10, BIT(3)}, - [IT83XX_IRQ_WKO100] = {GPIO_A, BIT(7), 10, BIT(4)}, - [IT83XX_IRQ_WKO101] = {GPIO_B, BIT(0), 10, BIT(5)}, - [IT83XX_IRQ_WKO102] = {GPIO_B, BIT(1), 10, BIT(6)}, - [IT83XX_IRQ_WKO103] = {GPIO_B, BIT(3), 10, BIT(7)}, - [IT83XX_IRQ_WKO104] = {GPIO_B, BIT(5), 11, BIT(0)}, - [IT83XX_IRQ_WKO105] = {GPIO_B, BIT(6), 11, BIT(1)}, - [IT83XX_IRQ_WKO106] = {GPIO_B, BIT(7), 11, BIT(2)}, - [IT83XX_IRQ_WKO107] = {GPIO_C, BIT(1), 11, BIT(3)}, - [IT83XX_IRQ_WKO108] = {GPIO_C, BIT(3), 11, BIT(4)}, - [IT83XX_IRQ_WKO109] = {GPIO_C, BIT(5), 11, BIT(5)}, - [IT83XX_IRQ_WKO110] = {GPIO_D, BIT(3), 11, BIT(6)}, - [IT83XX_IRQ_WKO111] = {GPIO_D, BIT(4), 11, BIT(7)}, - [IT83XX_IRQ_WKO112] = {GPIO_D, BIT(5), 12, BIT(0)}, - [IT83XX_IRQ_WKO113] = {GPIO_D, BIT(6), 12, BIT(1)}, - [IT83XX_IRQ_WKO114] = {GPIO_E, BIT(4), 12, BIT(2)}, - [IT83XX_IRQ_WKO115] = {GPIO_G, BIT(0), 12, BIT(3)}, - [IT83XX_IRQ_WKO116] = {GPIO_G, BIT(1), 12, BIT(4)}, - [IT83XX_IRQ_WKO117] = {GPIO_G, BIT(2), 12, BIT(5)}, - [IT83XX_IRQ_WKO118] = {GPIO_G, BIT(6), 12, BIT(6)}, - [IT83XX_IRQ_WKO119] = {GPIO_I, BIT(0), 12, BIT(7)}, - [IT83XX_IRQ_WKO120] = {GPIO_I, BIT(1), 13, BIT(0)}, - [IT83XX_IRQ_WKO121] = {GPIO_I, BIT(2), 13, BIT(1)}, - [IT83XX_IRQ_WKO122] = {GPIO_I, BIT(3), 13, BIT(2)}, -#ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO123] = {GPIO_G, BIT(3), 13, BIT(3)}, - [IT83XX_IRQ_WKO124] = {GPIO_G, BIT(4), 13, BIT(4)}, - [IT83XX_IRQ_WKO125] = {GPIO_G, BIT(5), 13, BIT(5)}, - [IT83XX_IRQ_WKO126] = {GPIO_G, BIT(7), 13, BIT(6)}, -#endif - [IT83XX_IRQ_WKO128] = {GPIO_J, BIT(0), 14, BIT(0)}, - [IT83XX_IRQ_WKO129] = {GPIO_J, BIT(1), 14, BIT(1)}, - [IT83XX_IRQ_WKO130] = {GPIO_J, BIT(2), 14, BIT(2)}, - [IT83XX_IRQ_WKO131] = {GPIO_J, BIT(3), 14, BIT(3)}, - [IT83XX_IRQ_WKO132] = {GPIO_J, BIT(4), 14, BIT(4)}, - [IT83XX_IRQ_WKO133] = {GPIO_J, BIT(5), 14, BIT(5)}, - [IT83XX_IRQ_WKO134] = {GPIO_J, BIT(6), 14, BIT(6)}, - [IT83XX_IRQ_WKO136] = {GPIO_L, BIT(0), 15, BIT(0)}, - [IT83XX_IRQ_WKO137] = {GPIO_L, BIT(1), 15, BIT(1)}, - [IT83XX_IRQ_WKO138] = {GPIO_L, BIT(2), 15, BIT(2)}, - [IT83XX_IRQ_WKO139] = {GPIO_L, BIT(3), 15, BIT(3)}, - [IT83XX_IRQ_WKO140] = {GPIO_L, BIT(4), 15, BIT(4)}, - [IT83XX_IRQ_WKO141] = {GPIO_L, BIT(5), 15, BIT(5)}, - [IT83XX_IRQ_WKO142] = {GPIO_L, BIT(6), 15, BIT(6)}, - [IT83XX_IRQ_WKO143] = {GPIO_L, BIT(7), 15, BIT(7)}, -#ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO144] = {GPIO_M, BIT(0), 16, BIT(0)}, - [IT83XX_IRQ_WKO145] = {GPIO_M, BIT(1), 16, BIT(1)}, - [IT83XX_IRQ_WKO146] = {GPIO_M, BIT(2), 16, BIT(2)}, - [IT83XX_IRQ_WKO147] = {GPIO_M, BIT(3), 16, BIT(3)}, - [IT83XX_IRQ_WKO148] = {GPIO_M, BIT(4), 16, BIT(4)}, - [IT83XX_IRQ_WKO149] = {GPIO_M, BIT(5), 16, BIT(5)}, - [IT83XX_IRQ_WKO150] = {GPIO_M, BIT(6), 16, BIT(6)}, -#endif -#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [IT83XX_IRQ_GPO0] = {GPIO_O, BIT(0), 19, BIT(0)}, - [IT83XX_IRQ_GPO1] = {GPIO_O, BIT(1), 19, BIT(1)}, - [IT83XX_IRQ_GPO2] = {GPIO_O, BIT(2), 19, BIT(2)}, - [IT83XX_IRQ_GPO3] = {GPIO_O, BIT(3), 19, BIT(3)}, - [IT83XX_IRQ_GPP0] = {GPIO_P, BIT(0), 20, BIT(0)}, - [IT83XX_IRQ_GPP1] = {GPIO_P, BIT(1), 20, BIT(1)}, - [IT83XX_IRQ_GPP2] = {GPIO_P, BIT(2), 20, BIT(2)}, - [IT83XX_IRQ_GPP3] = {GPIO_P, BIT(3), 20, BIT(3)}, - [IT83XX_IRQ_GPP4] = {GPIO_P, BIT(4), 20, BIT(4)}, - [IT83XX_IRQ_GPP5] = {GPIO_P, BIT(5), 20, BIT(5)}, - [IT83XX_IRQ_GPP6] = {GPIO_P, BIT(6), 20, BIT(6)}, - [IT83XX_IRQ_GPQ0] = {GPIO_Q, BIT(0), 21, BIT(0)}, - [IT83XX_IRQ_GPQ1] = {GPIO_Q, BIT(1), 21, BIT(1)}, - [IT83XX_IRQ_GPQ2] = {GPIO_Q, BIT(2), 21, BIT(2)}, - [IT83XX_IRQ_GPQ3] = {GPIO_Q, BIT(3), 21, BIT(3)}, - [IT83XX_IRQ_GPQ4] = {GPIO_Q, BIT(4), 21, BIT(4)}, - [IT83XX_IRQ_GPQ5] = {GPIO_Q, BIT(5), 21, BIT(5)}, - [IT83XX_IRQ_GPR0] = {GPIO_R, BIT(0), 22, BIT(0)}, - [IT83XX_IRQ_GPR1] = {GPIO_R, BIT(1), 22, BIT(1)}, - [IT83XX_IRQ_GPR2] = {GPIO_R, BIT(2), 22, BIT(2)}, - [IT83XX_IRQ_GPR3] = {GPIO_R, BIT(3), 22, BIT(3)}, - [IT83XX_IRQ_GPR4] = {GPIO_R, BIT(4), 22, BIT(4)}, - [IT83XX_IRQ_GPR5] = {GPIO_R, BIT(5), 22, BIT(5)}, -#endif - [IT83XX_IRQ_COUNT] = { 0, 0, 0, 0}, -}; -BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1); - -/** - * Given a GPIO port and mask, find the corresponding WKO interrupt number. - * - * @param port GPIO port - * @param mask GPIO mask - * - * @return IRQ for the WKO interrupt on the corresponding input pin. - */ -static int gpio_to_irq(uint8_t port, uint8_t mask) -{ - int i; - - for (i = 0; i < IT83XX_IRQ_COUNT; i++) { - if (gpio_irqs[i].gpio_port == port && - gpio_irqs[i].gpio_mask == mask) - return i; - } - - return -1; -} - -struct gpio_1p8v_t { - volatile uint8_t *reg; - uint8_t sel; -}; - -static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = { -#ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC24, BIT(1)}, - [6] = {&IT83XX_GPIO_GRC24, BIT(5)}, - [7] = {&IT83XX_GPIO_GRC24, BIT(6)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC19, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC24, BIT(4)} }, - [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, - [4] = {&IT83XX_GPIO_GRC24, BIT(2)}, - [6] = {&IT83XX_GPIO_GRC24, BIT(3)}, - [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(6)}, - [5] = {&IT83XX_GPIO_GRC22, BIT(4)}, - [6] = {&IT83XX_GPIO_GRC22, BIT(5)}, - [7] = {&IT83XX_GPIO_GRC22, BIT(6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, - [1] = {&IT83XX_GPIO_GCR28, BIT(6)}, - [2] = {&IT83XX_GPIO_GCR28, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(2)}, - [5] = {&IT83XX_GPIO_GRC22, BIT(3)}, - [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, - [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)}, - [1] = {&IT83XX_GPIO_GCR28, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, - [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(4)}, - [2] = {&IT83XX_GPIO_GCR28, BIT(3)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(3)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC21, BIT(0)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(7)}, - [6] = {&IT83XX_GPIO_GCR28, BIT(0)} }, - [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, - [4] = {&IT83XX_GPIO_GRC23, BIT(7)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(4)}, - [6] = {&IT83XX_GPIO_GCR27, BIT(5)}, - [7] = {&IT83XX_GPIO_GCR27, BIT(6)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR27, BIT(0)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(1)}, - [6] = {&IT83XX_GPIO_GCR27, BIT(2)} }, - [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR26, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR26, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR26, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR26, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR26, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR26, BIT(6)}, - [7] = {&IT83XX_GPIO_GCR26, BIT(7)} }, - [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR25, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR25, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR25, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR25, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR25, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR25, BIT(6)}, - [7] = {&IT83XX_GPIO_GCR25, BIT(7)} }, -#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR31, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR31, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR31, BIT(3)} }, - [GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR32, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR32, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR32, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR32, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR32, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR32, BIT(6)} }, -#endif -#else - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC24, BIT(1)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC19, BIT(6)} }, - [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, - [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, - [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC21, BIT(0)} }, - [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, - [4] = {&IT83XX_GPIO_GRC23, BIT(7)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(3)} }, -#endif -}; - -static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v) -{ - volatile uint8_t *reg_1p8v = gpio_1p8v_sel[port][pin].reg; - uint8_t sel = gpio_1p8v_sel[port][pin].sel; - - if (reg_1p8v == NULL) - return; - - if (sel_1p8v) - *reg_1p8v |= sel; - else - *reg_1p8v &= ~sel; -} - -static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin, - enum gpio_alternate_func func) -{ - /* - * If func is not ALT_FUNC_NONE, set for alternate function. - * Otherwise, turn the pin into an input as it's default. - */ - if (func != GPIO_ALT_FUNC_NONE) - IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT | - GPCR_PORT_PIN_MODE_INPUT); - else - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT) - & ~GPCR_PORT_PIN_MODE_OUTPUT; -} - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - uint32_t pin = 0; - - /* For each bit high in the mask, set that pin to use alt. func. */ - while (mask > 0) { - if (mask & 1) - it83xx_set_alt_func(port, pin, func); - pin++; - mask >>= 1; - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return (IT83XX_GPIO_DATA(gpio_list[signal].port) & - gpio_list[signal].mask) ? 1 : 0; -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - uint32_t int_mask = get_int_mask(); - - /* critical section with interrupts off */ - interrupt_disable(); - if (value) - IT83XX_GPIO_DATA(gpio_list[signal].port) |= - gpio_list[signal].mask; - else - IT83XX_GPIO_DATA(gpio_list[signal].port) &= - ~gpio_list[signal].mask; - /* restore interrupts */ - set_int_mask(int_mask); -} - -void gpio_kbs_pin_gpio_mode(uint32_t port, uint32_t mask, uint32_t flags) -{ - if (port == GPIO_KSO_H) - IT83XX_KBS_KSOHGCTRL |= mask; - else if (port == GPIO_KSO_L) - IT83XX_KBS_KSOLGCTRL |= mask; - else if (port == GPIO_KSI) - IT83XX_KBS_KSIGCTRL |= mask; -} - -#ifndef IT83XX_GPIO_INT_FLEXIBLE -/* Returns true when the falling trigger bit actually mean both trigger. */ -static int group_falling_is_both(const int group) -{ - return group == 7 || group == 10 || group == 12; -} - -static const char *get_gpio_string(const int port, const int mask) -{ - static char buffer[3]; - int i; - - buffer[0] = port - GPIO_A + 'A'; - buffer[1] = '!'; - - for (i = 0; i < 8; ++i) { - if (mask & BIT(i)) { - buffer[1] = i + '0'; - break; - } - } - return buffer; -} -#endif /* IT83XX_GPIO_INT_FLEXIBLE */ - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - uint32_t pin = 0; - uint32_t mask_copy = mask; - - if (port > GPIO_PORT_COUNT) { - /* set up GPIO of KSO/KSI pins (support input only). */ - gpio_kbs_pin_gpio_mode(port, mask, flags); - return; - } - - /* - * Select open drain first, so that we don't glitch the signal - * when changing the line to an output. - */ - if (flags & GPIO_OPEN_DRAIN) - IT83XX_GPIO_GPOT(port) |= mask; - else - IT83XX_GPIO_GPOT(port) &= ~mask; - - /* If output, set level before changing type to an output. */ - if (flags & GPIO_OUTPUT) { - if (flags & GPIO_HIGH) - IT83XX_GPIO_DATA(port) |= mask; - else if (flags & GPIO_LOW) - IT83XX_GPIO_DATA(port) &= ~mask; - } - - /* For each bit high in the mask, set input/output and pullup/down. */ - while (mask_copy > 0) { - if (mask_copy & 1) { - /* Set input or output. */ - if (flags & GPIO_OUTPUT) - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_OUTPUT) & - ~GPCR_PORT_PIN_MODE_INPUT; - else - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_INPUT) & - ~GPCR_PORT_PIN_MODE_OUTPUT; - - /* Handle pullup / pulldown */ - if (flags & GPIO_PULL_UP) { - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_PULLUP) & - ~GPCR_PORT_PIN_MODE_PULLDOWN; - } else if (flags & GPIO_PULL_DOWN) { - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_PULLDOWN) & - ~GPCR_PORT_PIN_MODE_PULLUP; - } else { - /* No pull up/down */ - IT83XX_GPIO_CTRL(port, pin) &= - ~(GPCR_PORT_PIN_MODE_PULLUP | - GPCR_PORT_PIN_MODE_PULLDOWN); - } - - /* To select 1.8v or 3.3v support. */ - gpio_1p8v_3p3v_sel_by_pin(port, pin, - (flags & GPIO_SEL_1P8V)); - } - - pin++; - mask_copy >>= 1; - } - - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) { - int irq, wuc_group, wuc_mask; - irq = gpio_to_irq(port, mask); - wuc_group = gpio_irqs[irq].wuc_group; - wuc_mask = gpio_irqs[irq].wuc_mask; - - /* - * Set both edges interrupt. - * The WUBEMR register is valid on IT8320 DX version. - * And the setting (falling or rising edge) of WUEMR register is - * invalid if this mode is set. - */ -#ifdef IT83XX_GPIO_INT_FLEXIBLE - if ((flags & GPIO_INT_BOTH) == GPIO_INT_BOTH) - *(wubemr(wuc_group)) |= wuc_mask; - else - *(wubemr(wuc_group)) &= ~wuc_mask; -#endif - - if (flags & GPIO_INT_F_FALLING) { -#ifndef IT83XX_GPIO_INT_FLEXIBLE - if (!!(flags & GPIO_INT_F_RISING) != - group_falling_is_both(wuc_group)) { - ccprintf("!!Fix GPIO %s interrupt config!!\n", - get_gpio_string(port, mask)); - } -#endif - *(wuemr(wuc_group)) |= wuc_mask; - } else { - *(wuemr(wuc_group)) &= ~wuc_mask; - } - /* - * Always write 1 to clear the WUC status register after - * modifying edge mode selection register (WUBEMR and WUEMR). - */ - *(wuesr(wuc_group)) = wuc_mask; - } -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask); - - if (irq == -1) - return EC_ERROR_UNKNOWN; - else - task_enable_irq(irq); - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask); - - if (irq == -1) - return EC_ERROR_UNKNOWN; - else - task_disable_irq(irq); - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - int irq = gpio_to_irq(gpio_list[signal].port, gpio_list[signal].mask); - - if (irq == -1) - return EC_ERROR_UNKNOWN; - - *(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask; - task_clear_pending_irq(irq); - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - int is_warm = system_is_reboot_warm(); - int flags; - int i; - - IT83XX_GPIO_GCR = 0x06; - -#ifndef CONFIG_USB_PD_TCPM_ITE83XX - /* To prevent cc pins leakage if we don't use pd module */ - for (i = 0; i < USBPD_PORT_COUNT; i++) { - IT83XX_USBPD_CCGCR(i) = 0x1f; - /* - * bit7 and bit3: Dis-connect CC with UP/RD/DET/TX/RX. - * bit6 and bit2: Dis-connect CC with 5.1K resister to GND. - * bit5 and bit1: Disable CC voltage detector. - * bit4 and bit0: Disable CC. - */ - IT83XX_USBPD_CCCSR(i) = 0xff; - IT83XX_USBPD_CCPSR(i) = 0x66; - } -#endif - -#ifndef CONFIG_USB - /* - * We need to enable USB's clock so we can config USB control register. - * This is important for a software reset as the hardware clock may - * already be disabled from the previous run. - * We will disable clock to USB module in clock_module_disable() later. - */ - clock_enable_peripheral(CGC_OFFSET_USB, 0, 0); - /* - * Disable default pull-down of USB controller (GPH5 and GPH6) if we - * don't use this module. - */ - IT83XX_USB_P0MCR &= ~USB_DP_DM_PULL_DOWN_EN; -#endif - -#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - /* Q group pins are default GPI mode, clear alternate setting. */ - IT83XX_VBATPC_XLPIER = 0x0; - /* - * R group pins are default alternate output low, we clear alternate - * setting (sink power switch from VBAT to VSTBY) to become GPO output - * low. - * NOTE: GPR0~5 pins are output low by default. It should consider - * that if output low signal effect external circuit or not, - * until we reconfig these pins in gpio.inc. - */ - IT83XX_VBATPC_BGPOPSCR = 0x0; -#endif - - for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - /* Set up GPIO based on flags */ - gpio_set_flags_by_mask(g->port, g->mask, flags); - } -} - -/** - * Handle a GPIO interrupt by calling the pins corresponding handler if - * one exists. - * - * @param port GPIO port (GPIO_*) - * @param mask GPIO mask - */ -static void gpio_interrupt(int port, uint8_t mask) -{ - int i = 0; - const struct gpio_info *g = gpio_list; - - for (i = 0; i < GPIO_IH_COUNT; i++, g++) { - if (port == g->port && (mask & g->mask)) { - gpio_irq_handlers[i](i); - return; - } - } -} - -/** - * Define one IRQ function to handle all GPIO interrupts. The IRQ determines - * the interrupt number which was triggered, calls the master handler above, - * and clears status registers. - */ -static void __gpio_irq(void) -{ - /* Determine interrupt number. */ - int irq = intc_get_ec_int(); - -#ifdef HAS_TASK_KEYSCAN - if (irq == IT83XX_IRQ_WKINTC) { - keyboard_raw_interrupt(); - return; - } -#endif - -#ifdef CONFIG_HOSTCMD_X86 - if (irq == IT83XX_IRQ_WKINTAD) - return; -#endif - - /* - * Clear the WUC status register. Note the external pin first goes - * to the WUC module and is always edge triggered. - */ - *(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask; - - /* - * Clear the interrupt controller status register. Note the interrupt - * controller is level triggered from the WUC status. - */ - task_clear_pending_irq(irq); - - /* Run the GPIO master handler above with corresponding port/mask. */ - gpio_interrupt(gpio_irqs[irq].gpio_port, gpio_irqs[irq].gpio_mask); -} - -/* Route all WKO interrupts coming from INT#2 into __gpio_irq. */ -DECLARE_IRQ(CPU_INT_2_ALL_GPIOS, __gpio_irq, 1); diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c deleted file mode 100644 index 1fc90ebe67..0000000000 --- a/chip/it83xx/hwtimer.c +++ /dev/null @@ -1,346 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "cpu.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "hwtimer_chip.h" -#include "intc.h" -#include "irq_chip.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * The IT839X series support combinational mode for combining specific pairs of - * timers: 3(24-bit) and 4(32-bit) / timer 5(24-bit) and 6(32-bit) / - * timer 7(24-bit) and 8(32-bit). - * - * 32-bit MHz free-running counter: We combine (bit3@IT83XX_ETWD_ETXCTRL) - * timer 3(TIMER_L) and 4(TIMER_H) and set clock source register to 8MHz. - * In combinational mode, the counter register(IT83XX_ETWD_ETXCNTLR) of timer 3 - * is a fixed value = 7, and observation register(IT83XX_ETWD_ETXCNTOR) - * of timer 4 will increase one per-us. - * - * For example, if - * __hw_clock_source_set() set 0 us, the counter setting registers are - * timer 3(TIMER_L) = 0x000007 (fixed, will not change) - * timer 4(TIMER_H) = 0xffffffff - * - * Note: - * In combinational mode, the counter observation value of - * timer 4(TIMER_H), 6, 8 will in incrementing order. - * For the above example, the counter observation value registers will be - * timer 3(TIMER_L) 0x0000007 - * timer 4(TIMER_H) ~0xffffffff = 0x00000000 - * - * The following will describe timer 3 and 4's operation in combinational mode: - * 1. When timer 3(TIMER_L) has completed each counting (per-us), - timer 4(TIMER_H) observation value++. - * 2. When timer 4(TIMER_H) observation value overflows: - * timer 4(TIMER_H) observation value = ~counter setting register. - * 3. Timer 4(TIMER_H) interrupt occurs. - * - * IT839X only supports terminal count interrupt. We need a separate - * 8 MHz 32-bit timer to handle events. - */ - -#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000) - -const struct ext_timer_ctrl_t et_ctrl_regs[] = { - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08, - IT83XX_IRQ_EXT_TIMER3}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10, - IT83XX_IRQ_EXT_TIMER4}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20, - IT83XX_IRQ_EXT_TIMER5}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40, - IT83XX_IRQ_EXT_TIMER6}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80, - IT83XX_IRQ_EXT_TIMER7}, - {&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01, - IT83XX_IRQ_EXT_TMR8}, -}; -BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT); - -static void free_run_timer_overflow(void) -{ - /* - * If timer 4 (TIMER_H) counter register != 0xffffffff. - * This usually happens once after sysjump, force time, and etc. - * (when __hw_clock_source_set is called and param 'ts' != 0) - */ - if (IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) != 0xffffffff) { - /* set timer counter register */ - IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff; - /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); - } - /* w/c interrupt status */ - task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq); - /* timer overflow */ - process_timers(1); - update_exc_start_time(); -} - -static void event_timer_clear_pending_isr(void) -{ - /* w/c interrupt status */ - task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq); -} - -uint32_t __ram_code __hw_clock_source_read(void) -{ -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES - /* - * In combinational mode, the counter observation register of - * timer 4(TIMER_H) will increment. - */ - return ext_observation_reg_read(FREE_EXT_TIMER_H); -#else - return IT83XX_ETWD_ETXCNTOR(FREE_EXT_TIMER_H); -#endif -} - -void __hw_clock_source_set(uint32_t ts) -{ - /* counting down timer, microseconds to timer counter register */ - IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts; - /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint32_t wait; - /* bit0, disable event timer */ - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); - /* w/c interrupt status */ - event_timer_clear_pending_isr(); - /* microseconds to timer counter */ - wait = deadline - __hw_clock_source_read(); - IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = - wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ? - EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff; - /* enable and re-start timer */ - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03; - task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq); -} - -uint32_t __hw_clock_event_get(void) -{ - uint32_t next_event_us = __hw_clock_source_read(); - - /* bit0, event timer is enabled */ - if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) { - /* timer counter observation value to microseconds */ - next_event_us += EVENT_TIMER_COUNT_TO_US( -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES - ext_observation_reg_read(EVENT_EXT_TIMER)); -#else - IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)); -#endif - } - return next_event_us; -} - -void __hw_clock_event_clear(void) -{ - /* stop event timer */ - ext_timer_stop(EVENT_EXT_TIMER, 1); - event_timer_clear_pending_isr(); -} - -int __hw_clock_source_init(uint32_t start_t) -{ - /* bit3, timer 3 and timer 4 combinational mode */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3); - /* init free running timer (timer 4, TIMER_H), clock source is 8mhz */ - ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1); - /* 1us counter setting (timer 3, TIMER_L) */ - ext_timer_ms(FREE_EXT_TIMER_L, EXT_PSR_8M_HZ, 1, 0, 7, 1, 1); - __hw_clock_source_set(start_t); - /* init event timer */ - ext_timer_ms(EVENT_EXT_TIMER, EXT_PSR_8M_HZ, 0, 0, 0xffffffff, 1, 1); - /* returns the IRQ number of event timer */ - return et_ctrl_regs[EVENT_EXT_TIMER].irq; -} - -static void __hw_clock_source_irq(void) -{ - /* Determine interrupt number. */ - int irq = intc_get_ec_int(); - - /* SW/HW interrupt of event timer. */ - if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) { - IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff; - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1); - event_timer_clear_pending_isr(); - process_timers(0); - return; - } - -#ifdef CONFIG_WATCHDOG - /* - * Both the external timer for the watchdog warning and the HW timer - * go through this irq. So, if this interrupt was caused by watchdog - * warning timer, then call that function. - */ - if (irq == et_ctrl_regs[WDT_EXT_TIMER].irq) { - watchdog_warning_irq(); - return; - } -#endif - -#ifdef CONFIG_FANS - if (irq == et_ctrl_regs[FAN_CTRL_EXT_TIMER].irq) { - fan_ext_timer_interrupt(); - return; - } -#endif - - /* Interrupt of free running timer TIMER_H. */ - if (irq == et_ctrl_regs[FREE_EXT_TIMER_H].irq) { - free_run_timer_overflow(); - return; - } - - /* - * This interrupt is used to wakeup EC from sleep mode - * to complete PLL frequency change. - */ - if (irq == et_ctrl_regs[LOW_POWER_EXT_TIMER].irq) { - ext_timer_stop(LOW_POWER_EXT_TIMER, 1); - return; - } -} -DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1); - -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES -/* Number of CPU cycles in 125 us */ -#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000) -uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer) -{ - uint32_t prev_mask = get_int_mask(); - uint32_t val; - - interrupt_disable(); - asm volatile( - /* read observation register for the first time */ - "lwi %0,[%1]\n\t" - /* - * the delay time between reading the first and second - * observation registers need to be greater than 0.125us and - * smaller than 0.250us. - */ - ".rept %2\n\t" - "nop\n\t" - ".endr\n\t" - /* read for the second time */ - "lwi %0,[%1]\n\t" - : "=&r"(val) - : "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)), - "i"(CYCLES_125NS)); - /* restore interrupts */ - set_int_mask(prev_mask); - - return val; -} -#endif - -void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq) -{ - /* enable external timer n */ - IT83XX_ETWD_ETXCTRL(ext_timer) |= 0x03; - - if (en_irq) { - task_clear_pending_irq(et_ctrl_regs[ext_timer].irq); - task_enable_irq(et_ctrl_regs[ext_timer].irq); - } -} - -void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq) -{ - /* disable external timer n */ - IT83XX_ETWD_ETXCTRL(ext_timer) &= ~0x01; - - if (dis_irq) - task_disable_irq(et_ctrl_regs[ext_timer].irq); -} - -static void ext_timer_ctrl(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int with_int, - int32_t count) -{ - uint8_t intc_mask; - - /* rising-edge-triggered */ - intc_mask = et_ctrl_regs[ext_timer].mask; - *et_ctrl_regs[ext_timer].mode |= intc_mask; - *et_ctrl_regs[ext_timer].polarity &= ~intc_mask; - - /* clear interrupt status */ - task_clear_pending_irq(et_ctrl_regs[ext_timer].irq); - - /* These bits control the clock input source to the exttimer 3 - 8 */ - IT83XX_ETWD_ETXPSR(ext_timer) = ext_timer_clock; - - /* The count number of external timer n. */ - IT83XX_ETWD_ETXCNTLR(ext_timer) = count; - - ext_timer_stop(ext_timer, 0); - if (start) - ext_timer_start(ext_timer, 0); - - if (with_int) - task_enable_irq(et_ctrl_regs[ext_timer].irq); - else - task_disable_irq(et_ctrl_regs[ext_timer].irq); -} - -int ext_timer_ms(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int with_int, - int32_t ms, - int first_time_enable, - int raw) -{ - uint32_t count; - - if (raw) { - count = ms; - } else { - if (ext_timer_clock == EXT_PSR_32P768K_HZ) - count = MS_TO_COUNT(32768, ms); - else if (ext_timer_clock == EXT_PSR_1P024K_HZ) - count = MS_TO_COUNT(1024, ms); - else if (ext_timer_clock == EXT_PSR_32_HZ) - count = MS_TO_COUNT(32, ms); - else if (ext_timer_clock == EXT_PSR_8M_HZ) - count = 8000 * ms; - else - return -1; - } - - if (count == 0) - return -3; - - if (first_time_enable) { - ext_timer_start(ext_timer, 0); - ext_timer_stop(ext_timer, 0); - } - - ext_timer_ctrl(ext_timer, ext_timer_clock, start, with_int, count); - - return 0; -} diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h deleted file mode 100644 index ef53c4e871..0000000000 --- a/chip/it83xx/hwtimer_chip.h +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* External timers control module for IT83xx. */ - -#ifndef __CROS_EC_HWTIMER_CHIP_H -#define __CROS_EC_HWTIMER_CHIP_H - -#define TIMER_COUNT_1US_SHIFT 3 - -/* Microseconds to event timer counter setting register */ -#define EVENT_TIMER_US_TO_COUNT(us) ((us) << TIMER_COUNT_1US_SHIFT) -/* Event timer counter observation value to microseconds */ -#define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT) - -#define FREE_EXT_TIMER_L EXT_TIMER_3 -#define FREE_EXT_TIMER_H EXT_TIMER_4 -#define FAN_CTRL_EXT_TIMER EXT_TIMER_5 -#define EVENT_EXT_TIMER EXT_TIMER_6 -#define WDT_EXT_TIMER EXT_TIMER_7 -#define LOW_POWER_EXT_TIMER EXT_TIMER_8 - -enum ext_timer_clock_source { - EXT_PSR_32P768K_HZ = 0, - EXT_PSR_1P024K_HZ = 1, - EXT_PSR_32_HZ = 2, - EXT_PSR_8M_HZ = 3 -}; - -/* - * 24-bit timers: external timer 3, 5, and 7 - * 32-bit timers: external timer 4, 6, and 8 - */ -enum ext_timer_sel { - /* timer 3 and 4 combine mode for free running timer */ - EXT_TIMER_3 = 0, - EXT_TIMER_4, - /* For fan control */ - EXT_TIMER_5, - /* timer 6 for event timer */ - EXT_TIMER_6, - /* For WDT capture important state information before being reset */ - EXT_TIMER_7, - /* HW timer for low power mode */ - EXT_TIMER_8, - EXT_TIMER_COUNT, -}; - -struct ext_timer_ctrl_t { - volatile uint8_t *mode; - volatile uint8_t *polarity; - volatile uint8_t *isr; - uint8_t mask; - uint8_t irq; -}; - -extern const struct ext_timer_ctrl_t et_ctrl_regs[]; -#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES -uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer); -#endif -void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq); -void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq); -void fan_ext_timer_interrupt(void); -void update_exc_start_time(void); - -/** - * Config a external timer. - * - * @param raw (!=0) timer count equal to param "ms" no conversion. - */ -int ext_timer_ms(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int et_int, - int32_t ms, - int first_time_enable, - int raw); - -#endif /* __CROS_EC_HWTIMER_CHIP_H */ diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c deleted file mode 100644 index 1160b1bd2c..0000000000 --- a/chip/it83xx/i2c.c +++ /dev/null @@ -1,899 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* Default maximum time we allow for an I2C transfer */ -#define I2C_TIMEOUT_DEFAULT_US (100 * MSEC) - -enum enhanced_i2c_transfer_direct { - TX_DIRECT, - RX_DIRECT, -}; - -enum i2c_host_status { - /* Host busy */ - HOSTA_HOBY = 0x01, - /* Finish Interrupt */ - HOSTA_FINTR = 0x02, - /* Device error */ - HOSTA_DVER = 0x04, - /* Bus error */ - HOSTA_BSER = 0x08, - /* Fail */ - HOSTA_FAIL = 0x10, - /* Not response ACK */ - HOSTA_NACK = 0x20, - /* Time-out error */ - HOSTA_TMOE = 0x40, - /* Byte done status */ - HOSTA_BDS = 0x80, - /* Error bit is set */ - HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | - HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE), - /* W/C for next byte */ - HOSTA_NEXT_BYTE = HOSTA_BDS, - /* W/C host status register */ - HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS), -}; - -enum enhanced_i2c_host_status { - /* ACK receive */ - E_HOSTA_ACK = 0x01, - /* Interrupt pending */ - E_HOSTA_INTP = 0x02, - /* Read/Write */ - E_HOSTA_RW = 0x04, - /* Time out error */ - E_HOSTA_TMOE = 0x08, - /* Arbitration lost */ - E_HOSTA_ARB = 0x10, - /* Bus busy */ - E_HOSTA_BB = 0x20, - /* Address match */ - E_HOSTA_AM = 0x40, - /* Byte done status */ - E_HOSTA_BDS = 0x80, - /* time out or lost arbitration */ - E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB), - /* Byte transfer done and ACK receive */ - E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK), -}; - -enum enhanced_i2c_ctl { - /* Hardware reset */ - E_HW_RST = 0x01, - /* Stop */ - E_STOP = 0x02, - /* Start & Repeat start */ - E_START = 0x04, - /* Acknowledge */ - E_ACK = 0x08, - /* State reset */ - E_STS_RST = 0x10, - /* Mode select */ - E_MODE_SEL = 0x20, - /* I2C interrupt enable */ - E_INT_EN = 0x40, - /* 0 : Standard mode , 1 : Receive mode */ - E_RX_MODE = 0x80, - /* State reset and hardware reset */ - E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST), - /* Generate start condition and transmit slave address */ - E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST), - /* Generate stop condition */ - E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST), -}; - -enum i2c_reset_cause { - I2C_RC_NO_IDLE_FOR_START = 1, - I2C_RC_TIMEOUT, -}; - -struct i2c_ch_freq { - int kpbs; - uint8_t freq_set; -}; - -static const struct i2c_ch_freq i2c_freq_select[] = { - { 50, 1}, - { 100, 2}, - { 400, 3}, - { 1000, 4}, -}; - -struct i2c_pin { - volatile uint8_t *pin_clk; - volatile uint8_t *pin_data; - volatile uint8_t *pin_clk_ctrl; - volatile uint8_t *pin_data_ctrl; - volatile uint8_t *mirror_clk; - volatile uint8_t *mirror_data; - uint8_t clk_mask; - uint8_t data_mask; -}; - -static const struct i2c_pin i2c_pin_regs[] = { - { &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4, - &IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB, - &IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB, - 0x08, 0x10}, - { &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2, - &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC, - &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC, - 0x02, 0x04}, -#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 - { &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7, - &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF, - &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF, - 0x80, 0x80}, -#else - { &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7, - &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF, - &IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF, - 0x40, 0x80}, -#endif - { &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, - &IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH, - &IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH, - 0x02, 0x04}, - { &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7, - &IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE, - &IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE, - 0x01, 0x80}, - { &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5, - &IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA, - &IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA, - 0x10, 0x20}, -}; - -struct i2c_ctrl_t { - uint8_t irq; - enum clock_gate_offsets clock_gate; - int reg_shift; -}; - -const struct i2c_ctrl_t i2c_ctrl_regs[] = { - {IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1}, - {IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1}, - {IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1}, - {IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3}, - {IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0}, - {IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1}, -}; - -enum i2c_ch_status { - I2C_CH_NORMAL = 0, - I2C_CH_REPEAT_START, - I2C_CH_WAIT_READ, - I2C_CH_WAIT_NEXT_XFER, -}; - -/* I2C port state data */ -struct i2c_port_data { - const uint8_t *out; /* Output data pointer */ - int out_size; /* Output data to transfer, in bytes */ - uint8_t *in; /* Input data pointer */ - int in_size; /* Input data to transfer, in bytes */ - int flags; /* Flags (I2C_XFER_*) */ - int widx; /* Index into output data */ - int ridx; /* Index into input data */ - int err; /* Error code, if any */ - uint8_t addr_8bit; /* address of device */ - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - uint8_t freq; /* Frequency setting */ - - enum i2c_ch_status i2ccs; - /* Task waiting on port, or TASK_ID_INVALID if none. */ - volatile int task_waiting; -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -static int i2c_ch_reg_shift(int p) -{ - /* - * only enhanced port needs to be changed the parameter of registers - */ - ASSERT(p >= I2C_STANDARD_PORT_COUNT && p < I2C_PORT_COUNT); - - /* - * The registers of i2c enhanced ports are not sequential. - * This routine transfers the i2c port number to related - * parameter of registers. - * - * IT83xx chip : i2c enhanced ports - channel D,E,F - * channel D registers : 0x3680 ~ 0x36FF - * channel E registers : 0x3500 ~ 0x357F - * channel F registers : 0x3580 ~ 0x35FF - */ - return i2c_ctrl_regs[p].reg_shift; -} - -static void i2c_reset(int p, int cause) -{ - int p_ch; - - if (p < I2C_STANDARD_PORT_COUNT) { - /* bit1, kill current transaction. */ - IT83XX_SMB_HOCTL(p) = 0x2; - IT83XX_SMB_HOCTL(p) = 0; - /* W/C host status register */ - IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT; - } else { - /* Shift register */ - p_ch = i2c_ch_reg_shift(p); - /* State reset and hardware reset */ - IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; - } - CPRINTS("I2C ch%d reset cause %d", p, cause); -} - -static void i2c_r_last_byte(int p) -{ - struct i2c_port_data *pd = pdata + p; - - /* - * bit5, The firmware shall write 1 to this bit - * when the next byte will be the last byte for i2c read. - */ - if ((pd->flags & I2C_XFER_STOP) && (pd->ridx == pd->in_size - 1)) - IT83XX_SMB_HOCTL(p) |= 0x20; -} - -static void i2c_w2r_change_direction(int p) -{ - /* I2C switch direction */ - if (IT83XX_SMB_HOCTL2(p) & 0x08) { - i2c_r_last_byte(p); - IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE; - } else { - /* - * bit2, I2C switch direction wait. - * bit3, I2C switch direction enable. - */ - IT83XX_SMB_HOCTL2(p) |= 0x0C; - IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE; - i2c_r_last_byte(p); - IT83XX_SMB_HOCTL2(p) &= ~0x04; - } -} - -static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct, - uint8_t data, int first_byte) -{ - struct i2c_port_data *pd = pdata + p; - int p_ch; - int nack = 0; - - /* Shift register */ - p_ch = i2c_ch_reg_shift(p); - - if (first_byte) { - /* First byte must be slave address. */ - IT83XX_I2C_DTR(p_ch) = - data | (direct == RX_DIRECT ? BIT(0) : 0); - /* start or repeat start signal. */ - IT83XX_I2C_CTR(p_ch) = E_START_ID; - } else { - if (direct == TX_DIRECT) - /* Transmit data */ - IT83XX_I2C_DTR(p_ch) = data; - else { - /* - * Receive data. - * Last byte should be NACK in the end of read cycle - */ - if (((pd->ridx + 1) == pd->in_size) && - (pd->flags & I2C_XFER_STOP)) - nack = 1; - } - /* Set hardware reset to start next transmission */ - IT83XX_I2C_CTR(p_ch) = - E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK); - } -} - -static int i2c_tran_write(int p) -{ - struct i2c_port_data *pd = pdata + p; - - if (pd->flags & I2C_XFER_START) { - /* i2c enable */ - IT83XX_SMB_HOCTL2(p) = 0x13; - /* - * bit0, Direction of the host transfer. - * bit[1:7}, Address of the targeted slave. - */ - IT83XX_SMB_TRASLA(p) = pd->addr_8bit; - /* Send first byte */ - IT83XX_SMB_HOBDB(p) = *(pd->out++); - pd->widx++; - /* clear start flag */ - pd->flags &= ~I2C_XFER_START; - /* - * bit0, Host interrupt enable. - * bit[2:4}, Extend command. - * bit6, start. - */ - IT83XX_SMB_HOCTL(p) = 0x5D; - } else { - /* Host has completed the transmission of a byte */ - if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) { - if (pd->widx < pd->out_size) { - /* Send next byte */ - IT83XX_SMB_HOBDB(p) = *(pd->out++); - pd->widx++; - /* W/C byte done for next byte */ - IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE; - if (pd->i2ccs == I2C_CH_REPEAT_START) { - pd->i2ccs = I2C_CH_NORMAL; - task_enable_irq(i2c_ctrl_regs[p].irq); - } - } else { - /* done */ - pd->out_size = 0; - if (pd->in_size > 0) { - /* write to read */ - i2c_w2r_change_direction(p); - } else { - if (pd->flags & I2C_XFER_STOP) { - /* set I2C_EN = 0 */ - IT83XX_SMB_HOCTL2(p) = 0x11; - /* W/C byte done for finish */ - IT83XX_SMB_HOSTA(p) = - HOSTA_NEXT_BYTE; - } else { - pd->i2ccs = I2C_CH_REPEAT_START; - return 0; - } - } - } - } - } - return 1; -} - -static int i2c_tran_read(int p) -{ - struct i2c_port_data *pd = pdata + p; - - if (pd->flags & I2C_XFER_START) { - /* i2c enable */ - IT83XX_SMB_HOCTL2(p) = 0x13; - /* - * bit0, Direction of the host transfer. - * bit[1:7}, Address of the targeted slave. - */ - IT83XX_SMB_TRASLA(p) = pd->addr_8bit | 0x01; - /* clear start flag */ - pd->flags &= ~I2C_XFER_START; - /* - * bit0, Host interrupt enable. - * bit[2:4}, Extend command. - * bit5, The firmware shall write 1 to this bit - * when the next byte will be the last byte. - * bit6, start. - */ - if ((1 == pd->in_size) && (pd->flags & I2C_XFER_STOP)) - IT83XX_SMB_HOCTL(p) = 0x7D; - else - IT83XX_SMB_HOCTL(p) = 0x5D; - } else { - if ((pd->i2ccs == I2C_CH_REPEAT_START) || - (pd->i2ccs == I2C_CH_WAIT_READ)) { - if (pd->i2ccs == I2C_CH_REPEAT_START) { - /* write to read */ - i2c_w2r_change_direction(p); - } else { - /* For last byte */ - i2c_r_last_byte(p); - /* W/C for next byte */ - IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE; - } - pd->i2ccs = I2C_CH_NORMAL; - task_enable_irq(i2c_ctrl_regs[p].irq); - } else if (IT83XX_SMB_HOSTA(p) & HOSTA_BDS) { - if (pd->ridx < pd->in_size) { - /* To get received data. */ - *(pd->in++) = IT83XX_SMB_HOBDB(p); - pd->ridx++; - /* For last byte */ - i2c_r_last_byte(p); - /* done */ - if (pd->ridx == pd->in_size) { - pd->in_size = 0; - if (pd->flags & I2C_XFER_STOP) { - /* W/C for finish */ - IT83XX_SMB_HOSTA(p) = - HOSTA_NEXT_BYTE; - } else { - pd->i2ccs = I2C_CH_WAIT_READ; - return 0; - } - } else { - /* W/C for next byte */ - IT83XX_SMB_HOSTA(p) = HOSTA_NEXT_BYTE; - } - } - } - } - return 1; -} - -static void enhanced_i2c_start(int p) -{ - /* Shift register */ - int p_ch = i2c_ch_reg_shift(p); - - /* State reset and hardware reset */ - IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; - /* Set i2c frequency */ - IT83XX_I2C_PSR(p_ch) = pdata[p].freq; - IT83XX_I2C_HSPR(p_ch) = pdata[p].freq; - /* - * Set time out register. - * I2C D/E/F clock/data low timeout. - */ - IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT; - /* bit1: Enable enhanced i2c module */ - IT83XX_I2C_CTR1(p_ch) = BIT(1); -} - -static int enhanced_i2c_tran_write(int p) -{ - struct i2c_port_data *pd = pdata + p; - uint8_t out_data; - int p_ch; - - /* Shift register */ - p_ch = i2c_ch_reg_shift(p); - - if (pd->flags & I2C_XFER_START) { - /* Clear start bit */ - pd->flags &= ~I2C_XFER_START; - enhanced_i2c_start(p); - /* Send ID */ - i2c_pio_trans_data(p, TX_DIRECT, pd->addr_8bit, 1); - } else { - /* Host has completed the transmission of a byte */ - if (pd->widx < pd->out_size) { - out_data = *(pd->out++); - pd->widx++; - - /* Send Byte */ - i2c_pio_trans_data(p, TX_DIRECT, out_data, 0); - if (pd->i2ccs == I2C_CH_WAIT_NEXT_XFER) { - pd->i2ccs = I2C_CH_NORMAL; - task_enable_irq(i2c_ctrl_regs[p].irq); - } - } else { - /* done */ - pd->out_size = 0; - if (pd->in_size > 0) { - /* Write to read protocol */ - pd->i2ccs = I2C_CH_REPEAT_START; - /* Repeat Start */ - i2c_pio_trans_data(p, RX_DIRECT, - pd->addr_8bit, 1); - } else { - if (pd->flags & I2C_XFER_STOP) { - IT83XX_I2C_CTR(p_ch) = E_FINISH; - /* wait for stop bit interrupt*/ - return 1; - } - /* Direct write with direct read */ - pd->i2ccs = I2C_CH_WAIT_NEXT_XFER; - return 0; - } - } - } - return 1; -} - -static int enhanced_i2c_tran_read(int p) -{ - struct i2c_port_data *pd = pdata + p; - uint8_t in_data = 0; - int p_ch; - - /* Shift register */ - p_ch = i2c_ch_reg_shift(p); - - if (pd->flags & I2C_XFER_START) { - /* clear start flag */ - pd->flags &= ~I2C_XFER_START; - enhanced_i2c_start(p); - /* Direct read */ - pd->i2ccs = I2C_CH_WAIT_READ; - /* Send ID */ - i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit, 1); - } else { - if (pd->i2ccs) { - if (pd->i2ccs == I2C_CH_REPEAT_START) { - pd->i2ccs = I2C_CH_NORMAL; - /* Receive data */ - i2c_pio_trans_data(p, RX_DIRECT, in_data, 0); - } else if (pd->i2ccs == I2C_CH_WAIT_READ) { - pd->i2ccs = I2C_CH_NORMAL; - /* Receive data */ - i2c_pio_trans_data(p, RX_DIRECT, in_data, 0); - /* Turn on irq before next direct read */ - task_enable_irq(i2c_ctrl_regs[p].irq); - } else { - /* Write to read */ - pd->i2ccs = I2C_CH_WAIT_READ; - /* Send ID */ - i2c_pio_trans_data(p, RX_DIRECT, - pd->addr_8bit, 1); - task_enable_irq(i2c_ctrl_regs[p].irq); - } - } else { - if (pd->ridx < pd->in_size) { - /* read data */ - *(pd->in++) = IT83XX_I2C_DRR(p_ch); - pd->ridx++; - - /* done */ - if (pd->ridx == pd->in_size) { - pd->in_size = 0; - if (pd->flags & I2C_XFER_STOP) { - pd->i2ccs = I2C_CH_NORMAL; - IT83XX_I2C_CTR(p_ch) = E_FINISH; - /* wait for stop bit interrupt*/ - return 1; - } - /* End the transaction */ - pd->i2ccs = I2C_CH_WAIT_READ; - return 0; - } - /* read next byte */ - i2c_pio_trans_data(p, RX_DIRECT, in_data, 0); - } - } - } - return 1; -} - -static int enhanced_i2c_error(int p) -{ - struct i2c_port_data *pd = pdata + p; - /* Shift register */ - int p_ch = i2c_ch_reg_shift(p); - int i2c_str = IT83XX_I2C_STR(p_ch); - - if (i2c_str & E_HOSTA_ANY_ERROR) { - pd->err = i2c_str & E_HOSTA_ANY_ERROR; - /* device does not respond ACK */ - } else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) { - if (IT83XX_I2C_CTR(p_ch) & E_ACK) - pd->err = E_HOSTA_ACK; - } - - return pd->err; -} - -static int i2c_transaction(int p) -{ - struct i2c_port_data *pd = pdata + p; - int p_ch; - - if (p < I2C_STANDARD_PORT_COUNT) { - /* any error */ - if (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR) { - pd->err = (IT83XX_SMB_HOSTA(p) & HOSTA_ANY_ERROR); - } else { - /* i2c write */ - if (pd->out_size) - return i2c_tran_write(p); - /* i2c read */ - else if (pd->in_size) - return i2c_tran_read(p); - /* wait finish */ - if (!(IT83XX_SMB_HOSTA(p) & HOSTA_FINTR)) - return 1; - } - /* W/C */ - IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT; - /* disable the SMBus host interface */ - IT83XX_SMB_HOCTL2(p) = 0x00; - } else { - /* no error */ - if (!(enhanced_i2c_error(p))) { - /* i2c write */ - if (pd->out_size) - return enhanced_i2c_tran_write(p); - /* i2c read */ - else if (pd->in_size) - return enhanced_i2c_tran_read(p); - } - p_ch = i2c_ch_reg_shift(p); - IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; - IT83XX_I2C_CTR1(p_ch) = 0; - } - /* done doing work */ - return 0; -} - -int i2c_is_busy(int port) -{ - int p_ch; - - if (port < I2C_STANDARD_PORT_COUNT) - return (IT83XX_SMB_HOSTA(port) & - (HOSTA_HOBY | HOSTA_ALL_WC_BIT)); - - p_ch = i2c_ch_reg_shift(port); - return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB); -} - -int chip_i2c_xfer(int port, uint16_t slave_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) -{ - struct i2c_port_data *pd = pdata + port; - uint32_t events = 0; - - if (out_size == 0 && in_size == 0) - return EC_SUCCESS; - - if (pd->i2ccs) { - if ((flags & I2C_XFER_SINGLE) == I2C_XFER_SINGLE) - flags &= ~I2C_XFER_START; - } - - /* Copy data to port struct */ - pd->out = out; - pd->out_size = out_size; - pd->in = in; - pd->in_size = in_size; - pd->flags = flags; - pd->widx = 0; - pd->ridx = 0; - pd->err = 0; - pd->addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - - /* Make sure we're in a good state to start */ - if ((flags & I2C_XFER_START) && (i2c_is_busy(port) - || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { - /* Attempt to unwedge the port. */ - i2c_unwedge(port); - /* reset i2c port */ - i2c_reset(port, I2C_RC_NO_IDLE_FOR_START); - } - - pd->task_waiting = task_get_current(); - if (pd->flags & I2C_XFER_START) { - pd->i2ccs = I2C_CH_NORMAL; - /* enable i2c interrupt */ - task_clear_pending_irq(i2c_ctrl_regs[port].irq); - task_enable_irq(i2c_ctrl_regs[port].irq); - } - /* Start transaction */ - i2c_transaction(port); - /* Wait for transfer complete or timeout */ - events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, pd->timeout_us); - /* disable i2c interrupt */ - task_disable_irq(i2c_ctrl_regs[port].irq); - pd->task_waiting = TASK_ID_INVALID; - - /* Handle timeout */ - if (!(events & TASK_EVENT_I2C_IDLE)) { - pd->err = EC_ERROR_TIMEOUT; - /* reset i2c port */ - i2c_reset(port, I2C_RC_TIMEOUT); - } - - /* reset i2c channel status */ - if (pd->err) - pd->i2ccs = I2C_CH_NORMAL; - - return pd->err; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return !!(*i2c_pin_regs[port].mirror_clk & - i2c_pin_regs[port].clk_mask); - - /* If no SCL pin defined for this port, then return 1 to appear idle */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return !!(*i2c_pin_regs[port].mirror_data & - i2c_pin_regs[port].data_mask); - - /* If no SDA pin defined for this port, then return 1 to appear idle */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - int pin_sts = 0; - - if (port < I2C_STANDARD_PORT_COUNT) - return IT83XX_SMB_SMBPCTL(port) & 0x03; - - if (*i2c_pin_regs[port].mirror_clk & i2c_pin_regs[port].clk_mask) - pin_sts |= I2C_LINE_SCL_HIGH; - if (*i2c_pin_regs[port].mirror_data & i2c_pin_regs[port].data_mask) - pin_sts |= I2C_LINE_SDA_HIGH; - - return pin_sts; -} - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; -} - -void i2c_interrupt(int port) -{ - int id = pdata[port].task_waiting; - - /* Clear the interrupt status */ - task_clear_pending_irq(i2c_ctrl_regs[port].irq); - - /* If no task is waiting, just return */ - if (id == TASK_ID_INVALID) - return; - - /* If done doing work, wake up the task waiting for the transfer */ - if (!i2c_transaction(port)) { - task_disable_irq(i2c_ctrl_regs[port].irq); - task_set_event(id, TASK_EVENT_I2C_IDLE, 0); - } -} - -static void i2c_freq_changed(void) -{ - int i, f, clk_div, psr, freq; - int p_ch; - - /* - * Standard I2C Channels - */ - for (i = 0; i < i2c_ports_used; i++) { - freq = i2c_ports[i].kbps; - if (i2c_ports[i].port < I2C_STANDARD_PORT_COUNT) { - for (f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) { - if (freq >= i2c_freq_select[f].kpbs) { - IT83XX_SMB_SCLKTS(i2c_ports[i].port) = - i2c_freq_select[f].freq_set; - break; - } - } - } else { - p_ch = i2c_ch_reg_shift(i2c_ports[i].port); - /* - * Let psr(Prescale) = IT83XX_I2C_PSR(p_ch) - * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle - * SMBus clock = PLL_CLOCK / clk_div - * SMBus clock cycle = 1 / SMBus clock - * 1 SCL cycle = 1 / (1000 x freq) - * 1 / (1000 x freq) = - * 2 x (psr + 2) x (1 / (PLL_CLOCK / clk_div)) - * psr = ((PLL_CLOCK / clk_div) x - * (1 / (1000 x freq)) x (1 / 2)) - 2 - */ - if (freq) { - /* Get SMBus clock divide value */ - clk_div = (IT83XX_ECPM_SCDCR2 & 0x0F) + 1; - /* Calculate PSR value */ - psr = (PLL_CLOCK / - (clk_div * (2 * 1000 * freq))) - 2; - /* Set psr value under 0xFD */ - if (psr > 0xFD) - psr = 0xFD; - - /* Set I2C Speed */ - IT83XX_I2C_PSR(p_ch) = (psr & 0xFF); - IT83XX_I2C_HSPR(p_ch) = (psr & 0xFF); - - /* Backup */ - pdata[i2c_ports[i].port].freq = (psr & 0xFF); - } - } - } - /* This field defines the SMCLK0/1/2 clock/data low timeout. */ - IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT; -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_changed, HOOK_PRIO_DEFAULT); - -void i2c_init(void) -{ - int i, p, p_ch; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - -#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 - /* bit7, 0: SMCLK2 is located on GPF6, 1: SMCLK2 is located on GPC7 */ - IT83XX_GPIO_GRC7 |= 0x80; -#endif - - /* Enable I2C function. */ - for (i = 0; i < i2c_ports_used; i++) { - /* I2c port mapping. */ - p = i2c_ports[i].port; - - clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0); - - if (p < I2C_STANDARD_PORT_COUNT) { - /* - * bit0, The SMBus host interface is enabled. - * bit1, Enable to communicate with I2C device - * and support I2C-compatible cycles. - * bit4, This bit controls the reset mechanism - * of SMBus master to handle the SMDAT - * line low if 25ms reg timeout. - */ - IT83XX_SMB_HOCTL2(p) = 0x11; - /* - * bit1, Kill SMBus host transaction. - * bit0, Enable the interrupt for the master interface. - */ - IT83XX_SMB_HOCTL(p) = 0x03; - IT83XX_SMB_HOCTL(p) = 0x01; - /* W/C host status register */ - IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT; - IT83XX_SMB_HOCTL2(p) = 0x00; - } else { - /* Shift register */ - p_ch = i2c_ch_reg_shift(p); - switch (p) { - case IT83XX_I2C_CH_D: - #ifndef CONFIG_UART_HOST - /* Enable SMBus D channel */ - IT83XX_GPIO_GRC2 |= 0x20; - #endif - break; - case IT83XX_I2C_CH_E: - /* Enable SMBus E channel */ - IT83XX_GCTRL_PMER1 |= 0x01; - break; - case IT83XX_I2C_CH_F: - /* Enable SMBus F channel */ - IT83XX_GCTRL_PMER1 |= 0x02; - break; - } - /* Software reset */ - IT83XX_I2C_DHTR(p_ch) |= 0x80; - IT83XX_I2C_DHTR(p_ch) &= 0x7F; - /* State reset and hardware reset */ - IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; - /* bit1, Module enable */ - IT83XX_I2C_CTR1(p_ch) = 0; - } - pdata[i].task_waiting = TASK_ID_INVALID; - } - - i2c_freq_changed(); - - for (i = 0; i < I2C_PORT_COUNT; i++) { - /* Use default timeout */ - i2c_set_timeout(i, 0); - } -} diff --git a/chip/it83xx/i2c_slave.c b/chip/it83xx/i2c_slave.c deleted file mode 100644 index adfa794d77..0000000000 --- a/chip/it83xx/i2c_slave.c +++ /dev/null @@ -1,345 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C module for Chrome EC */ - -#include "clock.h" -#include "compile_time_macros.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c_slave.h" -#include "registers.h" -#include <stddef.h> -#include <string.h> -#include "task.h" - -/* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* The size must be a power of 2 */ -#define I2C_MAX_BUFFER_SIZE 0x100 -#define I2C_SIZE_MASK (I2C_MAX_BUFFER_SIZE - 1) - -#define I2C_READ_MAXFIFO_DATA 16 -#define I2C_ENHANCED_CH_INTERVAL 0x80 - -/* Store master to slave data of channel D, E, F by DMA */ -static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE] - __attribute__((section(".h2ram.pool.i2cslv"))); -/* Store slave to master data of channel D, E, F by DMA */ -static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE] - __attribute__((section(".h2ram.pool.i2cslv"))); -/* Store read and write data of channel A by FIFO mode */ -static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE]; - -static uint32_t w_index; -static uint32_t r_index; -static int wr_done[I2C_ENHANCED_PORT_COUNT]; - -void buffer_index_reset(void) -{ - /* Reset write buffer index */ - w_index = 0; - /* Reset read buffer index */ - r_index = 0; -} - -/* Data structure to define I2C slave control configuration. */ -struct i2c_slv_ctrl_t { - int irq; /* slave irq */ - /* offset from base 0x00F03500 register; -1 means unused. */ - int offset; - enum clock_gate_offsets clock_gate; - int dma_index; -}; - -/* I2C slave control */ -const struct i2c_slv_ctrl_t i2c_slv_ctrl[] = { - [IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1, - .clock_gate = CGC_OFFSET_SMBA, .dma_index = -1}, - [IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180, - .clock_gate = CGC_OFFSET_SMBD, .dma_index = 0}, - [IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0, - .clock_gate = CGC_OFFSET_SMBE, .dma_index = 1}, - [IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80, - .clock_gate = CGC_OFFSET_SMBF, .dma_index = 2}, -}; - -void i2c_slave_read_write_data(int port) -{ - int slv_status, i; - - /* I2C slave channel A FIFO mode */ - if (port < I2C_STANDARD_PORT_COUNT) { - int count; - - slv_status = IT83XX_SMB_SLSTA; - - /* bit0-4 : FIFO byte count */ - count = IT83XX_SMB_SFFSTA & 0x1F; - - /* Slave data register is waiting for read or write. */ - if (slv_status & IT83XX_SMB_SDS) { - /* Master to read data */ - if (slv_status & IT83XX_SMB_RCS) { - for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++) - /* Return buffer data to master */ - IT83XX_SMB_SLDA = - pbuffer[(i + r_index) & I2C_SIZE_MASK]; - - /* Index to next 16 bytes of read buffer */ - r_index += I2C_READ_MAXFIFO_DATA; - } - /* Master to write data */ - else { - /* FIFO Full */ - if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) { - for (i = 0; i < count; i++) - /* Get data from master to buffer */ - pbuffer[(w_index + i) & - I2C_SIZE_MASK] = IT83XX_SMB_SLDA; - } - - /* Index to next byte of write buffer */ - w_index += count; - } - } - /* Stop condition, indicate stop condition detected. */ - if (slv_status & IT83XX_SMB_SPDS) { - /* Read data less 16 bytes status */ - if (slv_status & IT83XX_SMB_RCS) { - /* Disable FIFO mode to clear left count */ - IT83XX_SMB_SFFCTL &= ~IT83XX_SMB_SAFE; - - /* Slave A FIFO Enable */ - IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE; - } - /* Master to write data */ - else { - for (i = 0; i < count; i++) - /* Get data from master to buffer */ - pbuffer[(i + w_index) & - I2C_SIZE_MASK] = IT83XX_SMB_SLDA; - } - - /* Reset read and write buffer index */ - buffer_index_reset(); - } - /* Slave time status, timeout status occurs. */ - if (slv_status & IT83XX_SMB_STS) { - /* Reset read and write buffer index */ - buffer_index_reset(); - } - - /* Write clear the slave status */ - IT83XX_SMB_SLSTA = slv_status; - } - /* Enhanced I2C slave channel D, E, F DMA mode */ - else { - int ch, idx; - - /* Get enhanced i2c channel */ - ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL; - - idx = i2c_slv_ctrl[port].dma_index; - - /* Interrupt pending */ - if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) { - - slv_status = IT83XX_I2C_IRQ_ST(ch); - - /* Master to read data */ - if (slv_status & IT83XX_I2C_IDR_CLR) { - /* - * TODO(b:129360157): Return buffer data by - * "out_data" array. - * Ex: Write data to buffer from 0x00 to 0xFF - */ - for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++) - out_data[idx][i] = i; - } - /* Master to write data */ - if (slv_status & IT83XX_I2C_IDW_CLR) { - /* Master to write data finish flag */ - wr_done[idx] = 1; - } - /* Slave finish */ - if (slv_status & IT83XX_I2C_P_CLR) { - if (wr_done[idx]) { - /* - * TODO(b:129360157): Handle master write - * data by "in_data" array. - */ - CPRINTS("WData: %ph", - HEX_BUF(in_data[idx], - I2C_MAX_BUFFER_SIZE)); - wr_done[idx] = 0; - } - } - - /* Write clear the slave status */ - IT83XX_I2C_IRQ_ST(ch) = slv_status; - } - - /* Hardware reset */ - IT83XX_I2C_CTR(ch) |= IT83XX_I2C_HALT; - } -} - -void i2c_slv_interrupt(int port) -{ - /* Slave to read and write fifo data */ - i2c_slave_read_write_data(port); - - /* Clear the interrupt status */ - task_clear_pending_irq(i2c_slv_ctrl[port].irq); -} - -void i2c_slave_enable(int port, uint8_t slv_addr) -{ - - clock_enable_peripheral(i2c_slv_ctrl[port].clock_gate, 0, 0); - - /* I2C slave channel A FIFO mode */ - if (port < I2C_STANDARD_PORT_COUNT) { - - /* This field defines the SMCLK0/1/2 clock/data low timeout. */ - IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT; - - /* bit0 : Slave A FIFO Enable */ - IT83XX_SMB_SFFCTL |= IT83XX_SMB_SAFE; - - /* - * bit1 : Slave interrupt enable. - * bit2 : SMCLK/SMDAT will be released if timeout. - * bit3 : Slave detect STOP condition interrupt enable. - */ - IT83XX_SMB_SICR = 0x0E; - - /* Slave address 1 */ - IT83XX_SMB_RESLADR = slv_addr; - - /* Write clear all slave status */ - IT83XX_SMB_SLSTA = 0xE7; - - /* bit5 : Enable the SMBus slave device */ - IT83XX_SMB_HOCTL2(port) |= IT83XX_SMB_SLVEN; - } - /* Enhanced I2C slave channel D, E, F DMA mode */ - else { - int ch, idx; - uint32_t in_data_addr, out_data_addr; - - /* Get enhanced i2c channel */ - ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL; - - idx = i2c_slv_ctrl[port].dma_index; - - switch (port) { - case IT83XX_I2C_CH_D: - /* Enable I2C D channel */ - IT83XX_GPIO_GRC2 |= (1 << 5); - break; - case IT83XX_I2C_CH_E: - /* Enable I2C E channel */ - IT83XX_GCTRL_PMER1 |= (1 << 0); - break; - case IT83XX_I2C_CH_F: - /* Enable I2C F channel */ - IT83XX_GCTRL_PMER1 |= (1 << 1); - break; - } - - /* Software reset */ - IT83XX_I2C_DHTR(ch) |= (1 << 7); - IT83XX_I2C_DHTR(ch) &= ~(1 << 7); - - /* This field defines the SMCLK3/4/5 clock/data low timeout. */ - IT83XX_I2C_TOR(ch) = I2C_CLK_LOW_TIMEOUT; - - /* Bit stretching */ - IT83XX_I2C_TOS(ch) |= IT83XX_I2C_CLK_STR; - - /* Slave address(8-bit)*/ - IT83XX_I2C_IDR(ch) = slv_addr << 1; - - /* I2C interrupt enable and set acknowledge */ - IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT | - IT83XX_I2C_INTEN | IT83XX_I2C_ACK; - - /* - * bit3 : Slave ID write flag - * bit2 : Slave ID read flag - * bit1 : Slave received data flag - * bit0 : Slave finish - */ - IT83XX_I2C_IRQ_ST(ch) = 0xFF; - - /* Clear read and write data buffer of DMA */ - memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE); - memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE); - - if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { - in_data_addr = (uint32_t)in_data[idx] & 0xffffff; - out_data_addr = (uint32_t)out_data[idx] & 0xffffff; - } else { - in_data_addr = (uint32_t)in_data[idx] & 0xfff; - out_data_addr = (uint32_t)out_data[idx] & 0xfff; - } - - /* DMA write target address register */ - IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8; - IT83XX_I2C_RAMLA(ch) = in_data_addr; - - if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { - /* - * DMA write target address register - * for high order byte - */ - IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16; - /* - * DMA read target address register - * for high order byte - */ - IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16; - IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8; - IT83XX_I2C_CMD_ADDL(ch) = out_data_addr; - } else { - /* DMA read target address register */ - IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8; - IT83XX_I2C_RAMLA2(ch) = out_data_addr; - } - - /* I2C module enable and command queue mode */ - IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | - IT83XX_I2C_MDL_EN; - } -} - -static void i2c_slave_init(void) -{ - int i, p; - - /* DLM 52k~56k size select enable */ - IT83XX_GCTRL_MCCR2 |= (1 << 4); - - /* Enable I2C Slave function */ - for (i = 0; i < i2c_slvs_used; i++) { - - /* I2c slave port mapping. */ - p = i2c_slv_ports[i].port; - - /* To enable slave ch[x] */ - i2c_slave_enable(p, i2c_slv_ports[i].slave_adr); - - /* Clear the interrupt status */ - task_clear_pending_irq(i2c_slv_ctrl[p].irq); - - /* enable i2c interrupt */ - task_enable_irq(i2c_slv_ctrl[p].irq); - } -} -DECLARE_HOOK(HOOK_INIT, i2c_slave_init, HOOK_PRIO_INIT_I2C + 1); diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c deleted file mode 100644 index 8783a76983..0000000000 --- a/chip/it83xx/intc.c +++ /dev/null @@ -1,225 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "intc.h" -#include "it83xx_pd.h" -#include "kmsc_chip.h" -#include "registers.h" -#include "task.h" -#include "tcpm.h" -#include "usb_pd.h" - -#ifdef CONFIG_USB_PD_TCPM_ITE83XX -static void chip_pd_irq(enum usbpd_port port) -{ - task_clear_pending_irq(usbpd_ctrl_regs[port].irq); - - /* check status */ - if (USBPD_IS_HARD_RESET_DETECT(port)) { - /* clear interrupt */ - IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_DETECT; - task_set_event(PD_PORT_TO_TASK_ID(port), - PD_EVENT_TCPC_RESET, 0); - } else { - if (USBPD_IS_RX_DONE(port)) { - tcpm_enqueue_message(port); - /* clear RX done interrupt */ - IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_RX_DONE; - } - if (USBPD_IS_TX_DONE(port)) { - /* clear TX done interrupt */ - IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_TX_DONE; - task_set_event(PD_PORT_TO_TASK_ID(port), - TASK_EVENT_PHY_TX_DONE, 0); - } -#ifdef IT83XX_INTC_PLUG_IN_SUPPORT - if (USBPD_IS_PLUG_IN_OUT_DETECT(port)) { - /* - * When tcpc detect type-c plug in, then disable - * this interrupt. Because any cc volt changes - * (include pd negotiation) would trigger plug in - * interrupt, frequently plug in interrupt and wakeup - * pd task may cause task starvation or device dead - * (ex.transmit lots SRC_Cap). - * - * When polling disconnect will enable detect type-c - * plug in again. - * - * Clear detect type-c plug in interrupt status. - */ - IT83XX_USBPD_TCDCR(port) |= - (USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE | - USBPD_REG_PLUG_IN_OUT_DETECT_STAT); - task_set_event(PD_PORT_TO_TASK_ID(port), - PD_EVENT_CC, 0); - } -#endif //IT83XX_INTC_PLUG_IN_SUPPORT - } -} -#endif - -void intc_cpu_int_group_5(void) -{ - /* Determine interrupt number. */ - int intc_group_5 = intc_get_ec_int(); - - switch (intc_group_5) { -#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO) - case IT83XX_IRQ_KBC_OUT: - lpc_kbc_obe_interrupt(); - break; - - case IT83XX_IRQ_KBC_IN: - lpc_kbc_ibf_interrupt(); - break; -#endif - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_5, intc_cpu_int_group_5, 2); - -void intc_cpu_int_group_4(void) -{ - /* Determine interrupt number. */ - int intc_group_4 = intc_get_ec_int(); - - switch (intc_group_4) { -#ifdef CONFIG_HOSTCMD_X86 - case IT83XX_IRQ_PMC_IN: - pm1_ibf_interrupt(); - break; - - case IT83XX_IRQ_PMC2_IN: - pm2_ibf_interrupt(); - break; - - case IT83XX_IRQ_PMC3_IN: - pm3_ibf_interrupt(); - break; - - case IT83XX_IRQ_PMC4_IN: - pm4_ibf_interrupt(); - break; - - case IT83XX_IRQ_PMC5_IN: - pm5_ibf_interrupt(); - break; -#endif - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_4, intc_cpu_int_group_4, 2); - -void intc_cpu_int_group_12(void) -{ - /* Determine interrupt number. */ - int intc_group_12 = intc_get_ec_int(); - - switch (intc_group_12) { -#ifdef CONFIG_PECI - case IT83XX_IRQ_PECI: - peci_interrupt(); - break; -#endif -#ifdef CONFIG_HOSTCMD_ESPI - case IT83XX_IRQ_ESPI: - espi_interrupt(); - break; - - case IT83XX_IRQ_ESPI_VW: - espi_vw_interrupt(); - break; -#endif -#ifdef CONFIG_USB_PD_TCPM_ITE83XX - case IT83XX_IRQ_USBPD0: - chip_pd_irq(USBPD_PORT_A); - break; - - case IT83XX_IRQ_USBPD1: - chip_pd_irq(USBPD_PORT_B); - break; -#endif /* CONFIG_USB_PD_TCPM_ITE83XX */ - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_12, intc_cpu_int_group_12, 2); - -void intc_cpu_int_group_7(void) -{ - /* Determine interrupt number. */ - int intc_group_7 = intc_get_ec_int(); - - switch (intc_group_7) { -#ifdef CONFIG_ADC - case IT83XX_IRQ_ADC: - adc_interrupt(); - break; -#endif - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_7, intc_cpu_int_group_7, 2); - -void intc_cpu_int_group_6(void) -{ - /* Determine interrupt number. */ - int intc_group_6 = intc_get_ec_int(); - - switch (intc_group_6) { -#if defined(CONFIG_I2C_MASTER) || defined(CONFIG_I2C_SLAVE) - case IT83XX_IRQ_SMB_A: -#ifdef CONFIG_I2C_SLAVE - if (IT83XX_SMB_SFFCTL & IT83XX_SMB_SAFE) - i2c_slv_interrupt(IT83XX_I2C_CH_A); - else -#endif - i2c_interrupt(IT83XX_I2C_CH_A); - break; - - case IT83XX_IRQ_SMB_B: - i2c_interrupt(IT83XX_I2C_CH_B); - break; - - case IT83XX_IRQ_SMB_C: - i2c_interrupt(IT83XX_I2C_CH_C); - break; - - case IT83XX_IRQ_SMB_D: -#ifdef CONFIG_I2C_SLAVE - if (!(IT83XX_I2C_CTR(3) & IT83XX_I2C_MODE)) - i2c_slv_interrupt(IT83XX_I2C_CH_D); - else -#endif - i2c_interrupt(IT83XX_I2C_CH_D); - break; - - case IT83XX_IRQ_SMB_E: -#ifdef CONFIG_I2C_SLAVE - if (!(IT83XX_I2C_CTR(0) & IT83XX_I2C_MODE)) - i2c_slv_interrupt(IT83XX_I2C_CH_E); - else -#endif - i2c_interrupt(IT83XX_I2C_CH_E); - break; - - case IT83XX_IRQ_SMB_F: -#ifdef CONFIG_I2C_SLAVE - if (!(IT83XX_I2C_CTR(1) & IT83XX_I2C_MODE)) - i2c_slv_interrupt(IT83XX_I2C_CH_F); - else -#endif - i2c_interrupt(IT83XX_I2C_CH_F); - break; -#endif - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_6, intc_cpu_int_group_6, 2); diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h deleted file mode 100644 index add8e4b9d7..0000000000 --- a/chip/it83xx/intc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* INTC control module for IT83xx. */ - -#ifndef __CROS_EC_INTC_H -#define __CROS_EC_INTC_H - -/* - * The DSB instruction guarantees a modified architecture or hardware state - * can be seen by any following dependent data operations. - */ -static inline void data_serialization_barrier(void) -{ - if (IS_ENABLED(CHIP_CORE_NDS32)) - asm volatile ("dsb"); -} - -int intc_get_ec_int(void); -void pm1_ibf_interrupt(void); -void pm2_ibf_interrupt(void); -void pm3_ibf_interrupt(void); -void pm4_ibf_interrupt(void); -void pm5_ibf_interrupt(void); -void lpcrst_interrupt(enum gpio_signal signal); -void peci_interrupt(void); -void adc_interrupt(void); -void i2c_interrupt(int port); -#ifdef CONFIG_I2C_SLAVE -void i2c_slv_interrupt(int port); -#endif -void clock_sleep_mode_wakeup_isr(void); -int clock_ec_wake_from_sleep(void); -void __enter_hibernate(uint32_t seconds, uint32_t microseconds); -void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); -void espi_fw_reset_module(void); -void espi_interrupt(void); -void espi_vw_interrupt(void); -void espi_enable_pad(int enable); -void espi_init(void); -int chip_get_intc_group(int irq); -void clock_cpu_standby(void); - -#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO) -void lpc_kbc_ibf_interrupt(void); -void lpc_kbc_obe_interrupt(void); -#endif - -#endif /* __CROS_EC_INTC_H */ diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c deleted file mode 100644 index 498b7446f0..0000000000 --- a/chip/it83xx/irq.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IT83xx chip-specific part of the IRQ handling. - */ - -#include "common.h" -#include "irq_chip.h" -#include "registers.h" -#include "util.h" - -#define IRQ_GROUP(n, cpu_ints...) \ - {(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \ - (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \ - ##cpu_ints} - -static const struct { - uint8_t isr_off; - uint8_t ier_off; - uint8_t cpu_int[8]; -} irq_groups[] = { - IRQ_GROUP(0, {-1, 2, 5, 4, 6, 2, 2, 4}), - IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8}), - IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12}), - IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2}), - IRQ_GROUP(4, {11, 11, 11, 11, 8, 9, 9, 9}), - IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(7, {10, 10, 3, 12, 3, 3, 3, 3}), - IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12}), - IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2}), - IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, -1}), - IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7}), - IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3}), - IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}), -#if defined(IT83XX_INTC_GROUP_21_22_SUPPORT) - IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1}), -#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}), - IRQ_GROUP(22, { 2, 2, 2, 2, 2, 2, 2, 2}), -#else - IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}), - IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}), -#endif - IRQ_GROUP(23, { 2, 2, -1, -1, -1, -1, -1, 2}), - IRQ_GROUP(24, { 2, 2, 2, 2, 2, 2, -1, 2}), - IRQ_GROUP(25, { 2, 2, 2, 2, -1, -1, -1, -1}), - IRQ_GROUP(26, { 2, 2, 2, 2, 2, 2, 2, -1}), - IRQ_GROUP(27, { 2, 2, 2, 2, 2, 2, -1, -1}), - IRQ_GROUP(28, { 2, 2, 2, 2, 2, 2, -1, -1}), -}; - -int chip_get_intc_group(int irq) -{ - return irq_groups[irq / 8].cpu_int[irq % 8]; -} - -int chip_enable_irq(int irq) -{ - int group = irq / 8; - int bit = irq % 8; - - IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit); - if (IS_ENABLED(CHIP_CORE_NDS32)) - IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit); - - return irq_groups[group].cpu_int[bit]; -} - -int chip_disable_irq(int irq) -{ - int group = irq / 8; - int bit = irq % 8; - - IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); - if (IS_ENABLED(CHIP_CORE_NDS32)) - IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit); - - return -1; /* we don't want to mask other IRQs */ -} - -int chip_clear_pending_irq(int irq) -{ - int group = irq / 8; - int bit = irq % 8; - - /* always write 1 clear, no | */ - IT83XX_INTC_REG(irq_groups[group].isr_off) = BIT(bit); - - return -1; /* everything has been done */ -} - -int chip_trigger_irq(int irq) -{ - int group = irq / 8; - int bit = irq % 8; - - return irq_groups[group].cpu_int[bit]; -} - -void chip_init_irqs(void) -{ - int i; - - /* Clear all IERx and EXT_IERx */ - for (i = 0; i < ARRAY_SIZE(irq_groups); i++) { - IT83XX_INTC_REG(irq_groups[i].ier_off) = 0; - if (IS_ENABLED(CHIP_CORE_NDS32)) - IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(i)) = 0; - } -} diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S deleted file mode 100644 index 5265eb7253..0000000000 --- a/chip/it83xx/it83xx_fpu.S +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "config_chip.h" - -/* - * DLMB register = 0x80189: - * Disable all interrupts and switching CPU's - * ALU (Arithmetic Logic Unit) to floating point operation mode. - * (IEEE standard 754 floating point) - * - * DLMB register = 0x80009: - * Restore interrupts and ALU. - */ - .text - .align 2 - .global __addsf3 - .type __addsf3, @function -__addsf3: - sethi $r2, 0x80 /* r2 = 0x80000 */ - addi $r3, $r2, 0x189 /* r3 = 0x80189 */ - addi45 $r2, 0x9 /* r2 = 0x80009 */ - mtsr $r3, $dlmb /* dlmb = 0x80189 */ - dsb - /* Floating-point addition single-precision */ - add45 $r0, $r1 - mtsr $r2, $dlmb /* dlmb = 0x80009 */ - dsb - ret5 $lp - .size __addsf3, .-__addsf3 - - .text - .align 2 - .global __subsf3 - .type __subsf3, @function -__subsf3: - sethi $r2, 0x80 /* r2 = 0x80000 */ - addi $r3, $r2, 0x189 /* r3 = 0x80189 */ - addi45 $r2, 0x9 /* r2 = 0x80009 */ - mtsr $r3, $dlmb /* dlmb = 0x80189 */ - dsb - /* Floating-point subtraction single-precision */ - sub45 $r0, $r1 - mtsr $r2, $dlmb /* dlmb = 0x80009 */ - dsb - ret5 $lp - .size __subsf3, .-__subsf3 - - .text - .align 2 - .global __mulsf3 - .type __mulsf3, @function -__mulsf3: -#ifdef IT83XX_FPU_MUL_BY_DIV -#define SIGN $r2 -#define EXPOA $r3 -#define MANTA $r4 -#define VALUA $r5 -#define EXPOB $r6 -#define MANTB $r7 -#define VALUB $r8 -#define SPROD $r15 - /* save r6-r8 */ - smw.adm $r6, [$sp], $r8, #0x0 - xor SPROD, $r1, $r0 /* sign(A xor B) */ - move SIGN, #0x80000000 - and SPROD, SPROD, SIGN /* store sign bit */ - slli VALUA, $r0, 1 /* A<<1, (exponent and mantissa) */ - slli VALUB, $r1, 1 /* B<<1, (exponent and mantissa) */ - srli EXPOA, VALUA, 24 /* exponent(A) */ - srli EXPOB, VALUB, 24 /* exponent(B) */ - slli MANTA, VALUA, 7 /* A<<8, mantissa(A) with exponent's LSB */ - slli MANTB, VALUB, 7 /* A<<8, mantissa(B) with exponent's LSB */ - beqz VALUA, .LFzeroA /* exponent(A) and mantissa (A) are zero */ - beqc EXPOA, 0xff, .LFinfnanA /* A is inf or NaN */ - beqz VALUB, .LFzeroB /* exponent(B) and mantissa (B) are zero */ - beqc EXPOB, 0xff, .LFinfnanB /* B is inf or NaN */ - /* A*B = A/(1/B) */ - sethi $r2, 0x80 /* r2 = 0x80000 */ - addi $r3, $r2, 0x189 /* r3 = 0x80189 */ - addi45 $r2, 0x9 /* r2 = 0x80009 */ - mtsr $r3, $dlmb /* dlmb = 0x80189 */ - dsb - sethi $r5, #0x3f800 /* r5 = 1.0f */ - divsr $r1,$r1,$r5,$r1 /* r1 = 1.0f / r1 */ - divsr $r0,$r0,$r0,$r1 /* r0 = r0 / r1 */ - mtsr $r2, $dlmb /* dlmb = 0x80009 */ - dsb -.LFret: - /* restore r6-r8 */ - lmw.bim $r6, [$sp], $r8, #0x0 - ret5 $lp - -.LFzeroA: /* A is zero */ - beqc EXPOB, 0xff, .LFnan/*zero * inf = zero * NaN = NaN */ -.LFzero: - move $r0, SPROD /* return 0.0f or -0.0f */ - b .LFret -.LFinfnanA: /* exponent(A) is 0xff */ - bne MANTA, SIGN, .LFnan/* A is NaN: NaN * B = NaN */ - beqz VALUB, .LFnan /* A is inf and B is zero: inf * zero = NaN */ - bnec EXPOB, 0xff, .LFinf/* B is finite: inf * B = inf */ -.LFinfnanB: /* exponent(B) is 0xff */ - bne MANTB, SIGN, .LFnan/* B is NaN: A * NaN = NaN */ -.LFinf: - move $r0, #0x7f800000 - or $r0, $r0, SPROD /* return inf or -inf */ - b .LFret -.LFzeroB: /* B is zero and A is finit */ - b .LFzero /* B is zero */ -.LFnan: - move $r0, #0xffc00000 /* return NaN */ - b .LFret -#else /* !IT83XX_FPU_MUL_BY_DIV */ - sethi $r2, 0x80 /* r2 = 0x80000 */ - addi $r3, $r2, 0x189 /* r3 = 0x80189 */ - addi45 $r2, 0x9 /* r2 = 0x80009 */ - mtsr $r3, $dlmb /* dlmb = 0x80189 */ - dsb - /* Floating-point multiplication single-precision */ - mul33 $r0, $r1 - mtsr $r2, $dlmb /* dlmb = 0x80009 */ - dsb - ret5 $lp -#endif /* IT83XX_FPU_MUL_BY_DIV */ - .size __mulsf3, .-__mulsf3 - - .text - .align 2 - .global __divsf3 - .type __divsf3, @function -__divsf3: - sethi $r2, 0x80 /* r2 = 0x80000 */ - addi $r3, $r2, 0x189 /* r3 = 0x80189 */ - addi45 $r2, 0x9 /* r2 = 0x80009 */ - mtsr $r3, $dlmb /* dlmb = 0x80189 */ - dsb - /* Floating-point division single-precision */ - divsr $r0,$r0,$r0,$r1 - mtsr $r2, $dlmb /* dlmb = 0x80009 */ - dsb - ret5 $lp - .size __divsf3, .-__divsf3 diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c deleted file mode 100644 index 225063f90a..0000000000 --- a/chip/it83xx/keyboard_raw.c +++ /dev/null @@ -1,124 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "irq_chip.h" - -/* - * Initialize the raw keyboard interface. - */ -void keyboard_raw_init(void) -{ - /* Ensure top-level interrupt is disabled */ - keyboard_raw_enable_interrupt(0); - - /* - * bit2, Setting 1 enables the internal pull-up of the KSO[15:0] pins. - * To pull up KSO[17:16], set the GPCR registers of their - * corresponding GPIO ports. - * bit0, Setting 1 enables the open-drain mode of the KSO[17:0] pins. - */ - IT83XX_KBS_KSOCTRL = 0x05; - - /* bit2, 1 enables the internal pull-up of the KSI[7:0] pins. */ - IT83XX_KBS_KSICTRL = 0x04; - -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - /* KSO[2] is high, others are low. */ - IT83XX_KBS_KSOL = BIT(2); -#else - /* KSO[7:0] pins low. */ - IT83XX_KBS_KSOL = 0x00; -#endif - - /* KSO[15:8] pins low. */ - IT83XX_KBS_KSOH1 = 0x00; - - /* KSI[0-7] falling-edge triggered is selected */ - IT83XX_WUC_WUEMR3 = 0xFF; - - /* W/C */ - IT83XX_WUC_WUESR3 = 0xFF; - - task_clear_pending_irq(IT83XX_IRQ_WKINTC); - - /* Enable WUC for KSI[0-7] */ - IT83XX_WUC_WUENR3 = 0xFF; -} - -/* - * Finish initialization after task scheduling has started. - */ -void keyboard_raw_task_start(void) -{ - IT83XX_WUC_WUESR3 = 0xFF; - task_clear_pending_irq(IT83XX_IRQ_WKINTC); - task_enable_irq(IT83XX_IRQ_WKINTC); -} - -/* - * Drive the specified column low. - */ -test_mockable void keyboard_raw_drive_column(int col) -{ - int mask; - - /* Tri-state all outputs */ - if (col == KEYBOARD_COLUMN_NONE) - mask = 0xffff; - /* Assert all outputs */ - else if (col == KEYBOARD_COLUMN_ALL) - mask = 0; - /* Assert a single output */ - else - mask = 0xffff ^ BIT(col); - -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - /* KSO[2] is inverted. */ - mask ^= BIT(2); -#endif - IT83XX_KBS_KSOL = mask & 0xff; - IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff; -} - -/* - * Read raw row state. - * Bits are 1 if signal is present, 0 if not present. - */ -test_mockable int keyboard_raw_read_rows(void) -{ - /* Bits are active-low, so invert returned levels */ - return IT83XX_KBS_KSI ^ 0xff; -} - -/* - * Enable or disable keyboard matrix scan interrupts. - */ -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - IT83XX_WUC_WUESR3 = 0xFF; - task_clear_pending_irq(IT83XX_IRQ_WKINTC); - task_enable_irq(IT83XX_IRQ_WKINTC); - } else { - task_disable_irq(IT83XX_IRQ_WKINTC); - } -} - -/* - * Interrupt handler for keyboard matrix scan interrupt. - */ -void keyboard_raw_interrupt(void) -{ - IT83XX_WUC_WUESR3 = 0xFF; - task_clear_pending_irq(IT83XX_IRQ_WKINTC); - - /* Wake the scan task */ - task_wake(TASK_ID_KEYSCAN); -} diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h deleted file mode 100644 index cf4169a1c4..0000000000 --- a/chip/it83xx/kmsc_chip.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Keyboard matrix scan control module for IT83xx. */ - -#ifndef __CROS_EC_KMSC_CHIP_H -#define __CROS_EC_KMSC_CHIP_H - -void keyboard_raw_interrupt(void); - -#endif /* __CROS_EC_KMSC_CHIP_H */ diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c deleted file mode 100644 index cd4f9ad608..0000000000 --- a/chip/it83xx/lpc.c +++ /dev/null @@ -1,759 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* LPC module for Chrome EC */ - -#include "acpi.h" -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "ec2i_chip.h" -#include "espi.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "intc.h" -#include "irq_chip.h" -#include "keyboard_protocol.h" -#include "lpc.h" -#include "port80.h" -#include "pwm.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - -/* LPC PM channels */ -enum lpc_pm_ch { - LPC_PM1 = 0, - LPC_PM2, - LPC_PM3, - LPC_PM4, - LPC_PM5, -}; - -enum pm_ctrl_mask { - /* Input Buffer Full Interrupt Enable. */ - PM_CTRL_IBFIE = 0x01, - /* Output Buffer Empty Interrupt Enable. */ - PM_CTRL_OBEIE = 0x02, -}; - -#define LPC_ACPI_CMD LPC_PM1 /* ACPI commands 62h/66h port */ -#define LPC_HOST_CMD LPC_PM2 /* Host commands 200h/204h port */ -#define LPC_HOST_PORT_80H LPC_PM3 /* Host 80h port */ - -static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE] - __attribute__((section(".h2ram.pool.acpiec"))); -static uint8_t host_cmd_memmap[256] - __attribute__((section(".h2ram.pool.hostcmd"))); - -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ - -/* Params must be 32-bit aligned */ -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); -static int init_done; -static int p80l_index; - -static struct ec_lpc_host_args * const lpc_host_args = - (struct ec_lpc_host_args *)host_cmd_memmap; - -static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set) -{ - if (set) - IT83XX_PMC_PMCTL(ch) |= ctrl; - else - IT83XX_PMC_PMCTL(ch) &= ~ctrl; -} - -static void pm_set_status(enum lpc_pm_ch ch, uint8_t status, int set) -{ - if (set) - IT83XX_PMC_PMSTS(ch) |= status; - else - IT83XX_PMC_PMSTS(ch) &= ~status; -} - -static uint8_t pm_get_status(enum lpc_pm_ch ch) -{ - return IT83XX_PMC_PMSTS(ch); -} - -static uint8_t pm_get_data_in(enum lpc_pm_ch ch) -{ - return IT83XX_PMC_PMDI(ch); -} - -static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out) -{ - IT83XX_PMC_PMDO(ch) = out; -} - -static void pm_clear_ibf(enum lpc_pm_ch ch) -{ - /* bit7, write-1 clear IBF */ - IT83XX_PMC_PMIE(ch) |= BIT(7); -} - -#ifdef CONFIG_KEYBOARD_IRQ_GPIO -static void keyboard_irq_assert(void) -{ - /* - * Enforce signal-high for long enough for the signal to be pulled high - * by the external pullup resistor. This ensures the host will see the - * following falling edge, regardless of the line state before this - * function call. - */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); - udelay(4); - /* Generate a falling edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0); - udelay(4); - - /* Set signal high, now that we've generated the edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); -} -#endif - -/** - * Generate SMI pulse to the host chipset via GPIO. - * - * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is - * 60ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse - * length >61us. Both are short enough and events are infrequent, so just - * delay for 65us. - */ -static void lpc_generate_smi(void) -{ -#ifdef CONFIG_HOSTCMD_ESPI - espi_vw_set_wire(VW_SMI_L, 0); - udelay(65); - espi_vw_set_wire(VW_SMI_L, 1); -#else - gpio_set_level(GPIO_PCH_SMI_L, 0); - udelay(65); - gpio_set_level(GPIO_PCH_SMI_L, 1); -#endif -} - -static void lpc_generate_sci(void) -{ -#ifdef CONFIG_HOSTCMD_ESPI - espi_vw_set_wire(VW_SCI_L, 0); - udelay(65); - espi_vw_set_wire(VW_SCI_L, 1); -#else - gpio_set_level(GPIO_PCH_SCI_L, 0); - udelay(65); - gpio_set_level(GPIO_PCH_SCI_L, 1); -#endif -} - -/** - * Update the level-sensitive wake signal to the AP. - * - * @param wake_events Currently asserted wake events - */ -static void lpc_update_wake(host_event_t wake_events) -{ - /* - * Mask off power button event, since the AP gets that through a - * separate dedicated GPIO. - */ - wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); - - /* Signal is asserted low when wake events is non-zero */ - gpio_set_level(GPIO_PCH_WAKE_L, !wake_events); -} - -static void lpc_send_response(struct host_cmd_handler_args *args) -{ - uint8_t *out; - int size = args->response_size; - int csum; - int i; - - /* Ignore in-progress on LPC since interface is synchronous anyway */ - if (args->result == EC_RES_IN_PROGRESS) - return; - - /* Handle negative size */ - if (size < 0) { - args->result = EC_RES_INVALID_RESPONSE; - size = 0; - } - - /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; - - lpc_host_args->data_size = size; - - csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; - - for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) - csum += *out; - - lpc_host_args->checksum = (uint8_t)csum; - - /* Fail if response doesn't fit in the param buffer */ - if (size > EC_PROTO2_MAX_PARAM_SIZE) - args->result = EC_RES_INVALID_RESPONSE; - - /* Write result to the data byte. This sets the OBF status bit. */ - pm_put_data_out(LPC_HOST_CMD, args->result); - - /* Clear the busy bit, so the host knows the EC is done. */ - pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0); -} - -void lpc_update_host_event_status(void) -{ - int need_sci = 0; - int need_smi = 0; - - if (!init_done) - return; - - /* Disable PMC1 interrupt while updating status register */ - task_disable_irq(IT83XX_IRQ_PMC_IN); - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) { - /* Only generate SMI for first event */ - if (!(pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_SMI_PENDING)) - need_smi = 1; - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 1); - } else { - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SMI_PENDING, 0); - } - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) { - /* Generate SCI for every event */ - need_sci = 1; - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 1); - } else { - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_SCI_PENDING, 0); - } - - /* Copy host events to mapped memory */ - *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); - - task_enable_irq(IT83XX_IRQ_PMC_IN); - - /* Process the wake events. */ - lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE)); - - /* Send pulse on SMI signal if needed */ - if (need_smi) - lpc_generate_smi(); - - /* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */ - if (need_sci) - lpc_generate_sci(); -} - -static void lpc_send_response_packet(struct host_packet *pkt) -{ - /* Ignore in-progress on LPC since interface is synchronous anyway */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result to the data byte. */ - pm_put_data_out(LPC_HOST_CMD, pkt->driver_result); - - /* Clear the busy bit, so the host knows the EC is done. */ - pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0); -} - -uint8_t *lpc_get_memmap_range(void) -{ - return (uint8_t *)acpi_ec_memmap; -} - -int lpc_keyboard_has_char(void) -{ - /* OBE or OBF */ - return IT83XX_KBC_KBHISR & 0x01; -} - -int lpc_keyboard_input_pending(void) -{ - /* IBE or IBF */ - return IT83XX_KBC_KBHISR & 0x02; -} - -void lpc_keyboard_put_char(uint8_t chr, int send_irq) -{ - /* Clear programming data bit 7-4 */ - IT83XX_KBC_KBHISR &= 0x0F; - - /* keyboard */ - IT83XX_KBC_KBHISR |= 0x10; - -#ifdef CONFIG_KEYBOARD_IRQ_GPIO - task_clear_pending_irq(IT83XX_IRQ_KBC_OUT); - /* The data output to the KBC Data Output Register. */ - IT83XX_KBC_KBHIKDOR = chr; - task_enable_irq(IT83XX_IRQ_KBC_OUT); - if (send_irq) - keyboard_irq_assert(); -#else - /* - * bit0 = 0, The IRQ1 is controlled by the IRQ1B bit in KBIRQR. - * bit1 = 0, The IRQ12 is controlled by the IRQ12B bit in KBIRQR. - */ - IT83XX_KBC_KBHICR &= 0x3C; - - /* - * Enable the interrupt to keyboard driver in the host processor - * via SERIRQ when the output buffer is full. - */ - if (send_irq) - IT83XX_KBC_KBHICR |= 0x01; - - udelay(16); - - task_clear_pending_irq(IT83XX_IRQ_KBC_OUT); - /* The data output to the KBC Data Output Register. */ - IT83XX_KBC_KBHIKDOR = chr; - task_enable_irq(IT83XX_IRQ_KBC_OUT); -#endif -} - -void lpc_keyboard_clear_buffer(void) -{ - uint32_t int_mask = get_int_mask(); - interrupt_disable(); - /* bit6, write-1 clear OBF */ - IT83XX_KBC_KBHICR |= BIT(6); - IT83XX_KBC_KBHICR &= ~BIT(6); - set_int_mask(int_mask); -} - -void lpc_keyboard_resume_irq(void) -{ - if (lpc_keyboard_has_char()) { -#ifdef CONFIG_KEYBOARD_IRQ_GPIO - keyboard_irq_assert(); -#else - /* The IRQ1 is controlled by the IRQ1B bit in KBIRQR. */ - IT83XX_KBC_KBHICR &= ~0x01; - - /* - * When the OBFKIE bit in KBC Host Interface Control Register - * (KBHICR) is 0, the bit directly controls the IRQ1 signal. - */ - IT83XX_KBC_KBIRQR |= 0x01; -#endif - - task_clear_pending_irq(IT83XX_IRQ_KBC_OUT); - - task_enable_irq(IT83XX_IRQ_KBC_OUT); - } -} - -void lpc_set_acpi_status_mask(uint8_t mask) -{ - pm_set_status(LPC_ACPI_CMD, mask, 1); -} - -void lpc_clear_acpi_status_mask(uint8_t mask) -{ - pm_set_status(LPC_ACPI_CMD, mask, 0); -} - -#ifndef CONFIG_HOSTCMD_ESPI -int lpc_get_pltrst_asserted(void) -{ - return !gpio_get_level(GPIO_PCH_PLTRST_L); -} -#endif - -#ifdef HAS_TASK_KEYPROTO -/* KBC and PMC control modules */ -void lpc_kbc_ibf_interrupt(void) -{ - if (lpc_keyboard_input_pending()) { - keyboard_host_write(IT83XX_KBC_KBHIDIR, - (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); - /* bit7, write-1 clear IBF */ - IT83XX_KBC_KBHICR |= BIT(7); - IT83XX_KBC_KBHICR &= ~BIT(7); - } - - task_clear_pending_irq(IT83XX_IRQ_KBC_IN); - - task_wake(TASK_ID_KEYPROTO); -} - -void lpc_kbc_obe_interrupt(void) -{ - task_disable_irq(IT83XX_IRQ_KBC_OUT); - - task_clear_pending_irq(IT83XX_IRQ_KBC_OUT); - -#ifndef CONFIG_KEYBOARD_IRQ_GPIO - if (!(IT83XX_KBC_KBHICR & 0x01)) { - IT83XX_KBC_KBIRQR &= ~0x01; - - IT83XX_KBC_KBHICR |= 0x01; - } -#endif - - task_wake(TASK_ID_KEYPROTO); -} -#endif /* HAS_TASK_KEYPROTO */ - -void pm1_ibf_interrupt(void) -{ - int is_cmd; - uint8_t value, result; - - if (pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_FROM_HOST) { - /* Set the busy bit */ - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 1); - - /* data from command port or data port */ - is_cmd = pm_get_status(LPC_ACPI_CMD) & EC_LPC_STATUS_LAST_CMD; - - /* Get command or data */ - value = pm_get_data_in(LPC_ACPI_CMD); - - /* Handle whatever this was. */ - if (acpi_ap_to_ec(is_cmd, value, &result)) - pm_put_data_out(LPC_ACPI_CMD, result); - - pm_clear_ibf(LPC_ACPI_CMD); - - /* Clear the busy bit */ - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0); - - /* - * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty - * Output Buffer Full condition on the kernel channel. - */ - lpc_generate_sci(); - } - - task_clear_pending_irq(IT83XX_IRQ_PMC_IN); -} - -void pm2_ibf_interrupt(void) -{ - uint8_t value __attribute__((unused)) = 0; - uint8_t status; - - status = pm_get_status(LPC_HOST_CMD); - /* IBE */ - if (!(status & EC_LPC_STATUS_FROM_HOST)) { - task_clear_pending_irq(IT83XX_IRQ_PMC2_IN); - return; - } - - /* IBF and data port */ - if (!(status & EC_LPC_STATUS_LAST_CMD)) { - /* R/C IBF*/ - value = pm_get_data_in(LPC_HOST_CMD); - pm_clear_ibf(LPC_HOST_CMD); - task_clear_pending_irq(IT83XX_IRQ_PMC2_IN); - return; - } - - /* Set the busy bit */ - pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 1); - - /* - * Read the command byte. This clears the FRMH bit in - * the status byte. - */ - host_cmd_args.command = pm_get_data_in(LPC_HOST_CMD); - - host_cmd_args.result = EC_RES_SUCCESS; - if (host_cmd_args.command != EC_COMMAND_PROTOCOL_3) - host_cmd_args.send_response = lpc_send_response; - host_cmd_flags = lpc_host_args->flags; - - /* We only support new style command (v3) now */ - if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) { - lpc_packet.send_response = lpc_send_response_packet; - - lpc_packet.request = (const void *)host_cmd_memmap; - lpc_packet.request_temp = params_copy; - lpc_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE; - - lpc_packet.response = (void *)host_cmd_memmap; - lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE; - lpc_packet.response_size = 0; - - lpc_packet.driver_result = EC_RES_SUCCESS; - host_packet_receive(&lpc_packet); - - pm_clear_ibf(LPC_HOST_CMD); - task_clear_pending_irq(IT83XX_IRQ_PMC2_IN); - return; - } else { - /* Old style command, now unsupported */ - host_cmd_args.result = EC_RES_INVALID_COMMAND; - } - - /* Hand off to host command handler */ - host_command_received(&host_cmd_args); - - pm_clear_ibf(LPC_HOST_CMD); - task_clear_pending_irq(IT83XX_IRQ_PMC2_IN); -} - -void pm3_ibf_interrupt(void) -{ - int new_p80_idx, i; - enum ec2i_message ec2i_r; - - /* set LDN */ - if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) { - /* get P80L current index */ - ec2i_r = ec2i_read(HOST_INDEX_DSLDC6); - /* clear IBF */ - pm_clear_ibf(LPC_HOST_PORT_80H); - /* read OK */ - if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS) { - new_p80_idx = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK; - for (i = 0; i < (P80L_P80LE - P80L_P80LB + 1); i++) { - if (++p80l_index > P80L_P80LE) - p80l_index = P80L_P80LB; - port_80_write(IT83XX_BRAM_BANK1(p80l_index)); - if (p80l_index == new_p80_idx) - break; - } - } - } else { - pm_clear_ibf(LPC_HOST_PORT_80H); - } - - task_clear_pending_irq(IT83XX_IRQ_PMC3_IN); -} - -void pm4_ibf_interrupt(void) -{ - pm_clear_ibf(LPC_PM4); - task_clear_pending_irq(IT83XX_IRQ_PMC4_IN); -} - -void pm5_ibf_interrupt(void) -{ - pm_clear_ibf(LPC_PM5); - task_clear_pending_irq(IT83XX_IRQ_PMC5_IN); -} - -static void lpc_init(void) -{ - enum ec2i_message ec2i_r; - - /* SPI slave interface is disabled */ - IT83XX_GCTRL_SSCR = 0; - /* - * DLM 52k~56k size select enable. - * For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF. - */ - IT83XX_GCTRL_MCCR2 |= 0x10; - - /* The register pair to access PNPCFG is 004Eh and 004Fh */ - IT83XX_GCTRL_BADRSEL = 0x01; - - /* Disable KBC IRQ */ - IT83XX_KBC_KBIRQR = 0x00; - - /* - * bit2, Output Buffer Empty CPU Interrupt Enable. - * bit3, Input Buffer Full CPU Interrupt Enable. - * bit5, IBF/OBF EC clear mode. - * 0b: IBF cleared if EC read data register, EC reset, or host reset. - * OBF cleared if host read data register, or EC reset. - * 1b: IBF cleared if EC write-1 to bit7 at related registers, - * EC reset, or host reset. - * OBF cleared if host read data register, EC write-1 to bit6 at - * related registers, or EC reset. - */ - IT83XX_KBC_KBHICR |= 0x2C; - - /* PM1 Input Buffer Full Interrupt Enable for 62h/66 port */ - pm_set_ctrl(LPC_ACPI_CMD, PM_CTRL_IBFIE, 1); - - /* PM2 Input Buffer Full Interrupt Enable for 200h/204 port */ - pm_set_ctrl(LPC_HOST_CMD, PM_CTRL_IBFIE, 1); - - memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE); - memset(lpc_host_args, 0, sizeof(*lpc_host_args)); - - /* Host LPC I/O cycle mapping to RAM */ - /* - * bit[4], H2RAM through LPC IO cycle. - * bit[1], H2RAM window 1 enabled. - * bit[0], H2RAM window 0 enabled. - */ - IT83XX_SMFI_HRAMWC |= 0x13; - - /* - * bit[7:6] - * Host RAM Window[x] Read Protect Enable - * 00b: Disabled - * 01b: Lower half of RAM window protected - * 10b: Upper half of RAM window protected - * 11b: All protected - * - * bit[5:4] - * Host RAM Window[x] Write Protect Enable - * 00b: Disabled - * 01b: Lower half of RAM window protected - * 10b: Upper half of RAM window protected - * 11b: All protected - * - * bit[2:0] - * Host RAM Window 1 Size (HRAMW1S) - * 0h: 16 bytes - * 1h: 32 bytes - * 2h: 64 bytes - * 3h: 128 bytes - * 4h: 256 bytes - * 5h: 512 bytes - * 6h: 1024 bytes - * 7h: 2048 bytes - */ - - /* H2RAM Win 0 Base Address 800h allow r/w for host_cmd_memmap */ - IT83XX_SMFI_HRAMW0BA = 0x80; - IT83XX_SMFI_HRAMW0AAS = 0x04; - - /* H2RAM Win 1 Base Address 900h allow r for acpi_ec_memmap */ - IT83XX_SMFI_HRAMW1BA = 0x90; - IT83XX_SMFI_HRAMW1AAS = 0x34; - - /* We support LPC args and version 3 protocol */ - *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; - - /* - * bit[5], Dedicated interrupt - * INT3: PMC1 Output Buffer Empty Int - * INT25: PMC1 Input Buffer Full Int - * INT26: PMC2 Output Buffer Empty Int - * INT27: PMC2 Input Buffer Full Int - */ - IT83XX_PMC_MBXCTRL |= 0x20; - - /* PM3 Input Buffer Full Interrupt Enable for 80h port */ - pm_set_ctrl(LPC_HOST_PORT_80H, PM_CTRL_IBFIE, 1); - - p80l_index = P80L_P80LC; - if (ec2i_write(HOST_INDEX_LDN, LDN_RTCT) == EC2I_WRITE_SUCCESS) { - /* get P80L current index */ - ec2i_r = ec2i_read(HOST_INDEX_DSLDC6); - /* read OK */ - if ((ec2i_r & 0xff00) == EC2I_READ_SUCCESS) - p80l_index = ec2i_r & P80L_BRAM_BANK1_SIZE_MASK; - } - - /* - * bit[7], enable P80L function. - * bit[6], accept port 80h cycle. - * bit[1-0], 10b: I2EC is read-only. - */ - IT83XX_GCTRL_SPCTRL1 |= 0xC2; - -#ifndef CONFIG_HOSTCMD_ESPI - gpio_enable_interrupt(GPIO_PCH_PLTRST_L); -#endif - -#ifdef HAS_TASK_KEYPROTO - task_clear_pending_irq(IT83XX_IRQ_KBC_OUT); - task_disable_irq(IT83XX_IRQ_KBC_OUT); - - task_clear_pending_irq(IT83XX_IRQ_KBC_IN); - task_enable_irq(IT83XX_IRQ_KBC_IN); -#endif - - task_clear_pending_irq(IT83XX_IRQ_PMC_IN); - pm_set_status(LPC_ACPI_CMD, EC_LPC_STATUS_PROCESSING, 0); - task_enable_irq(IT83XX_IRQ_PMC_IN); - - task_clear_pending_irq(IT83XX_IRQ_PMC2_IN); - pm_set_status(LPC_HOST_CMD, EC_LPC_STATUS_PROCESSING, 0); - task_enable_irq(IT83XX_IRQ_PMC2_IN); - - task_clear_pending_irq(IT83XX_IRQ_PMC3_IN); - task_enable_irq(IT83XX_IRQ_PMC3_IN); - -#ifdef CONFIG_HOSTCMD_ESPI - espi_init(); -#endif - /* Sufficiently initialized */ - init_done = 1; - - /* Update host events now that we can copy them to memmap */ - lpc_update_host_event_status(); -} -/* - * Set prio to higher than default; this way LPC memory mapped data is ready - * before other inits try to initialize their memmap data. - */ -DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); - -#ifndef CONFIG_HOSTCMD_ESPI -void lpcrst_interrupt(enum gpio_signal signal) -{ - if (lpc_get_pltrst_asserted()) - /* Store port 80 reset event */ - port_80_write(PORT_80_EVENT_RESET); - - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); -} -#endif - -/* Enable LPC ACPI-EC interrupts */ -void lpc_enable_acpi_interrupts(void) -{ - task_enable_irq(IT83XX_IRQ_PMC_IN); -} - -/* Disable LPC ACPI-EC interrupts */ -void lpc_disable_acpi_interrupts(void) -{ - task_disable_irq(IT83XX_IRQ_PMC_IN); -} - -/* Get protocol information */ -static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->flags = 0; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c deleted file mode 100644 index 07336eaaf6..0000000000 --- a/chip/it83xx/peci.c +++ /dev/null @@ -1,216 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PECI interface for Chrome EC */ - -#include "clock.h" -#include "hooks.h" -#include "peci.h" -#include "registers.h" -#include "util.h" -#include "timer.h" -#include "task.h" - -enum peci_status { - PECI_STATUS_NO_ERR = 0x00, - PECI_STATUS_HOBY = 0x01, - PECI_STATUS_FINISH = 0x02, - PECI_STATUS_RD_FCS_ERR = 0x04, - PECI_STATUS_WR_FCS_ERR = 0x08, - PECI_STATUS_EXTERR = 0x20, - PECI_STATUS_BUSERR = 0x40, - PECI_STATUS_RCV_ERRCODE = 0x80, - PECI_STATUS_ERR_NEED_RST = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR), - PECI_STATUS_ANY_ERR = (PECI_STATUS_RCV_ERRCODE | - PECI_STATUS_BUSERR | - PECI_STATUS_EXTERR | - PECI_STATUS_WR_FCS_ERR | - PECI_STATUS_RD_FCS_ERR), - PECI_STATUS_ANY_BIT = 0xFE, - PECI_STATUS_TIMEOUT = 0xFF, -}; - -static task_id_t peci_current_task; - -static void peci_init_vtt_freq(void) -{ - /* - * bit2, enable the PECI interrupt generated by data valid event - * from PECI. - * - * bit[1-0], these bits are used to set PECI VTT level. - * 00b: 1.10v - * 01b: 1.05v - * 10b: 1.00v - */ - IT83XX_PECI_PADCTLR = 0x06; - - /* - * bit[2-0], these bits are used to set PECI host's optimal - * transfer rate. - * 000b: 2.0 MHz - * 001b: 1.0 MHz - * 100b: 1.6 MHz - */ - IT83XX_PECI_HOCTL2R = 0x01; -} - -static void peci_reset(void) -{ - /* Reset PECI */ - IT83XX_GCTRL_RSTC4 |= 0x10; - - /* short delay */ - udelay(15); - - peci_init_vtt_freq(); -} - -/** - * Start a PECI transaction - * - * @param peci transaction data - * - * @return zero if successful, non-zero if error - */ -int peci_transaction(struct peci_data *peci) -{ - uint8_t status; - int index; - - /* To enable PECI function pin */ - IT83XX_GPIO_GPCRF6 = 0x00; - - /* - * bit5, Both write and read data FIFO pointers will be cleared. - * - * bit4, This bit enables the PECI host to abort the transaction - * when FCS error occurs. - * - * bit2, This bit enables the contention mechanism of the PECI bus. - * When this bit is set, the host will abort the transaction - * if the PECI bus is contentious. - */ - IT83XX_PECI_HOCTLR |= 0x34; - - /* This register is the target address field of the PECI protocol. */ - IT83XX_PECI_HOTRADDR = peci->addr; - - /* This register is the write length field of the PECI protocol. */ - ASSERT(peci->w_len <= PECI_WRITE_DATA_FIFO_SIZE); - - if (peci->cmd_code == PECI_CMD_PING) { - /* write length is 0 */ - IT83XX_PECI_HOWRLR = 0x00; - } else { - if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) || - (peci->cmd_code == PECI_CMD_WR_IAMSR) || - (peci->cmd_code == PECI_CMD_WR_PCI_CFG) || - (peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) { - - /* write length include Cmd Code + AW FCS */ - IT83XX_PECI_HOWRLR = peci->w_len + 2; - - /* bit1, The bit enables the AW_FCS hardwired mechanism - * based on the PECI command. This bit is functional - * only when the AW_FCS supported command of - * PECI 2.0/3.0/3.1 is issued. - * When this bit is set, the hardware will handle the - * calculation of AW_FCS. - */ - IT83XX_PECI_HOCTLR |= 0x02; - } else { - /* write length include Cmd Code */ - IT83XX_PECI_HOWRLR = peci->w_len + 1; - - IT83XX_PECI_HOCTLR &= ~0x02; - } - } - - /* This register is the read length field of the PECI protocol. */ - ASSERT(peci->r_len <= PECI_READ_DATA_FIFO_SIZE); - IT83XX_PECI_HORDLR = peci->r_len; - - /* This register is the command field of the PECI protocol. */ - IT83XX_PECI_HOCMDR = peci->cmd_code; - - /* The write data field of the PECI protocol. */ - for (index = 0x00; index < peci->w_len; index++) - IT83XX_PECI_HOWRDR = peci->w_buf[index]; - - peci_current_task = task_get_current(); - task_clear_pending_irq(IT83XX_IRQ_PECI); - task_enable_irq(IT83XX_IRQ_PECI); - - /* start */ - IT83XX_PECI_HOCTLR |= 0x01; - - /* pre-set timeout */ - index = peci->timeout_us; - if (task_wait_event(peci->timeout_us) != TASK_EVENT_TIMER) - index = 0; - - task_disable_irq(IT83XX_IRQ_PECI); - - peci_current_task = TASK_ID_INVALID; - - if (index < peci->timeout_us) { - - status = IT83XX_PECI_HOSTAR; - - /* any error */ - if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) { - - if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST) - peci_reset(); - - } else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) { - - /* The read data field of the PECI protocol. */ - for (index = 0x00; index < peci->r_len; index++) - peci->r_buf[index] = IT83XX_PECI_HORDDR; - - /* W/C */ - IT83XX_PECI_HOSTAR = PECI_STATUS_FINISH; - status = IT83XX_PECI_HOSTAR; - } - } else { - /* transaction timeout */ - status = PECI_STATUS_TIMEOUT; - } - - /* Don't disable PECI host controller if controller already enable. */ - IT83XX_PECI_HOCTLR = 0x08; - - /* W/C */ - IT83XX_PECI_HOSTAR = PECI_STATUS_ANY_BIT; - - /* Disable PECI function pin */ - IT83XX_GPIO_GPCRF6 = 0x80; - - return status; -} - -void peci_interrupt(void) -{ - task_clear_pending_irq(IT83XX_IRQ_PECI); - task_disable_irq(IT83XX_IRQ_PECI); - - if (peci_current_task != TASK_ID_INVALID) - task_wake(peci_current_task); -} - -static void peci_init(void) -{ - clock_enable_peripheral(CGC_OFFSET_PECI, 0, 0); - peci_init_vtt_freq(); - - /* bit3,this bit enables the PECI host controller. */ - IT83XX_PECI_HOCTLR |= 0x08; - - /* bit4, PECI enable */ - IT83XX_GPIO_GRC2 |= 0x10; -} -DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT); diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c deleted file mode 100644 index 8aae12b9a1..0000000000 --- a/chip/it83xx/pwm.c +++ /dev/null @@ -1,273 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for IT83xx. */ - -#include "clock.h" -#include "gpio.h" -#include "hooks.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "util.h" -#include "math_util.h" - -#define PWM_CTRX_MIN 100 -#define PWM_EC_FREQ 8000000 - -const struct pwm_ctrl_t pwm_ctrl_regs[] = { - { &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0}, - { &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1}, - { &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2}, - { &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3}, - { &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4}, - { &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5}, - { &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6}, - { &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7}, -}; - -const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = { - { &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS, - &IT83XX_PWM_PCFSR, 0x01}, - { &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS, - &IT83XX_PWM_PCFSR, 0x02}, - { &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS, - &IT83XX_PWM_PCFSR, 0x04}, - { &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS, - &IT83XX_PWM_PCFSR, 0x08}, -}; - -static int pwm_get_cycle_time(enum pwm_channel ch) -{ - int pcs_shift; - int pcs_mask; - int pcs_reg; - int cycle_time_setting; - - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* bit shift for "Prescaler Clock Source Select Group" register. */ - pcs_shift = (ch % 4) * 2; - - /* setting of "Prescaler Clock Source Select Group" register. */ - pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source; - - /* only bit0 bit1 information. */ - pcs_mask = (pcs_reg >> pcs_shift) & 0x03; - - /* get cycle time setting of PWM channel x. */ - cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time; - - return cycle_time_setting; -} - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* - * enabled : pin to PWM function. - * disabled : pin to GPIO input function. - */ - if (enabled) - *pwm_ctrl_regs[ch].pwm_pin = 0x00; - else - *pwm_ctrl_regs[ch].pwm_pin = 0x80 | - ((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ? - 4 : 2); -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* pin is PWM function and PWMs clock counter was enabled */ - return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 && - IT83XX_PWM_ZTIER & 0x02) ? 1 : 0; -} - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - int pcs_shift; - int pcs_mask; - int pcs_reg; - int cycle_time_setting; - - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) - percent = 100 - percent; - - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* bit shift for "Prescaler Clock Source Select Group" register. */ - pcs_shift = (ch % 4) * 2; - - /* setting of "Prescaler Clock Source Select Group" register.*/ - pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source; - - /* only bit0 bit1 information. */ - pcs_mask = (pcs_reg >> pcs_shift) & 0x03; - - /* get cycle time setting of PWM channel x. */ - cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time; - - /* to update PWM DCRx depend on CTRx setting. */ - if (percent == 100) { - *pwm_ctrl_regs[ch].pwm_duty = cycle_time_setting; - } else { - *pwm_ctrl_regs[ch].pwm_duty = - ((cycle_time_setting + 1) * percent) / 100; - } -} - -int pwm_get_duty(enum pwm_channel ch) -{ - int pcs_mask; - int pcs_reg; - int cycle_time_setting; - int percent; - int ch_idx; - - ch_idx = ch; - - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* setting of "Prescaler Clock Source Select Group" register.*/ - pcs_reg = *pwm_ctrl_regs[ch].pwm_clock_source; - - /* only bit0 bit1 information. */ - pcs_mask = (pcs_reg >> ((ch % 4) * 2)) & 0x03; - - /* get cycle time setting of PWM channel x. */ - cycle_time_setting = *pwm_clock_ctrl_regs[pcs_mask].pwm_cycle_time; - - percent = *pwm_ctrl_regs[ch].pwm_duty * 100 / cycle_time_setting; - - if (pwm_channels[ch_idx].flags & PWM_CONFIG_ACTIVE_LOW) - percent = 100 - percent; - - /* output signal duty cycle. */ - return percent; -} - -void pwm_duty_inc(enum pwm_channel ch) -{ - int cycle_time, pwm_ch; - - /* pwm channel mapping */ - pwm_ch = pwm_channels[ch].channel; - - cycle_time = pwm_get_cycle_time(ch); - - if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) { - if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0) - *pwm_ctrl_regs[pwm_ch].pwm_duty -= 1; - } else { - if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time) - *pwm_ctrl_regs[pwm_ch].pwm_duty += 1; - } -} - -void pwm_duty_reduce(enum pwm_channel ch) -{ - int cycle_time, pwm_ch; - - /* pwm channel mapping */ - pwm_ch = pwm_channels[ch].channel; - - cycle_time = pwm_get_cycle_time(ch); - - if (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) { - if (*pwm_ctrl_regs[pwm_ch].pwm_duty < cycle_time) - *pwm_ctrl_regs[pwm_ch].pwm_duty += 1; - } else { - if (*pwm_ctrl_regs[pwm_ch].pwm_duty > 0) - *pwm_ctrl_regs[pwm_ch].pwm_duty -= 1; - } -} - -static int pwm_ch_freq(enum pwm_channel ch) -{ - int actual_freq = -1, targe_freq, deviation; - int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask; - int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ? - 32768 : PWM_EC_FREQ; - - targe_freq = pwm_channels[ch].freq_hz; - deviation = (targe_freq / 100) + 1; - - for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) { - pcfsr = (pwm_clk_src / (ctr + 1) / targe_freq) - 1; - if (pcfsr >= 0) { - actual_freq = pwm_clk_src / (ctr + 1) / (pcfsr + 1); - if (ABS(actual_freq - targe_freq) < deviation) - break; - } - } - - if (ctr < PWM_CTRX_MIN) { - actual_freq = -1; - } else { - pcfsr_sel = pwm_channels[ch].pcfsr_sel; - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cycle_time = ctr; - - if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) - /* - * Select 32.768KHz as PWM clock source. -] * - * NOTE: - * For pwm_channels[], the maximum supported pwm output - * signal frequency is 324 Hz (32768/(PWM_CTRX_MIN+1)). - */ - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg &= - ~pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl; - else - /* ec clock 8MHz */ - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_reg |= - pwm_clock_ctrl_regs[pcfsr_sel].pwm_pcfsr_ctrl; - - /* pwm channel mapping */ - ch = pwm_channels[ch].channel; - - /* - * bit shift for "Prescaler Clock Source Select Group" - * register. - */ - pcs_shift = (ch % 4) * 2; - pcs_mask = pcfsr_sel << pcs_shift; - - *pwm_ctrl_regs[ch].pwm_clock_source &= ~(0x3 << pcs_shift); - *pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask; - - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF; - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb = - (pcfsr >> 8) & 0xFF; - } - - return actual_freq; -} - -static void pwm_init(void) -{ - int ch; - - for (ch = 0; ch < PWM_CH_COUNT; ch++) - pwm_ch_freq(ch); - - /* enable PWMs clock counter. */ - IT83XX_PWM_ZTIER |= 0x02; -} - -/* The chip PWM module initialization. */ -DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM); diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h deleted file mode 100644 index 4e8aba1c62..0000000000 --- a/chip/it83xx/pwm_chip.h +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for IT83xx. */ - -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -enum pwm_pcfsr_sel { - PWM_PRESCALER_C4 = 1, - PWM_PRESCALER_C6 = 2, - PWM_PRESCALER_C7 = 3, -}; - -enum pwm_hw_channel { - PWM_HW_CH_DCR0 = 0, - PWM_HW_CH_DCR1, - PWM_HW_CH_DCR2, - PWM_HW_CH_DCR3, - PWM_HW_CH_DCR4, - PWM_HW_CH_DCR5, - PWM_HW_CH_DCR6, - PWM_HW_CH_DCR7, - - PWM_HW_CH_TOTAL, -}; - -enum tach_ch_sel { - /* Pin GPIOD.6 */ - TACH_CH_TACH0A = 0, - /* Pin GPIOD.7 */ - TACH_CH_TACH1A, - /* Pin GPIOJ.2 */ - TACH_CH_TACH0B, - /* Pin GPIOJ.3 */ - TACH_CH_TACH1B, - /* Number of TACH channels */ - TACH_CH_COUNT, - - TACH_CH_NULL = 0xFF, -}; - -/* Data structure to define PWM channel control registers. */ -struct pwm_ctrl_t { - /* PWM channel output duty register. */ - volatile uint8_t *pwm_duty; - /* PWM channel clock source selection register. */ - volatile uint8_t *pwm_clock_source; - /* PWM channel pin control register. */ - volatile uint8_t *pwm_pin; -}; - -/* Data structure to define PWM channel control registers part 2. */ -struct pwm_ctrl_t2 { - /* PWM cycle time register. */ - volatile uint8_t *pwm_cycle_time; - /* PWM channel clock prescaler register (LSB). */ - volatile uint8_t *pwm_cpr_lsb; - /* PWM channel clock prescaler register (MSB). */ - volatile uint8_t *pwm_cpr_msb; - /* PWM prescaler clock frequency select register. */ - volatile uint8_t *pwm_pcfsr_reg; - /* PWM prescaler clock frequency select register setting. */ - uint8_t pwm_pcfsr_ctrl; -}; - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* PWM channel ID */ - int channel; - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; - int freq_hz; - enum pwm_pcfsr_sel pcfsr_sel; -}; - -/* Tachometer channel of each physical fan */ -struct fan_tach_t { - enum tach_ch_sel ch_tach; - /* the numbers of square pulses per revolution of fan. */ - int fan_p; - /* allow actual rpm ~= targe rpm +- rpm_re */ - int rpm_re; - /* startup duty of fan */ - int s_duty; -}; - -extern const struct pwm_t pwm_channels[]; -/* The list of tachometer channel of fans is instantiated in board.c. */ -extern const struct fan_tach_t fan_tach[]; - -void pwm_duty_inc(enum pwm_channel ch); -void pwm_duty_reduce(enum pwm_channel ch); - -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h deleted file mode 100644 index 65460009b7..0000000000 --- a/chip/it83xx/registers.h +++ /dev/null @@ -1,1614 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for IT83xx processor - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" - -#define __ram_code __attribute__((section(".ram_code"))) - -/* IRQ numbers */ -/* Group 0 */ -#define IT83XX_IRQ_WKO20 1 -#define IT83XX_IRQ_KBC_OUT 2 -#define IT83XX_IRQ_PMC_OUT 3 -#define IT83XX_IRQ_SMB_D 4 -#define IT83XX_IRQ_WKINTAD 5 -#define IT83XX_IRQ_WKO23 6 -#define IT83XX_IRQ_PWM 7 -/* Group 1 */ -#define IT83XX_IRQ_ADC 8 -#define IT83XX_IRQ_SMB_A 9 -#define IT83XX_IRQ_SMB_B 10 -#define IT83XX_IRQ_KB_MATRIX 11 -#define IT83XX_IRQ_WKO26 12 -#define IT83XX_IRQ_WKINTC 13 -#define IT83XX_IRQ_WKO25 14 -#define IT83XX_IRQ_CIR 15 -/* Group 2 */ -#define IT83XX_IRQ_SMB_C 16 -#define IT83XX_IRQ_WKO24 17 -#define IT83XX_IRQ_PS2_2 18 -#define IT83XX_IRQ_PS2_1 19 -#define IT83XX_IRQ_PS2_0 20 -#define IT83XX_IRQ_WKO22 21 -#define IT83XX_IRQ_SMFI 22 -#define IT83XX_IRQ_USB 23 -/* Group 3 */ -#define IT83XX_IRQ_KBC_IN 24 -#define IT83XX_IRQ_PMC_IN 25 -#define IT83XX_IRQ_PMC2_OUT 26 -#define IT83XX_IRQ_PMC2_IN 27 -#define IT83XX_IRQ_GINT 28 -#define IT83XX_IRQ_EGPC 29 -#define IT83XX_IRQ_EXT_TIMER1 30 -#define IT83XX_IRQ_WKO21 31 -/* Group 4 */ -#define IT83XX_IRQ_GPINT0 32 -#define IT83XX_IRQ_GPINT1 33 -#define IT83XX_IRQ_GPINT2 34 -#define IT83XX_IRQ_GPINT3 35 -#define IT83XX_IRQ_CIR_GPINT 36 -#define IT83XX_IRQ_SSPI 37 -#define IT83XX_IRQ_UART1 38 -#define IT83XX_IRQ_UART2 39 -/* Group 5 */ -#define IT83XX_IRQ_WKO50 40 -#define IT83XX_IRQ_WKO51 41 -#define IT83XX_IRQ_WKO52 42 -#define IT83XX_IRQ_WKO53 43 -#define IT83XX_IRQ_WKO54 44 -#define IT83XX_IRQ_WKO55 45 -#define IT83XX_IRQ_WKO56 46 -#define IT83XX_IRQ_WKO57 47 -/* Group 6 */ -#define IT83XX_IRQ_WKO60 48 -#define IT83XX_IRQ_WKO61 49 -#define IT83XX_IRQ_WKO62 50 -#define IT83XX_IRQ_WKO63 51 -#define IT83XX_IRQ_WKO64 52 -#define IT83XX_IRQ_WKO65 53 -#define IT83XX_IRQ_WKO66 54 -#define IT83XX_IRQ_WKO67 55 -/* Group 7 */ -#define IT83XX_IRQ_RTCT_ALARM1 56 -#define IT83XX_IRQ_RTCT_ALARM2 57 -#define IT83XX_IRQ_EXT_TIMER2 58 -#define IT83XX_IRQ_DEFERRED_SPI 59 -#define IT83XX_IRQ_TMR_A0 60 -#define IT83XX_IRQ_TMR_A1 61 -#define IT83XX_IRQ_TMR_B0 62 -#define IT83XX_IRQ_TMR_B1 63 -/* Group 8 */ -#define IT83XX_IRQ_PMC2EX_OUT 64 -#define IT83XX_IRQ_PMC2EX_IN 65 -#define IT83XX_IRQ_PMC3_OUT 66 -#define IT83XX_IRQ_PMC3_IN 67 -#define IT83XX_IRQ_PMC4_OUT 68 -#define IT83XX_IRQ_PMC4_IN 69 -#define IT83XX_IRQ_I2BRAM 71 -/* Group 9 */ -#define IT83XX_IRQ_WKO70 72 -#define IT83XX_IRQ_WKO71 73 -#define IT83XX_IRQ_WKO72 74 -#define IT83XX_IRQ_WKO73 75 -#define IT83XX_IRQ_WKO74 76 -#define IT83XX_IRQ_WKO75 77 -#define IT83XX_IRQ_WKO76 78 -#define IT83XX_IRQ_WKO77 79 -/* Group 10 */ -#define IT83XX_IRQ_EXT_TMR8 80 -#define IT83XX_IRQ_SMB_CLOCK_HELD 81 -#define IT83XX_IRQ_CEC 82 -#define IT83XX_IRQ_H2RAM_LPC 83 -#define IT83XX_IRQ_HW_KB_SCAN 84 -#define IT83XX_IRQ_WKO88 85 -#define IT83XX_IRQ_WKO89 86 -#define IT83XX_IRQ_WKO90 87 -/* Group 11 */ -#define IT83XX_IRQ_WKO80 88 -#define IT83XX_IRQ_WKO81 89 -#define IT83XX_IRQ_WKO82 90 -#define IT83XX_IRQ_WKO83 91 -#define IT83XX_IRQ_WKO84 92 -#define IT83XX_IRQ_WKO85 93 -#define IT83XX_IRQ_WKO86 94 -#define IT83XX_IRQ_WKO87 95 -/* Group 12 */ -#define IT83XX_IRQ_WKO91 96 -#define IT83XX_IRQ_WKO92 97 -#define IT83XX_IRQ_WKO93 98 -#define IT83XX_IRQ_WKO94 99 -#define IT83XX_IRQ_WKO95 100 -#define IT83XX_IRQ_WKO96 101 -#define IT83XX_IRQ_WKO97 102 -#define IT83XX_IRQ_WKO98 103 -/* Group 13 */ -#define IT83XX_IRQ_WKO99 104 -#define IT83XX_IRQ_WKO100 105 -#define IT83XX_IRQ_WKO101 106 -#define IT83XX_IRQ_WKO102 107 -#define IT83XX_IRQ_WKO103 108 -#define IT83XX_IRQ_WKO104 109 -#define IT83XX_IRQ_WKO105 110 -#define IT83XX_IRQ_WKO106 111 -/* Group 14 */ -#define IT83XX_IRQ_WKO107 112 -#define IT83XX_IRQ_WKO108 113 -#define IT83XX_IRQ_WKO109 114 -#define IT83XX_IRQ_WKO110 115 -#define IT83XX_IRQ_WKO111 116 -#define IT83XX_IRQ_WKO112 117 -#define IT83XX_IRQ_WKO113 118 -#define IT83XX_IRQ_WKO114 119 -/* Group 15 */ -#define IT83XX_IRQ_WKO115 120 -#define IT83XX_IRQ_WKO116 121 -#define IT83XX_IRQ_WKO117 122 -#define IT83XX_IRQ_WKO118 123 -#define IT83XX_IRQ_WKO119 124 -#define IT83XX_IRQ_WKO120 125 -#define IT83XX_IRQ_WKO121 126 -#define IT83XX_IRQ_WKO122 127 -/* Group 16 */ -#define IT83XX_IRQ_WKO128 128 -#define IT83XX_IRQ_WKO129 129 -#define IT83XX_IRQ_WKO130 130 -#define IT83XX_IRQ_WKO131 131 -#define IT83XX_IRQ_WKO132 132 -#define IT83XX_IRQ_WKO133 133 -#define IT83XX_IRQ_WKO134 134 -/* Group 17 */ -#define IT83XX_IRQ_WKO136 136 -#define IT83XX_IRQ_WKO137 137 -#define IT83XX_IRQ_WKO138 138 -#define IT83XX_IRQ_WKO139 139 -#define IT83XX_IRQ_WKO140 140 -#define IT83XX_IRQ_WKO141 141 -#define IT83XX_IRQ_WKO142 142 -#define IT83XX_IRQ_WKO143 143 -/* Group 18 */ -#define IT83XX_IRQ_WKO123 144 -#define IT83XX_IRQ_WKO124 145 -#define IT83XX_IRQ_WKO125 146 -#define IT83XX_IRQ_WKO126 147 -#define IT83XX_IRQ_PMC5_OUT 149 -#define IT83XX_IRQ_PMC5_IN 150 -#define IT83XX_IRQ_V_COMP 151 -/* Group 19 */ -#define IT83XX_IRQ_SMB_E 152 -#define IT83XX_IRQ_SMB_F 153 -#define IT83XX_IRQ_OSC_DMA 154 -#define IT83XX_IRQ_EXT_TIMER3 155 -#define IT83XX_IRQ_EXT_TIMER4 156 -#define IT83XX_IRQ_EXT_TIMER5 157 -#define IT83XX_IRQ_EXT_TIMER6 158 -#define IT83XX_IRQ_EXT_TIMER7 159 -/* Group 20 */ -#define IT83XX_IRQ_PECI 160 -#define IT83XX_IRQ_SOFTWARE 161 -#define IT83XX_IRQ_ESPI 162 -#define IT83XX_IRQ_ESPI_VW 163 -#define IT83XX_IRQ_PCH_P80 164 -#define IT83XX_IRQ_USBPD0 165 -#define IT83XX_IRQ_USBPD1 166 -/* Group 21 */ -#if defined(CHIP_FAMILY_IT8320) -#define IT83XX_IRQ_WKO40 168 -#define IT83XX_IRQ_WKO45 169 -#define IT83XX_IRQ_WKO46 170 -#define IT83XX_IRQ_WKO144 171 -#define IT83XX_IRQ_WKO145 172 -#define IT83XX_IRQ_WKO146 173 -#define IT83XX_IRQ_WKO147 174 -#define IT83XX_IRQ_WKO148 175 -/* Group 22 */ -#define IT83XX_IRQ_WKO149 176 -#define IT83XX_IRQ_WKO150 177 - -#define IT83XX_IRQ_COUNT 178 -#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) -/* Group 21 */ -#define IT83XX_IRQ_AUDIO_IF 170 -#define IT83XX_IRQ_SPI_SLAVE 171 -#define IT83XX_IRQ_DSP_ENGINE 172 -#define IT83XX_IRQ_NN_ENGINE 173 -#define IT83XX_IRQ_USBPD2 174 -#define IT83XX_IRQ_CRYPTO 175 -/* Group 22 */ -#define IT83XX_IRQ_WKO40 176 -#define IT83XX_IRQ_WKO45 177 -#define IT83XX_IRQ_WKO46 178 -#define IT83XX_IRQ_WKO144 179 -#define IT83XX_IRQ_WKO145 180 -#define IT83XX_IRQ_WKO146 181 -#define IT83XX_IRQ_WKO147 182 -#define IT83XX_IRQ_WKO148 183 -/* Group 23 */ -#define IT83XX_IRQ_WKO149 184 -#define IT83XX_IRQ_WKO150 185 -#define IT83XX_IRQ_SSPI1 191 -/* Group 24 */ -#define IT83XX_IRQ_XLPIN0 192 -#define IT83XX_IRQ_XLPIN1 193 -#define IT83XX_IRQ_XLPIN2 194 -#define IT83XX_IRQ_XLPIN3 195 -#define IT83XX_IRQ_XLPIN4 196 -#define IT83XX_IRQ_XLPIN5 197 -#define IT83XX_IRQ_WEEK_ALARM 199 -/* Group 25 */ -#define IT83XX_IRQ_GPO0 200 -#define IT83XX_IRQ_GPO1 201 -#define IT83XX_IRQ_GPO2 202 -#define IT83XX_IRQ_GPO3 203 -/* Group 26 */ -#define IT83XX_IRQ_GPP0 208 -#define IT83XX_IRQ_GPP1 209 -#define IT83XX_IRQ_GPP2 210 -#define IT83XX_IRQ_GPP3 211 -#define IT83XX_IRQ_GPP4 212 -#define IT83XX_IRQ_GPP5 213 -#define IT83XX_IRQ_GPP6 214 -/* Group 27 */ -#define IT83XX_IRQ_GPQ0 216 -#define IT83XX_IRQ_GPQ1 217 -#define IT83XX_IRQ_GPQ2 218 -#define IT83XX_IRQ_GPQ3 219 -#define IT83XX_IRQ_GPQ4 220 -#define IT83XX_IRQ_GPQ5 221 -/* Group 28 */ -#define IT83XX_IRQ_GPR0 224 -#define IT83XX_IRQ_GPR1 225 -#define IT83XX_IRQ_GPR2 226 -#define IT83XX_IRQ_GPR3 227 -#define IT83XX_IRQ_GPR4 228 -#define IT83XX_IRQ_GPR5 229 - -#define IT83XX_IRQ_COUNT 230 -#endif /* !defined(CHIP_FAMILY_IT8320) */ - -/* IRQ dispatching to CPU INT vectors */ -#define IT83XX_CPU_INT_IRQ_1 2 -#define IT83XX_CPU_INT_IRQ_2 5 -#define IT83XX_CPU_INT_IRQ_3 4 -#define IT83XX_CPU_INT_IRQ_4 6 -#define IT83XX_CPU_INT_IRQ_5 2 -#define IT83XX_CPU_INT_IRQ_6 2 -#define IT83XX_CPU_INT_IRQ_7 4 -#define IT83XX_CPU_INT_IRQ_8 7 -#define IT83XX_CPU_INT_IRQ_9 6 -#define IT83XX_CPU_INT_IRQ_10 6 -#define IT83XX_CPU_INT_IRQ_11 5 -#define IT83XX_CPU_INT_IRQ_12 2 -#define IT83XX_CPU_INT_IRQ_13 2 -#define IT83XX_CPU_INT_IRQ_14 2 -#define IT83XX_CPU_INT_IRQ_15 8 -#define IT83XX_CPU_INT_IRQ_16 6 -#define IT83XX_CPU_INT_IRQ_17 2 -#define IT83XX_CPU_INT_IRQ_18 8 -#define IT83XX_CPU_INT_IRQ_19 8 -#define IT83XX_CPU_INT_IRQ_20 8 -#define IT83XX_CPU_INT_IRQ_21 2 -#define IT83XX_CPU_INT_IRQ_22 12 -#define IT83XX_CPU_INT_IRQ_23 12 -#define IT83XX_CPU_INT_IRQ_24 5 -#define IT83XX_CPU_INT_IRQ_25 4 -#define IT83XX_CPU_INT_IRQ_26 4 -#define IT83XX_CPU_INT_IRQ_27 4 -#define IT83XX_CPU_INT_IRQ_28 11 -#define IT83XX_CPU_INT_IRQ_29 11 -#define IT83XX_CPU_INT_IRQ_30 3 -#define IT83XX_CPU_INT_IRQ_31 2 -#define IT83XX_CPU_INT_IRQ_32 11 -#define IT83XX_CPU_INT_IRQ_33 11 -#define IT83XX_CPU_INT_IRQ_34 11 -#define IT83XX_CPU_INT_IRQ_35 11 -#define IT83XX_CPU_INT_IRQ_36 8 -#define IT83XX_CPU_INT_IRQ_37 9 -#define IT83XX_CPU_INT_IRQ_38 9 -#define IT83XX_CPU_INT_IRQ_39 9 -#define IT83XX_CPU_INT_IRQ_40 2 -#define IT83XX_CPU_INT_IRQ_41 2 -#define IT83XX_CPU_INT_IRQ_42 2 -#define IT83XX_CPU_INT_IRQ_43 2 -#define IT83XX_CPU_INT_IRQ_44 2 -#define IT83XX_CPU_INT_IRQ_45 2 -#define IT83XX_CPU_INT_IRQ_46 2 -#define IT83XX_CPU_INT_IRQ_47 2 -#define IT83XX_CPU_INT_IRQ_48 2 -#define IT83XX_CPU_INT_IRQ_49 2 -#define IT83XX_CPU_INT_IRQ_50 2 -#define IT83XX_CPU_INT_IRQ_51 2 -#define IT83XX_CPU_INT_IRQ_52 2 -#define IT83XX_CPU_INT_IRQ_53 2 -#define IT83XX_CPU_INT_IRQ_54 2 -#define IT83XX_CPU_INT_IRQ_55 2 -#define IT83XX_CPU_INT_IRQ_56 10 -#define IT83XX_CPU_INT_IRQ_57 10 -#define IT83XX_CPU_INT_IRQ_58 3 -#define IT83XX_CPU_INT_IRQ_59 12 -#define IT83XX_CPU_INT_IRQ_60 3 -#define IT83XX_CPU_INT_IRQ_61 3 -#define IT83XX_CPU_INT_IRQ_62 3 -#define IT83XX_CPU_INT_IRQ_63 3 -#define IT83XX_CPU_INT_IRQ_64 4 -#define IT83XX_CPU_INT_IRQ_65 4 -#define IT83XX_CPU_INT_IRQ_66 4 -#define IT83XX_CPU_INT_IRQ_67 4 -#define IT83XX_CPU_INT_IRQ_68 4 -#define IT83XX_CPU_INT_IRQ_69 4 -#define IT83XX_CPU_INT_IRQ_71 12 -#define IT83XX_CPU_INT_IRQ_72 2 -#define IT83XX_CPU_INT_IRQ_73 2 -#define IT83XX_CPU_INT_IRQ_74 2 -#define IT83XX_CPU_INT_IRQ_75 2 -#define IT83XX_CPU_INT_IRQ_76 2 -#define IT83XX_CPU_INT_IRQ_77 2 -#define IT83XX_CPU_INT_IRQ_78 2 -#define IT83XX_CPU_INT_IRQ_79 2 -#define IT83XX_CPU_INT_IRQ_80 3 -#define IT83XX_CPU_INT_IRQ_81 6 -#define IT83XX_CPU_INT_IRQ_82 12 -#define IT83XX_CPU_INT_IRQ_83 12 -#define IT83XX_CPU_INT_IRQ_84 5 -#define IT83XX_CPU_INT_IRQ_85 2 -#define IT83XX_CPU_INT_IRQ_86 2 -#define IT83XX_CPU_INT_IRQ_87 2 -#define IT83XX_CPU_INT_IRQ_88 2 -#define IT83XX_CPU_INT_IRQ_89 2 -#define IT83XX_CPU_INT_IRQ_90 2 -#define IT83XX_CPU_INT_IRQ_91 2 -#define IT83XX_CPU_INT_IRQ_92 2 -#define IT83XX_CPU_INT_IRQ_93 2 -#define IT83XX_CPU_INT_IRQ_94 2 -#define IT83XX_CPU_INT_IRQ_95 2 -#define IT83XX_CPU_INT_IRQ_96 2 -#define IT83XX_CPU_INT_IRQ_97 2 -#define IT83XX_CPU_INT_IRQ_98 2 -#define IT83XX_CPU_INT_IRQ_99 2 -#define IT83XX_CPU_INT_IRQ_100 2 -#define IT83XX_CPU_INT_IRQ_101 2 -#define IT83XX_CPU_INT_IRQ_102 2 -#define IT83XX_CPU_INT_IRQ_103 2 -#define IT83XX_CPU_INT_IRQ_104 2 -#define IT83XX_CPU_INT_IRQ_105 2 -#define IT83XX_CPU_INT_IRQ_106 2 -#define IT83XX_CPU_INT_IRQ_107 2 -#define IT83XX_CPU_INT_IRQ_108 2 -#define IT83XX_CPU_INT_IRQ_109 2 -#define IT83XX_CPU_INT_IRQ_110 2 -#define IT83XX_CPU_INT_IRQ_111 2 -#define IT83XX_CPU_INT_IRQ_112 2 -#define IT83XX_CPU_INT_IRQ_113 2 -#define IT83XX_CPU_INT_IRQ_114 2 -#define IT83XX_CPU_INT_IRQ_115 2 -#define IT83XX_CPU_INT_IRQ_116 2 -#define IT83XX_CPU_INT_IRQ_117 2 -#define IT83XX_CPU_INT_IRQ_118 2 -#define IT83XX_CPU_INT_IRQ_119 2 -#define IT83XX_CPU_INT_IRQ_120 2 -#define IT83XX_CPU_INT_IRQ_121 2 -#define IT83XX_CPU_INT_IRQ_122 2 -#define IT83XX_CPU_INT_IRQ_123 2 -#define IT83XX_CPU_INT_IRQ_124 2 -#define IT83XX_CPU_INT_IRQ_125 2 -#define IT83XX_CPU_INT_IRQ_126 2 -#define IT83XX_CPU_INT_IRQ_127 2 -#define IT83XX_CPU_INT_IRQ_128 2 -#define IT83XX_CPU_INT_IRQ_129 2 -#define IT83XX_CPU_INT_IRQ_130 2 -#define IT83XX_CPU_INT_IRQ_131 2 -#define IT83XX_CPU_INT_IRQ_132 2 -#define IT83XX_CPU_INT_IRQ_133 2 -#define IT83XX_CPU_INT_IRQ_134 2 -#define IT83XX_CPU_INT_IRQ_136 2 -#define IT83XX_CPU_INT_IRQ_137 2 -#define IT83XX_CPU_INT_IRQ_138 2 -#define IT83XX_CPU_INT_IRQ_139 2 -#define IT83XX_CPU_INT_IRQ_140 2 -#define IT83XX_CPU_INT_IRQ_141 2 -#define IT83XX_CPU_INT_IRQ_142 2 -#define IT83XX_CPU_INT_IRQ_143 2 -#define IT83XX_CPU_INT_IRQ_144 2 -#define IT83XX_CPU_INT_IRQ_145 2 -#define IT83XX_CPU_INT_IRQ_146 2 -#define IT83XX_CPU_INT_IRQ_147 2 -#define IT83XX_CPU_INT_IRQ_149 4 -#define IT83XX_CPU_INT_IRQ_150 4 -#define IT83XX_CPU_INT_IRQ_151 7 -#define IT83XX_CPU_INT_IRQ_152 6 -#define IT83XX_CPU_INT_IRQ_153 6 -#define IT83XX_CPU_INT_IRQ_154 12 -#define IT83XX_CPU_INT_IRQ_155 3 -#define IT83XX_CPU_INT_IRQ_156 3 -#define IT83XX_CPU_INT_IRQ_157 3 -#define IT83XX_CPU_INT_IRQ_158 3 -#define IT83XX_CPU_INT_IRQ_159 3 -#define IT83XX_CPU_INT_IRQ_160 12 -#define IT83XX_CPU_INT_IRQ_161 12 -#define IT83XX_CPU_INT_IRQ_162 12 -#define IT83XX_CPU_INT_IRQ_163 12 -#define IT83XX_CPU_INT_IRQ_164 12 -#define IT83XX_CPU_INT_IRQ_165 12 -#define IT83XX_CPU_INT_IRQ_166 12 -#define IT83XX_CPU_INT_IRQ_167 12 -#define IT83XX_CPU_INT_IRQ_168 2 -#define IT83XX_CPU_INT_IRQ_169 2 -#if defined(CHIP_FAMILY_IT8320) -#define IT83XX_CPU_INT_IRQ_170 2 -#define IT83XX_CPU_INT_IRQ_171 2 -#define IT83XX_CPU_INT_IRQ_172 2 -#define IT83XX_CPU_INT_IRQ_173 2 -#define IT83XX_CPU_INT_IRQ_174 2 -#define IT83XX_CPU_INT_IRQ_175 2 -#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) -#define IT83XX_CPU_INT_IRQ_170 12 -#define IT83XX_CPU_INT_IRQ_171 12 -#define IT83XX_CPU_INT_IRQ_172 12 -#define IT83XX_CPU_INT_IRQ_173 12 -#define IT83XX_CPU_INT_IRQ_174 12 -#define IT83XX_CPU_INT_IRQ_175 12 -#endif -#define IT83XX_CPU_INT_IRQ_176 2 -#define IT83XX_CPU_INT_IRQ_177 2 -#define IT83XX_CPU_INT_IRQ_178 2 -#define IT83XX_CPU_INT_IRQ_179 2 -#define IT83XX_CPU_INT_IRQ_180 2 -#define IT83XX_CPU_INT_IRQ_181 2 -#define IT83XX_CPU_INT_IRQ_182 2 -#define IT83XX_CPU_INT_IRQ_183 2 -#define IT83XX_CPU_INT_IRQ_184 2 -#define IT83XX_CPU_INT_IRQ_185 2 -#define IT83XX_CPU_INT_IRQ_191 2 -#define IT83XX_CPU_INT_IRQ_192 2 -#define IT83XX_CPU_INT_IRQ_193 2 -#define IT83XX_CPU_INT_IRQ_194 2 -#define IT83XX_CPU_INT_IRQ_195 2 -#define IT83XX_CPU_INT_IRQ_196 2 -#define IT83XX_CPU_INT_IRQ_197 2 -#define IT83XX_CPU_INT_IRQ_199 2 -#define IT83XX_CPU_INT_IRQ_200 2 -#define IT83XX_CPU_INT_IRQ_201 2 -#define IT83XX_CPU_INT_IRQ_202 2 -#define IT83XX_CPU_INT_IRQ_203 2 -#define IT83XX_CPU_INT_IRQ_208 2 -#define IT83XX_CPU_INT_IRQ_209 2 -#define IT83XX_CPU_INT_IRQ_210 2 -#define IT83XX_CPU_INT_IRQ_211 2 -#define IT83XX_CPU_INT_IRQ_212 2 -#define IT83XX_CPU_INT_IRQ_213 2 -#define IT83XX_CPU_INT_IRQ_214 2 -#define IT83XX_CPU_INT_IRQ_216 2 -#define IT83XX_CPU_INT_IRQ_217 2 -#define IT83XX_CPU_INT_IRQ_218 2 -#define IT83XX_CPU_INT_IRQ_219 2 -#define IT83XX_CPU_INT_IRQ_220 2 -#define IT83XX_CPU_INT_IRQ_221 2 -#define IT83XX_CPU_INT_IRQ_224 2 -#define IT83XX_CPU_INT_IRQ_225 2 -#define IT83XX_CPU_INT_IRQ_226 2 -#define IT83XX_CPU_INT_IRQ_227 2 -#define IT83XX_CPU_INT_IRQ_228 2 -#define IT83XX_CPU_INT_IRQ_229 2 - -/* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */ -#define CPU_INT_2_ALL_GPIOS 255 -#define IT83XX_CPU_INT_IRQ_255 2 - -#define CPU_INT_GROUP_5 254 -#define IT83XX_CPU_INT_IRQ_254 5 - -#define CPU_INT_GROUP_4 252 -#define IT83XX_CPU_INT_IRQ_252 4 - -#define CPU_INT_GROUP_12 253 -#define IT83XX_CPU_INT_IRQ_253 12 - -#define CPU_INT_GROUP_3 251 -#define IT83XX_CPU_INT_IRQ_251 3 - -#define CPU_INT_GROUP_6 250 -#define IT83XX_CPU_INT_IRQ_250 6 - -#define CPU_INT_GROUP_9 249 -#define IT83XX_CPU_INT_IRQ_249 9 - -#define CPU_INT_GROUP_7 248 -#define IT83XX_CPU_INT_IRQ_248 7 - -#define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq) - -/* --- INTC --- */ -#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE - -#define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE+(n)) - -#define IT83XX_INTC_AIVCT REG8(IT83XX_INTC_BASE+0x10) - -#define IT83XX_INTC_IER0 REG8(IT83XX_INTC_BASE+0x04) -#define IT83XX_INTC_IER1 REG8(IT83XX_INTC_BASE+0x05) -#define IT83XX_INTC_IER2 REG8(IT83XX_INTC_BASE+0x06) -#define IT83XX_INTC_IER3 REG8(IT83XX_INTC_BASE+0x07) -#define IT83XX_INTC_IER4 REG8(IT83XX_INTC_BASE+0x15) -#define IT83XX_INTC_IER5 REG8(IT83XX_INTC_BASE+0x19) -#define IT83XX_INTC_IER6 REG8(IT83XX_INTC_BASE+0x1d) -#define IT83XX_INTC_IER7 REG8(IT83XX_INTC_BASE+0x21) -#define IT83XX_INTC_IER8 REG8(IT83XX_INTC_BASE+0x25) -#define IT83XX_INTC_IER9 REG8(IT83XX_INTC_BASE+0x29) -#define IT83XX_INTC_IER10 REG8(IT83XX_INTC_BASE+0x2d) -#define IT83XX_INTC_IER11 REG8(IT83XX_INTC_BASE+0x31) -#define IT83XX_INTC_IER12 REG8(IT83XX_INTC_BASE+0x35) -#define IT83XX_INTC_IER13 REG8(IT83XX_INTC_BASE+0x39) -#define IT83XX_INTC_IER14 REG8(IT83XX_INTC_BASE+0x3d) -#define IT83XX_INTC_IER15 REG8(IT83XX_INTC_BASE+0x41) -#define IT83XX_INTC_IER16 REG8(IT83XX_INTC_BASE+0x45) -#define IT83XX_INTC_IER17 REG8(IT83XX_INTC_BASE+0x49) -#define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE+0x4d) -#define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE+0x51) -#define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE+0x55) -#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE+0x59) -#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE+0x5d) -#define IT83XX_INTC_IER23 REG8(IT83XX_INTC_BASE+0x91) -#define IT83XX_INTC_IER24 REG8(IT83XX_INTC_BASE+0x95) -#define IT83XX_INTC_IER25 REG8(IT83XX_INTC_BASE+0x99) -#define IT83XX_INTC_IER26 REG8(IT83XX_INTC_BASE+0x9d) -#define IT83XX_INTC_IER27 REG8(IT83XX_INTC_BASE+0xa1) -#define IT83XX_INTC_IER28 REG8(IT83XX_INTC_BASE+0xa5) - -#define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE+0x00) -#define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE+0x01) -#define IT83XX_INTC_ISR2 REG8(IT83XX_INTC_BASE+0x02) -#define IT83XX_INTC_ISR3 REG8(IT83XX_INTC_BASE+0x03) -#define IT83XX_INTC_ISR4 REG8(IT83XX_INTC_BASE+0x14) -#define IT83XX_INTC_ISR5 REG8(IT83XX_INTC_BASE+0x18) -#define IT83XX_INTC_ISR6 REG8(IT83XX_INTC_BASE+0x1c) -#define IT83XX_INTC_ISR7 REG8(IT83XX_INTC_BASE+0x20) -#define IT83XX_INTC_ISR8 REG8(IT83XX_INTC_BASE+0x24) -#define IT83XX_INTC_ISR9 REG8(IT83XX_INTC_BASE+0x28) -#define IT83XX_INTC_ISR10 REG8(IT83XX_INTC_BASE+0x2c) -#define IT83XX_INTC_ISR11 REG8(IT83XX_INTC_BASE+0x30) -#define IT83XX_INTC_ISR12 REG8(IT83XX_INTC_BASE+0x34) -#define IT83XX_INTC_ISR13 REG8(IT83XX_INTC_BASE+0x38) -#define IT83XX_INTC_ISR14 REG8(IT83XX_INTC_BASE+0x3c) -#define IT83XX_INTC_ISR15 REG8(IT83XX_INTC_BASE+0x40) -#define IT83XX_INTC_ISR16 REG8(IT83XX_INTC_BASE+0x44) -#define IT83XX_INTC_ISR17 REG8(IT83XX_INTC_BASE+0x48) -#define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE+0x4c) -#define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE+0x50) -#define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE+0x54) -#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE+0x58) -#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE+0x5c) -#define IT83XX_INTC_ISR23 REG8(IT83XX_INTC_BASE+0x90) -#define IT83XX_INTC_ISR24 REG8(IT83XX_INTC_BASE+0x94) -#define IT83XX_INTC_ISR25 REG8(IT83XX_INTC_BASE+0x98) -#define IT83XX_INTC_ISR26 REG8(IT83XX_INTC_BASE+0x9c) -#define IT83XX_INTC_ISR27 REG8(IT83XX_INTC_BASE+0xa0) -#define IT83XX_INTC_ISR28 REG8(IT83XX_INTC_BASE+0xa4) - -#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E) -#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F) -#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52) -#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53) - -#define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n)) -#define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE+0x80+(i)) - -/* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */ -#define IT83XX_EC2I_BASE 0x00F01200 - -#define IT83XX_EC2I_IHIOA REG8(IT83XX_EC2I_BASE+0x00) -#define IT83XX_EC2I_IHD REG8(IT83XX_EC2I_BASE+0x01) -#define IT83XX_EC2I_LSIOHA REG8(IT83XX_EC2I_BASE+0x02) -#define IT83XX_EC2I_SIOLV REG8(IT83XX_EC2I_BASE+0x03) -#define IT83XX_EC2I_IBMAE REG8(IT83XX_EC2I_BASE+0x04) -#define IT83XX_EC2I_IBCTL REG8(IT83XX_EC2I_BASE+0x05) - -/* --- System Wake-UP Control (SWUC) --- */ -#define IT83XX_SWUC_BASE 0x00F01400 -#define IT83XX_SWUC_SWCTL1 REG8(IT83XX_SWUC_BASE+0x00) - -/* --- Wake-Up Control (WUC) --- */ -#define IT83XX_WUC_BASE 0x00F01B00 - -#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00) -#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c) -#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04) -#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d) -#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c) -#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f) - -#define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE+0x21) -#define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE+0x25) - -#define IT83XX_WUC_WUEMR3 REG8(IT83XX_WUC_BASE+0x02) -#define IT83XX_WUC_WUESR3 REG8(IT83XX_WUC_BASE+0x06) -#define IT83XX_WUC_WUENR3 REG8(IT83XX_WUC_BASE+0x0A) - -#define IT83XX_WUC_WUEMR4 REG8(IT83XX_WUC_BASE+0x03) -#define IT83XX_WUC_WUESR4 REG8(IT83XX_WUC_BASE+0x07) -#define IT83XX_WUC_WUENR4 REG8(IT83XX_WUC_BASE+0x0B) - -/* --- UART --- */ -#define IT83XX_UART0_BASE 0x00F02700 -#define IT83XX_UART1_BASE 0x00F02800 - -#define IT83XX_UART_BASE(n) CONCAT3(IT83XX_UART, n, _BASE) -#define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset)) - -#define IT83XX_UART_DLL(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_DLM(n) IT83XX_UART_REG(n, 0x01) -#define IT83XX_UART_RBR(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_THR(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_IER(n) IT83XX_UART_REG(n, 0x01) -#define IT83XX_UART_IIR(n) IT83XX_UART_REG(n, 0x02) -#define IT83XX_UART_FCR(n) IT83XX_UART_REG(n, 0x02) -#define IT83XX_UART_LCR(n) IT83XX_UART_REG(n, 0x03) -#define IT83XX_UART_MCR(n) IT83XX_UART_REG(n, 0x04) -#define IT83XX_UART_LSR(n) IT83XX_UART_REG(n, 0x05) -#define IT83XX_UART_MSR(n) IT83XX_UART_REG(n, 0x06) -#define IT83XX_UART_SCR(n) IT83XX_UART_REG(n, 0x07) -#define IT83XX_UART_ECSMPR(n) IT83XX_UART_REG(n, 0x08) -#define IT83XX_UART_CSSR(n) IT83XX_UART_REG(n, 0x09) - -/* --- GPIO --- */ - -#define IT83XX_GPIO_BASE 0x00F01600 -#define IT83XX_GPIO2_BASE 0x00F03E00 - -#define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE+0x00) -#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1 -#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2 -#define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3 -#define IT83XX_GPIO_GCR_LPC_RST_POS 1 - -#define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE+0x01) -#define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE+0x02) -#define IT83XX_GPIO_GPDRC REG8(IT83XX_GPIO_BASE+0x03) -#define IT83XX_GPIO_GPDRE REG8(IT83XX_GPIO_BASE+0x05) -#define IT83XX_GPIO_GPDRF REG8(IT83XX_GPIO_BASE+0x06) -#define IT83XX_GPIO_GPDRH REG8(IT83XX_GPIO_BASE+0x08) - -#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE+0x10) -#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE+0x11) -#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE+0x12) -#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE+0x13) -#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE+0x14) -#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE+0x15) -#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE+0x16) -#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE+0x17) - -#define IT83XX_GPIO_GPCRB0 REG8(IT83XX_GPIO_BASE+0x18) -#define IT83XX_GPIO_GPCRB1 REG8(IT83XX_GPIO_BASE+0x19) -#define IT83XX_GPIO_GPCRB2 REG8(IT83XX_GPIO_BASE+0x1A) -#define IT83XX_GPIO_GPCRB3 REG8(IT83XX_GPIO_BASE+0x1B) -#define IT83XX_GPIO_GPCRB4 REG8(IT83XX_GPIO_BASE+0x1C) -#define IT83XX_GPIO_GPCRB5 REG8(IT83XX_GPIO_BASE+0x1D) -#define IT83XX_GPIO_GPCRB6 REG8(IT83XX_GPIO_BASE+0x1E) -#define IT83XX_GPIO_GPCRB7 REG8(IT83XX_GPIO_BASE+0x1F) - -#define IT83XX_GPIO_GPCRC0 REG8(IT83XX_GPIO_BASE+0x20) -#define IT83XX_GPIO_GPCRC1 REG8(IT83XX_GPIO_BASE+0x21) -#define IT83XX_GPIO_GPCRC2 REG8(IT83XX_GPIO_BASE+0x22) -#define IT83XX_GPIO_GPCRC3 REG8(IT83XX_GPIO_BASE+0x23) -#define IT83XX_GPIO_GPCRC4 REG8(IT83XX_GPIO_BASE+0x24) -#define IT83XX_GPIO_GPCRC5 REG8(IT83XX_GPIO_BASE+0x25) -#define IT83XX_GPIO_GPCRC6 REG8(IT83XX_GPIO_BASE+0x26) -#define IT83XX_GPIO_GPCRC7 REG8(IT83XX_GPIO_BASE+0x27) - -#define IT83XX_GPIO_GPCRE0 REG8(IT83XX_GPIO_BASE+0x30) -#define IT83XX_GPIO_GPCRE1 REG8(IT83XX_GPIO_BASE+0x31) -#define IT83XX_GPIO_GPCRE2 REG8(IT83XX_GPIO_BASE+0x32) -#define IT83XX_GPIO_GPCRE3 REG8(IT83XX_GPIO_BASE+0x33) -#define IT83XX_GPIO_GPCRE4 REG8(IT83XX_GPIO_BASE+0x34) -#define IT83XX_GPIO_GPCRE5 REG8(IT83XX_GPIO_BASE+0x35) -#define IT83XX_GPIO_GPCRE6 REG8(IT83XX_GPIO_BASE+0x36) -#define IT83XX_GPIO_GPCRE7 REG8(IT83XX_GPIO_BASE+0x37) - -#define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE+0x38) -#define IT83XX_GPIO_GPCRF1 REG8(IT83XX_GPIO_BASE+0x39) -#define IT83XX_GPIO_GPCRF2 REG8(IT83XX_GPIO_BASE+0x3A) -#define IT83XX_GPIO_GPCRF3 REG8(IT83XX_GPIO_BASE+0x3B) -#define IT83XX_GPIO_GPCRF4 REG8(IT83XX_GPIO_BASE+0x3C) -#define IT83XX_GPIO_GPCRF5 REG8(IT83XX_GPIO_BASE+0x3D) -#define IT83XX_GPIO_GPCRF6 REG8(IT83XX_GPIO_BASE+0x3E) -#define IT83XX_GPIO_GPCRF7 REG8(IT83XX_GPIO_BASE+0x3F) - -#define IT83XX_GPIO_GPCRH0 REG8(IT83XX_GPIO_BASE+0x48) -#define IT83XX_GPIO_GPCRH1 REG8(IT83XX_GPIO_BASE+0x49) -#define IT83XX_GPIO_GPCRH2 REG8(IT83XX_GPIO_BASE+0x4A) -#define IT83XX_GPIO_GPCRH3 REG8(IT83XX_GPIO_BASE+0x4B) -#define IT83XX_GPIO_GPCRH4 REG8(IT83XX_GPIO_BASE+0x4C) -#define IT83XX_GPIO_GPCRH5 REG8(IT83XX_GPIO_BASE+0x4D) -#define IT83XX_GPIO_GPCRH6 REG8(IT83XX_GPIO_BASE+0x4E) -#define IT83XX_GPIO_GPCRH7 REG8(IT83XX_GPIO_BASE+0x4F) - -#define IT83XX_GPIO_GPCRI0 REG8(IT83XX_GPIO_BASE+0x50) -#define IT83XX_GPIO_GPCRI1 REG8(IT83XX_GPIO_BASE+0x51) -#define IT83XX_GPIO_GPCRI2 REG8(IT83XX_GPIO_BASE+0x52) -#define IT83XX_GPIO_GPCRI3 REG8(IT83XX_GPIO_BASE+0x53) -#define IT83XX_GPIO_GPCRI4 REG8(IT83XX_GPIO_BASE+0x54) -#define IT83XX_GPIO_GPCRI5 REG8(IT83XX_GPIO_BASE+0x55) -#define IT83XX_GPIO_GPCRI6 REG8(IT83XX_GPIO_BASE+0x56) -#define IT83XX_GPIO_GPCRI7 REG8(IT83XX_GPIO_BASE+0x57) - -#define IT83XX_GPIO_GPCRM5 REG8(IT83XX_GPIO_BASE+0xA5) - -#define IT83XX_GPIO_GPDMRA REG8(IT83XX_GPIO_BASE+0x61) -#define IT83XX_GPIO_GPDMRB REG8(IT83XX_GPIO_BASE+0x62) -#define IT83XX_GPIO_GPDMRC REG8(IT83XX_GPIO_BASE+0x63) -#define IT83XX_GPIO_GPDMRE REG8(IT83XX_GPIO_BASE+0x65) -#define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE+0x66) -#define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE+0x68) - -#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE+0x98) -#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE+0x99) -#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE+0x9A) -#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE+0x9B) - -#define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE+0xF0) -#define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE+0xF1) -#define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE+0xF2) -#define IT83XX_GPIO_GRC4 REG8(IT83XX_GPIO_BASE+0xF3) -#define IT83XX_GPIO_GRC5 REG8(IT83XX_GPIO_BASE+0xF4) -#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE+0xF5) -#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE+0xF6) -#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE+0xF7) -#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE+0xE4) -#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE+0xE5) -#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE+0xE6) -#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE+0xE7) -#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE+0xE8) -#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE+0xE9) -#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE+0xD1) -#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE+0xD2) -#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE+0xD3) -#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE+0xD4) -#define IT83XX_GPIO_GCR30 REG8(IT83XX_GPIO_BASE+0xED) -#define IT83XX_GPIO_GCR31 REG8(IT83XX_GPIO_BASE+0xD5) -#define IT83XX_GPIO_GCR32 REG8(IT83XX_GPIO_BASE+0xD6) - -#define IT83XX_VBATPC_BGPOPSCR REG8(IT83XX_GPIO2_BASE+0xF0) -#define IT83XX_VBATPC_XLPIER REG8(IT83XX_GPIO2_BASE+0xF5) - -enum { - /* GPIO group index */ - GPIO_A = 0x1, - GPIO_B = 0x2, - GPIO_C = 0x3, - GPIO_D = 0x4, - GPIO_E = 0x5, - GPIO_F = 0x6, - GPIO_G = 0x7, - GPIO_H = 0x8, - GPIO_I = 0x9, - GPIO_J = 0xa, - GPIO_K = 0xb, - GPIO_L = 0xc, - GPIO_M = 0xd, -#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - GPIO_O = 0xe, - GPIO_P = 0xf, - GPIO_Q = 0x10, - GPIO_R = 0x11, -#endif - GPIO_PORT_COUNT, - - /* NOTE: Support GPIO input only if KSO/KSI pins are used as GPIO. */ - /* KSI[7-0] GPIO data mirror register. */ - GPIO_KSI, - /* KSO[15-8] GPIO data mirror register. */ - GPIO_KSO_H, - /* KSO[7-0] GPIO data mirror register. */ - GPIO_KSO_L, - /* Compiler check COUNT and gpio_group_to_reg member cnt match or not */ - COUNT, -}; - -struct gpio_reg_t { - /* GPIO port data register (bit mapping to pin) */ - uint32_t reg_gpdr; - /* GPIO port output type register (bit mapping to pin) */ - uint32_t reg_gpotr; - /* GPIO port control register (byte mapping to pin) */ - uint32_t reg_gpcr; -}; - -/* GPIO group index convert to GPIO data/output type/ctrl group address */ -static const struct gpio_reg_t gpio_group_to_reg[] = { - /* GPDR, GPOTR, GPCR */ - [GPIO_A] = { 0x00F01601, 0x00F01671, 0x00F01610 }, - [GPIO_B] = { 0x00F01602, 0x00F01672, 0x00F01618 }, - [GPIO_C] = { 0x00F01603, 0x00F01673, 0x00F01620 }, - [GPIO_D] = { 0x00F01604, 0x00F01674, 0x00F01628 }, - [GPIO_E] = { 0x00F01605, 0x00F01675, 0x00F01630 }, - [GPIO_F] = { 0x00F01606, 0x00F01676, 0x00F01638 }, - [GPIO_G] = { 0x00F01607, 0x00F01677, 0x00F01640 }, - [GPIO_H] = { 0x00F01608, 0x00F01678, 0x00F01648 }, - [GPIO_I] = { 0x00F01609, 0x00F01679, 0x00F01650 }, - [GPIO_J] = { 0x00F0160a, 0x00F0167a, 0x00F01658 }, - [GPIO_K] = { 0x00F0160b, 0x00F0167b, 0x00F01690 }, - [GPIO_L] = { 0x00F0160c, 0x00F0167c, 0x00F01698 }, - [GPIO_M] = { 0x00F0160d, 0x00F0167d, 0x00F016a0 }, -#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [GPIO_O] = { 0x00F03E01, 0x00F03E71, 0x00F03E10 }, - [GPIO_P] = { 0x00F03E02, 0x00F03E72, 0x00F03E18 }, - [GPIO_Q] = { 0x00F03E03, 0x00F03E73, 0x00F03E20 }, - [GPIO_R] = { 0x00F03E04, 0x00F03E74, 0x00F03E28 }, -#endif - [GPIO_KSI] = { 0x00F01D09, -1, -1 }, - [GPIO_KSO_H] = { 0x00F01D0C, -1, -1 }, - [GPIO_KSO_L] = { 0x00F01D0F, -1, -1 }, -}; -BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT)); - -#define DUMMY_GPIO_BANK GPIO_A - -#define IT83XX_GPIO_DATA(port) \ - REG8(gpio_group_to_reg[port].reg_gpdr) -#define IT83XX_GPIO_GPOT(port) \ - REG8(gpio_group_to_reg[port].reg_gpotr) -#define IT83XX_GPIO_CTRL(port, pin_offset) \ - REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset) -#define GPCR_PORT_PIN_MODE_INPUT BIT(7) -#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) -#define GPCR_PORT_PIN_MODE_PULLUP BIT(2) -#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) - -/* --- Clock and Power Management (ECPM) --- */ - -#define IT83XX_ECPM_BASE 0x00F01E00 - -#define IT83XX_ECPM_CGCTRL1R_OFF 0x01 -#define IT83XX_ECPM_CGCTRL2R_OFF 0x02 -#define IT83XX_ECPM_CGCTRL3R_OFF 0x05 -#define IT83XX_ECPM_CGCTRL4R_OFF 0x09 - -#define IT83XX_ECPM_PLLCTRL REG8(IT83XX_ECPM_BASE+0x03) -enum ec_pll_ctrl { - EC_PLL_DOZE = 0, - EC_PLL_SLEEP = 1, - EC_PLL_DEEP_DOZE = 3, -}; - -#define IT83XX_ECPM_AUTOCG REG8(IT83XX_ECPM_BASE+0x04) -#define IT83XX_ECPM_PLLFREQR REG8(IT83XX_ECPM_BASE+0x06) -#define IT83XX_ECPM_PLLCSS REG8(IT83XX_ECPM_BASE+0x08) -#define IT83XX_ECPM_SCDCR0 REG8(IT83XX_ECPM_BASE+0x0c) -#define IT83XX_ECPM_SCDCR1 REG8(IT83XX_ECPM_BASE+0x0d) -#define IT83XX_ECPM_SCDCR2 REG8(IT83XX_ECPM_BASE+0x0e) -#define IT83XX_ECPM_SCDCR3 REG8(IT83XX_ECPM_BASE+0x0f) -#define IT83XX_ECPM_SCDCR4 REG8(IT83XX_ECPM_BASE+0x10) - -/* - * The clock gate offsets combine the register offset from ECPM_BASE and the - * mask within that register into one value. These are used for - * clock_enable_peripheral() and clock_disable_peripheral() - */ -enum clock_gate_offsets { - CGC_OFFSET_EGPC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40), - CGC_OFFSET_CIR = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20), - CGC_OFFSET_SWUC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10), - CGC_OFFSET_USB = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20), - CGC_OFFSET_PECI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08), - CGC_OFFSET_UART = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04), - CGC_OFFSET_SSPI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02), - CGC_OFFSET_DBGR = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01), - CGC_OFFSET_SMBF = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80), - CGC_OFFSET_SMBE = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40), - CGC_OFFSET_SMBD = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20), - CGC_OFFSET_SMBC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10), - CGC_OFFSET_SMBB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08), - CGC_OFFSET_SMBA = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04), - CGC_OFFSET_SMB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02), - CGC_OFFSET_CEC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01) -}; - -/* --- Timer (TMR) --- */ -#define IT83XX_TMR_BASE 0x00F02900 - -#define IT83XX_TMR_PRSC REG8(IT83XX_TMR_BASE+0x00) -#define IT83XX_TMR_GCSMS REG8(IT83XX_TMR_BASE+0x01) -#define IT83XX_TMR_CTR_A0 REG8(IT83XX_TMR_BASE+0x02) -#define IT83XX_TMR_CTR_A1 REG8(IT83XX_TMR_BASE+0x03) -#define IT83XX_TMR_CTR_B0 REG8(IT83XX_TMR_BASE+0x04) -#define IT83XX_TMR_CTR_B1 REG8(IT83XX_TMR_BASE+0x05) -#define IT83XX_TMR_DCR_A0 REG8(IT83XX_TMR_BASE+0x06) -#define IT83XX_TMR_DCR_A1 REG8(IT83XX_TMR_BASE+0x07) -#define IT83XX_TMR_DCR_B0 REG8(IT83XX_TMR_BASE+0x08) -#define IT83XX_TMR_DCR_B1 REG8(IT83XX_TMR_BASE+0x09) -#define IT83XX_TMR_CCGSR REG8(IT83XX_TMR_BASE+0x0A) -#define IT83XX_TMR_TMRCE REG8(IT83XX_TMR_BASE+0x0B) -#define IT83XX_TMR_TMRIE REG8(IT83XX_TMR_BASE+0x0C) - -/* --- External Timer and Watchdog (ETWD) --- */ -#define IT83XX_ETWD_BASE 0x00F01F00 - -#define IT83XX_ETWD_ETWCFG REG8(IT83XX_ETWD_BASE+0x01) -#define IT83XX_ETWD_ET1PSR REG8(IT83XX_ETWD_BASE+0x02) -#define IT83XX_ETWD_ET1CNTLHR REG8(IT83XX_ETWD_BASE+0x03) -#define IT83XX_ETWD_ET1CNTLLR REG8(IT83XX_ETWD_BASE+0x04) -#define IT83XX_ETWD_ETWCTRL REG8(IT83XX_ETWD_BASE+0x05) -#define IT83XX_ETWD_EWDCNTLLR REG8(IT83XX_ETWD_BASE+0x06) -#define IT83XX_ETWD_EWDKEYR REG8(IT83XX_ETWD_BASE+0x07) -#define IT83XX_ETWD_EWDCNTLHR REG8(IT83XX_ETWD_BASE+0x09) -#define IT83XX_ETWD_ETXCTRL(n) REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3)) -#define IT83XX_ETWD_ETXPSR(n) REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3)) -#define IT83XX_ETWD_ETXCNTLR(n) REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3)) -#define IT83XX_ETWD_ETXCNTOR(n) REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2)) - -/* --- General Control (GCTRL) --- */ -#define IT83XX_GCTRL_BASE 0x00F02000 - -#ifdef IT83XX_CHIP_ID_3BYTES -#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x85) -#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x86) -#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE+0x87) -#else -#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x00) -#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x01) -#endif -#define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE+0x02) -#define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) -#define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) -#define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE+0x0A) -#define IT83XX_GCTRL_SPCTRL1 REG8(IT83XX_GCTRL_BASE+0x0D) -#define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE+0x10) -#define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE+0x11) -#define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE+0x1C) -#define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE+0x30) -#define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE+0x32) -#define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE+0x33) -#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37) -#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) -#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) -#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) -#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) -/* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ -#define ETWD_HW_RST_EN BIT(0) -#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) -#define ILMCR_ILM2_ENABLE BIT(2) -#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) -#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) -#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i) - -/* --- Pulse Width Modulation (PWM) --- */ -#define IT83XX_PWM_BASE 0x00F01800 - -#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE+0x00) -#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE+0x01) -#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE+0x02) -#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE+0x03) -#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE+0x04) -#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE+0x05) -#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE+0x06) -#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE+0x07) -#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE+0x08) -#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE+0x09) -#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE+0x0A) -#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE+0x0B) -#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE+0x0C) -#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE+0x0D) -#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE+0x0E) -#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE+0x0F) -#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE+0x1E) -#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE+0x1F) -#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE+0x20) -#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE+0x21) -#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE+0x22) -#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE+0x23) -#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE+0x24) -#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE+0x27) -#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE+0x28) -#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE+0x2B) -#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE+0x2C) -#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE+0x2D) -#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE+0x2E) -#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE+0x40) -#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE+0x41) -#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE+0x42) -#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE+0x43) -#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE+0x44) -#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE+0x45) -#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE+0x46) -#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE+0x47) -#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE+0x48) -#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE+0x49) - -/* Analog to Digital Converter (ADC) */ -#define IT83XX_ADC_BASE 0x00F01900 - -#define IT83XX_ADC_ADCSTS REG8(IT83XX_ADC_BASE+0x00) -#define IT83XX_ADC_ADCCFG REG8(IT83XX_ADC_BASE+0x01) -#define IT83XX_ADC_ADCCTL REG8(IT83XX_ADC_BASE+0x02) -#define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE+0x03) -#define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE+0x04) -#define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE+0x05) -#define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE+0x06) -#define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE+0x07) -#define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE+0x08) -#define IT83XX_ADC_VCH2CTL REG8(IT83XX_ADC_BASE+0x09) -#define IT83XX_ADC_VCH2DATL REG8(IT83XX_ADC_BASE+0x0A) -#define IT83XX_ADC_VCH2DATM REG8(IT83XX_ADC_BASE+0x0B) -#define IT83XX_ADC_VCH3CTL REG8(IT83XX_ADC_BASE+0x0C) -#define IT83XX_ADC_VCH3DATL REG8(IT83XX_ADC_BASE+0x0D) -#define IT83XX_ADC_VCH3DATM REG8(IT83XX_ADC_BASE+0x0E) -#define IT83XX_ADC_VHSCDBL REG8(IT83XX_ADC_BASE+0x14) -#define IT83XX_ADC_VHSCDBM REG8(IT83XX_ADC_BASE+0x15) -#define IT83XX_ADC_VCH0DATL REG8(IT83XX_ADC_BASE+0x18) -#define IT83XX_ADC_VCH0DATM REG8(IT83XX_ADC_BASE+0x19) -#define IT83XX_ADC_VHSGCDBL REG8(IT83XX_ADC_BASE+0x1C) -#define IT83XX_ADC_VHSGCDBM REG8(IT83XX_ADC_BASE+0x1D) -#define IT83XX_ADC_ADCSAR REG8(IT83XX_ADC_BASE+0x32) -#define IT83XX_ADC_VCMPSCP REG8(IT83XX_ADC_BASE+0x37) -#define IT83XX_ADC_VCH4CTL REG8(IT83XX_ADC_BASE+0x38) -#define IT83XX_ADC_VCH4DATM REG8(IT83XX_ADC_BASE+0x39) -#define IT83XX_ADC_VCH4DATL REG8(IT83XX_ADC_BASE+0x3A) -#define IT83XX_ADC_VCH5CTL REG8(IT83XX_ADC_BASE+0x3B) -#define IT83XX_ADC_VCH5DATM REG8(IT83XX_ADC_BASE+0x3C) -#define IT83XX_ADC_VCH5DATL REG8(IT83XX_ADC_BASE+0x3D) -#define IT83XX_ADC_VCH6CTL REG8(IT83XX_ADC_BASE+0x3E) -#define IT83XX_ADC_VCH6DATM REG8(IT83XX_ADC_BASE+0x3F) -#define IT83XX_ADC_VCH6DATL REG8(IT83XX_ADC_BASE+0x40) -#define IT83XX_ADC_VCH7CTL REG8(IT83XX_ADC_BASE+0x41) -#define IT83XX_ADC_VCH7DATM REG8(IT83XX_ADC_BASE+0x42) -#define IT83XX_ADC_VCH7DATL REG8(IT83XX_ADC_BASE+0x43) -#define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE+0x44) -#define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE+0x45) -#define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE+0x46) -#define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE+0x47) -#define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE+0x48) -#define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE+0x49) -#define IT83XX_ADC_CMP1THRDATM REG8(IT83XX_ADC_BASE+0x4A) -#define IT83XX_ADC_CMP1THRDATL REG8(IT83XX_ADC_BASE+0x4B) -#define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE+0x4C) -#define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE+0x4D) -#define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE+0x4E) -#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE+0x60) -#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE+0x61) -#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE+0x62) -#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE+0x63) -#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE+0x64) -#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE+0x65) -#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE+0x66) -#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE+0x67) -#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE+0x68) -#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE+0x69) -#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE+0x6A) -#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE+0x6B) -#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE+0x6C) - -/* Keyboard Controller (KBC) */ -#define IT83XX_KBC_BASE 0x00F01300 - -#define IT83XX_KBC_KBHICR REG8(IT83XX_KBC_BASE+0x00) -#define IT83XX_KBC_KBIRQR REG8(IT83XX_KBC_BASE+0x02) -#define IT83XX_KBC_KBHISR REG8(IT83XX_KBC_BASE+0x04) -#define IT83XX_KBC_KBHIKDOR REG8(IT83XX_KBC_BASE+0x06) -#define IT83XX_KBC_KBHIMDOR REG8(IT83XX_KBC_BASE+0x08) -#define IT83XX_KBC_KBHIDIR REG8(IT83XX_KBC_BASE+0x0A) - -/* Power Management Channel (PMC) */ -#define IT83XX_PMC_BASE 0x00F01500 - -#define IT83XX_PMC_PM1STS REG8(IT83XX_PMC_BASE+0x00) -#define IT83XX_PMC_PM1DO REG8(IT83XX_PMC_BASE+0x01) -#define IT83XX_PMC_PM1DOSCI REG8(IT83XX_PMC_BASE+0x02) -#define IT83XX_PMC_PM1DOSMI REG8(IT83XX_PMC_BASE+0x03) -#define IT83XX_PMC_PM1DI REG8(IT83XX_PMC_BASE+0x04) -#define IT83XX_PMC_PM1DISCI REG8(IT83XX_PMC_BASE+0x05) -#define IT83XX_PMC_PM1CTL REG8(IT83XX_PMC_BASE+0x06) -#define IT83XX_PMC_PM1IC REG8(IT83XX_PMC_BASE+0x07) -#define IT83XX_PMC_PM1IE REG8(IT83XX_PMC_BASE+0x08) -#define IT83XX_PMC_PM2STS REG8(IT83XX_PMC_BASE+0x10) -#define IT83XX_PMC_PM2DO REG8(IT83XX_PMC_BASE+0x11) -#define IT83XX_PMC_PM2DOSCI REG8(IT83XX_PMC_BASE+0x12) -#define IT83XX_PMC_PM2DOSMI REG8(IT83XX_PMC_BASE+0x13) -#define IT83XX_PMC_PM2DI REG8(IT83XX_PMC_BASE+0x14) -#define IT83XX_PMC_PM2DISCI REG8(IT83XX_PMC_BASE+0x15) -#define IT83XX_PMC_PM2CTL REG8(IT83XX_PMC_BASE+0x16) -#define IT83XX_PMC_PM2IC REG8(IT83XX_PMC_BASE+0x17) -#define IT83XX_PMC_PM2IE REG8(IT83XX_PMC_BASE+0x18) -#define IT83XX_PMC_PM3STS REG8(IT83XX_PMC_BASE+0x20) -#define IT83XX_PMC_PM3DO REG8(IT83XX_PMC_BASE+0x21) -#define IT83XX_PMC_PM3DI REG8(IT83XX_PMC_BASE+0x22) -#define IT83XX_PMC_PM3CTL REG8(IT83XX_PMC_BASE+0x23) -#define IT83XX_PMC_PM3IC REG8(IT83XX_PMC_BASE+0x24) -#define IT83XX_PMC_PM3IE REG8(IT83XX_PMC_BASE+0x25) -#define IT83XX_PMC_PM4STS REG8(IT83XX_PMC_BASE+0x30) -#define IT83XX_PMC_PM4DO REG8(IT83XX_PMC_BASE+0x31) -#define IT83XX_PMC_PM4DI REG8(IT83XX_PMC_BASE+0x32) -#define IT83XX_PMC_PM4CTL REG8(IT83XX_PMC_BASE+0x33) -#define IT83XX_PMC_PM4IC REG8(IT83XX_PMC_BASE+0x34) -#define IT83XX_PMC_PM4IE REG8(IT83XX_PMC_BASE+0x35) -#define IT83XX_PMC_PM5STS REG8(IT83XX_PMC_BASE+0x40) -#define IT83XX_PMC_PM5DO REG8(IT83XX_PMC_BASE+0x41) -#define IT83XX_PMC_PM5DI REG8(IT83XX_PMC_BASE+0x42) -#define IT83XX_PMC_PM5CTL REG8(IT83XX_PMC_BASE+0x43) -#define IT83XX_PMC_PM5IC REG8(IT83XX_PMC_BASE+0x44) -#define IT83XX_PMC_PM5IE REG8(IT83XX_PMC_BASE+0x45) -#define IT83XX_PMC_MBXCTRL REG8(IT83XX_PMC_BASE+0x19) -#define IT83XX_PMC_MBXEC_00 REG8(IT83XX_PMC_BASE+0xF0) -#define IT83XX_PMC_MBXEC_01 REG8(IT83XX_PMC_BASE+0xF1) -#define IT83XX_PMC_MBXEC_02 REG8(IT83XX_PMC_BASE+0xF2) -#define IT83XX_PMC_MBXEC_03 REG8(IT83XX_PMC_BASE+0xF3) -#define IT83XX_PMC_MBXEC_04 REG8(IT83XX_PMC_BASE+0xF4) -#define IT83XX_PMC_MBXEC_05 REG8(IT83XX_PMC_BASE+0xF5) -#define IT83XX_PMC_MBXEC_06 REG8(IT83XX_PMC_BASE+0xF6) -#define IT83XX_PMC_MBXEC_07 REG8(IT83XX_PMC_BASE+0xF7) -#define IT83XX_PMC_MBXEC_08 REG8(IT83XX_PMC_BASE+0xF8) -#define IT83XX_PMC_MBXEC_09 REG8(IT83XX_PMC_BASE+0xF9) -#define IT83XX_PMC_MBXEC_10 REG8(IT83XX_PMC_BASE+0xFA) -#define IT83XX_PMC_MBXEC_11 REG8(IT83XX_PMC_BASE+0xFB) -#define IT83XX_PMC_MBXEC_12 REG8(IT83XX_PMC_BASE+0xFC) -#define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE+0xFD) -#define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE+0xFE) -#define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE+0xFF) -#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4)) -#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4)) -#define IT83XX_PMC_PMDI(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4)) -#define IT83XX_PMC_PMCTL(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4)) -#define IT83XX_PMC_PMIE(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) - -/* Keyboard Matrix Scan control (KBS) */ -#define IT83XX_KBS_BASE 0x00F01D00 - -#define IT83XX_KBS_KSOL REG8(IT83XX_KBS_BASE+0x00) -#define IT83XX_KBS_KSOH1 REG8(IT83XX_KBS_BASE+0x01) -#define IT83XX_KBS_KSOCTRL REG8(IT83XX_KBS_BASE+0x02) -#define IT83XX_KBS_KSOH2 REG8(IT83XX_KBS_BASE+0x03) -#define IT83XX_KBS_KSI REG8(IT83XX_KBS_BASE+0x04) -#define IT83XX_KBS_KSICTRL REG8(IT83XX_KBS_BASE+0x05) -#define IT83XX_KBS_KSIGCTRL REG8(IT83XX_KBS_BASE+0x06) -#define IT83XX_KBS_KSIGOEN REG8(IT83XX_KBS_BASE+0x07) -#define IT83XX_KBS_KSIGDAT REG8(IT83XX_KBS_BASE+0x08) -#define IT83XX_KBS_KSIGDMRR REG8(IT83XX_KBS_BASE+0x09) -#define IT83XX_KBS_KSOHGCTRL REG8(IT83XX_KBS_BASE+0x0A) -#define IT83XX_KBS_KSOHGOEN REG8(IT83XX_KBS_BASE+0x0B) -#define IT83XX_KBS_KSOHGDMRR REG8(IT83XX_KBS_BASE+0x0C) -#define IT83XX_KBS_KSOLGCTRL REG8(IT83XX_KBS_BASE+0x0D) -#define IT83XX_KBS_KSOLGOEN REG8(IT83XX_KBS_BASE+0x0E) -#define IT83XX_KBS_KSOLGDMRR REG8(IT83XX_KBS_BASE+0x0F) -#define IT83XX_KBS_KSO0LSDR REG8(IT83XX_KBS_BASE+0x10) -#define IT83XX_KBS_KSO1LSDR REG8(IT83XX_KBS_BASE+0x11) -#define IT83XX_KBS_KSO2LSDR REG8(IT83XX_KBS_BASE+0x12) -#define IT83XX_KBS_KSO3LSDR REG8(IT83XX_KBS_BASE+0x13) -#define IT83XX_KBS_KSO4LSDR REG8(IT83XX_KBS_BASE+0x14) -#define IT83XX_KBS_KSO5LSDR REG8(IT83XX_KBS_BASE+0x15) -#define IT83XX_KBS_KSO6LSDR REG8(IT83XX_KBS_BASE+0x16) -#define IT83XX_KBS_KSO7LSDR REG8(IT83XX_KBS_BASE+0x17) -#define IT83XX_KBS_KSO8LSDR REG8(IT83XX_KBS_BASE+0x18) -#define IT83XX_KBS_KSO9LSDR REG8(IT83XX_KBS_BASE+0x19) -#define IT83XX_KBS_KSO10LSDR REG8(IT83XX_KBS_BASE+0x1A) -#define IT83XX_KBS_KSO11LSDR REG8(IT83XX_KBS_BASE+0x1B) -#define IT83XX_KBS_KSO12LSDR REG8(IT83XX_KBS_BASE+0x1C) -#define IT83XX_KBS_KSO13LSDR REG8(IT83XX_KBS_BASE+0x1D) -#define IT83XX_KBS_KSO14LSDR REG8(IT83XX_KBS_BASE+0x1E) -#define IT83XX_KBS_KSO15LSDR REG8(IT83XX_KBS_BASE+0x1F) -#define IT83XX_KBS_KSO16LSDR REG8(IT83XX_KBS_BASE+0x20) -#define IT83XX_KBS_KSO17LSDR REG8(IT83XX_KBS_BASE+0x21) -#define IT83XX_KBS_SDC1R REG8(IT83XX_KBS_BASE+0x22) -#define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE+0x23) -#define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE+0x24) -#define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE+0x25) - -/* Shared Memory Flash Interface Bridge (SMFI) */ -#define IT83XX_SMFI_BASE 0x00F01000 - -#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE+0x5A) -#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE+0x5B) -#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE+0x5C) -#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE+0x5D) -#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE+0x5E) -#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE+0x76) -#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE+0x77) -#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE+0x78) -#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE+0x79) -#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE+0x7A) -#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE+0x7B) -#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE+0x7C) -#define IT83XX_SMFI_ECINDAR0 REG8(IT83XX_SMFI_BASE+0x3B) -#define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE+0x3C) -#define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE+0x3D) -#define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE+0x3E) -#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) -#define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE+0x3F) -#define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE+0x46) -#define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE+0x47) -#define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE+0x48) -#define IT83XX_SMFI_FLHCTRL3R REG8(IT83XX_SMFI_BASE+0x63) -#define IT83XX_SMFI_STCDMACR REG8(IT83XX_SMFI_BASE+0x80) -#define IT83XX_SMFI_FLHCTRL6R REG8(IT83XX_SMFI_BASE+0xA2) -/* Enable EC-indirect page program command */ -#define IT83XX_SMFI_MASK_ECINDPP BIT(3) - -/* Serial Peripheral Interface (SSPI) */ -#define IT83XX_SSPI_BASE 0x00F02600 - -#define IT83XX_SSPI_SPIDATA REG8(IT83XX_SSPI_BASE+0x00) -#define IT83XX_SSPI_SPICTRL1 REG8(IT83XX_SSPI_BASE+0x01) -#define IT83XX_SSPI_SPICTRL2 REG8(IT83XX_SSPI_BASE+0x02) -#define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE+0x03) -#define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE+0x04) - -/* Platform Environment Control Interface (PECI) */ -#define IT83XX_PECI_BASE 0x00F02C00 - -#define IT83XX_PECI_HOSTAR REG8(IT83XX_PECI_BASE+0x00) -#define IT83XX_PECI_HOCTLR REG8(IT83XX_PECI_BASE+0x01) -#define IT83XX_PECI_HOCMDR REG8(IT83XX_PECI_BASE+0x02) -#define IT83XX_PECI_HOTRADDR REG8(IT83XX_PECI_BASE+0x03) -#define IT83XX_PECI_HOWRLR REG8(IT83XX_PECI_BASE+0x04) -#define IT83XX_PECI_HORDLR REG8(IT83XX_PECI_BASE+0x05) -#define IT83XX_PECI_HOWRDR REG8(IT83XX_PECI_BASE+0x06) -#define IT83XX_PECI_HORDDR REG8(IT83XX_PECI_BASE+0x07) -#define IT83XX_PECI_HOCTL2R REG8(IT83XX_PECI_BASE+0x08) -#define IT83XX_PECI_RWFCSV REG8(IT83XX_PECI_BASE+0x09) -#define IT83XX_PECI_RRFCSV REG8(IT83XX_PECI_BASE+0x0A) -#define IT83XX_PECI_WFCSV REG8(IT83XX_PECI_BASE+0x0B) -#define IT83XX_PECI_RFCSV REG8(IT83XX_PECI_BASE+0x0C) -#define IT83XX_PECI_AWFCSV REG8(IT83XX_PECI_BASE+0x0D) -#define IT83XX_PECI_PADCTLR REG8(IT83XX_PECI_BASE+0x0E) - -/* - * The count number of the counter for 25 ms register. - * The 25 ms register is calculated by (count number *1.024 kHz). - */ -#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ - -/* SMBus/I2C Interface (SMB/I2C) */ -#define IT83XX_SMB_BASE 0x00F01C00 - -#define IT83XX_SMB_4P7USL REG8(IT83XX_SMB_BASE+0x00) -#define IT83XX_SMB_4P0USL REG8(IT83XX_SMB_BASE+0x01) -#define IT83XX_SMB_300NS REG8(IT83XX_SMB_BASE+0x02) -#define IT83XX_SMB_250NS REG8(IT83XX_SMB_BASE+0x03) -#define IT83XX_SMB_25MS REG8(IT83XX_SMB_BASE+0x04) -#define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE+0x05) -#define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE+0x06) -#define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE+0x07) -#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE+0x08) -#define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE+0x09+ch) -#define IT83XX_SMB_CHSEF REG8(IT83XX_SMB_BASE+0x11) -#define IT83XX_SMB_CHSAB REG8(IT83XX_SMB_BASE+0x20) -#define IT83XX_SMB_CHSCD REG8(IT83XX_SMB_BASE+0x21) -#define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE+0x40+(ch << 6)) -#define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE+0x41+(ch << 6)) -#define IT83XX_SMB_HOCMD(ch) REG8(IT83XX_SMB_BASE+0x42+(ch << 6)) -#define IT83XX_SMB_TRASLA(ch) REG8(IT83XX_SMB_BASE+0x43+(ch << 6)) -#define IT83XX_SMB_D0REG(ch) REG8(IT83XX_SMB_BASE+0x44+(ch << 6)) -#define IT83XX_SMB_D1REG(ch) REG8(IT83XX_SMB_BASE+0x45+(ch << 6)) -#define IT83XX_SMB_HOBDB(ch) REG8(IT83XX_SMB_BASE+0x46+(ch << 6)) -#define IT83XX_SMB_PECERC(ch) REG8(IT83XX_SMB_BASE+0x47+(ch << 6)) -#define IT83XX_SMB_SMBPCTL(ch) REG8(IT83XX_SMB_BASE+0x4A+(ch << 6)) -#define IT83XX_SMB_HOCTL2(ch) REG8(IT83XX_SMB_BASE+0x50+(ch << 6)) -#define IT83XX_SMB_SLVEN (1 << 5) -#define IT83XX_SMB_RESLADR REG8(IT83XX_SMB_BASE+0x48) -#define IT83XX_SMB_SLDA REG8(IT83XX_SMB_BASE+0x49) -#define IT83XX_SMB_SLSTA REG8(IT83XX_SMB_BASE+0x4B) -#define IT83XX_SMB_SPDS (1 << 5) -#define IT83XX_SMB_RCS (1 << 3) -#define IT83XX_SMB_STS (1 << 2) -#define IT83XX_SMB_SDS (1 << 1) -#define IT83XX_SMB_SICR REG8(IT83XX_SMB_BASE+0x4C) -#define IT83XX_SMB_RESLADR2 REG8(IT83XX_SMB_BASE+0x51) -#define IT83XX_SMB_ENADDR2 (1 << 7) -#define IT83XX_SMB_SFFCTL REG8(IT83XX_SMB_BASE+0x55) -#define IT83XX_SMB_SAFE (1 << 0) -#define IT83XX_SMB_SFFSTA REG8(IT83XX_SMB_BASE+0x56) -#define IT83XX_SMB_SFFFULL (1 << 6) - -/* BRAM */ -#define IT83XX_BRAM_BASE 0x00F02200 - -/* offset 0 ~ 0x7f */ -#define IT83XX_BRAM_BANK0(i) REG8(IT83XX_BRAM_BASE + i) -/* Battery backed RAM indices. */ -enum bram_indices { - /* reset flags uses 4 bytes */ - BRAM_IDX_RESET_FLAGS0 = 0, - BRAM_IDX_RESET_FLAGS1 = 1, - BRAM_IDX_RESET_FLAGS2 = 2, - BRAM_IDX_RESET_FLAGS3 = 3, - - /* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */ - BRAM_IDX_PD0 = 4, - BRAM_IDX_PD1 = 5, - BRAM_IDX_PD2 = 6, - - /* index 7 is reserved */ - - BRAM_IDX_SCRATCHPAD0 = 8, - BRAM_IDX_SCRATCHPAD1 = 9, - BRAM_IDX_SCRATCHPAD2 = 0xa, - BRAM_IDX_SCRATCHPAD3 = 0xb, - /* index 0xc ~ 0xf are reserved */ - - /* NVCONTEXT uses 16 bytes */ - BRAM_IDX_NVCONTEXT = 0x10, - BRAM_IDX_NVCONTEXT_END = 0x1F, - - /* offset 0x20 ~ 0x7b are reserved for future use. */ - - /* This field is used to indicate BRAM is valid or not. */ - BRAM_IDX_VALID_FLAGS0 = 0x7c, - BRAM_IDX_VALID_FLAGS1 = 0x7d, - BRAM_IDX_VALID_FLAGS2 = 0x7e, - BRAM_IDX_VALID_FLAGS3 = 0x7f - /* offset 0x7f is the end of BRAM bank 0. */ -}; -#define BRAM_RESET_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0) -#define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1) -#define BRAM_RESET_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2) -#define BRAM_RESET_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3) - -#define BRAM_SCRATCHPAD0 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0) -#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1) -#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2) -#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3) - -#define BRAM_VALID_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0) -#define BRAM_VALID_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1) -#define BRAM_VALID_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2) -#define BRAM_VALID_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3) - -#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i) - -/* - * Enhanced SMBus/I2C Interface - * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580 - * Ch_D: ch = 0x03 , Ch_E: ch = 0x00 , Ch_F: ch = 0x01 - */ -#define IT83XX_I2C_BASE 0x00F03500 - -#define IT83XX_I2C_DRR(ch) REG8(IT83XX_I2C_BASE+0x00+(ch << 7)) -#define IT83XX_I2C_PSR(ch) REG8(IT83XX_I2C_BASE+0x01+(ch << 7)) -#define IT83XX_I2C_HSPR(ch) REG8(IT83XX_I2C_BASE+0x02+(ch << 7)) -#define IT83XX_I2C_STR(ch) REG8(IT83XX_I2C_BASE+0x03+(ch << 7)) -#define IT83XX_I2C_BB (1 << 5) -#define IT83XX_I2C_TIME_OUT (1 << 3) -#define IT83XX_I2C_RW (1 << 2) -#define IT83XX_I2C_INTPEND (1 << 1) -#define IT83XX_I2C_DHTR(ch) REG8(IT83XX_I2C_BASE+0x04+(ch << 7)) -#define IT83XX_I2C_TOR(ch) REG8(IT83XX_I2C_BASE+0x05+(ch << 7)) -#define IT83XX_I2C_DTR(ch) REG8(IT83XX_I2C_BASE+0x08+(ch << 7)) -#define IT83XX_I2C_CTR(ch) REG8(IT83XX_I2C_BASE+0x09+(ch << 7)) -#define IT83XX_I2C_INTEN (1 << 6) -#define IT83XX_I2C_MODE (1 << 5) -#define IT83XX_I2C_STARST (1 << 4) -#define IT83XX_I2C_ACK (1 << 3) -#define IT83XX_I2C_HALT (1 << 0) -#define IT83XX_I2C_CTR1(ch) REG8(IT83XX_I2C_BASE+0x0A+(ch << 7)) -#define IT83XX_I2C_COMQ_EN (1 << 7) -#define IT83XX_I2C_MDL_EN (1 << 1) -#define IT83XX_I2C_BYTE_CNT_L(ch) REG8(IT83XX_I2C_BASE+0x0C+(ch << 7)) -#define IT83XX_I2C_IRQ_ST(ch) REG8(IT83XX_I2C_BASE+0x0D+(ch << 7)) -#define IT83XX_I2C_IDW_CLR (1 << 3) -#define IT83XX_I2C_IDR_CLR (1 << 2) -#define IT83XX_I2C_SLVDATAFLG (1 << 1) -#define IT83XX_I2C_P_CLR (1 << 0) -#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE+0x06+(ch << 7)) -#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE+0x07+(ch << 7)) -#define IT83XX_I2C_CLK_STR (1 << 7) -#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE+0x1F+(ch << 7)) -#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE+0x23+(ch << 7)) -#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE+0x24+(ch << 7)) -#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE+0x2B+(ch << 7)) -#define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE+0x2C+(ch << 7)) -#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE+0x25+(ch << 7)) -#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE+0x26+(ch << 7)) -#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE+0x50+(ch << 7)) -#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE+0x52+(ch << 7)) - -enum i2c_channels { - IT83XX_I2C_CH_A, /* GPIO.B3/B4 */ - IT83XX_I2C_CH_B, /* GPIO.C1/C2 */ - IT83XX_I2C_CH_C, /* GPIO.F6/F7 or GPIO.C7/F7 */ - IT83XX_I2C_CH_D, /* GPIO.H1/H2 */ - IT83XX_I2C_CH_E, /* GPIO.E0/E7 */ - IT83XX_I2C_CH_F, /* GPIO.A4/A5 (for util/iteflash) */ - IT83XX_I2C_PORT_COUNT, -}; - -/* USBPD Controller */ -#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port))) - -#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0) -#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) -#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6) -#define USBPD_REG_MASK_BMC_PHY BIT(4) -#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3) -#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2) -#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) -#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0) -#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x01) -#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7) -#define USBPD_REG_MASK_SOPP_ENABLE BIT(6) -#define USBPD_REG_MASK_SOP_ENABLE BIT(5) -#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) -#define USBPD_REG_MASK_DISABLE_CC BIT(4) -#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) -#ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (BIT(3) | BIT(1)) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (BIT(7) | BIT(5)) -#else -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT BIT(3) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT BIT(7) -#endif -#define USBPD_CC1_DISCONNECTED(p) \ - ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \ - ~IT83XX_USBPD_REG_MASK_CC2_DISCONNECT) -#define USBPD_CC2_DISCONNECTED(p) \ - ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC2_DISCONNECT) & \ - ~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) - -#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) -#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x08) -#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x09) -#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C) -#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14) -#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7) -#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) -#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) -#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) -#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) -#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(2) -#define USBPD_REG_MASK_MSG_TX_DONE BIT(1) -#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) -#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) -#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18) -#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3) -#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2) -#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2) -#ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5 -#define USBPD_REG_MASK_TX_ERR_STAT BIT(5) -#else -#define USBPD_REG_MASK_TX_ERR_STAT BIT(1) -#endif -#define USBPD_REG_MASK_TX_START BIT(0) -#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19) -#define USBPD_REG_MASK_CABLE_ENABLE BIT(7) -#define USBPD_REG_MASK_SEND_HW_RESET BIT(6) -#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) -#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) -#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) -#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C) -#define USBPD_REG_MASK_RX_MSG_VALID BIT(0) -#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p)+0x1D) -#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p)+0x1E) -#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p)+0x1F) -#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p)+0x20) -#define IT83XX_USBPD_AGTMHLR(p) REG8(IT83XX_USBPD_BASE(p)+0x3C) -#define IT83XX_USBPD_AGTMHHR(p) REG8(IT83XX_USBPD_BASE(p)+0x3D) -#define IT83XX_USBPD_TMHLR(p) REG8(IT83XX_USBPD_BASE(p)+0x3E) -#define IT83XX_USBPD_TMHHR(p) REG8(IT83XX_USBPD_BASE(p)+0x3F) -#define IT83XX_USBPD_RDO0(p) REG32(IT83XX_USBPD_BASE(p)+0x40) -#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p)+0x5E) -#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x60) -#define IT83XX_USBPD_BMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x64) -#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p)+0x65) -#ifdef IT83XX_INTC_PLUG_IN_SUPPORT -#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67) -#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) -#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4) -#define USBPD_REG_PLUG_IN_OUT_SELECT BIT(3) -#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) -#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) -#endif //IT83XX_INTC_PLUG_IN_SUPPORT - -enum usbpd_port { - USBPD_PORT_A, - USBPD_PORT_B, - USBPD_PORT_COUNT, -}; - -#define USB_VID_ITE 0x048d - -#define IT83XX_ESPI_BASE 0x00F03100 - -#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE+0x05) -#define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE+0x90) -#define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE+0xA0) -#define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE+0xA1) -#define IT83XX_ESPI_ESGCTRL2 REG8(IT83XX_ESPI_BASE+0xA2) - -/* eSPI VW */ -#define IT83XX_ESPI_VW_BASE 0x00F03200 -#define IT83XX_ESPI_VWIDX(i) REG8(IT83XX_ESPI_VW_BASE+(i)) - -#define VW_LEVEL_FIELD(f) ((f) << 0) -#define VW_VALID_FIELD(f) ((f) << 4) - -#define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2 -#define VW_IDX_2_SLP_S3 BIT(0) -#define VW_IDX_2_SLP_S4 BIT(1) -#define VW_IDX_2_SLP_S5 BIT(2) - -#define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3 -#define VW_IDX_3_SUS_STAT BIT(0) -#define VW_IDX_3_PLTRST BIT(1) -#define VW_IDX_3_OOB_RST_WARN BIT(2) - -#define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4 -#define VW_IDX_4_OOB_RST_ACK BIT(0) -#define VW_IDX_4_WAKE BIT(2) -#define VW_IDX_4_PME BIT(3) - -#define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5 -#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0) -#define VW_IDX_5_FATAL BIT(1) -#define VW_IDX_5_NON_FATAL BIT(2) -#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3) -#define VW_IDX_5_BTLD_STATUS_DONE (VW_IDX_5_SLAVE_BTLD_DONE | \ - VW_IDX_5_SLAVE_BTLD_STATUS) - -#define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6 -#define VW_IDX_6_SCI BIT(0) -#define VW_IDX_6_SMI BIT(1) -#define VW_IDX_6_RCIN BIT(2) -#define VW_IDX_6_HOST_RST_ACK BIT(3) - -#define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7 -#define VW_IDX_7_HOST_RST_WARN BIT(0) - -#define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40 -#define VW_IDX_40_SUS_ACK BIT(0) - -#define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41 -#define VW_IDX_41_SUS_WARN BIT(0) -#define VW_IDX_41_SUS_PWRDN_ACK BIT(1) -#define VW_IDX_41_SLP_A BIT(3) - -#define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42 -#define VW_IDX_42_SLP_LAN BIT(0) -#define VW_IDX_42_SLP_WLAN BIT(1) - -#define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43 -#define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44 -#define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47 - -#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE+0x90) -#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7) - -#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91) -#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92) -#define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE+0x93) - -/* eSPI Queue 0 */ -#define IT83XX_ESPI_QUEUE_BASE 0x00F03300 -/* PUT_PC data byte 0 - 63 */ -#define IT83XX_ESPI_QUEUE_PUT_PC(i) REG8(IT83XX_ESPI_QUEUE_BASE+(i)) -/* PUT_OOB data byte 0 - 79 */ -#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i)) - -/* USB Controller */ -#define IT83XX_USB_BASE 0x00F02F00 - -#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE+0xE4) -#define USB_DP_DM_PULL_DOWN_EN BIT(4) - -/* Wake pin definitions, defined at board-level */ -extern const enum gpio_signal hibernate_wake_pins[]; -extern const int hibernate_wake_pins_used; - -/* --- MISC (not implemented yet) --- */ - -#define IT83XX_PS2_BASE 0x00F01700 -#define IT83XX_DAC_BASE 0x00F01A00 -#define IT83XX_EGPIO_BASE 0x00F02100 -#define IT83XX_CIR_BASE 0x00F02300 -#define IT83XX_DBGR_BASE 0x00F02500 -#define IT83XX_OW_BASE 0x00F02A00 -#define IT83XX_CEC_BASE 0x00F02E00 - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/it83xx/spi_master.c b/chip/it83xx/spi_master.c deleted file mode 100644 index 23cea9d2ab..0000000000 --- a/chip/it83xx/spi_master.c +++ /dev/null @@ -1,171 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SPI module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "spi.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -enum sspi_clk_sel { - sspi_clk_24mhz = 0, - sspi_clk_12mhz, - sspi_clk_8mhz, - sspi_clk_6mhz, - sspi_clk_4p8mhz, - sspi_clk_4mhz, - sspi_clk_3p428mhz, - sspi_clk_3mhz, -}; - -enum sspi_ch_sel { - SSPI_CH_CS0 = 0, - SSPI_CH_CS1, -}; - -static void sspi_frequency(enum sspi_clk_sel freq) -{ - /* - * bit[6:5] - * Bit 6:Clock Polarity (CLPOL) - * 0: SSCK is low in the idle mode. - * 1: SSCK is high in the idle mode. - * Bit 5:Clock Phase (CLPHS) - * 0: Latch data on the first SSCK edge. - * 1: Latch data on the second SSCK edge. - * - * bit[4:2] - * 000b: 1/2 clk_sspi - * 001b: 1/4 clk_sspi - * 010b: 1/6 clk_sspi - * 011b: 1/8 clk_sspi - * 100b: 1/10 clk_sspi - * 101b: 1/12 clk_sspi - * 110b: 1/14 clk_sspi - * 111b: 1/16 clk_sspi - * - * SSCK frequency is [freq] MHz and mode 3. - * note, clk_sspi need equal to 48MHz above. - */ - IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2)); -} - -static void sspi_transmission_end(void) -{ - /* Write 1 to end the SPI transmission. */ - IT83XX_SSPI_SPISTS = 0x20; - - /* Short delay for "Transfer End Flag" */ - IT83XX_GCTRL_WNCKR = 0; - - /* Write 1 to clear this bit and terminate data transmission. */ - IT83XX_SSPI_SPISTS = 0x02; -} - -/* We assume only one SPI port in the chip, one SPI device */ -int spi_enable(int port, int enable) -{ - if (enable) { - /* - * bit[5:4] - * 00b: SPI channel 0 and channel 1 are disabled. - * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled. - * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled. - * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled. - */ - if (port == SSPI_CH_CS1) - IT83XX_GPIO_GRC1 |= 0x20; - else - IT83XX_GPIO_GRC1 |= 0x10; - - gpio_config_module(MODULE_SPI_MASTER, 1); - } else { - if (port == SSPI_CH_CS1) - IT83XX_GPIO_GRC1 &= ~0x20; - else - IT83XX_GPIO_GRC1 &= ~0x10; - - gpio_config_module(MODULE_SPI_MASTER, 0); - } - - return EC_SUCCESS; -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int idx; - uint8_t port = spi_device->port; - static struct mutex spi_mutex; - - mutex_lock(&spi_mutex); - /* bit[0]: Write cycle */ - IT83XX_SSPI_SPICTRL2 &= ~0x04; - for (idx = 0x00; idx < txlen; idx++) { - IT83XX_SSPI_SPIDATA = txdata[idx]; - if (port == SSPI_CH_CS1) - /* Write 1 to start the data transmission of CS1 */ - IT83XX_SSPI_SPISTS |= 0x08; - else - /* Write 1 to start the data transmission of CS0 */ - IT83XX_SSPI_SPISTS |= 0x10; - } - - /* bit[1]: Read cycle */ - IT83XX_SSPI_SPICTRL2 |= 0x04; - for (idx = 0x00; idx < rxlen; idx++) { - if (port == SSPI_CH_CS1) - /* Write 1 to start the data transmission of CS1 */ - IT83XX_SSPI_SPISTS |= 0x08; - else - /* Write 1 to start the data transmission of CS0 */ - IT83XX_SSPI_SPISTS |= 0x10; - rxdata[idx] = IT83XX_SSPI_SPIDATA; - } - - sspi_transmission_end(); - mutex_unlock(&spi_mutex); - - return EC_SUCCESS; -} - -static void sspi_init(void) -{ - int i; - - clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0); - sspi_frequency(sspi_clk_8mhz); - - /* - * bit[5:3] Byte Width (BYTEWIDTH) - * 000b: 8-bit transmission - * 001b: 1-bit transmission - * 010b: 2-bit transmission - * 011b: 3-bit transmission - * 100b: 4-bit transmission - * 101b: 5-bit transmission - * 110b: 6-bit transmission - * 111b: 7-bit transmission - * - * bit[1] Blocking selection - */ - IT83XX_SSPI_SPICTRL2 |= 0x02; - - for (i = 0; i < spi_devices_used; i++) - /* Disabling spi module */ - spi_enable(spi_devices[i].port, 0); -} -DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI); diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c deleted file mode 100644 index 537455d4b9..0000000000 --- a/chip/it83xx/system.c +++ /dev/null @@ -1,336 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : hardware specific implementation */ - -#include "console.h" -#include "cpu.h" -#include "ec2i_chip.h" -#include "flash.h" -#include "hooks.h" -#include "host_command.h" -#include "intc.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "version.h" -#include "watchdog.h" - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - /* Flush console before hibernating */ - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* chip specific standby mode */ - __enter_hibernate(seconds, microseconds); -} - -static void check_reset_cause(void) -{ - uint32_t flags = 0; - uint8_t raw_reset_cause = IT83XX_GCTRL_RSTS & 0x03; - uint8_t raw_reset_cause2 = IT83XX_GCTRL_SPCTRL4 & 0x07; - - /* Restore saved reset flags. */ - flags |= BRAM_RESET_FLAGS0 << 24; - flags |= BRAM_RESET_FLAGS1 << 16; - flags |= BRAM_RESET_FLAGS2 << 8; - flags |= BRAM_RESET_FLAGS3; - - /* Clear reset cause. */ - IT83XX_GCTRL_RSTS |= 0x03; - IT83XX_GCTRL_SPCTRL4 |= 0x07; - - /* Determine if watchdog reset or power on reset. */ - if (raw_reset_cause & 0x02) { - flags |= EC_RESET_FLAG_WATCHDOG; - } else if (raw_reset_cause & 0x01) { - flags |= EC_RESET_FLAG_POWER_ON; - } else { - if ((IT83XX_GCTRL_RSTS & 0xC0) == 0x80) - flags |= EC_RESET_FLAG_POWER_ON; - } - - if (raw_reset_cause2 & 0x04) - flags |= EC_RESET_FLAG_RESET_PIN; - - /* watchdog module triggers these reset */ - if (flags & (EC_RESET_FLAG_HARD | EC_RESET_FLAG_SOFT)) - flags &= ~EC_RESET_FLAG_WATCHDOG; - - /* Clear saved reset flags. */ - BRAM_RESET_FLAGS0 = 0; - BRAM_RESET_FLAGS1 = 0; - BRAM_RESET_FLAGS2 = 0; - BRAM_RESET_FLAGS3 = 0; - - system_set_reset_flags(flags); -} - -static void system_reset_cause_is_unknown(void) -{ - /* No reset cause and not sysjump. */ - if (!system_get_reset_flags() && !system_jumped_to_this_image()) - /* - * We decrease 4 or 2 for "ec_reset_lp" here, that depend on - * which jump and link instruction has executed. - * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4) - */ - ccprintf("===Unknown reset! jump from %x or %x===\n", - ec_reset_lp - 4, ec_reset_lp - 2); -} -DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST); - -int system_is_reboot_warm(void) -{ - uint32_t reset_flags; - /* - * Check reset cause here, - * gpio_pre_init is executed faster than system_pre_init - */ - check_reset_cause(); - reset_flags = system_get_reset_flags(); - - if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT) || - (reset_flags & EC_RESET_FLAG_HIBERNATE)) - return 0; - else - return 1; -} - -void chip_pre_init(void) -{ - /* bit4, enable debug mode through SMBus */ - IT83XX_SMB_SLVISELR &= ~BIT(4); - - if (IS_ENABLED(IT83XX_ETWD_HW_RESET_SUPPORT)) - /* System triggers a soft reset by default (command: reboot). */ - IT83XX_GCTRL_ETWDUARTCR &= ~ETWD_HW_RST_EN; -} - -#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ -#define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff) -#define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff) -#define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff) -#define BRAM_VALID_MAGIC_FIELD3 ((BRAM_VALID_MAGIC >> 24) & 0xff) -void chip_bram_valid(void) -{ - int i; - - if ((BRAM_VALID_FLAGS0 != BRAM_VALID_MAGIC_FIELD0) || - (BRAM_VALID_FLAGS1 != BRAM_VALID_MAGIC_FIELD1) || - (BRAM_VALID_FLAGS2 != BRAM_VALID_MAGIC_FIELD2) || - (BRAM_VALID_FLAGS3 != BRAM_VALID_MAGIC_FIELD3)) { - /* - * Magic does not match, so BRAM must be uninitialized. Clear - * entire Bank0 BRAM, and set magic value. - */ - for (i = 0; i < BRAM_IDX_VALID_FLAGS0; i++) - IT83XX_BRAM_BANK0(i) = 0; - - BRAM_VALID_FLAGS0 = BRAM_VALID_MAGIC_FIELD0; - BRAM_VALID_FLAGS1 = BRAM_VALID_MAGIC_FIELD1; - BRAM_VALID_FLAGS2 = BRAM_VALID_MAGIC_FIELD2; - BRAM_VALID_FLAGS3 = BRAM_VALID_MAGIC_FIELD3; - } -} - -void system_pre_init(void) -{ - /* No initialization required */ - -} - -void system_reset(int flags) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot. */ - interrupt_disable(); - - /* Handle saving common reset flags. */ - system_encode_save_flags(flags, &save_flags); - - if (clock_ec_wake_from_sleep()) - save_flags |= EC_RESET_FLAG_HIBERNATE; - - /* Store flags to battery backed RAM. */ - BRAM_RESET_FLAGS0 = save_flags >> 24; - BRAM_RESET_FLAGS1 = (save_flags >> 16) & 0xff; - BRAM_RESET_FLAGS2 = (save_flags >> 8) & 0xff; - BRAM_RESET_FLAGS3 = save_flags & 0xff; - - /* If WAIT_EXT is set, then allow 10 seconds for external reset */ - if (flags & SYSTEM_RESET_WAIT_EXT) { - int i; - - /* Wait 10 seconds for external reset */ - for (i = 0; i < 1000; i++) { - watchdog_reload(); - udelay(10000); - } - } - - /* - * bit4, disable debug mode through SMBus. - * If we are in debug mode, we need disable it before triggering - * a soft reset or reset will fail. - */ - IT83XX_SMB_SLVISELR |= BIT(4); - - /* bit0: enable watchdog hardware reset. */ -#ifdef IT83XX_ETWD_HW_RESET_SUPPORT - if (flags & SYSTEM_RESET_HARD) - IT83XX_GCTRL_ETWDUARTCR |= ETWD_HW_RST_EN; -#endif - /* - * Writing invalid key to watchdog module triggers a soft or hardware - * reset. It depends on the setting of bit0 at ETWDUARTCR register. - */ - IT83XX_ETWD_ETWCFG |= 0x20; - IT83XX_ETWD_EWDKEYR = 0x00; - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -int system_set_scratchpad(uint32_t value) -{ - BRAM_SCRATCHPAD3 = (value >> 24) & 0xff; - BRAM_SCRATCHPAD2 = (value >> 16) & 0xff; - BRAM_SCRATCHPAD1 = (value >> 8) & 0xff; - BRAM_SCRATCHPAD0 = value & 0xff; - - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - uint32_t value = 0; - - value |= BRAM_SCRATCHPAD3 << 24; - value |= BRAM_SCRATCHPAD2 << 16; - value |= BRAM_SCRATCHPAD1 << 8; - value |= BRAM_SCRATCHPAD0; - - return value; -} - -static uint32_t system_get_chip_id(void) -{ -#ifdef IT83XX_CHIP_ID_3BYTES - return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) | - IT83XX_GCTRL_CHIPID3; -#else - return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2; -#endif -} - -static uint8_t system_get_chip_version(void) -{ - /* bit[3-0], chip version */ - return IT83XX_GCTRL_CHIPVER & 0x0F; -} - -static char to_hex(int x) -{ - if (x >= 0 && x <= 9) - return '0' + x; - return 'a' + x - 10; -} - -const char *system_get_chip_vendor(void) -{ - return "ite"; -} - -const char *system_get_chip_name(void) -{ - static char buf[8] = {'i', 't'}; - int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3); - uint32_t chip_id = system_get_chip_id(); - - for (int n = 2; num >= 0; n++, num--) - buf[n] = to_hex(chip_id >> (num * 4) & 0xF); - - return buf; -} - -const char *system_get_chip_revision(void) -{ - static char buf[3]; - uint8_t rev = system_get_chip_version(); - - buf[0] = to_hex(rev + 0xa); - buf[1] = 'x'; - buf[2] = '\0'; - return buf; -} - -static int bram_idx_lookup(enum system_bbram_idx idx) -{ - if (idx >= SYSTEM_BBRAM_IDX_VBNVBLOCK0 && - idx <= SYSTEM_BBRAM_IDX_VBNVBLOCK15) - return BRAM_IDX_NVCONTEXT + - idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0; - if (idx == SYSTEM_BBRAM_IDX_PD0) - return BRAM_IDX_PD0; - if (idx == SYSTEM_BBRAM_IDX_PD1) - return BRAM_IDX_PD1; - if (idx == SYSTEM_BBRAM_IDX_PD2) - return BRAM_IDX_PD2; - return -1; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int bram_idx = bram_idx_lookup(idx); - - if (bram_idx < 0) - return EC_ERROR_INVAL; - - *value = IT83XX_BRAM_BANK0(bram_idx); - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - int bram_idx = bram_idx_lookup(idx); - - if (bram_idx < 0) - return EC_ERROR_INVAL; - - IT83XX_BRAM_BANK0(bram_idx) = value; - return EC_SUCCESS; -} - -#define BRAM_NVCONTEXT_SIZE (BRAM_IDX_NVCONTEXT_END - BRAM_IDX_NVCONTEXT + 1) -BUILD_ASSERT(EC_VBNV_BLOCK_SIZE <= BRAM_NVCONTEXT_SIZE); - -uintptr_t system_get_fw_reset_vector(uintptr_t base) -{ - /* - * Because our reset vector is at the beginning of image copy - * (see init.S). So I just need to return 'base' here and EC will jump - * to the reset vector. - */ - return base; -} diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c deleted file mode 100644 index d0b645e68c..0000000000 --- a/chip/it83xx/uart.c +++ /dev/null @@ -1,247 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "intc.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Traces on UART1 */ -#define UART_PORT 0 -#define UART_PORT_HOST 1 - -static int init_done; - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (IT83XX_UART_IER(UART_PORT) & 0x02) - return; - - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - - /* Re-enable the transmit interrupt. */ - IT83XX_UART_IER(UART_PORT) |= 0x02; -} - -void uart_tx_stop(void) -{ - IT83XX_UART_IER(UART_PORT) &= ~0x02; - - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - /* - * Wait for transmit FIFO empty (TEMT) and transmitter holder - * register and transmitter shift registers to be empty (THRE). - */ - while ((IT83XX_UART_LSR(UART_PORT) & 0x60) != 0x60) - ; -} - -int uart_tx_ready(void) -{ - /* Transmit is ready when FIFO is empty (THRE). */ - return IT83XX_UART_LSR(UART_PORT) & 0x20; -} - -int uart_tx_in_progress(void) -{ - /* - * Transmit is in progress if transmit holding register or transmitter - * shift register are not empty (TEMT). - */ - return !(IT83XX_UART_LSR(UART_PORT) & 0x40); -} - -int uart_rx_available(void) -{ - return IT83XX_UART_LSR(UART_PORT) & 0x01; -} - -void uart_write_char(char c) -{ - /* Wait for space in transmit FIFO. */ - while (!uart_tx_ready()) - ; - - IT83XX_UART_THR(UART_PORT) = c; -} - -int uart_read_char(void) -{ - return IT83XX_UART_RBR(UART_PORT); -} - -static void uart_ec_interrupt(void) -{ - uint8_t uart_ier; - - /* clear interrupt status */ - task_clear_pending_irq(IT83XX_IRQ_UART1); - - /* Read input FIFO until empty, then fill output FIFO */ - uart_process_input(); - uart_process_output(); - - uart_ier = IT83XX_UART_IER(UART_PORT); - IT83XX_UART_IER(UART_PORT) = 0; - IT83XX_UART_IER(UART_PORT) = uart_ier; -} - -static void intc_cpu_int_group_9(void) -{ - /* Determine interrupt number. */ - int intc_group_9 = intc_get_ec_int(); - - switch (intc_group_9) { - case IT83XX_IRQ_UART1: - uart_ec_interrupt(); - break; - default: - break; - } -} -DECLARE_IRQ(CPU_INT_GROUP_9, intc_cpu_int_group_9, 1); - -static void uart_config(void) -{ - /* - * Specify clock source of the UART is 24MHz, - * must match CLK_UART_DIV_SEL. - */ - IT83XX_UART_CSSR(UART_PORT) = 0x01; - - /* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */ - IT83XX_UART_LCR(UART_PORT) = 0x83; - - /* Set divisor to set baud rate to 115200 */ - IT83XX_UART_DLM(UART_PORT) = 0x00; - IT83XX_UART_DLL(UART_PORT) = 0x01; - - /* - * Clear DLAB bit to exclude access to DLL and DLM and give access to - * RBR and THR. - */ - IT83XX_UART_LCR(UART_PORT) = 0x03; - - /* - * Enable TX and RX FIFOs and set RX FIFO interrupt level to the - * minimum 1 byte. - */ - IT83XX_UART_FCR(UART_PORT) = 0x07; - - /* - * set OUT2 bit to enable interrupt logic. - */ - IT83XX_UART_MCR(UART_PORT) = 0x08; -} - -#ifdef CONFIG_UART_HOST -static void host_uart_config(void) -{ - /* - * Specify clock source of the UART is 24MHz, - * must match CLK_UART_DIV_SEL. - */ - IT83XX_UART_CSSR(UART_PORT_HOST) = 0x01; - /* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */ - IT83XX_UART_LCR(UART_PORT_HOST) = 0x83; - /* Set divisor to set baud rate to 115200 */ - IT83XX_UART_DLM(UART_PORT_HOST) = 0x00; - IT83XX_UART_DLL(UART_PORT_HOST) = 0x01; - /* - * Clear DLAB bit to exclude access to DLL and DLM and give access to - * RBR and THR. - */ - IT83XX_UART_LCR(UART_PORT_HOST) = 0x03; - /* - * Enable TX and RX FIFOs and set RX FIFO interrupt level to the - * minimum 1 byte. - */ - IT83XX_UART_FCR(UART_PORT_HOST) = 0x07; -} -#endif - -#ifdef CONFIG_LOW_POWER_IDLE -void uart_enter_dsleep(void) -{ - gpio_clear_pending_interrupt(GPIO_UART1_RX); - gpio_enable_interrupt(GPIO_UART1_RX); -} - -void uart_exit_dsleep(void) -{ - gpio_disable_interrupt(GPIO_UART1_RX); - gpio_clear_pending_interrupt(GPIO_UART1_RX); -} - -void uart_deepsleep_interrupt(enum gpio_signal signal) -{ - clock_refresh_console_in_use(); - /* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */ - gpio_disable_interrupt(GPIO_UART1_RX); -} -#endif /* CONFIG_LOW_POWER_IDLE */ - -void uart_init(void) -{ - /* - * bit3: uart1 belongs to the EC side. - * This is necessary for enabling eSPI module. - */ - IT83XX_GCTRL_RSTDMMC |= BIT(3); - - /* reset uart before config it */ - IT83XX_GCTRL_RSTC4 |= BIT(1); - - /* Waiting for when we can use the GPIO module to set pin muxing */ - gpio_config_module(MODULE_UART, 1); - - /* switch UART1 on without hardware flow control */ - IT83XX_GPIO_GRC1 |= 0x01; - IT83XX_GPIO_GRC6 |= 0x03; - - /* Enable clocks to UART 1 and 2. */ - clock_enable_peripheral(CGC_OFFSET_UART, 0, 0); - - /* Config UART 1 */ - uart_config(); - -#ifdef CONFIG_UART_HOST - /* bit2, reset UART2 */ - IT83XX_GCTRL_RSTC4 |= BIT(2); - /* SIN1/SOUT1 of UART 2 is enabled. */ - IT83XX_GPIO_GRC1 |= BIT(2); - /* Config UART 2 */ - host_uart_config(); -#endif - - /* clear interrupt status */ - task_clear_pending_irq(IT83XX_IRQ_UART1); - - /* Enable interrupts */ - IT83XX_UART_IER(UART_PORT) = 0x03; - task_enable_irq(IT83XX_IRQ_UART1); - - init_done = 1; -} diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c deleted file mode 100644 index 6e12b9ba37..0000000000 --- a/chip/it83xx/watchdog.c +++ /dev/null @@ -1,135 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer_chip.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "watchdog.h" - -/* Panic data goes at the end of RAM. */ -static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; -/* Enter critical period or not. */ -static int wdt_warning_fired; - -/* - * We use WDT_EXT_TIMER to trigger an interrupt just before the watchdog timer - * will fire so that we can capture important state information before - * being reset. - */ - -/* Magic value to tickle the watchdog register. */ -#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C -/* Start to print warning message. */ -#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS -/* The interval to print warning message at critical period. */ -#define ITE83XX_WATCHDOG_CRITICAL_MS 30 - -/* set warning timer */ -static void watchdog_set_warning_timer(int32_t ms, int init) -{ - ext_timer_ms(WDT_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, ms, init, 0); -} - -void watchdog_warning_irq(void) -{ -#ifdef CONFIG_SOFTWARE_PANIC -#if defined(CHIP_CORE_NDS32) - pdata_ptr->nds_n8.ipc = get_ipc(); -#elif defined(CHIP_CORE_RISCV) - pdata_ptr->riscv.mepc = get_mepc(); -#endif -#endif - /* clear interrupt status */ - task_clear_pending_irq(et_ctrl_regs[WDT_EXT_TIMER].irq); - - /* Reset warning timer. */ - IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03; - -#if defined(CHIP_CORE_NDS32) - /* - * The IPC (Interruption Program Counter) is the shadow stack register - * of the PC (Program Counter). It stores the return address of program - * (PC->IPC) when the ISR was called. - * - * The LP (Link Pointer) stores the program address of the next - * sequential instruction for function call return purposes. - * LP = PC+4 after a jump and link instruction (jal). - */ - panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n", - get_ipc(), ilp, task_get_current()); -#elif defined(CHIP_CORE_RISCV) - panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n", - get_mepc(), ira, task_get_current()); -#endif - - if (!wdt_warning_fired++) - /* - * Reduce interval of warning timer, so we can print more - * warning messages during critical period. - */ - watchdog_set_warning_timer(ITE83XX_WATCHDOG_CRITICAL_MS, 0); -} - -void watchdog_reload(void) -{ - /* Reset warning timer. */ - IT83XX_ETWD_ETXCTRL(WDT_EXT_TIMER) = 0x03; - - /* Restart (tickle) watchdog timer. */ - IT83XX_ETWD_EWDKEYR = ITE83XX_WATCHDOG_MAGIC_WORD; - - if (wdt_warning_fired) { - wdt_warning_fired = 0; - /* Reset warning timer to default if watchdog is touched. */ - watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 0); - } -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - uint16_t wdt_count = CONFIG_WATCHDOG_PERIOD_MS * 1024 / 1000; - - /* Unlock access to watchdog registers. */ - IT83XX_ETWD_ETWCFG = 0x00; - - /* Set WD timer to use 1.024kHz clock. */ - IT83XX_ETWD_ET1PSR = 0x01; - - /* Set WDT key match enabled and WDT clock to use ET1PSR. */ - IT83XX_ETWD_ETWCFG = 0x30; - -#ifdef CONFIG_HIBERNATE - /* bit4: watchdog can be stopped. */ - IT83XX_ETWD_ETWCTRL |= BIT(4); -#else - /* Specify that watchdog cannot be stopped. */ - IT83XX_ETWD_ETWCTRL = 0x00; -#endif - - /* Start WDT_EXT_TIMER (CONFIG_AUX_TIMER_PERIOD_MS ms). */ - watchdog_set_warning_timer(ITE83XX_WATCHDOG_WARNING_MS, 1); - - /* Start timer 1 (must be started for watchdog timer to run). */ - IT83XX_ETWD_ET1CNTLLR = 0x00; - - /* - * Set watchdog timer to CONFIG_WATCHDOG_PERIOD_MS ms. - * Writing CNTLL starts timer. - */ - IT83XX_ETWD_EWDCNTLHR = (wdt_count >> 8) & 0xff; - IT83XX_ETWD_EWDCNTLLR = wdt_count & 0xff; - - /* Lock access to watchdog registers. */ - IT83XX_ETWD_ETWCFG = 0x3f; - - return EC_SUCCESS; -} diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk deleted file mode 100644 index e0f5636b2e..0000000000 --- a/chip/max32660/build.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -*- makefile -*- -# Copyright 2019 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# MAX32660 chip specific files build -# - -# MAX32660 SoC has a Cortex-M4F ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 - -# Required chip modules -chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o -chip-$(CONFIG_I2C)+=i2c_chip.o - -# Optional chip modules -chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o -chip-$(CONFIG_WATCHDOG)+=wdt_chip.o - diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c deleted file mode 100644 index 901c5d559c..0000000000 --- a/chip/max32660/clock_chip.c +++ /dev/null @@ -1,141 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Clocks and Power Management Module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" -#include "tmr_regs.h" -#include "gcr_regs.h" -#include "pwrseq_regs.h" - -#define MAX32660_SYSTEMCLOCK SYS_CLOCK_HIRC - -/** Clock source */ -typedef enum { - SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring - on MAX32660 */ - SYS_CLOCK_HFXIN = - MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ - SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ - SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency - Internal Oscillator */ -} sys_system_clock_t; - -/***** Functions ******/ -static void clock_wait_ready(uint32_t ready) -{ - // Start timeout, wait for ready - do { - if (MXC_GCR->clkcn & ready) { - return; - } - } while (1); -} - -extern void (*const __isr_vector[])(void); -uint32_t SystemCoreClock = HIRC96_FREQ; - -static void clock_update(void) -{ - uint32_t base_freq, divide, ovr; - - // Get the clock source and frequency - ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); - if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { - base_freq = HIRC96_FREQ / 4; - } else { - if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { - base_freq = HIRC96_FREQ / 2; - } else { - base_freq = HIRC96_FREQ; - } - } - - // Get the clock divider - divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> - MXC_F_GCR_CLKCN_PSC_POS; - - SystemCoreClock = base_freq >> divide; -} - -void clock_init(void) -{ - /* Switch system clock to HIRC */ - uint32_t ovr, divide; - - // Set FWS higher than what the minimum for the fastest clock is - MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS); - - // Enable 96MHz Clock - MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN; - - // Wait for the 96MHz clock - clock_wait_ready(MXC_F_GCR_CLKCN_HIRC_RDY); - - // Set 96MHz clock as System Clock - MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, - MXC_S_GCR_CLKCN_CLKSEL_HIRC); - - // Wait for system clock to be ready - clock_wait_ready(MXC_F_GCR_CLKCN_CKRDY); - - // Update the system core clock - clock_update(); - - // Get the clock divider - divide = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> - MXC_F_GCR_CLKCN_PSC_POS; - - // get ovr setting - ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); - - // Set flash wait settings - if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { - if (divide == 0) { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } else { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } - } else if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { - if (divide == 0) { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } else { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } - } else { - if (divide == 0) { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } else if (divide == 1) { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } else { - MXC_GCR->memckcn = - (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | - (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); - } - } -} diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h deleted file mode 100644 index b74ec591ad..0000000000 --- a/chip/max32660/config_chip.h +++ /dev/null @@ -1,104 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" - -/* 96.000 MHz internal oscillator frequency */ -#define INTERNAL_CLOCK 96000000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 132 - -/* Use a bigger console output buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 8192 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Number of I2C ports */ -#define I2C_PORT_COUNT 2 - -/* - * Time it takes to set the RTC match register. This value is conservatively - * set based on measurements around 200us. - */ -#define HIB_SET_RTC_MATCH_DELAY_USEC 300 - -/****************************************************************************/ -/* Memory mapping */ - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00018000 /* 96k MAX32660 SRAM Size*/ - -/* System stack size */ -#define CONFIG_STACK_SIZE 4096 - -/* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 768 -#define SMALLER_TASK_STACK_SIZE 384 - -/* Default task stack size */ -#define TASK_STACK_SIZE 512 - -#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 -#define CONFIG_FLASH_BANK_SIZE 0x00002000 /* protect bank size */ -#define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */ - -/* Ideal flash write size fills the 32-entry flash write buffer */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE (32 * 4) - -/* This is the physical size of the flash on the chip. We'll reserve one bank - * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware - * doesn't support a write-protect pin, and if we make the write-protection - * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE 0x00040000 /* 256K MAX32660 FLASH Size */ - -/****************************************************************************/ -/* Define our flash layout. */ - -/* Memory-mapped internal flash */ -#define CONFIG_INTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE - -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE - -/* Compute the rest of the flash params from these */ -#include "config_std_internal_flash.h" - -/****************************************************************************/ -/* Lock the boot configuration to prevent brickage. */ - -/* - * No GPIO trigger for ROM bootloader. - * Keep JTAG debugging enabled. - * Use 0xA442 flash write key. - * Lock it this way. - */ -#define CONFIG_BOOTCFG_VALUE 0x7ffffffe - -/****************************************************************************/ -/* Customize the build */ - -/* Optional features present on this chip */ -#define CONFIG_HOSTCMD_ALIGNED -#define CONFIG_RTC -#define CONFIG_SWITCH - -/* Chip needs to do custom pre-init */ -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c deleted file mode 100644 index ace87294a7..0000000000 --- a/chip/max32660/flash_chip.c +++ /dev/null @@ -1,404 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Flash Memory Module for Chrome EC */ - -#include "flash.h" -#include "switch.h" -#include "system.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" -#include "registers.h" -#include "common.h" -#include "icc_regs.h" -#include "flc_regs.h" - -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -/***** Definitions *****/ - -/// Bit mask that can be used to find the starting address of a page in flash -#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) - -/// Calculate the address of a page in flash from the page number -#define MXC_FLASH_PAGE_ADDR(page) \ - (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) - -void flash_operation(void) -{ - volatile uint32_t *line_addr; - volatile uint32_t __attribute__((unused)) line; - - // Clear the cache - MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN; - MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN; - - // Clear the line fill buffer - line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); - line = *line_addr; - - line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); - line = *line_addr; -} - -static int flash_busy(void) -{ - return (MXC_FLC->cn & - (MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE)); -} - -static int flash_init_controller(void) -{ - // Set flash clock divider to generate a 1MHz clock from the APB clock - MXC_FLC->clkdiv = SystemCoreClock / 1000000; - - /* Check if the flash controller is busy */ - if (flash_busy()) { - return EC_ERROR_BUSY; - } - - /* Clear stale errors */ - if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { - MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; - } - - /* Unlock flash */ - MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | - MXC_S_FLC_CN_UNLOCK_UNLOCKED; - - return EC_SUCCESS; -} - -static int flash_device_page_erase(uint32_t address) -{ - int err; - - if ((err = flash_init_controller()) != EC_SUCCESS) - return err; - - // Align address on page boundary - address = address - (address % MXC_FLASH_PAGE_SIZE); - - /* Write paflash_init_controllerde */ - MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | - MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE; - /* Issue page erase command */ - MXC_FLC->addr = address; - MXC_FLC->cn |= MXC_F_FLC_CN_PGE; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - - /* Lock flash */ - MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; - - /* Check access violations */ - if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { - MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; - return EC_ERROR_UNKNOWN; - } - - flash_operation(); - - return EC_SUCCESS; -} - -int flash_physical_write(int offset, int size, const char *data) -{ - int err; - uint32_t bytes_written; - uint8_t current_data[4]; - - if ((err = flash_init_controller()) != EC_SUCCESS) - return err; - - // write in 32-bit units until we are 128-bit aligned - MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST; - MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; - - // Align the address and read/write if we have to - if (offset & 0x3) { - - // Figure out how many bytes we have to write to round up the - // address - bytes_written = 4 - (offset & 0x3); - - // Save the data currently in the flash - memcpy(current_data, (void *)(offset & (~0x3)), 4); - - // Modify current_data to insert the data from buffer - memcpy(¤t_data[4 - bytes_written], data, bytes_written); - - // Write the modified data - MXC_FLC->addr = offset - (offset % 4); - memcpy((void *)&MXC_FLC->data[0], ¤t_data, 4); - MXC_FLC->cn |= MXC_F_FLC_CN_WR; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - - offset += bytes_written; - size -= bytes_written; - data += bytes_written; - } - - while ((size >= 4) && ((offset & 0x1F) != 0)) { - MXC_FLC->addr = offset; - memcpy((void *)&MXC_FLC->data[0], data, 4); - MXC_FLC->cn |= MXC_F_FLC_CN_WR; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - - offset += 4; - size -= 4; - data += 4; - } - - if (size >= 16) { - - // write in 128-bit bursts while we can - MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH; - - while (size >= 16) { - MXC_FLC->addr = offset; - memcpy((void *)&MXC_FLC->data[0], data, 16); - MXC_FLC->cn |= MXC_F_FLC_CN_WR; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - - offset += 16; - size -= 16; - data += 16; - } - - // Return to 32-bit writes. - MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; - } - - while (size >= 4) { - MXC_FLC->addr = offset; - memcpy((void *)&MXC_FLC->data[0], data, 4); - MXC_FLC->cn |= MXC_F_FLC_CN_WR; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - - offset += 4; - size -= 4; - data += 4; - } - - if (size > 0) { - // Save the data currently in the flash - memcpy(current_data, (void *)(offset), 4); - - // Modify current_data to insert the data from data - memcpy(current_data, data, size); - - MXC_FLC->addr = offset; - memcpy((void *)&MXC_FLC->data[0], current_data, 4); - MXC_FLC->cn |= MXC_F_FLC_CN_WR; - - /* Wait until flash operation is complete */ - while (flash_busy()) - ; - } - - /* Lock flash */ - MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; - - /* Check access violations */ - if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { - MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; - return EC_ERROR_UNKNOWN; - } - - flash_operation(); - - return EC_SUCCESS; -} - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_erase(int offset, int size) -{ - int i; - int pages; - int error_status; - - /* - * erase 'size' number of bytes starting at address 'offset' - */ - /* calculate the number of pages */ - pages = size / CONFIG_FLASH_ERASE_SIZE; - /* iterate over the number of pages */ - for (i = 0; i < pages; i++) { - /* erase the page after calculating the start address */ - error_status = flash_device_page_erase( - offset + (i * CONFIG_FLASH_ERASE_SIZE)); - if (error_status != EC_SUCCESS) { - return error_status; - } - } - return EC_SUCCESS; -} - -int flash_physical_get_protect(int bank) -{ - /* Not protected */ - return 0; -} - -uint32_t flash_physical_get_protect_flags(void) -{ - /* no flags set */ - return 0; -} - -uint32_t flash_physical_get_valid_flags(void) -{ - /* These are the flags we're going to pay attention to */ - return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - /* no flags writable */ - return 0; -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - /* nothing to do here */ - return EC_SUCCESS; -} - -int flash_physical_protect_now(int all) -{ - /* nothing to do here */ - return EC_SUCCESS; -} - -/*****************************************************************************/ -/* High-level APIs */ - -int flash_pre_init(void) -{ - return EC_SUCCESS; -} - -/*****************************************************************************/ -/* Test Commands */ - -/* - * Read, Write, and Erase a page of flash memory using chip routines - * NOTE: This is a DESTRUCTIVE test for the range of flash pages tested - * make sure that PAGE_START is beyond your flash code. - */ -static int command_flash_test1(int argc, char **argv) -{ - int i; - uint8_t *ptr; - const uint32_t PAGE_START = 9; - const uint32_t PAGE_END = 32; - uint32_t page; - int error_status; - uint32_t flash_address; - const int BUFFER_SIZE = 32; - uint8_t buffer[BUFFER_SIZE]; - - /* - * As a test, write unique data to each page in this for loop, later - * verify data in pages - */ - for (page = PAGE_START; page < PAGE_END; page++) { - flash_address = page * CONFIG_FLASH_ERASE_SIZE; - - /* - * erase page - */ - error_status = flash_physical_erase(flash_address, - CONFIG_FLASH_ERASE_SIZE); - if (error_status != EC_SUCCESS) { - CPRINTS("Error with flash_physical_erase\n"); - return EC_ERROR_UNKNOWN; - } - - /* - * verify page was erased - */ - // CPRINTS("read flash page %d, address %x, ", page, - // flash_address); - ptr = (uint8_t *)flash_address; - for (i = 0; i < CONFIG_FLASH_ERASE_SIZE; i++) { - if (*ptr++ != 0xff) { - CPRINTS("Error with verifying page erase\n"); - return EC_ERROR_UNKNOWN; - } - } - - /* - * write pattern to page, just write BUFFER_SIZE worth of data - */ - for (i = 0; i < BUFFER_SIZE; i++) { - buffer[i] = i + page; - } - error_status = flash_physical_write(flash_address, BUFFER_SIZE, - buffer); - if (error_status != EC_SUCCESS) { - CPRINTS("Error with flash_physical_write\n"); - return EC_ERROR_UNKNOWN; - } - } - - /* - * Verify data in pages - */ - for (page = PAGE_START; page < PAGE_END; page++) { - flash_address = page * CONFIG_FLASH_ERASE_SIZE; - - /* - * read a portion of flash memory - */ - ptr = (uint8_t *)flash_address; - for (i = 0; i < BUFFER_SIZE; i++) { - if (*ptr++ != (i + page)) { - CPRINTS("Error with verifing written test " - "data\n"); - return EC_ERROR_UNKNOWN; - } - } - CPRINTS("Verified Erase, Write, Read page %d", page); - } - - /* - * Clean up after tests - */ - for (page = PAGE_START; page <= PAGE_END; page++) { - flash_address = page * CONFIG_FLASH_ERASE_SIZE; - error_status = flash_physical_erase(flash_address, - CONFIG_FLASH_ERASE_SIZE); - if (error_status != EC_SUCCESS) { - CPRINTS("Error with flash_physical_erase\n"); - return EC_ERROR_UNKNOWN; - } - } - - CPRINTS("done command_flash_test1."); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(flashtest1, command_flash_test1, "flashtest1", - "Flash chip routine tests"); diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h deleted file mode 100644 index a484763c0b..0000000000 --- a/chip/max32660/flc_regs.h +++ /dev/null @@ -1,283 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the FLC Peripheral Module - */ - -#ifndef _FLC_REGS_H_ -#define _FLC_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/* **** Definitions **** */ - -/** - * Registers, Bit Masks and Bit Positions for the FLC Peripheral - * Module. - */ - -/** - * Structure type to access the FLC Registers. - */ -typedef struct { - __IO uint32_t addr; /**< <tt>\b 0x00:<\tt> FLC ADDR Register */ - __IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */ - __IO uint32_t cn; /**< <tt>\b 0x08:<\tt> FLC CN Register */ - __R uint32_t rsv_0xc_0x23[6]; - __IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */ - __R uint32_t rsv_0x28_0x2f[2]; - __IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */ - __O uint32_t acntl; /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */ -} mxc_flc_regs_t; - -/* Register offsets for module FLC */ -/** - * FLC Peripheral Register Offsets from the FLC Base Peripheral - * Address. - */ -#define MXC_R_FLC_ADDR \ - ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_FLC_CLKDIV \ - ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_FLC_CN \ - ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x008 */ -#define MXC_R_FLC_INTR \ - ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x024 */ -#define MXC_R_FLC_DATA \ - ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x030 */ -#define MXC_R_FLC_ACNTL \ - ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> \ - 0x0x040 */ - -/** - * Flash Write Address. - */ -#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ -#define MXC_F_FLC_ADDR_ADDR \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ - -/** - * Flash Clock Divide. The clock (PLL0) is divided by this value to - * generate a 1 MHz clock for Flash controller. - */ -#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ -#define MXC_F_FLC_CLKDIV_CLKDIV \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ - -/** - * Flash Control Register. - */ -#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ -#define MXC_F_FLC_CN_WR \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ -#define MXC_V_FLC_CN_WR_COMPLETE \ - ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value \ - */ -#define MXC_S_FLC_CN_WR_COMPLETE \ - (MXC_V_FLC_CN_WR_COMPLETE \ - << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */ -#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */ -#define MXC_S_FLC_CN_WR_START \ - (MXC_V_FLC_CN_WR_START \ - << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */ - -#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ -#define MXC_F_FLC_CN_ME \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ - -#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ -#define MXC_F_FLC_CN_PGE \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ - -#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */ -#define MXC_F_FLC_CN_WDTH \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ -#define MXC_V_FLC_CN_WDTH_SIZE128 \ - ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ -#define MXC_S_FLC_CN_WDTH_SIZE128 \ - (MXC_V_FLC_CN_WDTH_SIZE128 \ - << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */ -#define MXC_V_FLC_CN_WDTH_SIZE32 \ - ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \ - */ -#define MXC_S_FLC_CN_WDTH_SIZE32 \ - (MXC_V_FLC_CN_WDTH_SIZE32 \ - << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */ - -#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ -#define MXC_F_FLC_CN_ERASE_CODE \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ -#define MXC_V_FLC_CN_ERASE_CODE_NOP \ - ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ -#define MXC_S_FLC_CN_ERASE_CODE_NOP \ - (MXC_V_FLC_CN_ERASE_CODE_NOP \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ -#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ - ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ -#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \ - (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting \ - */ -#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ - ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ -#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL \ - (MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting \ - */ - -#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ -#define MXC_F_FLC_CN_PEND \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ -#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ -#define MXC_S_FLC_CN_PEND_IDLE \ - (MXC_V_FLC_CN_PEND_IDLE \ - << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */ -#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */ -#define MXC_S_FLC_CN_PEND_BUSY \ - (MXC_V_FLC_CN_PEND_BUSY \ - << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */ - -#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */ -#define MXC_F_FLC_CN_LVE \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */ -#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ -#define MXC_S_FLC_CN_LVE_DIS \ - (MXC_V_FLC_CN_LVE_DIS \ - << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */ -#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */ -#define MXC_S_FLC_CN_LVE_EN \ - (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting \ - */ - -#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */ -#define MXC_F_FLC_CN_BRST \ - ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ -#define MXC_V_FLC_CN_BRST_DISABLE \ - ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ -#define MXC_S_FLC_CN_BRST_DISABLE \ - (MXC_V_FLC_CN_BRST_DISABLE \ - << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */ -#define MXC_V_FLC_CN_BRST_ENABLE \ - ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \ - */ -#define MXC_S_FLC_CN_BRST_ENABLE \ - (MXC_V_FLC_CN_BRST_ENABLE \ - << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */ - -#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ -#define MXC_F_FLC_CN_UNLOCK \ - ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ -#define MXC_V_FLC_CN_UNLOCK_UNLOCKED \ - ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ -#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ - (MXC_V_FLC_CN_UNLOCK_UNLOCKED \ - << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ - -/** - * Flash Interrupt Register. - */ -#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ -#define MXC_F_FLC_INTR_DONE \ - ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ -#define MXC_V_FLC_INTR_DONE_INACTIVE \ - ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ -#define MXC_S_FLC_INTR_DONE_INACTIVE \ - (MXC_V_FLC_INTR_DONE_INACTIVE \ - << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ -#define MXC_V_FLC_INTR_DONE_PENDING \ - ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ -#define MXC_S_FLC_INTR_DONE_PENDING \ - (MXC_V_FLC_INTR_DONE_PENDING \ - << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ - -#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ -#define MXC_F_FLC_INTR_AF \ - ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ -#define MXC_V_FLC_INTR_AF_NOERROR \ - ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ -#define MXC_S_FLC_INTR_AF_NOERROR \ - (MXC_V_FLC_INTR_AF_NOERROR \ - << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */ -#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ -#define MXC_S_FLC_INTR_AF_ERROR \ - (MXC_V_FLC_INTR_AF_ERROR \ - << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */ - -#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ -#define MXC_F_FLC_INTR_DONEIE \ - ((uint32_t)( \ - 0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ -#define MXC_V_FLC_INTR_DONEIE_DISABLE \ - ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_DISABLE \ - (MXC_V_FLC_INTR_DONEIE_DISABLE \ - << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */ -#define MXC_V_FLC_INTR_DONEIE_ENABLE \ - ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_ENABLE \ - (MXC_V_FLC_INTR_DONEIE_ENABLE \ - << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */ - -#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ -#define MXC_F_FLC_INTR_AFIE \ - ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ - -/** - * Flash Write Data. - */ -#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ -#define MXC_F_FLC_DATA_DATA \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ - -/** - * Access Control Register. Writing the ACNTL register with the - * following values in the order shown, allows read and write access to the - * system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = - * 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will - * disable access to system and user information block. Readback of this - * register is always zero. - */ -#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */ -#define MXC_F_FLC_ACNTL_ACNTL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */ - -#ifdef __cplusplus -} -#endif - -#endif /* _FLC_REGS_H_ */ diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h deleted file mode 100644 index c9de13812c..0000000000 --- a/chip/max32660/gcr_regs.h +++ /dev/null @@ -1,1365 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the GCR Peripheral Module - */ - -#ifndef _GCR_REGS_H_ -#define _GCR_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/* **** Definitions **** */ - -/** - * Registers, Bit Masks and Bit Positions for the GCR Peripheral - * Module. - */ - -/** - * Structure type to access the GCR Registers. - */ -typedef struct { - __IO uint32_t scon; /**< <tt>\b 0x00:<\tt> GCR SCON Register */ - __IO uint32_t rstr0; /**< <tt>\b 0x04:<\tt> GCR RSTR0 Register */ - __IO uint32_t clkcn; /**< <tt>\b 0x08:<\tt> GCR CLKCN Register */ - __IO uint32_t pm; /**< <tt>\b 0x0C:<\tt> GCR PM Register */ - __R uint32_t rsv_0x10_0x17[2]; - __IO uint32_t pckdiv; /**< <tt>\b 0x18:<\tt> GCR PCKDIV Register */ - __R uint32_t rsv_0x1c_0x23[2]; - __IO uint32_t perckcn0; /**< <tt>\b 0x24:<\tt> GCR PERCKCN0 Register */ - __IO uint32_t memckcn; /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */ - __IO uint32_t memzcn; /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */ - __R uint32_t rsv_0x30; - __IO uint32_t scck; /**< <tt>\b 0x34:<\tt> GCR SCCK Register */ - __IO uint32_t mpri0; /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */ - __IO uint32_t mpri1; /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */ - __IO uint32_t sysst; /**< <tt>\b 0x40:<\tt> GCR SYSST Register */ - __IO uint32_t rstr1; /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */ - __IO uint32_t perckcn1; /**< <tt>\b 0x48:<\tt> GCR PERCKCN1 Register */ - __IO uint32_t evten; /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */ - __I uint32_t revision; /**< <tt>\b 0x50:<\tt> GCR REVISION Register */ - __IO uint32_t syssie; /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */ -} mxc_gcr_regs_t; - -/** - * GCR Peripheral Register Offsets from the GCR Base Peripheral - * Address. - */ -#define MXC_R_GCR_SCON \ - ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_GCR_RSTR0 \ - ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_GCR_CLKCN \ - ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x008 */ -#define MXC_R_GCR_PM \ - ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> \ - 0x0x00C */ -#define MXC_R_GCR_PCKDIV \ - ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x018 */ -#define MXC_R_GCR_PERCKCN0 \ - ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x024 */ -#define MXC_R_GCR_MEMCKCN \ - ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x028 */ -#define MXC_R_GCR_MEMZCN \ - ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> \ - 0x0x02C */ -#define MXC_R_GCR_SCCK \ - ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x034 */ -#define MXC_R_GCR_MPRI0 \ - ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x038 */ -#define MXC_R_GCR_MPRI1 \ - ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> \ - 0x0x03C */ -#define MXC_R_GCR_SYSST \ - ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x040 */ -#define MXC_R_GCR_RSTR1 \ - ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x044 */ -#define MXC_R_GCR_PERCKCN1 \ - ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x048 */ -#define MXC_R_GCR_EVTEN \ - ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> \ - 0x0x04C */ -#define MXC_R_GCR_REVISION \ - ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x050 */ -#define MXC_R_GCR_SYSSIE \ - ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> \ - 0x0x054 */ - -/** - * System Control. - */ -#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ -#define MXC_F_GCR_SCON_SBUSARB \ - ((uint32_t)(0x3UL \ - << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ -#define MXC_V_GCR_SCON_SBUSARB_FIX \ - ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ -#define MXC_S_GCR_SCON_SBUSARB_FIX \ - (MXC_V_GCR_SCON_SBUSARB_FIX \ - << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ -#define MXC_V_GCR_SCON_SBUSARB_ROUND \ - ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ -#define MXC_S_GCR_SCON_SBUSARB_ROUND \ - (MXC_V_GCR_SCON_SBUSARB_ROUND \ - << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ - -#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \ - 4 /**< SCON_FLASH_PAGE_FLIP Position */ -#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< \ - SCON_FLASH_PAGE_FLIP \ - Mask */ -#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ - ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ -#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ - (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ - << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< \ - SCON_FLASH_PAGE_FLIP_NORMAL \ - Setting */ -#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ - ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */ -#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ - (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ - << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< \ - SCON_FLASH_PAGE_FLIP_SWAPPED \ - Setting */ - -#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ -#define MXC_F_GCR_SCON_FPU_DIS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ -#define MXC_V_GCR_SCON_FPU_DIS_ENABLE \ - ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_ENABLE \ - (MXC_V_GCR_SCON_FPU_DIS_ENABLE \ - << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */ -#define MXC_V_GCR_SCON_FPU_DIS_DISABLE \ - ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_DISABLE \ - (MXC_V_GCR_SCON_FPU_DIS_DISABLE \ - << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */ - -#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ -#define MXC_F_GCR_SCON_CCACHE_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH \ - Mask */ -#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ - ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ -#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL \ - (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL \ - Setting */ -#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ - ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ -#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH \ - (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH \ - Setting */ - -#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ -#define MXC_F_GCR_SCON_SWD_DIS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ -#define MXC_V_GCR_SCON_SWD_DIS_ENABLE \ - ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_ENABLE \ - (MXC_V_GCR_SCON_SWD_DIS_ENABLE \ - << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */ -#define MXC_V_GCR_SCON_SWD_DIS_DISABLE \ - ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_DISABLE \ - (MXC_V_GCR_SCON_SWD_DIS_DISABLE \ - << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */ - -/** - * Reset Register 0. - */ -#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ -#define MXC_F_GCR_RSTR0_DMA \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ -#define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */ -#define MXC_S_GCR_RSTR0_DMA_RFU \ - (MXC_V_GCR_RSTR0_DMA_RFU \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */ -#define MXC_V_GCR_RSTR0_DMA_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET \ - (MXC_V_GCR_RSTR0_DMA_RESET \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */ -#define MXC_V_GCR_RSTR0_DMA_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ - (MXC_V_GCR_RSTR0_DMA_RESET_DONE \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_DMA_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \ - */ -#define MXC_S_GCR_RSTR0_DMA_BUSY \ - (MXC_V_GCR_RSTR0_DMA_BUSY \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ -#define MXC_F_GCR_RSTR0_WDT \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */ -#define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */ -#define MXC_S_GCR_RSTR0_WDT_RFU \ - (MXC_V_GCR_RSTR0_WDT_RFU \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */ -#define MXC_V_GCR_RSTR0_WDT_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET \ - (MXC_V_GCR_RSTR0_WDT_RESET \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */ -#define MXC_V_GCR_RSTR0_WDT_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET_DONE \ - (MXC_V_GCR_RSTR0_WDT_RESET_DONE \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_WDT_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \ - */ -#define MXC_S_GCR_RSTR0_WDT_BUSY \ - (MXC_V_GCR_RSTR0_WDT_BUSY \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ -#define MXC_F_GCR_RSTR0_GPIO0 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ -#define MXC_V_GCR_RSTR0_GPIO0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RFU \ - (MXC_V_GCR_RSTR0_GPIO0_RFU \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET \ - (MXC_V_GCR_RSTR0_GPIO0_RESET \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE \ - (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */ -#define MXC_S_GCR_RSTR0_GPIO0_BUSY \ - (MXC_V_GCR_RSTR0_GPIO0_BUSY \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ -#define MXC_F_GCR_RSTR0_TIMER0 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ -#define MXC_V_GCR_RSTR0_TIMER0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RFU \ - (MXC_V_GCR_RSTR0_TIMER0_RFU \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER0_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RESET \ - (MXC_V_GCR_RSTR0_TIMER0_RESET \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting \ - */ -#define MXC_V_GCR_RSTR0_TIMER0_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER0_BUSY \ - (MXC_V_GCR_RSTR0_TIMER0_BUSY \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ -#define MXC_F_GCR_RSTR0_TIMER1 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ -#define MXC_V_GCR_RSTR0_TIMER1_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RFU \ - (MXC_V_GCR_RSTR0_TIMER1_RFU \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER1_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RESET \ - (MXC_V_GCR_RSTR0_TIMER1_RESET \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting \ - */ -#define MXC_V_GCR_RSTR0_TIMER1_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER1_BUSY \ - (MXC_V_GCR_RSTR0_TIMER1_BUSY \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ -#define MXC_F_GCR_RSTR0_TIMER2 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ -#define MXC_V_GCR_RSTR0_TIMER2_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RFU \ - (MXC_V_GCR_RSTR0_TIMER2_RFU \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER2_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RESET \ - (MXC_V_GCR_RSTR0_TIMER2_RESET \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting \ - */ -#define MXC_V_GCR_RSTR0_TIMER2_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER2_BUSY \ - (MXC_V_GCR_RSTR0_TIMER2_BUSY \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ -#define MXC_F_GCR_RSTR0_UART0 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ -#define MXC_V_GCR_RSTR0_UART0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */ -#define MXC_S_GCR_RSTR0_UART0_RFU \ - (MXC_V_GCR_RSTR0_UART0_RFU \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */ -#define MXC_V_GCR_RSTR0_UART0_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET \ - (MXC_V_GCR_RSTR0_UART0_RESET \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */ -#define MXC_V_GCR_RSTR0_UART0_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART0_RESET_DONE \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_UART0_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART0_BUSY \ - (MXC_V_GCR_RSTR0_UART0_BUSY \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ -#define MXC_F_GCR_RSTR0_UART1 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */ -#define MXC_V_GCR_RSTR0_UART1_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */ -#define MXC_S_GCR_RSTR0_UART1_RFU \ - (MXC_V_GCR_RSTR0_UART1_RFU \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */ -#define MXC_V_GCR_RSTR0_UART1_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET \ - (MXC_V_GCR_RSTR0_UART1_RESET \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */ -#define MXC_V_GCR_RSTR0_UART1_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART1_RESET_DONE \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_UART1_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART1_BUSY \ - (MXC_V_GCR_RSTR0_UART1_BUSY \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ -#define MXC_F_GCR_RSTR0_SPI0 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask \ - */ -#define MXC_V_GCR_RSTR0_SPI0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \ - */ -#define MXC_S_GCR_RSTR0_SPI0_RFU \ - (MXC_V_GCR_RSTR0_SPI0_RFU \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */ -#define MXC_V_GCR_RSTR0_SPI0_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET \ - (MXC_V_GCR_RSTR0_SPI0_RESET \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */ -#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SPI0_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI0_BUSY \ - (MXC_V_GCR_RSTR0_SPI0_BUSY \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ -#define MXC_F_GCR_RSTR0_SPI1 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask \ - */ -#define MXC_V_GCR_RSTR0_SPI1_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \ - */ -#define MXC_S_GCR_RSTR0_SPI1_RFU \ - (MXC_V_GCR_RSTR0_SPI1_RFU \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */ -#define MXC_V_GCR_RSTR0_SPI1_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET \ - (MXC_V_GCR_RSTR0_SPI1_RESET \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */ -#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SPI1_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI1_BUSY \ - (MXC_V_GCR_RSTR0_SPI1_BUSY \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ -#define MXC_F_GCR_RSTR0_I2C0 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask \ - */ -#define MXC_V_GCR_RSTR0_I2C0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \ - */ -#define MXC_S_GCR_RSTR0_I2C0_RFU \ - (MXC_V_GCR_RSTR0_I2C0_RFU \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */ -#define MXC_V_GCR_RSTR0_I2C0_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET \ - (MXC_V_GCR_RSTR0_I2C0_RESET \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */ -#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE \ - (MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_I2C0_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */ -#define MXC_S_GCR_RSTR0_I2C0_BUSY \ - (MXC_V_GCR_RSTR0_I2C0_BUSY \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ -#define MXC_F_GCR_RSTR0_RTC \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */ -#define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */ -#define MXC_S_GCR_RSTR0_RTC_RFU \ - (MXC_V_GCR_RSTR0_RTC_RFU \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */ -#define MXC_V_GCR_RSTR0_RTC_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET \ - (MXC_V_GCR_RSTR0_RTC_RESET \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */ -#define MXC_V_GCR_RSTR0_RTC_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET_DONE \ - (MXC_V_GCR_RSTR0_RTC_RESET_DONE \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_RTC_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \ - */ -#define MXC_S_GCR_RSTR0_RTC_BUSY \ - (MXC_V_GCR_RSTR0_RTC_BUSY \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ -#define MXC_F_GCR_RSTR0_SRST \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask \ - */ -#define MXC_V_GCR_RSTR0_SRST_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \ - */ -#define MXC_S_GCR_RSTR0_SRST_RFU \ - (MXC_V_GCR_RSTR0_SRST_RFU \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */ -#define MXC_V_GCR_RSTR0_SRST_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET \ - (MXC_V_GCR_RSTR0_SRST_RESET \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */ -#define MXC_V_GCR_RSTR0_SRST_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_SRST_RESET_DONE \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SRST_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_SRST_BUSY \ - (MXC_V_GCR_RSTR0_SRST_BUSY \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ -#define MXC_F_GCR_RSTR0_PRST \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask \ - */ -#define MXC_V_GCR_RSTR0_PRST_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \ - */ -#define MXC_S_GCR_RSTR0_PRST_RFU \ - (MXC_V_GCR_RSTR0_PRST_RFU \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */ -#define MXC_V_GCR_RSTR0_PRST_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET \ - (MXC_V_GCR_RSTR0_PRST_RESET \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */ -#define MXC_V_GCR_RSTR0_PRST_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_PRST_RESET_DONE \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_PRST_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_PRST_BUSY \ - (MXC_V_GCR_RSTR0_PRST_BUSY \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */ - -#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ -#define MXC_F_GCR_RSTR0_SYSTEM \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ -#define MXC_V_GCR_RSTR0_SYSTEM_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RFU \ - (MXC_V_GCR_RSTR0_SYSTEM_RFU \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */ -#define MXC_V_GCR_RSTR0_SYSTEM_RESET \ - ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RESET \ - (MXC_V_GCR_RSTR0_SYSTEM_RESET \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */ -#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE \ - (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting \ - */ -#define MXC_V_GCR_RSTR0_SYSTEM_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_BUSY \ - (MXC_V_GCR_RSTR0_SYSTEM_BUSY \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */ - -/** - * Clock Control. - */ -#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ -#define MXC_F_GCR_CLKCN_PSC \ - ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ -#define MXC_V_GCR_CLKCN_PSC_DIV1 \ - ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \ - */ -#define MXC_S_GCR_CLKCN_PSC_DIV1 \ - (MXC_V_GCR_CLKCN_PSC_DIV1 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV2 \ - ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \ - */ -#define MXC_S_GCR_CLKCN_PSC_DIV2 \ - (MXC_V_GCR_CLKCN_PSC_DIV2 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV4 \ - ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \ - */ -#define MXC_S_GCR_CLKCN_PSC_DIV4 \ - (MXC_V_GCR_CLKCN_PSC_DIV4 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV8 \ - ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \ - */ -#define MXC_S_GCR_CLKCN_PSC_DIV8 \ - (MXC_V_GCR_CLKCN_PSC_DIV8 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV16 \ - ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV16 \ - (MXC_V_GCR_CLKCN_PSC_DIV16 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV32 \ - ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV32 \ - (MXC_V_GCR_CLKCN_PSC_DIV32 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV64 \ - ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV64 \ - (MXC_V_GCR_CLKCN_PSC_DIV64 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV128 \ - ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV128 \ - (MXC_V_GCR_CLKCN_PSC_DIV128 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ - -#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ -#define MXC_F_GCR_CLKCN_CLKSEL \ - ((uint32_t)(0x7UL \ - << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ -#define MXC_V_GCR_CLKCN_CLKSEL_HIRC \ - ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ - (MXC_V_GCR_CLKCN_CLKSEL_HIRC \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ -#define MXC_V_GCR_CLKCN_CLKSEL_NANORING \ - ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_NANORING \ - (MXC_V_GCR_CLKCN_CLKSEL_NANORING \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */ -#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ - ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN \ - (MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */ - -#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ -#define MXC_F_GCR_CLKCN_CKRDY \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ -#define MXC_V_GCR_CLKCN_CKRDY_BUSY \ - ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ - (MXC_V_GCR_CLKCN_CKRDY_BUSY \ - << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */ -#define MXC_V_GCR_CLKCN_CKRDY_READY \ - ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_READY \ - (MXC_V_GCR_CLKCN_CKRDY_READY \ - << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */ - -#define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ -#define MXC_F_GCR_CLKCN_X32K_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */ -#define MXC_V_GCR_CLKCN_X32K_EN_DIS \ - ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_DIS \ - (MXC_V_GCR_CLKCN_X32K_EN_DIS \ - << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */ -#define MXC_V_GCR_CLKCN_X32K_EN_EN \ - ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_EN \ - (MXC_V_GCR_CLKCN_X32K_EN_EN \ - << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */ - -#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ -#define MXC_F_GCR_CLKCN_HIRC_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ -#define MXC_V_GCR_CLKCN_HIRC_EN_DIS \ - ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ - (MXC_V_GCR_CLKCN_HIRC_EN_DIS \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */ -#define MXC_V_GCR_CLKCN_HIRC_EN_EN \ - ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ - (MXC_V_GCR_CLKCN_HIRC_EN_EN \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */ - -#define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ -#define MXC_F_GCR_CLKCN_X32K_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */ -#define MXC_V_GCR_CLKCN_X32K_RDY_NOT \ - ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_NOT \ - (MXC_V_GCR_CLKCN_X32K_RDY_NOT \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */ -#define MXC_V_GCR_CLKCN_X32K_RDY_READY \ - ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_READY \ - (MXC_V_GCR_CLKCN_X32K_RDY_READY \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */ - -#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ -#define MXC_F_GCR_CLKCN_HIRC_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ -#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ - ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ - (MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */ -#define MXC_V_GCR_CLKCN_HIRC_RDY_READY \ - ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ - (MXC_V_GCR_CLKCN_HIRC_RDY_READY \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */ - -#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ -#define MXC_F_GCR_CLKCN_LIRC8K_RDY \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY \ - Mask */ -#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ - ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT \ - (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting \ - */ -#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ - ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY \ - (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY \ - Setting */ - -/** - * Power Management. - */ -#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ -#define MXC_F_GCR_PM_MODE \ - ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ -#define MXC_V_GCR_PM_MODE_ACTIVE \ - ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value \ - */ -#define MXC_S_GCR_PM_MODE_ACTIVE \ - (MXC_V_GCR_PM_MODE_ACTIVE \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ -#define MXC_V_GCR_PM_MODE_SHUTDOWN \ - ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ -#define MXC_S_GCR_PM_MODE_SHUTDOWN \ - (MXC_V_GCR_PM_MODE_SHUTDOWN \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ -#define MXC_V_GCR_PM_MODE_BACKUP \ - ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \ - */ -#define MXC_S_GCR_PM_MODE_BACKUP \ - (MXC_V_GCR_PM_MODE_BACKUP \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ - -#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ -#define MXC_F_GCR_PM_GPIOWKEN \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ -#define MXC_V_GCR_PM_GPIOWKEN_DIS \ - ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ -#define MXC_S_GCR_PM_GPIOWKEN_DIS \ - (MXC_V_GCR_PM_GPIOWKEN_DIS \ - << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */ -#define MXC_V_GCR_PM_GPIOWKEN_EN \ - ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \ - */ -#define MXC_S_GCR_PM_GPIOWKEN_EN \ - (MXC_V_GCR_PM_GPIOWKEN_EN \ - << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */ - -#define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ -#define MXC_F_GCR_PM_RTCWKEN \ - ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask \ - */ -#define MXC_V_GCR_PM_RTCWKEN_DIS \ - ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \ - */ -#define MXC_S_GCR_PM_RTCWKEN_DIS \ - (MXC_V_GCR_PM_RTCWKEN_DIS \ - << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */ -#define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */ -#define MXC_S_GCR_PM_RTCWKEN_EN \ - (MXC_V_GCR_PM_RTCWKEN_EN \ - << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */ - -#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ -#define MXC_F_GCR_PM_HIRCPD \ - ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ -#define MXC_V_GCR_PM_HIRCPD_ACTIVE \ - ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ -#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ - (MXC_V_GCR_PM_HIRCPD_ACTIVE \ - << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */ -#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ - ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ -#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ - (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ - << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */ - -/** - * Peripheral Clock Divider. - */ -#define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */ -#define MXC_F_GCR_PCKDIV_AONCD \ - ((uint32_t)(0x3UL \ - << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ - ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ - ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ - ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ - ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ - -/** - * Peripheral Clock Disable. - */ -#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ -#define MXC_F_GCR_PERCKCN0_GPIO0D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_GPIO0D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ - (MXC_V_GCR_PERCKCN0_GPIO0D_EN \ - << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ - (MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ - << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ -#define MXC_F_GCR_PERCKCN0_DMAD \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ -#define MXC_V_GCR_PERCKCN0_DMAD_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_EN \ - (MXC_V_GCR_PERCKCN0_DMAD_EN \ - << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */ -#define MXC_V_GCR_PERCKCN0_DMAD_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_DIS \ - (MXC_V_GCR_PERCKCN0_DMAD_DIS \ - << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ -#define MXC_F_GCR_PERCKCN0_SPI0D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */ -#define MXC_V_GCR_PERCKCN0_SPI0D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_EN \ - (MXC_V_GCR_PERCKCN0_SPI0D_EN \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_SPI0D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI0D_DIS \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ -#define MXC_F_GCR_PERCKCN0_SPI1D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ -#define MXC_V_GCR_PERCKCN0_SPI1D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_EN \ - (MXC_V_GCR_PERCKCN0_SPI1D_EN \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_SPI1D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI1D_DIS \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ -#define MXC_F_GCR_PERCKCN0_UART0D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_UART0D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_EN \ - (MXC_V_GCR_PERCKCN0_UART0D_EN \ - << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_UART0D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_DIS \ - (MXC_V_GCR_PERCKCN0_UART0D_DIS \ - << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ -#define MXC_F_GCR_PERCKCN0_UART1D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_UART1D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_EN \ - (MXC_V_GCR_PERCKCN0_UART1D_EN \ - << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_UART1D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_DIS \ - (MXC_V_GCR_PERCKCN0_UART1D_DIS \ - << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ -#define MXC_F_GCR_PERCKCN0_I2C0D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ -#define MXC_V_GCR_PERCKCN0_I2C0D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_EN \ - (MXC_V_GCR_PERCKCN0_I2C0D_EN \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_I2C0D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C0D_DIS \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ -#define MXC_F_GCR_PERCKCN0_T0D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */ -#define MXC_V_GCR_PERCKCN0_T0D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T0D_EN \ - (MXC_V_GCR_PERCKCN0_T0D_EN \ - << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T0D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T0D_DIS \ - (MXC_V_GCR_PERCKCN0_T0D_DIS \ - << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ -#define MXC_F_GCR_PERCKCN0_T1D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */ -#define MXC_V_GCR_PERCKCN0_T1D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T1D_EN \ - (MXC_V_GCR_PERCKCN0_T1D_EN \ - << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T1D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T1D_DIS \ - (MXC_V_GCR_PERCKCN0_T1D_DIS \ - << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ -#define MXC_F_GCR_PERCKCN0_T2D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */ -#define MXC_V_GCR_PERCKCN0_T2D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T2D_EN \ - (MXC_V_GCR_PERCKCN0_T2D_EN \ - << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T2D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T2D_DIS \ - (MXC_V_GCR_PERCKCN0_T2D_DIS \ - << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */ - -#define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ -#define MXC_F_GCR_PERCKCN0_I2C1D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */ -#define MXC_V_GCR_PERCKCN0_I2C1D_EN \ - ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_EN \ - (MXC_V_GCR_PERCKCN0_I2C1D_EN \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_I2C1D_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C1D_DIS \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */ - -/** - * Memory Clock Control Register. - */ -#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ -#define MXC_F_GCR_MEMCKCN_FWS \ - ((uint32_t)( \ - 0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ - -#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM0LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ - ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE \ - Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< \ - MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - Setting */ - -#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM1LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ - ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE \ - Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< \ - MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - Setting */ - -#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM2LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ - ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE \ - Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< \ - MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - Setting */ - -#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM3LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ - ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE \ - Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< \ - MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - Setting */ - -#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */ -#define MXC_F_GCR_MEMCKCN_ICACHELS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ - ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE \ - Setting */ -#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ - ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP \ - Setting */ - -/** - * Memory Zeroize Control. - */ -#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ -#define MXC_F_GCR_MEMZCN_SRAM0Z \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ -#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ - ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ - (MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */ -#define MXC_V_GCR_MEMZCN_SRAM0Z_START \ - ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ - (MXC_V_GCR_MEMZCN_SRAM0Z_START \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */ - -#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */ -#define MXC_F_GCR_MEMZCN_ICACHEZ \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ -#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ - ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP \ - (MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */ -#define MXC_V_GCR_MEMZCN_ICACHEZ_START \ - ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_START \ - (MXC_V_GCR_MEMZCN_ICACHEZ_START \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */ - -/** - * System Status Register. - */ -#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */ -#define MXC_F_GCR_SYSST_ICECLOCK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */ -#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \ - ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */ -#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED \ - (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \ - << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \ - */ -#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ - ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */ -#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED \ - (MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ - << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting \ - */ - -#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ -#define MXC_F_GCR_SYSST_CODEINTERR \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR \ - Mask */ -#define MXC_V_GCR_SYSST_CODEINTERR_NORM \ - ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */ -#define MXC_S_GCR_SYSST_CODEINTERR_NORM \ - (MXC_V_GCR_SYSST_CODEINTERR_NORM \ - << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \ - */ -#define MXC_V_GCR_SYSST_CODEINTERR_CODE \ - ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */ -#define MXC_S_GCR_SYSST_CODEINTERR_CODE \ - (MXC_V_GCR_SYSST_CODEINTERR_CODE \ - << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting \ - */ - -#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ -#define MXC_F_GCR_SYSST_SCMEMF \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ -#define MXC_V_GCR_SYSST_SCMEMF_NORM \ - ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */ -#define MXC_S_GCR_SYSST_SCMEMF_NORM \ - (MXC_V_GCR_SYSST_SCMEMF_NORM \ - << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */ -#define MXC_V_GCR_SYSST_SCMEMF_MEMORY \ - ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */ -#define MXC_S_GCR_SYSST_SCMEMF_MEMORY \ - (MXC_V_GCR_SYSST_SCMEMF_MEMORY \ - << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */ - -/** - * Reset Register. - */ -#define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */ -#define MXC_F_GCR_RSTR1_I2C1 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask \ - */ -#define MXC_V_GCR_RSTR1_I2C1_RESET \ - ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET \ - (MXC_V_GCR_RSTR1_I2C1_RESET \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */ -#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ - ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE \ - (MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR1_I2C1_BUSY \ - ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */ -#define MXC_S_GCR_RSTR1_I2C1_BUSY \ - (MXC_V_GCR_RSTR1_I2C1_BUSY \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */ - -/** - * Peripheral Clock Disable. - */ -#define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */ -#define MXC_F_GCR_PERCKCN1_FLCD \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */ -#define MXC_V_GCR_PERCKCN1_FLCD_EN \ - ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_EN \ - (MXC_V_GCR_PERCKCN1_FLCD_EN \ - << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */ -#define MXC_V_GCR_PERCKCN1_FLCD_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_DIS \ - (MXC_V_GCR_PERCKCN1_FLCD_DIS \ - << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */ - -#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ -#define MXC_F_GCR_PERCKCN1_ICACHED \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED \ - Mask */ -#define MXC_V_GCR_PERCKCN1_ICACHED_EN \ - ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */ -#define MXC_S_GCR_PERCKCN1_ICACHED_EN \ - (MXC_V_GCR_PERCKCN1_ICACHED_EN \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting \ - */ -#define MXC_V_GCR_PERCKCN1_ICACHED_DIS \ - ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */ -#define MXC_S_GCR_PERCKCN1_ICACHED_DIS \ - (MXC_V_GCR_PERCKCN1_ICACHED_DIS \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting \ - */ - -/** - * Event Enable Register. - */ -#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ -#define MXC_F_GCR_EVTEN_DMAEVENT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ - -#define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */ -#define MXC_F_GCR_EVTEN_RXEVENT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */ - -/** - * Revision Register. - */ -#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ -#define MXC_F_GCR_REVISION_REVISION \ - ((uint32_t)( \ - 0xFFFFUL \ - << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION \ - Mask */ - -/** - * System Status Interrupt Enable Register. - */ -#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ -#define MXC_F_GCR_SYSSIE_ICEULIE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ -#define MXC_V_GCR_SYSSIE_ICEULIE_DIS \ - ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ - (MXC_V_GCR_SYSSIE_ICEULIE_DIS \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_ICEULIE_EN \ - ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ - (MXC_V_GCR_SYSSIE_ICEULIE_EN \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */ - -#define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ -#define MXC_F_GCR_SYSSIE_CIEIE \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */ -#define MXC_V_GCR_SYSSIE_CIEIE_DIS \ - ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_DIS \ - (MXC_V_GCR_SYSSIE_CIEIE_DIS \ - << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_CIEIE_EN \ - ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_EN \ - (MXC_V_GCR_SYSSIE_CIEIE_EN \ - << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */ - -#define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ -#define MXC_F_GCR_SYSSIE_SCMFIE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */ -#define MXC_V_GCR_SYSSIE_SCMFIE_DIS \ - ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_DIS \ - (MXC_V_GCR_SYSSIE_SCMFIE_DIS \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_SCMFIE_EN \ - ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_EN \ - (MXC_V_GCR_SYSSIE_SCMFIE_EN \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */ - -#endif /* _GCR_REGS_H_ */ diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c deleted file mode 100644 index 1ed7d386ae..0000000000 --- a/chip/max32660/gpio_chip.c +++ /dev/null @@ -1,222 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 GPIO module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "switch.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "registers.h" -#include "gpio_regs.h" - -#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) - -/* 0-terminated list of GPIO base addresses */ -static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0}; - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); - - switch (func) { - case GPIO_ALT_FUNC_1: - gpio->en_clr = mask; - gpio->en1_clr = mask; - break; - case GPIO_ALT_FUNC_2: - gpio->en_clr = mask; - gpio->en1_set = mask; - break; - case GPIO_ALT_FUNC_3: - gpio->en_set = mask; - gpio->en1_set = mask; - break; - default: - /* Default as input */ - gpio->out_en_clr = mask; - gpio->en_set = mask; - gpio->en1_clr = mask; - break; - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port); - - return (gpio->in & gpio_list[signal].mask); -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port); - - if (value) { - gpio->out_set = gpio_list[signal].mask; - } else { - gpio->out_clr = gpio_list[signal].mask; - } -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); - - if (flags & GPIO_OUTPUT) { - gpio->out_en_set = mask; - gpio->en_set = mask; - gpio->en1_clr = mask; - } else { - gpio->out_en_clr = mask; - gpio->en_set = mask; - gpio->en1_clr = mask; - } - - /* Handle pullup / pulldown */ - if (flags & GPIO_PULL_UP) { - gpio->pad_cfg1 |= mask; - gpio->pad_cfg2 &= ~mask; - gpio->ps |= mask; - } else if (flags & GPIO_PULL_DOWN) { - gpio->pad_cfg1 &= ~mask; - gpio->pad_cfg2 |= mask; - gpio->ps &= ~mask; - } else { - /* No pull up/down */ - gpio->pad_cfg1 &= ~mask; - gpio->pad_cfg2 &= ~mask; - gpio->ps &= ~mask; - } - - /* Set gpio as level or edge trigger */ - if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) { - gpio->int_mod &= ~mask; - } else { - gpio->int_mod |= mask; - } - - /* Handle interrupting on both edges */ - if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { - gpio->int_dual_edge |= mask; - } else { - if (flags & GPIO_INT_F_RISING) { - gpio->int_pol |= mask; - gpio->int_dual_edge &= ~mask; - } - if (flags & GPIO_INT_F_FALLING) { - gpio->int_pol &= ~mask; - gpio->int_dual_edge &= ~mask; - } - } - - /* Set level */ - if (flags & GPIO_HIGH) { - gpio->out_set = mask; - } else if (flags & GPIO_LOW) { - gpio->out_clr = mask; - } -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port); - - gpio->int_en_set = gpio_list[signal].mask; - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port); - - gpio->int_en_clr = gpio_list[signal].mask; - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpio_list[signal].port); - - gpio->int_clr = gpio_list[signal].mask; - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - int i; - - /* Mask all GPIO interrupts */ - for (i = 0; gpio_bases[i]; i++) - gpio_bases[i]->int_en = 0; - - /* Set all GPIOs to defaults */ - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* Use as GPIO, not alternate function */ - gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); - - /* Set up GPIO based on flags */ - gpio_set_flags_by_mask(g->port, g->mask, flags); - } -} - -static void gpio_init(void) -{ - /* do nothing */ -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/*****************************************************************************/ -/* Interrupt handlers */ - -/** - * Handle a GPIO interrupt. - * - * port GPIO port - * mis Masked interrupt status value for that port - */ -static void gpio_interrupt(int port, uint32_t mis) -{ - int i = 0; - const struct gpio_info *g = gpio_list; - - for (i = 0; i < GPIO_IH_COUNT && mis; i++, g++) { - if (port == g->port && (mis & g->mask)) { - gpio_irq_handlers[i](i); - mis &= ~g->mask; - } - } -} - -/** - * Handlers for each GPIO port. These read and clear the interrupt bits for - * the port, then call the master handler above. - */ -#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \ - void irqfunc(void) \ - { \ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase); \ - uint32_t mis = gpio->int_stat; \ - gpio->int_clr = mis; \ - gpio_interrupt(gpiobase, mis); \ - } - -GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0); -#undef GPIO_IRQ_FUNC -DECLARE_IRQ(EC_GPIO0_IRQn, __gpio_0_interrupt, 1); diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h deleted file mode 100644 index 1c6fcf7a71..0000000000 --- a/chip/max32660/gpio_regs.h +++ /dev/null @@ -1,866 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the GPIO Peripheral - * Module */ - -#ifndef _GPIO_REGS_H_ -#define _GPIO_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/* **** Definitions **** */ - -/** - * gpio - * Individual I/O for each GPIO - */ - -/** - * gpio_registers - * Structure type to access the GPIO Registers. - */ -typedef struct { - __IO uint32_t en; /**< <tt>\b 0x00:<\tt> GPIO EN Register */ - __IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */ - __IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */ - __IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */ - __IO uint32_t - out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */ - __IO uint32_t - out_en_clr; /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */ - __IO uint32_t out; /**< <tt>\b 0x18:<\tt> GPIO OUT Register */ - __O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */ - __O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */ - __I uint32_t in; /**< <tt>\b 0x24:<\tt> GPIO IN Register */ - __IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */ - __IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */ - __R uint32_t rsv_0x30; - __IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */ - __IO uint32_t - int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */ - __IO uint32_t - int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */ - __I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */ - __R uint32_t rsv_0x44; - __IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */ - __IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */ - __IO uint32_t - wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */ - __IO uint32_t - wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */ - __R uint32_t rsv_0x58; - __IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE - Register */ - __IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */ - __IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */ - __IO uint32_t en1; /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */ - __IO uint32_t en1_set; /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */ - __IO uint32_t en1_clr; /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */ - __IO uint32_t en2; /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */ - __IO uint32_t en2_set; /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */ - __IO uint32_t en2_clr; /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */ - __R uint32_t rsv_0x80_0xa7[10]; - __IO uint32_t is; /**< <tt>\b 0xA8:<\tt> GPIO IS Register */ - __IO uint32_t sr; /**< <tt>\b 0xAC:<\tt> GPIO SR Register */ - __IO uint32_t ds; /**< <tt>\b 0xB0:<\tt> GPIO DS Register */ - __IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */ - __IO uint32_t ps; /**< <tt>\b 0xB8:<\tt> GPIO PS Register */ - __R uint32_t rsv_0xbc; - __IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */ -} mxc_gpio_regs_t; - -#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ -#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ -#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ -#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ -#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ -#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ -#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ -#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ -#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ -#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ -#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ -#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ -#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ -#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */ -#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */ -#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */ -#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */ -#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */ -#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */ -#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */ -#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */ -#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */ -#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */ -#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */ -#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */ -#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */ -#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */ -#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */ -#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */ -#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */ -#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */ -#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */ - -/** - * Enumeration type for the GPIO Function Type - */ -typedef enum { - GPIO_FUNC_IN, /**< GPIO Input */ - GPIO_FUNC_OUT, /**< GPIO Output */ - GPIO_FUNC_ALT1, /**< Alternate Function Selection */ - GPIO_FUNC_ALT2, /**< Alternate Function Selection */ - GPIO_FUNC_ALT3, /**< Alternate Function Selection */ - GPIO_FUNC_ALT4, /**< Alternate Function Selection */ -} gpio_func_t; - -/** - * Enumeration type for the type of GPIO pad on a given pin. - */ -typedef enum { - GPIO_PAD_NONE, /**< No pull-up or pull-down */ - GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ - GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */ -} gpio_pad_t; - -/** - * Structure type for configuring a GPIO port. - */ -typedef struct { - uint32_t port; /**< Index of GPIO port */ - uint32_t mask; /**< Pin mask (multiple pins may be set) */ - gpio_func_t func; /**< Function type */ - gpio_pad_t pad; /**< Pad type */ -} gpio_cfg_t; - -typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t; - -typedef enum { - GPIO_INTERRUPT_FALLING = 0, /**< Interrupt triggers on falling edge */ - GPIO_INTERRUPT_HIGH = GPIO_INTERRUPT_FALLING, /**< Interrupt triggers - when level is high */ - GPIO_INTERRUPT_RISING, /**< Interrupt triggers on rising edge */ - GPIO_INTERRUPT_LOW = GPIO_INTERRUPT_RISING, /**< Interrupt triggers when - level is low */ - GPIO_INTERRUPT_BOTH /**< Interrupt triggers on either edge */ -} gpio_int_pol_t; - -/* Register offsets for module GPIO */ -#define MXC_R_GPIO_EN \ - ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_GPIO_EN_SET \ - ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_GPIO_EN_CLR \ - ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x008 */ -#define MXC_R_GPIO_OUT_EN \ - ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x00C */ -#define MXC_R_GPIO_OUT_EN_SET \ - ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x010 */ -#define MXC_R_GPIO_OUT_EN_CLR \ - ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x014 */ -#define MXC_R_GPIO_OUT \ - ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x018 */ -#define MXC_R_GPIO_OUT_SET \ - ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x01C */ -#define MXC_R_GPIO_OUT_CLR \ - ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x020 */ -#define MXC_R_GPIO_IN \ - ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x024 */ -#define MXC_R_GPIO_INT_MOD \ - ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x028 */ -#define MXC_R_GPIO_INT_POL \ - ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x02C */ -#define MXC_R_GPIO_INT_EN \ - ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x034 */ -#define MXC_R_GPIO_INT_EN_SET \ - ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x038 */ -#define MXC_R_GPIO_INT_EN_CLR \ - ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x03C */ -#define MXC_R_GPIO_INT_STAT \ - ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x040 */ -#define MXC_R_GPIO_INT_CLR \ - ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x048 */ -#define MXC_R_GPIO_WAKE_EN \ - ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x04C */ -#define MXC_R_GPIO_WAKE_EN_SET \ - ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x050 */ -#define MXC_R_GPIO_WAKE_EN_CLR \ - ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x054 */ -#define MXC_R_GPIO_INT_DUAL_EDGE \ - ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x05C */ -#define MXC_R_GPIO_PAD_CFG1 \ - ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x060 */ -#define MXC_R_GPIO_PAD_CFG2 \ - ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x064 */ -#define MXC_R_GPIO_EN1 \ - ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x068 */ -#define MXC_R_GPIO_EN1_SET \ - ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x06C */ -#define MXC_R_GPIO_EN1_CLR \ - ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x070 */ -#define MXC_R_GPIO_EN2 \ - ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x074 */ -#define MXC_R_GPIO_EN2_SET \ - ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x078 */ -#define MXC_R_GPIO_EN2_CLR \ - ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x07C */ -#define MXC_R_GPIO_IS \ - ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0A8 */ -#define MXC_R_GPIO_SR \ - ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0AC */ -#define MXC_R_GPIO_DS \ - ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0B0 */ -#define MXC_R_GPIO_DS1 \ - ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0B4 */ -#define MXC_R_GPIO_PS \ - ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0B8 */ -#define MXC_R_GPIO_VSSEL \ - ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> \ - 0x0x0C0 */ - -/** - * GPIO Function Enable Register. Each bit controls the GPIO_EN - * setting for one GPIO pin on the associated port. - */ -#define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ -#define MXC_F_GPIO_EN_GPIO_EN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ -#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ - ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ -#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ - (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ -#define MXC_V_GPIO_EN_GPIO_EN_GPIO \ - ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ -#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ - (MXC_V_GPIO_EN_GPIO_EN_GPIO \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ - -/** - * GPIO Set Function Enable Register. Writing a 1 to one or more bits - * in this register sets the bits in the same positions in GPIO_EN to 1, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ -#define MXC_F_GPIO_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ - -/** - * GPIO Clear Function Enable Register. Writing a 1 to one or more - * bits in this register clears the bits in the same positions in GPIO_EN to 0, - * without affecting other bits in that register. - */ -#define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ -#define MXC_F_GPIO_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ - -/** - * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN - * setting for one GPIO pin in the associated port. - */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS \ - 0 /**< OUT_EN_GPIO_OUT_EN Position \ - */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \ - Mask */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \ - Setting */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \ - Setting */ - -/** - * GPIO Output Enable Set Function Enable Register. Writing a 1 to one - * or more bits in this register sets the bits in the same positions in - * GPIO_OUT_EN to 1, without affecting other bits in that register. - */ -#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ -#define MXC_F_GPIO_OUT_EN_SET_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ - -/** - * GPIO Output Enable Clear Function Enable Register. Writing a 1 to - * one or more bits in this register clears the bits in the same positions in - * GPIO_OUT_EN to 0, without affecting other bits in that register. - */ -#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ -#define MXC_F_GPIO_OUT_EN_CLR_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ - -/** - * GPIO Output Register. Each bit controls the GPIO_OUT setting for - * one pin in the associated port. This register can be written either - * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. - */ -#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ -#define MXC_F_GPIO_OUT_GPIO_OUT \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ -#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ - ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ - (MXC_V_GPIO_OUT_GPIO_OUT_LOW \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ -#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ - ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ - (MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ - -/** - * GPIO Output Set. Writing a 1 to one or more bits in this register - * sets the bits in the same positions in GPIO_OUT to 1, without affecting other - * bits in that register. - */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \ - 0 /**< OUT_SET_GPIO_OUT_SET Position */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< \ - OUT_SET_GPIO_OUT_SET \ - Mask */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ -#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \ - Setting */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ - ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ -#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET \ - (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET \ - Setting */ -/** - * GPIO Output Clear. Writing a 1 to one or more bits in this register - * clears the bits in the same positions in GPIO_OUT to 0, without affecting - * other bits in that register. - */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \ - 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< \ - OUT_CLR_GPIO_OUT_CLR \ - Mask */ - -/** - * GPIO Input Register. Read-only register to read from the logic - * states of the GPIO pins on this port. - */ -#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ -#define MXC_F_GPIO_IN_GPIO_IN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ - -/** - * GPIO Interrupt Mode Register. Each bit in this register controls - * the interrupt mode setting for the associated GPIO pin on this port. - */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \ - 0 /**< INT_MOD_GPIO_INT_MOD Position */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< \ - INT_MOD_GPIO_INT_MOD \ - Mask */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ - ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ -#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ - (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ - INT_MOD_GPIO_INT_MOD_LEVEL \ - Setting */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ -#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ - INT_MOD_GPIO_INT_MOD_EDGE \ - Setting */ - -/** - * GPIO Interrupt Polarity Register. Each bit in this register - * controls the interrupt polarity setting for one GPIO pin in the associated - * port. - */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \ - 0 /**< INT_POL_GPIO_INT_POL Position */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< \ - INT_POL_GPIO_INT_POL \ - Mask */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ - ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ -#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING \ - (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ - << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< \ - INT_POL_GPIO_INT_POL_FALLING \ - Setting */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ - ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ -#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING \ - (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ - << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< \ - INT_POL_GPIO_INT_POL_RISING \ - Setting */ - -/** - * GPIO Interrupt Enable Register. Each bit in this register controls - * the GPIO interrupt enable for the associated pin on the GPIO port. - */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS \ - 0 /**< INT_EN_GPIO_INT_EN Position \ - */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \ - Mask */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ - ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \ - Setting */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ - ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \ - Setting */ - -/** - * GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this - * register sets the bits in the same positions in GPIO_INT_EN to 1, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \ - 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< \ - INT_EN_SET_GPIO_INT_EN_SET \ - Mask */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ - ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ -#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ - (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ - << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< \ - INT_EN_SET_GPIO_INT_EN_SET_NO \ - Setting */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ - ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ -#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ - (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ - << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< \ - INT_EN_SET_GPIO_INT_EN_SET_SET \ - Setting */ -/** - * GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in - * this register clears the bits in the same positions in GPIO_INT_EN to 0, - * without affecting other bits in that register. - */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \ - 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< \ - INT_EN_CLR_GPIO_INT_EN_CLR \ - Mask */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ - ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ -#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ - (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ - << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< \ - INT_EN_CLR_GPIO_INT_EN_CLR_NO \ - Setting */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ - ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ -#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ - (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ - << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< \ - INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ - Setting */ -/** - * GPIO Interrupt Status Register. Each bit in this register contains - * the pending interrupt status for the associated GPIO pin in this port. - */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \ - 0 /**< INT_STAT_GPIO_INT_STAT Position */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< \ - INT_STAT_GPIO_INT_STAT \ - Mask */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ - ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ -#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO \ - (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ - << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< \ - INT_STAT_GPIO_INT_STAT_NO \ - Setting */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ - ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ -#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ - (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ - << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< \ - INT_STAT_GPIO_INT_STAT_PENDING \ - Setting */ - -/** - * GPIO Status Clear. Writing a 1 to one or more bits in this register - * clears the bits in the same positions in GPIO_INT_STAT to 0, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ -#define MXC_F_GPIO_INT_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ - -/** - * GPIO Wake Enable Register. Each bit in this register controls the - * PMU wakeup enable for the associated GPIO pin in this port. - */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \ - 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< \ - WAKE_EN_GPIO_WAKE_EN \ - Mask */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ - ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ -#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ - (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \ - Setting */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ -#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \ - Setting */ - -/** - * GPIO Wake Enable Set. Writing a 1 to one or more bits in this - * register sets the bits in the same positions in GPIO_WAKE_EN to 1, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \ - Mask */ - -/** - * GPIO Wake Enable Clear. Writing a 1 to one or more bits in this - * register clears the bits in the same positions in GPIO_WAKE_EN to 0, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \ - Mask */ - -/** - * GPIO Interrupt Dual Edge Mode Register. Each bit in this register - * selects dual edge mode for the associated GPIO pin in this port. - */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \ - 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< \ - INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - Mask \ - */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ - ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ -#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ - (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ - << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< \ - INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ - Setting */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ - ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ -#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ - (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ - << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< \ - INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ - Setting */ - -/** - * GPIO Input Mode Config 1. Each bit in this register enables the - * weak pull-up for the associated GPIO pin in this port. - */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \ - 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< \ - PAD_CFG1_GPIO_PAD_CFG1 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ - ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ -#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ - (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ - PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ - Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ - ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ -#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ - (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ - PAD_CFG1_GPIO_PAD_CFG1_PU \ - Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ - ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ -#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ - (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ - PAD_CFG1_GPIO_PAD_CFG1_PD \ - Setting */ - -/** - * GPIO Input Mode Config 2. Each bit in this register enables the - * weak pull-up for the associated GPIO pin in this port. - */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \ - 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< \ - PAD_CFG2_GPIO_PAD_CFG2 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ - ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ -#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ - (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ - PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ - Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ - ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ -#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ - (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ - PAD_CFG2_GPIO_PAD_CFG2_PU \ - Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ - ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ -#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ - (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ - PAD_CFG2_GPIO_PAD_CFG2_PD \ - Setting */ - -/** - * GPIO Alternate Function Enable Register. Each bit in this register - * selects between primary/secondary functions for the associated GPIO pin in - * this port. - */ -#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ -#define MXC_F_GPIO_EN1_GPIO_EN1 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ -#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ - ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ -#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ - ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \ - */ - -/** - * GPIO Alternate Function Set. Writing a 1 to one or more bits in - * this register sets the bits in the same positions in GPIO_EN1 to 1, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ -#define MXC_F_GPIO_EN1_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ - -/** - * GPIO Alternate Function Clear. Writing a 1 to one or more bits in - * this register clears the bits in the same positions in GPIO_EN1 to 0, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ -#define MXC_F_GPIO_EN1_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ - -/** - * GPIO Alternate Function Enable Register. Each bit in this register - * selects between primary/secondary functions for the associated GPIO pin in - * this port. - */ -#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ -#define MXC_F_GPIO_EN2_GPIO_EN2 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ -#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ - ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ -#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ - ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \ - */ - -/** - * GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in - * this register sets the bits in the same positions in GPIO_EN2 to 1, without - * affecting other bits in that register. - */ -#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ -#define MXC_F_GPIO_EN2_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ - -/** - * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits - * in this register clears the bits in the same positions in GPIO_EN2 to 0, - * without affecting other bits in that register. - */ -#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ -#define MXC_F_GPIO_EN2_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ - -/** - * GPIO Drive Strength Register. Each bit in this register selects - * the drive strength for the associated GPIO pin in this port. Refer to the - * Datasheet for sink/source current of GPIO pins in each mode. - */ -#define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ -#define MXC_F_GPIO_DS_DS \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ -#define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ -#define MXC_S_GPIO_DS_DS_LD \ - (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ -#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ -#define MXC_S_GPIO_DS_DS_HD \ - (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ - -/** - * GPIO Drive Strength 1 Register. Each bit in this register selects - * the drive strength for the associated GPIO pin in this port. Refer to the - * Datasheet for sink/source current of GPIO pins in each mode. - */ -#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ -#define MXC_F_GPIO_DS1_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ - -/** - * GPIO Pull Select Mode. - */ -#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ -#define MXC_F_GPIO_PS_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \ - */ - -/** - * GPIO Voltage Select. - */ -#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ -#define MXC_F_GPIO_VSSEL_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ - -#endif /* _GPIO_REGS_H_ */ diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c deleted file mode 100644 index b2f0643e0f..0000000000 --- a/chip/max32660/hwtimer_chip.c +++ /dev/null @@ -1,226 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 HW Timer module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "task.h" -#include "timer.h" -#include "registers.h" -#include "tmr_regs.h" -#include "gcr_regs.h" - -/* Define the rollover timer */ -#define TMR_ROLLOVER MXC_TMR0 -#define TMR_ROLLOVER_IRQ EC_TMR0_IRQn - -/* Define the event timer */ -#define TMR_EVENT MXC_TMR1 -#define TMR_EVENT_IRQ EC_TMR1_IRQn - -#define ROLLOVER_EVENT 1 -#define NOT_ROLLOVER_EVENT 0 - -#define TMR_PRESCALER MXC_V_TMR_CN_PRES_DIV8 -#define TMR_DIV (1 << TMR_PRESCALER) - -/* The frequency of timer using the prescaler */ -#define TIMER_FREQ_HZ (PeripheralClock / TMR_DIV) - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -static uint32_t last_deadline; - -/* brief Timer prescaler values */ -enum tmr_pres { - TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1, /// Divide input clock by 1 - TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2, /// Divide input clock by 2 - TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4, /// Divide input clock by 4 - TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8, /// Divide input clock by 8 - TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16, /// Divide input clock by 16 - TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32, /// Divide input clock by 32 - TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64, /// Divide input clock by 64 - TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128 - TMR_PRES_256 = - (0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256 - TMR_PRES_512 = - (0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512 - TMR_PRES_1024 = - (0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024 - TMR_PRES_2048 = - (0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048 - TMR_PRES_4096 = - (0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096 -}; - -/* Timer modes */ -enum tmr_mode { - TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT - TMR_MODE_CONTINUOUS = - MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode CONTINUOUS - TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER - TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM - TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE - TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE - TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED - TMR_MODE_CAPTURE_COMPARE = - MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE -}; - -/* - * Calculate the number of microseconds for a given timer tick - */ -static inline uint32_t ticks_to_usecs(uint32_t ticks) -{ - return (uint64_t)ticks * SECOND / TIMER_FREQ_HZ; -} - -/* - * Calculate the number of timer ticks for a given microsecond value - */ -static inline uint32_t usecs_to_ticks(uint32_t usecs) -{ - return ((uint64_t)(usecs)*TIMER_FREQ_HZ / SECOND); -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint32_t event_time_us; - uint32_t event_time_ticks; - uint32_t time_now; - - last_deadline = deadline; - time_now = __hw_clock_source_read(); - - /* check if the deadline has rolled over */ - if (deadline < time_now) { - event_time_us = (0xFFFFFFFF - time_now) + deadline; - } else { - /* How long from the current time to the deadline? */ - event_time_us = (deadline - __hw_clock_source_read()); - } - - /* Convert event_time to ticks rounding up */ - event_time_ticks = usecs_to_ticks(event_time_us) + 1; - - /* set the event time into the timer compare */ - TMR_EVENT->cmp = event_time_ticks; - /* zero out the timer */ - TMR_EVENT->cnt = 0; - TMR_EVENT->cn |= MXC_F_TMR_CN_TEN; -} - -uint32_t __hw_clock_event_get(void) -{ - return last_deadline; -} - -void __hw_clock_event_clear(void) -{ - TMR_EVENT->cn &= ~(MXC_F_TMR_CN_TEN); -} - -uint32_t __hw_clock_source_read(void) -{ - uint32_t timer_count_ticks; - - /* Read the timer value and return the results in microseconds */ - timer_count_ticks = TMR_ROLLOVER->cnt; - return ticks_to_usecs(timer_count_ticks); -} - -void __hw_clock_source_set(uint32_t ts) -{ - uint32_t timer_count_ticks; - timer_count_ticks = usecs_to_ticks(ts); - TMR_ROLLOVER->cnt = timer_count_ticks; -} - -/** - * Interrupt handler for Timer - */ -static void __timer_event_isr(void) -{ - /* Clear the event timer */ - TMR_EVENT->intr = MXC_F_TMR_INTR_IRQ_CLR; - /* Process the timer, pass in that this was NOT a rollover event */ - if (TMR_ROLLOVER->intr) { - TMR_ROLLOVER->intr = MXC_F_TMR_INTR_IRQ_CLR; - process_timers(ROLLOVER_EVENT); - } else { - process_timers(NOT_ROLLOVER_EVENT); - } -} -DECLARE_IRQ(EC_TMR1_IRQn, __timer_event_isr, 1); - -static void init_timer(mxc_tmr_regs_t *timer, enum tmr_pres prescaler, - enum tmr_mode mode, uint32_t count) -{ - /* Disable the Timer */ - timer->cn &= ~(MXC_F_TMR_CN_TEN); - - if (timer == MXC_TMR0) { - /* Enable Timer 0 Clock */ - MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T0D); - } else if (timer == MXC_TMR1) { - /* Enable Timer 1 Clock */ - MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T1D); - } else if (timer == MXC_TMR2) { - /* Enable Timer 2 Clock */ - MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_T2D); - } - - /* Disable timer and clear settings */ - timer->cn = 0; - - /* Clear interrupt flag */ - timer->intr = MXC_F_TMR_INTR_IRQ_CLR; - - /* Set the prescaler */ - timer->cn = (prescaler << MXC_F_TMR_CN_PRES_POS); - - /* Configure the timer */ - timer->cn = (timer->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) | - ((mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) | - ((0 << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL); - - timer->cnt = 0x1; - timer->cmp = count; -} - -int __hw_clock_source_init(uint32_t start_t) -{ - /* Initialize two timers, one for the OS Rollover and one for the OS - * Events */ - init_timer(TMR_ROLLOVER, TMR_PRESCALER, TMR_MODE_CONTINUOUS, - 0xffffffff); - init_timer(TMR_EVENT, TMR_PRESCALER, TMR_MODE_COMPARE, 0x0); - __hw_clock_source_set(start_t); - - /* Enable the timers */ - TMR_ROLLOVER->cn |= MXC_F_TMR_CN_TEN; - TMR_EVENT->cn |= MXC_F_TMR_CN_TEN; - - /* Enable the IRQ */ - task_enable_irq(TMR_EVENT_IRQ); - - /* Return the Event timer IRQ number (NOT the Rollover IRQ) */ - return TMR_EVENT_IRQ; -} - -static int hwtimer_display(int argc, char **argv) -{ - CPRINTS(" TMR_EVENT count 0x%08x", TMR_EVENT->cnt); - CPRINTS(" TMR_ROLLOVER count 0x%08x", TMR_ROLLOVER->cnt); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(hwtimer, hwtimer_display, "hwtimer", - "Display hwtimer counts"); diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c deleted file mode 100644 index 18448e16c3..0000000000 --- a/chip/max32660/i2c_chip.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 I2C port module for Chrome EC. */ - -#include <stdint.h> -#include <stddef.h> -#include "common.h" -#include "config_chip.h" -#include "hooks.h" -#include "i2c.h" -#include "system.h" -#include "task.h" -#include "registers.h" -#include "i2c_regs.h" - -/** - * Byte to use if the EC HOST requested more data - * than the I2C Slave is able to send. - */ -#define EC_PADDING_BYTE 0xec - -/* **** Definitions **** */ -#define I2C_ERROR \ - (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \ - MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \ - MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \ - MXC_F_I2C_INT_FL0_STOP_ER) - -#define T_LOW_MIN (160) /* tLOW minimum in nanoseconds */ -#define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */ -#define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */ -#define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */ -#define T_AF_MIN (10) /* tAF minimun in nanoseconds */ - -/** - * typedef i2c_speed_t - I2C speed modes. - * @I2C_STD_MODE: 100KHz bus speed - * @I2C_FAST_MODE: 400KHz Bus Speed - * @I2C_FASTPLUS_MODE: 1MHz Bus Speed - * @I2C_HS_MODE: 3.4MHz Bus Speed - */ -typedef enum { - I2C_STD_MODE = 100000, - I2C_FAST_MODE = 400000, - I2C_FASTPLUS_MODE = 1000000, - I2C_HS_MODE = 3400000 -} i2c_speed_t; - -/** - * typedef i2c_autoflush_disable_t - Enable/Disable TXFIFO Autoflush mode. - */ -typedef enum { - I2C_AUTOFLUSH_ENABLE = 0, - I2C_AUTOFLUSH_DISABLE = 1 -} i2c_autoflush_disable_t; - -/** - * typedef i2c_master_state_t - Available transaction states for I2C Master. - */ -typedef enum { - I2C_MASTER_IDLE = 1, - I2C_MASTER_START = 2, - I2C_MASTER_WRITE_COMPLETE = 3, - I2C_MASTER_READ_COMPLETE = 4 -} i2c_master_state_t; - -/** - * typedef i2c_slave_state_t - Available transaction states for I2C Slave. - */ -typedef enum { - I2C_SLAVE_WRITE_COMPLETE = 0, - I2C_SLAVE_ADDR_MATCH_READ = 1, - I2C_SLAVE_ADDR_MATCH_WRITE = 2, -} i2c_slave_state_t; - -/** - * typedef i2c_req_t - I2C Transaction request. - */ -typedef struct i2c_req i2c_req_t; - -/** - * typedef i2c_req_state_t - Saves the state of the non-blocking requests. - * @req: Pointer to I2C transaction request information. - */ -typedef struct { - i2c_req_t *req; -} i2c_req_state_t; - -/** - * struct i2c_req - I2C Transaction request. - * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0. - * Only supports 7-bit addressing. LSb of the given - * address will be used as the read/write bit, the addr - * will not be shifted. Used for both master and slave - * transactions. - * @addr_match_flag: Indicates which slave address was matched. - * 0x1 indicates first slave address matched. - * 0x2 indicates second slave address matched. - * 0x4 indicates third slave address matched. - * 0x8 indicates fourth slave address matched. - * @tx_data: Data for master write/slave read. - * @rx_data: Data for master read/slave write. - * @received_count: Number of rx bytes sent. - * @tx_remain: Number of bytes to transmit to the master. This - * value is -1 if should clock stretch, 0 if start - * sending EC_PADDING_BYTE. Any other values in this - * field will transmit data to the Master. - * @restart: Restart or stop bit indicator. - * 0 to send a stop bit at the end of the transaction - * Non-zero to send a restart at end of the transaction - * Only used for Master transactions. - * @callback: Callback for asynchronous request. - * First argument is to the transaction request. - * Second argument is the error code. - */ -struct i2c_req { - uint8_t addr; - uint8_t addr_match_flag; - const uint8_t *tx_data; - uint8_t *rx_data; - volatile unsigned received_count; - volatile int tx_remain; - volatile i2c_slave_state_t state; - volatile int restart; -}; - -static i2c_req_state_t states[MXC_I2C_INSTANCES]; - -/** - * struct i2c_port_data - * @out: Output data pointer. - * @out_size: Output data to transfer, in bytes. - * @in: Input data pointer. - * @in_size: Input data to transfer, in bytes. - * @flags: Flags (I2C_XFER_*). - * @idx: Index into input/output data. - * @err: Error code, if any. - * @timeout_us: Transaction timeout, or 0 to use default. - * @task_waiting: Task waiting on port, or TASK_ID_INVALID if none. - */ -struct i2c_port_data { - const uint8_t *out; - int out_size; - uint8_t *in; - int in_size; - int flags; - int idx; - int err; - uint32_t timeout_us; - volatile int task_waiting; -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -/* **** Function Prototypes **** */ -static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed); -static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, const uint8_t *data, int len, - int restart); -static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, uint8_t *data, int len, int restart); - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -static void init_i2cs(int port); -static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req); -static void i2c_slave_handler(mxc_i2c_regs_t *i2c); -#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */ - -/* Port address for each I2C */ -static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1}; - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS -static void i2c_send_board_response(int len); -static void i2c_process_board_command(int read, int addr, int len); -void board_i2c_process(int read, uint8_t addr, int len, char *buffer, - void (*send_response)(int len)); -#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */ -#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */ - -/** - * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes. - * @port: Port to access - * @slave_addr: Slave device address - * @out: Data to send - * @out_size: Number of bytes to send - * @in: Destination buffer for received data - * @in_size: Number of bytes to receive - * @flags: Flags (see I2C_XFER_* above) - * - * Chip-level function to transmit one block of raw data, then receive one - * block of raw data. - * - * This is a low-level chip-dependent function and should only be called by - * i2c_xfer().\ - * - * Return EC_SUCCESS, or non-zero if error. - */ -int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out, - int out_size, uint8_t *in, int in_size, int flags) -{ - int xfer_start; - int xfer_stop; - int status; - - xfer_start = flags & I2C_XFER_START; - xfer_stop = flags & I2C_XFER_STOP; - - if (out_size) { - status = i2c_master_write(i2c_bus_ports[port], slave_addr_flags, - xfer_start, xfer_stop, out, out_size, - 1); - if (status != EC_SUCCESS) { - return status; - } - } - if (in_size) { - status = i2c_master_read(i2c_bus_ports[port], slave_addr_flags, - xfer_start, xfer_stop, in, in_size, 0); - if (status != EC_SUCCESS) { - return status; - } - } - return EC_SUCCESS; -} - -/** - * i2c_get_line_levels() - Read the current digital levels on the I2C pins. - * @port: Port number to use when reading line levels. - * - * Return a byte where bit 0 is the line level of SCL and - * bit 1 is the line level of SDA. - */ -int i2c_get_line_levels(int port) -{ - /* Retrieve the current levels of SCL and SDA from the control reg. */ - return (i2c_bus_ports[port]->ctrl >> MXC_F_I2C_CTRL_SCL_POS) & 0x03; -} - -/** - * i2c_set_timeout() - * @port: Port number to set timeout for. - * @timeout: Timeout duration in microseconds. - */ -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; -} - -/** - * i2c_init() - Initialize the I2C ports used on device. - */ -void i2c_init(void) -{ - int i; - int port; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Initialize all I2C ports used. */ - for (i = 0; i < i2c_ports_used; i++) { - port = i2c_ports[i].port; - i2c_init_peripheral(i2c_bus_ports[port], - i2c_ports[i].kbps * 1000); - i2c_set_timeout(i, 0); - } - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - /* Initialize the I2C Slave */ - init_i2cs(I2C_PORT_EC); -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - /* - * Set the secondary I2C slave address for the board. - */ - /* Index the secondary slave address. */ - i2c_bus_ports[I2C_PORT_EC]->slave_addr = - (i2c_bus_ports[I2C_PORT_EC]->slave_addr & - ~(MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX | - MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS)) | - (1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS); - /* Set the secondary slave address. */ - i2c_bus_ports[I2C_PORT_EC]->slave_addr = - (1 << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS) | - CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS; -#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */ -#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */ - -} - -/** - * I2C Slave Implentation - */ -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -/* IRQ for each I2C */ -static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn}; - -/** - * Buffer for received host command packets (including prefix byte on request, - * and result/size on response). After any protocol-specific headers, the - * buffers must be 32-bit aligned. - */ -static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + - CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t *const host_buffer = host_buffer_padded + 2; -static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); -static struct host_packet i2c_packet; - -static i2c_req_t req_slave; -volatile int ec_pending_response = 0; - -/** - * i2c_send_response_packet() - Send the response packet to get processed. - * @pkt: Packet to send. - */ -static void i2c_send_response_packet(struct host_packet *pkt) -{ - int size = pkt->response_size; - uint8_t *out = host_buffer; - - /* Ignore host command in-progress. */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result and size to first two bytes. */ - *out++ = pkt->driver_result; - *out++ = size; - - /* Host_buffer data range. */ - req_slave.tx_remain = size + 2; - - /* Call the handler to send the response packet. */ - i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]); -} - -/** - * i2c_process_command() - Process the command in the i2c host buffer. - */ -static void i2c_process_command(void) -{ - char *buff = host_buffer; - - i2c_packet.send_response = i2c_send_response_packet; - i2c_packet.request = (const void *)(&buff[1]); - i2c_packet.request_temp = params_copy; - i2c_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer. */ - i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; - - /* - * Stuff response at buff[2] to leave the first two bytes of - * buffer available for the result and size to send over i2c. Note - * that this 2-byte offset and the 2-byte offset from host_buffer - * add up to make the response buffer 32-bit aligned. - */ - i2c_packet.response = (void *)(&buff[2]); - i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; - i2c_packet.response_size = 0; - - if (*buff >= EC_COMMAND_PROTOCOL_3) { - i2c_packet.driver_result = EC_RES_SUCCESS; - } else { - /* Only host command protocol 3 is supported. */ - i2c_packet.driver_result = EC_RES_INVALID_HEADER; - } - - host_packet_receive(&i2c_packet); -} - -/** - * i2c_slave_service() - Called by the I2C slave interrupt controller. - * @req: Request currently being processed. - */ -void i2c_slave_service(i2c_req_t *req) -{ - /* Check if there was a host command (I2C master write). */ - if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) { - req->state = I2C_SLAVE_WRITE_COMPLETE; - -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - if (req->addr_match_flag != 0x1) { - i2c_process_board_command( - 1, CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS, - req->received_count); - } else -#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */ - i2c_process_command(); - } -} - -/** - * I2C0_IRQHandler() - Async Handler for I2C Slave driver. - */ -void I2C0_IRQHandler(void) -{ - i2c_slave_handler(i2c_bus_ports[0]); -} - -/** - * I2C1_IRQHandler() - Async Handler for I2C Slave driver. - */ -void I2C1_IRQHandler(void) -{ - i2c_slave_handler(i2c_bus_ports[1]); -} - -DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1); -DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1); - -/** - * i2c_slave_service_read() - Services the Master I2C read from the slave. - * @i2c: I2C peripheral pointer. - * @req: Pointer to the request info. - */ -static void i2c_slave_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req) -{ - /* Clear the RX Threshold interrupt if set. */ - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - /* Clear the TX Threshold interrupt if set. */ - if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_THRESH) { - i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_THRESH; - } - /** - * If there is nothing to transmit to the EC HOST, then default - * to clock stretching. - */ - if (req->tx_remain < 0) { - return; - } - /* If there is data to send to the Master then fill the TX FIFO. */ - if (req->tx_remain != 0) { - /* Fill the FIFO with data to transimit to the I2C Master. */ - while ((req->tx_remain > 0) && - !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { - i2c->fifo = *(req->tx_data)++; - req->tx_remain--; - } - } - /* - * If we have sent everything to the Master that we can, - * then send padding byte. - */ - if (req->tx_remain == 0) { - /* Fill the FIFO with the EC padding byte. */ - while (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { - i2c->fifo = EC_PADDING_BYTE; - } - } - /* Set the threshold for TX, the threshold is a four bit field. */ - i2c->tx_ctrl1 = ((i2c->tx_ctrl1 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | - (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); - /* Enable TX Threshold, Done and Error interrupts. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR; -} - -/** - * i2c_slave_service_write() - Services the Master I2C write to the slave. - * @i2c: I2C peripheral pointer. - * @req: Pointer to the request info. - */ -static void i2c_slave_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req) -{ - /* Clear the RX Threshold interrupt if set. */ - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - /* Read out any data in the RX FIFO. */ - while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { - *(req->rx_data)++ = i2c->fifo; - req->received_count++; - } - /* Set the RX threshold interrupt level. */ - i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & - ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | - (MXC_I2C_FIFO_DEPTH - 1) - << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); - /* Enable RXTH interrupt and Error interrupts. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE | I2C_ERROR; -} - -/** - * i2c_slave_handler() - I2C interrupt handler. - * @i2c: Base address of the I2C module. - * - * This function should be called by the application from the interrupt - * handler if I2C interrupts are enabled. Alternately, this function - * can be periodically called by the application if I2C interrupts are - * disabled. - */ -static void i2c_slave_handler(mxc_i2c_regs_t *i2c) -{ - i2c_req_t *req; - - /* Get the request context for this interrupt. */ - req = states[MXC_I2C_GET_IDX(i2c)].req; - - /* Check for DONE interrupt. */ - if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) { - /* Clear all interrupts except a possible address match. */ - i2c->int_fl0 = i2c->int_fl0 & ~MXC_F_I2C_INT_FL0_ADDR_MATCH; - i2c->int_fl1 = i2c->int_fl1; - - /* Disable all interrupts except address match. */ - i2c->int_en1 = 0; - i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH; - - if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) { - /* Read out any data in the RX FIFO. */ - while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { - *(req->rx_data)++ = i2c->fifo; - req->received_count++; - } - } - /* Manually clear the TXFIFO. */ - i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; - - /* Process the Master write that just finished. */ - i2c_slave_service(req); - - /* No longer inhibit deep sleep after done. */ - enable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* Check for an address match. */ - if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH) { - /* - * Save the address match index to identify - * targeted slave address. - */ - req->addr_match_flag = - (i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >> - MXC_F_I2C_INT_FL0_MAMI_POS; - - /* Check if Master is writing to the slave. */ - if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) { - /* I2C Master is writing to the slave. */ - req->rx_data = host_buffer; - req->tx_data = host_buffer; - req->tx_remain = -1; /* Nothing to send yet. */ - /* Clear the RX (receive from I2C Master) byte counter. */ - req->received_count = 0; - req->state = I2C_SLAVE_ADDR_MATCH_WRITE; - } else { - /* The Master is reading from the slave. */ - /* Start transmitting to the Master from the start of buffer. */ - req->tx_data = host_buffer; - req->state = I2C_SLAVE_ADDR_MATCH_READ; - } - - /* Clear all interrupt flags. */ - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - - /* Respond to the DONE interrupt. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE; - /* Inhibit sleep mode when addressed until STOPF flag is set. */ - disable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - if (i2c->int_fl0 & I2C_ERROR) { - /* Clear the error interrupt. */ - i2c->int_fl0 = I2C_ERROR; - i2c->int_en0 = 0; - /* Manually clear the TXFIFO. */ - i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; - /* Disable and clear interrupts. */ - i2c->int_en0 = 0; - i2c->int_en1 = 0; - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - /* Cycle the I2C peripheral enable on error. */ - i2c->ctrl = 0; - i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; - return; - } - - /* Check for an I2C Master Read or Write. */ - if (req->state == I2C_SLAVE_ADDR_MATCH_READ) { - /* Service a read request from the I2C Master. */ - i2c_slave_service_read(i2c, req); - return; - } - if (req->state == I2C_SLAVE_ADDR_MATCH_WRITE) { - /* Service a write request from the I2C Master. */ - i2c_slave_service_write(i2c, req); - return; - } -} - -/** - * init_i2cs() - Async Handler for I2C Slave driver. - * @port: I2C port number to initialize. - */ -void init_i2cs(int port) -{ - int error; - - error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE); - if (error != EC_SUCCESS) { - while (1) - ; - } - /* Prepare for interrupt driven slave requests. */ - req_slave.addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS; - req_slave.tx_data = host_buffer; /* Transmitted to host. */ - req_slave.tx_remain = -1; - req_slave.rx_data = host_buffer; /* Received from host. */ - req_slave.restart = 0; - states[port].req = &req_slave; - error = i2c_slave_async(i2c_bus_ports[port], &req_slave); - if (error != EC_SUCCESS) { - while (1) - ; - } - - task_enable_irq(i2c_bus_irqs[port]); -} - -/** - * i2c_slave_async() - Slave Read and Write Asynchronous. - * @i2c: Pointer to I2C regs. - * @req: Request for an I2C transaction. - * - * Return EC_SUCCESS if successful, otherwise returns a common error code. - */ -static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req) -{ - /* Make sure the I2C has been initialized. */ - if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) - return EC_ERROR_UNKNOWN; - /* Disable master mode. */ - i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST); - /* Set the Slave Address in the I2C peripheral register. */ - i2c->slave_addr = req->addr; - /* Clear the receive count from the I2C Master. */ - req->received_count = 0; - /* Disable and clear the interrupts. */ - i2c->int_en0 = 0; - i2c->int_en1 = 0; - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - /* Only enable the I2C Address match interrupt. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH; - - return EC_SUCCESS; -} - -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - -static void i2c_send_board_response(int len) -{ - /* Set the number of bytes to send to the I2C master. */ - req_slave.tx_remain = len; - - /* Call the handler for transmition of response packet. */ - i2c_slave_handler(i2c_bus_ports[I2C_PORT_EC]); -} - - -static void i2c_process_board_command(int read, int addr, int len) -{ - board_i2c_process(read, addr, len, &host_buffer[0], - i2c_send_board_response); -} -#endif /* CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS */ -#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */ - -/** - * i2c_set_speed() - Set the transfer speed of the selected I2C. - * @i2c: Pointer to I2C peripheral. - * @i2cspeed: Speed to set. - * - * Return EC_SUCCESS, or non-zero if error. - */ -static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed) -{ - uint32_t ticks; - uint32_t ticks_lo; - uint32_t ticks_hi; - uint32_t time_pclk; - uint32_t target_bus_freq; - uint32_t time_scl_min; - uint32_t clock_low_min; - uint32_t clock_high_min; - uint32_t clock_min; - - if (i2cspeed == I2C_HS_MODE) { - /* Compute dividers for high speed mode. */ - time_pclk = 1000000 / (PeripheralClock / 1000); - - target_bus_freq = i2cspeed; - if (target_bus_freq < 1000) { - return EC_ERROR_INVAL; - } - - time_scl_min = 1000000 / (target_bus_freq / 1000); - clock_low_min = - ((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) / - time_pclk) - 1; - clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) - - T_AF_MIN) / - time_pclk) - 1; - clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2; - - ticks_lo = (clock_low_min > (clock_min - clock_high_min)) - ? (clock_low_min) - : (clock_min - clock_high_min); - ticks_hi = clock_high_min; - - if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >> - MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) || - (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >> - MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) { - return EC_ERROR_INVAL; - } - - /* Write results to destination registers. */ - i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) | - (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS); - - /* Still need to load dividers for the preamble that each - * high-speed transaction starts with. Switch setting to fast - * mode and fall out of if statement. - */ - i2cspeed = I2C_FAST_MODE; - } - - /* Get the number of periph clocks needed to achieve selected speed. */ - ticks = PeripheralClock / i2cspeed; - - /* For a 50% duty cycle, half the ticks will be spent high and half will - * be low. - */ - ticks_hi = (ticks >> 1) - 1; - ticks_lo = (ticks >> 1) - 1; - - /* Account for rounding error in odd tick counts. */ - if (ticks & 1) { - ticks_hi++; - } - - /* Will results fit into 9 bit registers? (ticks_hi will always be >= - * ticks_lo. No need to check ticks_lo.) - */ - if (ticks_hi > 0x1FF) { - return EC_ERROR_INVAL; - } - - /* 0 is an invalid value for the destination registers. (ticks_hi will - * always be >= ticks_lo. No need to check ticks_hi.) - */ - if (ticks_lo == 0) { - return EC_ERROR_INVAL; - } - - /* Write results to destination registers. */ - i2c->clk_lo = ticks_lo; - i2c->clk_hi = ticks_hi; - - return EC_SUCCESS; -} - -/** - * i2c_init_peripheral() - Initialize and enable I2C. - * @i2c: Pointer to I2C peripheral registers. - * @i2cspeed: Desired speed (I2C mode). - * @sys_cfg: System configuration object. - * - * Return EC_SUCCESS, or non-zero if error. - */ -static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed) -{ - /** - * Always disable the HW autoflush on data NACK and let the SW handle - * the flushing. - */ - i2c->tx_ctrl0 |= 0x20; - - i2c->ctrl = 0; /* Clear configuration bits. */ - i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */ - i2c->master_ctrl = 0; /* Clear master configuration bits. */ - i2c->status = 0; /* Clear status bits. */ - - i2c->ctrl = 0; /* Clear configuration bits. */ - i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C. */ - i2c->master_ctrl = 0; /* Clear master configuration bits. */ - i2c->status = 0; /* Clear status bits. */ - - /* Check for HS mode. */ - if (i2cspeed == I2C_HS_MODE) { - i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode. */ - } - - /* Disable and clear interrupts. */ - i2c->int_en0 = 0; - i2c->int_en1 = 0; - i2c->int_fl0 = i2c->int_fl0; - i2c->int_fl1 = i2c->int_fl1; - - i2c->timeout = 0x0; /* Set timeout. */ - i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* Clear the RX FIFO. */ - i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* Clear the TX FIFO. */ - - return i2c_set_speed(i2c, i2cspeed); -} - -/** - * i2c_master_write() - * @i2c: Pointer to I2C regs. - * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1. - * Only supports 7-bit addressing. LSb of the given address - * will be used as the read/write bit, the \p addr <b>will - * not be shifted. Used for both master and - * slave transactions. - * @data: Data to be written. - * @len: Number of bytes to Write. - * @restart: 0 to send a stop bit at the end of the transaction, - * otherwise send a restart. - * - * Will block until transaction is complete. - * - * Return EC_SUCCESS, or non-zero if error. - */ -static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, const uint8_t *data, int len, int restart) -{ - if (len == 0) { - return EC_SUCCESS; - } - - /* Clear the interrupt flag. */ - i2c->int_fl0 = i2c->int_fl0; - - /* Make sure the I2C has been initialized. */ - if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { - return EC_ERROR_UNKNOWN; - } - - /* Enable master mode. */ - i2c->ctrl |= MXC_F_I2C_CTRL_MST; - - /* Load FIFO with slave address for WRITE and as much data as we can. */ - while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) { - } - - if (start) { - /** - * The slave address is right-aligned, bits 6 to 0, shift - * to the left and make room for the write bit. - */ - i2c->fifo = (addr << 1) & ~(0x1); - } - - while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { - i2c->fifo = *data++; - len--; - } - /* Generate Start signal. */ - if (start) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; - } - - /* Write remaining data to FIFO. */ - while (len > 0) { - /* Check for errors. */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit. */ - i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - - if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { - i2c->fifo = *data++; - len--; - } - } - /* Check if Repeated Start requested. */ - if (restart) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; - } else { - if (stop) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - } - } - - if (stop) { - /* Wait for Done. */ - while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) { - /* Check for errors */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit */ - i2c->master_ctrl &= - ~(MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - } - /* Clear Done interrupt flag. */ - i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE; - } - - /* Wait for Stop if requested and there is no restart. */ - if (stop && !restart) { - while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) { - /* Check for errors */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit */ - i2c->master_ctrl &= - ~(MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - } - /* Clear stop interrupt flag. */ - i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP; - } - - /* Check for errors. */ - if (i2c->int_fl0 & I2C_ERROR) { - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/** - * i2c_master_read() - * @i2c: Pointer to I2C regs. - * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0. - * @data: Data to be written. - * @len: Number of bytes to Write. - * @restart: 0 to send a stop bit at the end of the transaction, - * otherwise send a restart. - * - * Will block until transaction is complete. - * - * Return: EC_SUCCESS if successful, otherwise returns a common error code - */ -static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, uint8_t *data, int len, int restart) -{ - volatile int length = len; - int interactive_receive_mode; - - if (len == 0) { - return EC_SUCCESS; - } - - if (len > 255) { - return EC_ERROR_INVAL; - } - - /* Clear the interrupt flag. */ - i2c->int_fl0 = i2c->int_fl0; - - /* Make sure the I2C has been initialized. */ - if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { - return EC_ERROR_UNKNOWN; - } - - /* Enable master mode. */ - i2c->ctrl |= MXC_F_I2C_CTRL_MST; - - if (stop) { - /* Set receive count. */ - i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE; - i2c->rx_ctrl1 = len; - interactive_receive_mode = 0; - } else { - i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE; - i2c->rx_ctrl1 = 1; - interactive_receive_mode = 1; - } - - /* Load FIFO with slave address. */ - if (start) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; - while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) { - } - /** - * The slave address is right-aligned, bits 6 to 0, shift - * to the left and make room for the read bit. - */ - i2c->fifo = ((addr << 1) | 1); - } - - /* Wait for all data to be received or error. */ - while (length > 0) { - /* Check for errors */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit. */ - i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - - /* If in interactive receive mode then ack each received byte. */ - if (interactive_receive_mode) { - while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE)) - ; - if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) { - /* Read the data. */ - *data++ = i2c->fifo; - length--; - /* Clear the bit. */ - if (length != 1) { - i2c->int_fl0 = - MXC_F_I2C_INT_EN0_RX_MODE; - } - } - } else { - if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { - *data++ = i2c->fifo; - length--; - } - } - } - - if (restart) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; - } else { - if (stop) { - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - } - } - - /* Wait for Done. */ - if (stop) { - while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) { - /* Check for errors. */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit. */ - i2c->master_ctrl &= - ~(MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - } - /* Clear Done interrupt flag. */ - i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE; - } - - /* Wait for Stop. */ - if (!restart) { - if (stop) { - while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) { - /* Check for errors. */ - if (i2c->int_fl0 & I2C_ERROR) { - /* Set the stop bit. */ - i2c->master_ctrl &= ~( - MXC_F_I2C_MASTER_CTRL_RESTART); - i2c->master_ctrl |= - MXC_F_I2C_MASTER_CTRL_STOP; - return EC_ERROR_UNKNOWN; - } - } - /* Clear Stop interrupt flag. */ - i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP; - } - } - - /* Check for errors. */ - if (i2c->int_fl0 & I2C_ERROR) { - return EC_ERROR_UNKNOWN; - } - return EC_SUCCESS; -} diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h deleted file mode 100644 index 8cd2fd8868..0000000000 --- a/chip/max32660/i2c_regs.h +++ /dev/null @@ -1,1627 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the I2C Peripheral */ - -#ifndef _I2C_REGS_H_ -#define _I2C_REGS_H_ - -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/** - * Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. - */ - -/** - * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ - __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ - __IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */ - __IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */ - __IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */ - __IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */ - __IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */ - __IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */ - __IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */ - __IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */ - __IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */ - __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ - __IO uint32_t - master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */ - __IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */ - __IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */ - __IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */ - __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ - __IO uint32_t - slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */ - __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ -} mxc_i2c_regs_t; - -/* Register offsets for module I2C */ -/** - * I2C Peripheral Register Offsets from the I2C Base Peripheral Address. - */ -#define MXC_R_I2C_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> \ - 0x0000</tt> */ -#define MXC_R_I2C_STATUS \ - ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> \ - 0x0004</tt> */ -#define MXC_R_I2C_INT_FL0 \ - ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> \ - 0x0008</tt> */ -#define MXC_R_I2C_INT_EN0 \ - ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> \ - 0x000C</tt> */ -#define MXC_R_I2C_INT_FL1 \ - ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> \ - 0x0010</tt> */ -#define MXC_R_I2C_INT_EN1 \ - ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> \ - 0x0014</tt> */ -#define MXC_R_I2C_FIFO_LEN \ - ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> \ - 0x0018</tt> */ -#define MXC_R_I2C_RX_CTRL0 \ - ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> \ - 0x001C</tt> */ -#define MXC_R_I2C_RX_CTRL1 \ - ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> \ - 0x0020</tt> */ -#define MXC_R_I2C_TX_CTRL0 \ - ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> \ - 0x0024</tt> */ -#define MXC_R_I2C_TX_CTRL1 \ - ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> \ - 0x0028</tt> */ -#define MXC_R_I2C_FIFO \ - ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> \ - 0x002C</tt> */ -#define MXC_R_I2C_MASTER_CTRL \ - ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> \ - 0x0030</tt> */ -#define MXC_R_I2C_CLK_LO \ - ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> \ - 0x0034</tt> */ -#define MXC_R_I2C_CLK_HI \ - ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> \ - 0x0038</tt> */ -#define MXC_R_I2C_HS_CLK \ - ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> \ - 0x003C</tt> */ -#define MXC_R_I2C_TIMEOUT \ - ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> \ - 0x0040</tt> */ -#define MXC_R_I2C_SLAVE_ADDR \ - ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> \ - 0x0044</tt> */ -#define MXC_R_I2C_DMA \ - ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> \ - 0x0048</tt> */ - -/** - * Control Register0. - */ -#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ -#define MXC_F_I2C_CTRL_I2C_EN \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ -#define MXC_V_I2C_CTRL_I2C_EN_DIS \ - ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */ -#define MXC_S_I2C_CTRL_I2C_EN_DIS \ - (MXC_V_I2C_CTRL_I2C_EN_DIS \ - << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */ -#define MXC_V_I2C_CTRL_I2C_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value \ - */ -#define MXC_S_I2C_CTRL_I2C_EN_EN \ - (MXC_V_I2C_CTRL_I2C_EN_EN \ - << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */ - -#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ -#define MXC_F_I2C_CTRL_MST \ - ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ -#define MXC_V_I2C_CTRL_MST_SLAVE_MODE \ - ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */ -#define MXC_S_I2C_CTRL_MST_SLAVE_MODE \ - (MXC_V_I2C_CTRL_MST_SLAVE_MODE \ - << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */ -#define MXC_V_I2C_CTRL_MST_MASTER_MODE \ - ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */ -#define MXC_S_I2C_CTRL_MST_MASTER_MODE \ - (MXC_V_I2C_CTRL_MST_MASTER_MODE \ - << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */ - -#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ -#define MXC_F_I2C_CTRL_GEN_CALL_ADDR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR \ - Mask */ -#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \ - ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */ -#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS \ - (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \ - << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS \ - Setting */ -#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \ - ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */ -#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN \ - (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \ - << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN \ - Setting */ - -#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ -#define MXC_F_I2C_CTRL_RX_MODE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ -#define MXC_V_I2C_CTRL_RX_MODE_DIS \ - ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */ -#define MXC_S_I2C_CTRL_RX_MODE_DIS \ - (MXC_V_I2C_CTRL_RX_MODE_DIS \ - << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */ -#define MXC_V_I2C_CTRL_RX_MODE_EN \ - ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */ -#define MXC_S_I2C_CTRL_RX_MODE_EN \ - (MXC_V_I2C_CTRL_RX_MODE_EN \ - << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */ - -#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ -#define MXC_F_I2C_CTRL_RX_MODE_ACK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK \ - Mask */ -#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \ - ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */ -#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK \ - (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \ - << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting \ - */ -#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \ - ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */ -#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK \ - (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \ - << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting \ - */ - -#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ -#define MXC_F_I2C_CTRL_SCL_OUT \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ -#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \ - ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */ -#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \ - (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \ - << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW \ - Setting */ -#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \ - ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */ -#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL \ - (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \ - << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting \ - */ - -#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ -#define MXC_F_I2C_CTRL_SDA_OUT \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ -#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \ - ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */ -#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \ - (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \ - << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW \ - Setting */ -#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \ - ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */ -#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA \ - (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \ - << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting \ - */ - -#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ -#define MXC_F_I2C_CTRL_SCL \ - ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - -#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ -#define MXC_F_I2C_CTRL_SDA \ - ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - -#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ -#define MXC_F_I2C_CTRL_SW_OUT_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ -#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \ - ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */ -#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \ - (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \ - << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE \ - Setting */ -#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \ - ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */ -#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \ - (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \ - << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE \ - Setting */ - -#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ -#define MXC_F_I2C_CTRL_READ \ - ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ -#define MXC_V_I2C_CTRL_READ_WRITE \ - ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */ -#define MXC_S_I2C_CTRL_READ_WRITE \ - (MXC_V_I2C_CTRL_READ_WRITE \ - << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */ -#define MXC_V_I2C_CTRL_READ_READ \ - ((uint32_t)0x1UL) /**< CTRL_READ_READ Value \ - */ -#define MXC_S_I2C_CTRL_READ_READ \ - (MXC_V_I2C_CTRL_READ_READ \ - << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */ - -#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS \ - 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */ -#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< \ - CTRL_SCL_CLK_STRECH_DIS \ - Mask */ -#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \ - ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */ -#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \ - (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \ - << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< \ - CTRL_SCL_CLK_STRECH_DIS_EN \ - Setting */ -#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \ - ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */ -#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \ - (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \ - << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< \ - CTRL_SCL_CLK_STRECH_DIS_DIS \ - Setting */ - -#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ -#define MXC_F_I2C_CTRL_SCL_PP_MODE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE \ - Mask */ -#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \ - ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */ -#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS \ - (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \ - << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting \ - */ -#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN \ - ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */ -#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN \ - (MXC_V_I2C_CTRL_SCL_PP_MODE_EN \ - << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting \ - */ - -#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */ -#define MXC_F_I2C_CTRL_HS_MODE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */ -#define MXC_V_I2C_CTRL_HS_MODE_DIS \ - ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */ -#define MXC_S_I2C_CTRL_HS_MODE_DIS \ - (MXC_V_I2C_CTRL_HS_MODE_DIS \ - << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */ -#define MXC_V_I2C_CTRL_HS_MODE_EN \ - ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */ -#define MXC_S_I2C_CTRL_HS_MODE_EN \ - (MXC_V_I2C_CTRL_HS_MODE_EN \ - << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */ - -/** - * I2C_STATUS I2C_STATUS - */ -#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ -#define MXC_F_I2C_STATUS_BUS \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask \ - */ -#define MXC_V_I2C_STATUS_BUS_IDLE \ - ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */ -#define MXC_S_I2C_STATUS_BUS_IDLE \ - (MXC_V_I2C_STATUS_BUS_IDLE \ - << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */ -#define MXC_V_I2C_STATUS_BUS_BUSY \ - ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */ -#define MXC_S_I2C_STATUS_BUS_BUSY \ - (MXC_V_I2C_STATUS_BUS_BUSY \ - << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */ - -#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ -#define MXC_F_I2C_STATUS_RX_EMPTY \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \ - Mask */ -#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \ - ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */ -#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY \ - (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \ - << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY \ - Setting */ -#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \ - ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */ -#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY \ - (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \ - << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting \ - */ - -#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ -#define MXC_F_I2C_STATUS_RX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ -#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \ - ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */ -#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL \ - (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \ - << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting \ - */ -#define MXC_V_I2C_STATUS_RX_FULL_FULL \ - ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */ -#define MXC_S_I2C_STATUS_RX_FULL_FULL \ - (MXC_V_I2C_STATUS_RX_FULL_FULL \ - << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */ - -#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ -#define MXC_F_I2C_STATUS_TX_EMPTY \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \ - Mask */ -#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \ - ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */ -#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY \ - (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \ - << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY \ - Setting */ -#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \ - ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */ -#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY \ - (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \ - << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting \ - */ - -#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ -#define MXC_F_I2C_STATUS_TX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ -#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \ - ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */ -#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY \ - (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \ - << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY \ - Setting */ -#define MXC_V_I2C_STATUS_TX_FULL_EMPTY \ - ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */ -#define MXC_S_I2C_STATUS_TX_FULL_EMPTY \ - (MXC_V_I2C_STATUS_TX_FULL_EMPTY \ - << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */ - -#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ -#define MXC_F_I2C_STATUS_CLK_MODE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE \ - Mask */ -#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \ - ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \ - Value */ -#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \ - (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \ - << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< \ - STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \ - Setting */ -#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \ - ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \ - Value */ -#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \ - (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \ - << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< \ - STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \ - Setting */ - -#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */ -#define MXC_F_I2C_STATUS_STATUS \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ -#define MXC_V_I2C_STATUS_STATUS_IDLE \ - ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */ -#define MXC_S_I2C_STATUS_STATUS_IDLE \ - (MXC_V_I2C_STATUS_STATUS_IDLE \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */ -#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR \ - ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */ -#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR \ - (MXC_V_I2C_STATUS_STATUS_MTX_ADDR \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting \ - */ -#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \ - ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */ -#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK \ - (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \ - ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */ -#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR \ - (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \ - ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */ -#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR \ - (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR \ - ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */ -#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR \ - (MXC_V_I2C_STATUS_STATUS_SRX_ADDR \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting \ - */ -#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \ - ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */ -#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK \ - (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \ - ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */ -#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR \ - (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \ - ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */ -#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \ - (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK \ - Setting */ -#define MXC_V_I2C_STATUS_STATUS_TX \ - ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */ -#define MXC_S_I2C_STATUS_STATUS_TX \ - (MXC_V_I2C_STATUS_STATUS_TX \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */ -#define MXC_V_I2C_STATUS_STATUS_RX_ACK \ - ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */ -#define MXC_S_I2C_STATUS_STATUS_RX_ACK \ - (MXC_V_I2C_STATUS_STATUS_RX_ACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */ -#define MXC_V_I2C_STATUS_STATUS_RX \ - ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */ -#define MXC_S_I2C_STATUS_STATUS_RX \ - (MXC_V_I2C_STATUS_STATUS_RX \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */ -#define MXC_V_I2C_STATUS_STATUS_TX_ACK \ - ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */ -#define MXC_S_I2C_STATUS_STATUS_TX_ACK \ - (MXC_V_I2C_STATUS_STATUS_TX_ACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */ -#define MXC_V_I2C_STATUS_STATUS_NACK \ - ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */ -#define MXC_S_I2C_STATUS_STATUS_NACK \ - (MXC_V_I2C_STATUS_STATUS_NACK \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */ -#define MXC_V_I2C_STATUS_STATUS_BY_ST \ - ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */ -#define MXC_S_I2C_STATUS_STATUS_BY_ST \ - (MXC_V_I2C_STATUS_STATUS_BY_ST \ - << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */ - -/** - * Interrupt Status Register. - */ -#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ -#define MXC_F_I2C_INT_FL0_DONE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ -#define MXC_V_I2C_INT_FL0_DONE_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_DONE_INACTIVE \ - (MXC_V_I2C_INT_FL0_DONE_INACTIVE \ - << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */ -#define MXC_V_I2C_INT_FL0_DONE_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */ -#define MXC_S_I2C_INT_FL0_DONE_PENDING \ - (MXC_V_I2C_INT_FL0_DONE_PENDING \ - << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */ - -#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ -#define MXC_F_I2C_INT_FL0_RX_MODE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE \ - Mask */ -#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE \ - (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \ - << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */ -#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING \ - (MXC_V_I2C_INT_FL0_RX_MODE_PENDING \ - << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS \ - 2 /**< INT_FL0_GEN_CALL_ADDR Position */ -#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< \ - INT_FL0_GEN_CALL_ADDR \ - Mask */ -#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \ - (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \ - << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< \ - INT_FL0_GEN_CALL_ADDR_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */ -#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \ - (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \ - << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< \ - INT_FL0_GEN_CALL_ADDR_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ -#define MXC_F_I2C_INT_FL0_ADDR_MATCH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH \ - Mask */ -#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE \ - (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \ - << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */ -#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING \ - (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \ - << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ -#define MXC_F_I2C_INT_FL0_RX_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH \ - Mask */ -#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE \ - (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \ - << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */ -#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING \ - (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \ - << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ -#define MXC_F_I2C_INT_FL0_TX_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH \ - Mask */ -#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE \ - (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \ - << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */ -#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING \ - (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \ - << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ -#define MXC_F_I2C_INT_FL0_STOP \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ -#define MXC_V_I2C_INT_FL0_STOP_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_STOP_INACTIVE \ - (MXC_V_I2C_INT_FL0_STOP_INACTIVE \ - << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */ -#define MXC_V_I2C_INT_FL0_STOP_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */ -#define MXC_S_I2C_INT_FL0_STOP_PENDING \ - (MXC_V_I2C_INT_FL0_STOP_PENDING \ - << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */ - -#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ -#define MXC_F_I2C_INT_FL0_ADDR_ACK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK \ - Mask */ -#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE \ - (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \ - << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */ -#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING \ - (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \ - << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ -#define MXC_F_I2C_INT_FL0_ARB_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ -#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting \ - */ -#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING \ - (MXC_V_I2C_INT_FL0_ARB_ER_PENDING \ - << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting \ - */ - -#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ -#define MXC_F_I2C_INT_FL0_TO_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ -#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting \ - */ -#define MXC_V_I2C_INT_FL0_TO_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_TO_ER_PENDING \ - (MXC_V_I2C_INT_FL0_TO_ER_PENDING \ - << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */ - -#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS \ - 10 /**< INT_FL0_ADDR_NACK_ER Position */ -#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< \ - INT_FL0_ADDR_NACK_ER \ - Mask */ -#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< \ - INT_FL0_ADDR_NACK_ER_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING \ - (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \ - << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< \ - INT_FL0_ADDR_NACK_ER_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ -#define MXC_F_I2C_INT_FL0_DATA_ER \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER \ - Mask */ -#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING \ - (MXC_V_I2C_INT_FL0_DATA_ER_PENDING \ - << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS \ - 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ -#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< \ - INT_FL0_DO_NOT_RESP_ER \ - Mask */ -#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< \ - INT_FL0_DO_NOT_RESP_ER_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \ - (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \ - << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< \ - INT_FL0_DO_NOT_RESP_ER_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ -#define MXC_F_I2C_INT_FL0_START_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER \ - Mask */ -#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_START_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_START_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_START_ER_PENDING \ - (MXC_V_I2C_INT_FL0_START_ER_PENDING \ - << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ -#define MXC_F_I2C_INT_FL0_STOP_ER \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER \ - Mask */ -#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */ -#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE \ - (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \ - << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */ -#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING \ - (MXC_V_I2C_INT_FL0_STOP_ER_PENDING \ - << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS \ - 15 /**< INT_FL0_TX_LOCK_OUT Position */ -#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< \ - INT_FL0_TX_LOCK_OUT \ - Mask */ - -#define MXC_F_I2C_INT_FL0_MAMI_POS 16 /**< INT_FL0_MAMI Position */ -/* INT_FL0_MAMI Mask */ -#define MXC_F_I2C_INT_FL0_MAMI_MASK \ - ((uint32_t)(0xFUL << MXC_F_I2C_INT_FL0_MAMI_POS)) -/* INT_FL0_MAMI Address Match 0 */ -#define MXC_F_I2C_INT_FL0_MAMI_MATCH_0 \ - ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_MAMI_POS)) -/* INT_FL0_MAMI Address Match 1 */ -#define MXC_F_I2C_INT_FL0_MAMI_MATCH_1 \ - ((uint32_t)(0x2UL << MXC_F_I2C_INT_FL0_MAMI_POS)) -/* INT_FL0_MAMI Address Match 2 */ -#define MXC_F_I2C_INT_FL0_MAMI_MATCH_2 \ - ((uint32_t)(0x4UL << MXC_F_I2C_INT_FL0_MAMI_POS)) -/* INT_FL0_MAMI Address Match 3 */ -#define MXC_F_I2C_INT_FL0_MAMI_MATCH_3 \ - ((uint32_t)(0x8UL << MXC_F_I2C_INT_FL0_MAMI_POS)) - -/** - * Interrupt Enable Register. - */ -#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ -#define MXC_F_I2C_INT_EN0_DONE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ -#define MXC_V_I2C_INT_EN0_DONE_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */ -#define MXC_S_I2C_INT_EN0_DONE_DIS \ - (MXC_V_I2C_INT_EN0_DONE_DIS \ - << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */ -#define MXC_V_I2C_INT_EN0_DONE_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */ -#define MXC_S_I2C_INT_EN0_DONE_EN \ - (MXC_V_I2C_INT_EN0_DONE_EN \ - << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */ - -#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ -#define MXC_F_I2C_INT_EN0_RX_MODE \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE \ - Mask */ -#define MXC_V_I2C_INT_EN0_RX_MODE_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */ -#define MXC_S_I2C_INT_EN0_RX_MODE_DIS \ - (MXC_V_I2C_INT_EN0_RX_MODE_DIS \ - << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */ -#define MXC_V_I2C_INT_EN0_RX_MODE_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */ -#define MXC_S_I2C_INT_EN0_RX_MODE_EN \ - (MXC_V_I2C_INT_EN0_RX_MODE_EN \ - << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */ - -#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS \ - 2 /**< INT_EN0_GEN_CTRL_ADDR Position */ -#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< \ - INT_EN0_GEN_CTRL_ADDR \ - Mask */ -#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */ -#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \ - (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \ - << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< \ - INT_EN0_GEN_CTRL_ADDR_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */ -#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN \ - (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \ - << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN \ - Setting */ - -#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ -#define MXC_F_I2C_INT_EN0_ADDR_MATCH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH \ - Mask */ -#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */ -#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS \ - (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \ - << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */ -#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN \ - (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \ - << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN \ - Setting */ - -#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ -#define MXC_F_I2C_INT_EN0_RX_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH \ - Mask */ -#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */ -#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS \ - (MXC_V_I2C_INT_EN0_RX_THRESH_DIS \ - << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_RX_THRESH_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */ -#define MXC_S_I2C_INT_EN0_RX_THRESH_EN \ - (MXC_V_I2C_INT_EN0_RX_THRESH_EN \ - << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting \ - */ - -#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ -#define MXC_F_I2C_INT_EN0_TX_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH \ - Mask */ -#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */ -#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS \ - (MXC_V_I2C_INT_EN0_TX_THRESH_DIS \ - << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_TX_THRESH_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */ -#define MXC_S_I2C_INT_EN0_TX_THRESH_EN \ - (MXC_V_I2C_INT_EN0_TX_THRESH_EN \ - << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting \ - */ - -#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ -#define MXC_F_I2C_INT_EN0_STOP \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ -#define MXC_V_I2C_INT_EN0_STOP_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */ -#define MXC_S_I2C_INT_EN0_STOP_DIS \ - (MXC_V_I2C_INT_EN0_STOP_DIS \ - << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */ -#define MXC_V_I2C_INT_EN0_STOP_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */ -#define MXC_S_I2C_INT_EN0_STOP_EN \ - (MXC_V_I2C_INT_EN0_STOP_EN \ - << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */ - -#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ -#define MXC_F_I2C_INT_EN0_ADDR_ACK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK \ - Mask */ -#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */ -#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS \ - (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \ - << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting \ - */ -#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */ -#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN \ - (MXC_V_I2C_INT_EN0_ADDR_ACK_EN \ - << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting \ - */ - -#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ -#define MXC_F_I2C_INT_EN0_ARB_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ -#define MXC_V_I2C_INT_EN0_ARB_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_ARB_ER_DIS \ - (MXC_V_I2C_INT_EN0_ARB_ER_DIS \ - << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */ -#define MXC_V_I2C_INT_EN0_ARB_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_ARB_ER_EN \ - (MXC_V_I2C_INT_EN0_ARB_ER_EN \ - << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */ - -#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ -#define MXC_F_I2C_INT_EN0_TO_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ -#define MXC_V_I2C_INT_EN0_TO_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_TO_ER_DIS \ - (MXC_V_I2C_INT_EN0_TO_ER_DIS \ - << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */ -#define MXC_V_I2C_INT_EN0_TO_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_TO_ER_EN \ - (MXC_V_I2C_INT_EN0_TO_ER_EN \ - << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */ - -#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */ -#define MXC_F_I2C_INT_EN0_ADDR_ER \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER \ - Mask */ -#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS \ - (MXC_V_I2C_INT_EN0_ADDR_ER_DIS \ - << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */ -#define MXC_V_I2C_INT_EN0_ADDR_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_ADDR_ER_EN \ - (MXC_V_I2C_INT_EN0_ADDR_ER_EN \ - << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */ - -#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ -#define MXC_F_I2C_INT_EN0_DATA_ER \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER \ - Mask */ -#define MXC_V_I2C_INT_EN0_DATA_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_DATA_ER_DIS \ - (MXC_V_I2C_INT_EN0_DATA_ER_DIS \ - << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */ -#define MXC_V_I2C_INT_EN0_DATA_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_DATA_ER_EN \ - (MXC_V_I2C_INT_EN0_DATA_ER_EN \ - << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */ - -#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS \ - 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ -#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< \ - INT_EN0_DO_NOT_RESP_ER \ - Mask */ -#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \ - (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \ - << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< \ - INT_EN0_DO_NOT_RESP_ER_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN \ - (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \ - << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< \ - INT_EN0_DO_NOT_RESP_ER_EN \ - Setting */ - -#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ -#define MXC_F_I2C_INT_EN0_START_ER \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER \ - Mask */ -#define MXC_V_I2C_INT_EN0_START_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_START_ER_DIS \ - (MXC_V_I2C_INT_EN0_START_ER_DIS \ - << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting \ - */ -#define MXC_V_I2C_INT_EN0_START_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_START_ER_EN \ - (MXC_V_I2C_INT_EN0_START_ER_EN \ - << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting \ - */ - -#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ -#define MXC_F_I2C_INT_EN0_STOP_ER \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER \ - Mask */ -#define MXC_V_I2C_INT_EN0_STOP_ER_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */ -#define MXC_S_I2C_INT_EN0_STOP_ER_DIS \ - (MXC_V_I2C_INT_EN0_STOP_ER_DIS \ - << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */ -#define MXC_V_I2C_INT_EN0_STOP_ER_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */ -#define MXC_S_I2C_INT_EN0_STOP_ER_EN \ - (MXC_V_I2C_INT_EN0_STOP_ER_EN \ - << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */ - -#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS \ - 15 /**< INT_EN0_TX_LOCK_OUT Position */ -#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< \ - INT_EN0_TX_LOCK_OUT \ - Mask */ -#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \ - ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */ -#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS \ - (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \ - << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \ - ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */ -#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN \ - (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \ - << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN \ - Setting */ - -/** - * Interrupt Status Register 1. - */ -#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS \ - 0 /**< INT_FL1_RX_OVERFLOW Position \ - */ -#define MXC_F_I2C_INT_FL1_RX_OVERFLOW \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< \ - INT_FL1_RX_OVERFLOW \ - Mask */ -#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */ -#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \ - (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \ - << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< \ - INT_FL1_RX_OVERFLOW_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */ -#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING \ - (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \ - << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< \ - INT_FL1_RX_OVERFLOW_PENDING \ - Setting */ - -#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS \ - 1 /**< INT_FL1_TX_UNDERFLOW Position */ -#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< \ - INT_FL1_TX_UNDERFLOW \ - Mask */ -#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \ - ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */ -#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \ - (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \ - << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< \ - INT_FL1_TX_UNDERFLOW_INACTIVE \ - Setting */ -#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \ - ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */ -#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING \ - (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \ - << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< \ - INT_FL1_TX_UNDERFLOW_PENDING \ - Setting */ - -/** - * Interrupt Staus Register 1. - */ -#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS \ - 0 /**< INT_EN1_RX_OVERFLOW Position \ - */ -#define MXC_F_I2C_INT_EN1_RX_OVERFLOW \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< \ - INT_EN1_RX_OVERFLOW \ - Mask */ -#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \ - ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */ -#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS \ - (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \ - << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \ - ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */ -#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN \ - (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \ - << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN \ - Setting */ - -#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS \ - 1 /**< INT_EN1_TX_UNDERFLOW Position */ -#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< \ - INT_EN1_TX_UNDERFLOW \ - Mask */ -#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \ - ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */ -#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS \ - (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \ - << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS \ - Setting */ -#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \ - ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */ -#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN \ - (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \ - << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN \ - Setting */ - -/** - * FIFO Configuration Register. - */ -#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ -#define MXC_F_I2C_FIFO_LEN_RX_LEN \ - ((uint32_t)(0xFFUL \ - << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN \ - Mask */ - -#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ -#define MXC_F_I2C_FIFO_LEN_TX_LEN \ - ((uint32_t)(0xFFUL \ - << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN \ - Mask */ - -/** - * Receive Control Register 0. - */ -#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ -#define MXC_F_I2C_RX_CTRL0_DNR \ - ((uint32_t)(0x1UL \ - << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ -#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND \ - ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */ -#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND \ - (MXC_V_I2C_RX_CTRL0_DNR_RESPOND \ - << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */ -#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \ - ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */ -#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \ - (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \ - << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< \ - RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \ - Setting */ - -#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ -#define MXC_F_I2C_RX_CTRL0_RX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH \ - Mask */ -#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \ - ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */ -#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \ - (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \ - << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< \ - RX_CTRL0_RX_FLUSH_NOT_FLUSHED \ - Setting */ -#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \ - ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */ -#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH \ - (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \ - << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH \ - Setting */ - -#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ -#define MXC_F_I2C_RX_CTRL0_RX_THRESH \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH \ - Mask */ - -/** - * Receive Control Register 1. - */ -#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ -#define MXC_F_I2C_RX_CTRL1_RX_CNT \ - ((uint32_t)(0xFFUL \ - << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT \ - Mask */ - -#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ -#define MXC_F_I2C_RX_CTRL1_RX_FIFO \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO \ - Mask */ - -/** - * Transmit Control Register 0. - */ -#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS \ - 0 /**< TX_CTRL0_TX_PRELOAD Position \ - */ -#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< \ - TX_CTRL0_TX_PRELOAD \ - Mask */ - -#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS \ - 1 /**< TX_CTRL0_TX_READY_MODE Position */ -#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< \ - TX_CTRL0_TX_READY_MODE \ - Mask */ -#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \ - ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */ -#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN \ - (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \ - << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< \ - TX_CTRL0_TX_READY_MODE_EN \ - Setting */ -#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \ - ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */ -#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS \ - (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \ - << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< \ - TX_CTRL0_TX_READY_MODE_DIS \ - Setting */ - -#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ -#define MXC_F_I2C_TX_CTRL0_TX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH \ - Mask */ -#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \ - ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */ -#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \ - (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \ - << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< \ - TX_CTRL0_TX_FLUSH_NOT_FLUSHED \ - Setting */ -#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \ - ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */ -#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH \ - (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \ - << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH \ - Setting */ - -#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ -#define MXC_F_I2C_TX_CTRL0_TX_THRESH \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH \ - Mask */ - -/** - * Transmit Control Register 1. - */ -#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ -#define MXC_F_I2C_TX_CTRL1_TX_READY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY \ - Mask */ - -#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */ -#define MXC_F_I2C_TX_CTRL1_TX_LAST \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST \ - Mask */ -#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \ - ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */ -#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \ - (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \ - << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW \ - Setting */ -#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \ - ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */ -#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \ - (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \ - << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< \ - TX_CTRL1_TX_LAST_END_TRANSACTION \ - Setting */ - -#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */ -#define MXC_F_I2C_TX_CTRL1_TX_FIFO \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO \ - Mask */ - -/** - * Data Register. - */ -#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ -#define MXC_F_I2C_FIFO_DATA \ - ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ - -/** - * Master Control Register. - */ -#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ -#define MXC_F_I2C_MASTER_CTRL_START \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START \ - Mask */ - -#define MXC_F_I2C_MASTER_CTRL_RESTART_POS \ - 1 /**< MASTER_CTRL_RESTART Position \ - */ -#define MXC_F_I2C_MASTER_CTRL_RESTART \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< \ - MASTER_CTRL_RESTART \ - Mask */ - -#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ -#define MXC_F_I2C_MASTER_CTRL_STOP \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP \ - Mask */ - -#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS \ - 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ -#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< \ - MASTER_CTRL_SL_EX_ADDR \ - Mask */ -#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \ - ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */ -#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \ - (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \ - << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< \ - MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \ - Setting */ -#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \ - ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */ -#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \ - (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \ - << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< \ - MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \ - Setting */ - -#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS \ - 8 /**< MASTER_CTRL_MASTER_CODE Position */ -#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE \ - ((uint32_t)( \ - 0x7UL \ - << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< \ - MASTER_CTRL_MASTER_CODE \ - Mask */ - -#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS \ - 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */ -#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< \ - MASTER_CTRL_SCL_SPEED_UP \ - Mask */ -#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \ - ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */ -#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \ - (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \ - << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< \ - MASTER_CTRL_SCL_SPEED_UP_EN \ - Setting */ -#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \ - ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */ -#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \ - (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \ - << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< \ - MASTER_CTRL_SCL_SPEED_UP_DIS \ - Setting */ - -/** - * Clock Low Register. - */ -#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */ -#define MXC_F_I2C_CLK_LO_CLK_LO \ - ((uint32_t)( \ - 0x1FFUL \ - << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */ - -/** - * Clock high Register. - */ -#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */ -#define MXC_F_I2C_CLK_HI_CKH \ - ((uint32_t)(0x1FFUL \ - << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */ - -/** - * HS-Mode Clock Control Register - */ -#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ -#define MXC_F_I2C_HS_CLK_HS_CLK_LO \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO \ - Mask */ - -#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ -#define MXC_F_I2C_HS_CLK_HS_CLK_HI \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI \ - Mask */ - -/** - * Timeout Register - */ -#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ -#define MXC_F_I2C_TIMEOUT_TO \ - ((uint32_t)(0xFFFFUL \ - << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ - -/** - * Slave Address Register. - */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS \ - 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \ - ((uint32_t)( \ - 0x3FFUL \ - << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< \ - SLAVE_ADDR_SLAVE_ADDR \ - Mask */ - -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS \ - 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< \ - SLAVE_ADDR_SLAVE_ADDR_DIS \ - Mask */ - -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS \ - 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */ -#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \ - ((uint32_t)( \ - 0xFUL \ - << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< \ - SLAVE_ADDR_SLAVE_ADDR_IDX \ - Mask */ - -#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS \ - 15 /**< SLAVE_ADDR_EX_ADDR Position \ - */ -#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR \ - Mask */ -#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ -#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< \ - SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \ - Setting */ -#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ -#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< \ - SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \ - Setting */ - -/** - * DMA Register. - */ -#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ -#define MXC_F_I2C_DMA_TX_EN \ - ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ -#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */ -#define MXC_S_I2C_DMA_TX_EN_DIS \ - (MXC_V_I2C_DMA_TX_EN_DIS \ - << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */ -#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */ -#define MXC_S_I2C_DMA_TX_EN_EN \ - (MXC_V_I2C_DMA_TX_EN_EN \ - << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */ - -#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ -#define MXC_F_I2C_DMA_RX_EN \ - ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ -#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */ -#define MXC_S_I2C_DMA_RX_EN_DIS \ - (MXC_V_I2C_DMA_RX_EN_DIS \ - << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */ -#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */ -#define MXC_S_I2C_DMA_RX_EN_EN \ - (MXC_V_I2C_DMA_RX_EN_EN \ - << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */ - -#endif /* _I2C_REGS_H_ */ diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h deleted file mode 100644 index 5f40e4203d..0000000000 --- a/chip/max32660/icc_regs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the ICC */ - -#ifndef _ICC_REGS_H_ -#define _ICC_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/** - * Structure type to access the ICC Registers. - */ -typedef struct { - __I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */ - __I uint32_t memcfg; /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */ - __R uint32_t rsv_0x8_0xff[62]; - __IO uint32_t - cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */ - __R uint32_t rsv_0x104_0x6ff[383]; - __IO uint32_t - invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */ -} mxc_icc_regs_t; - -/** - * ICC Peripheral Register Offsets from the ICC Base Peripheral - * Address. - */ -#define MXC_R_ICC_CACHE_ID \ - ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_ICC_MEMCFG \ - ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_ICC_CACHE_CTRL \ - ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> \ - 0x0x100 */ -#define MXC_R_ICC_INVALIDATE \ - ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> \ - 0x0x700 */ - -/** - * Cache ID Register. - */ -#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ -#define MXC_F_ICC_CACHE_ID_RELNUM \ - ((uint32_t)( \ - 0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \ - Mask */ - -#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ -#define MXC_F_ICC_CACHE_ID_PARTNUM \ - ((uint32_t)(0xFUL \ - << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \ - Mask */ - -#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ -#define MXC_F_ICC_CACHE_ID_CCHID \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ - -/** - * Memory Configuration Register. - */ -#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ -#define MXC_F_ICC_MEMCFG_CCHSZ \ - ((uint32_t)(0xFFFFUL \ - << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ - -#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ -#define MXC_F_ICC_MEMCFG_MEMSZ \ - ((uint32_t)(0xFFFFUL \ - << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ - -/** - * Cache Control and Status Register. - */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS \ - 0 /**< CACHE_CTRL_CACHE_EN Position \ - */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< \ - CACHE_CTRL_CACHE_EN \ - Mask */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ - ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS \ - (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \ - Setting */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ - ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN \ - (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \ - Setting */ - -#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \ - 16 /**< CACHE_CTRL_CACHE_RDY Position */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< \ - CACHE_CTRL_CACHE_RDY \ - Mask */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ - ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ - (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ - << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \ - CACHE_CTRL_CACHE_RDY_NOTREADY \ - Setting */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ - ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY \ - (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ - << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \ - CACHE_CTRL_CACHE_RDY_READY \ - Setting */ - -#endif /* _ICC_REGS_H_ */ diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h deleted file mode 100644 index f323b4568c..0000000000 --- a/chip/max32660/pwrseq_regs.h +++ /dev/null @@ -1,489 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */
-
-#ifndef _PWRSEQ_REGS_H_
-#define _PWRSEQ_REGS_H_
-
-/* **** Includes **** */
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
-#pragma system_include
-#endif
-
-#if defined(__CC_ARM)
-#pragma anon_unions
-#endif
-
-/*
- If types are not defined elsewhere (CMSIS) define them here
-*/
-#ifndef __IO
-#define __IO volatile
-#endif
-#ifndef __I
-#define __I volatile const
-#endif
-#ifndef __O
-#define __O volatile
-#endif
-#ifndef __R
-#define __R volatile const
-#endif
-
-/* **** Definitions **** */
-
-/**
- * mxc_pwrseq_regs_t
- * Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral
- * Module.
- */
-
-/**
- * pwrseq_registers
- * Structure type to access the PWRSEQ Registers.
- */
-typedef struct {
- __IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
- __IO uint32_t
- lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
- __IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
- __R uint32_t rsv_0xc_0x3f[13];
- __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
-} mxc_pwrseq_regs_t;
-
-/**
- * Register offsets for module PWRSEQ
- * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
- */
-#define MXC_R_PWRSEQ_LP_CTRL \
- ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
- \ \ \ 0x0000</tt> */
-#define MXC_R_PWRSEQ_LP_WAKEFL \
- ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
- \ \ \ 0x0004</tt> */
-#define MXC_R_PWRSEQ_LPWK_EN \
- ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
- \ \ \ 0x0008</tt> */
-#define MXC_R_PWRSEQ_LPMEMSD \
- ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
- \ \ \ 0x0040</tt> */
-
-/**
- * pwrseq_registers
- * Low Power Control Register.
- */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \
- 0 /**< LP_CTRL_RAMRET_SEL0 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \
- LP_CTRL_RAMRET_SEL0 \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \
- 1 /**< LP_CTRL_RAMRET_SEL1 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \
- LP_CTRL_RAMRET_SEL1 \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \
- 2 /**< LP_CTRL_RAMRET_SEL2 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \
- LP_CTRL_RAMRET_SEL2 \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \
- 3 /**< LP_CTRL_RAMRET_SEL3 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \
- LP_CTRL_RAMRET_SEL3 \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
- (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
- << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
-#define MXC_F_PWRSEQ_LP_CTRL_OVR \
- ((uint32_t)(0x3UL \
- << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
- ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
- << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
- ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
- << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
- ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
- << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \
- 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \ \
- LP_CTRL_VCORE_DET_BYPASS \
- \ \
- \ \ \ \ \
- Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
- ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_DET_BYPASS_ENABLED \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
- ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_DET_BYPASS_DISABLE \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \
- 8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \
- */
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
- \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \
- (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
- << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \
- \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \
- 10 /**< LP_CTRL_FAST_WK_EN Position */
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \
- LP_CTRL_FAST_WK_EN \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
- \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
- (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
- << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \
- \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \
- ((uint32_t)( \
- 0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
- ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \
- (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
- << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
- ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF \
- (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
- << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
- * \ \
- * \ \ \
- * \ \ \ \
- */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \
- 12 /**< LP_CTRL_VCORE_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \
- LP_CTRL_VCORE_POR_DIS \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
- ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_POR_DIS_DIS \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
- ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_POR_DIS_EN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS \
- ((uint32_t)(0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
- ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \
- (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
- << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \
- * \ \
- * \ \ \
- * \ \ \ \
- * \ \ \ \ \
- */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
- ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
- * \ \
- * \ \ \
- * \ \ \ \
- * \ \ \ \ \
- */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \
- 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \
- LP_CTRL_VCORE_SVM_DIS \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
- ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_SVM_DIS_EN \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
- ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VCORE_SVM_DIS_DIS \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \
- 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \
- LP_CTRL_VDDIO_POR_DIS \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
- ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
- (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
- << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VDDIO_POR_DIS_EN \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
- ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
-#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
- (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
- << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
- LP_CTRL_VDDIO_POR_DIS_DIS \
- \ \ \ \ Setting */
-
-/**
- * pwrseq_registers
- * Low Power Mode Wakeup Flags for GPIO0
- */
-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
-#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \
- ((uint32_t)( \
- 0x3FFFUL \
- << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \
- \ \ \ Mask */
-
-/**
- * pwrseq_registers
- * Low Power I/O Wakeup Enable Register 0. This register enables low
- * power wakeup functionality for GPIO0.
- */
-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \
- ((uint32_t)(0x3FFFUL \
- << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \
- \ \ \ Mask */
-
-/**
- * pwrseq_registers
- * Low Power Memory Shutdown Control.
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \
- 0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
- ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
- ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \
- LPMEMSD_SRAM0_OFF_SHUTDOWN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \
- 1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
- ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
- ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \
- LPMEMSD_SRAM1_OFF_SHUTDOWN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \
- 2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
- ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
- ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \
- LPMEMSD_SRAM2_OFF_SHUTDOWN \
- \ \ \ \ Setting */
-
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \
- 3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \
- */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \
- ((uint32_t)( \
- 0x1UL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \
- \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
- ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \
- \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
- ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
- (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
- << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \
- LPMEMSD_SRAM3_OFF_SHUTDOWN \
- \ \ \ \ Setting */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _PWRSEQ_REGS_H_ */
diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h deleted file mode 100644 index 8a2a072898..0000000000 --- a/chip/max32660/registers.h +++ /dev/null @@ -1,224 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Register map, needed for a common include file */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include <stdint.h> - -#define EC_PF_IRQn 0 /* 0x10 0x0040 16: Power Fail */ -#define EC_WDT0_IRQn 1 /* 0x11 0x0044 17: Watchdog 0 */ -#define EC_RSV00_IRQn 2 /* 0x12 0x0048 18: RSV00 */ -#define EC_RTC_IRQn 3 /* 0x13 0x004C 19: RTC */ -#define EC_RSV1_IRQn 4 /* 0x14 0x0050 20: RSV1 */ -#define EC_TMR0_IRQn 5 /* 0x15 0x0054 21: Timer 0 */ -#define EC_TMR1_IRQn 6 /* 0x16 0x0058 22: Timer 1 */ -#define EC_TMR2_IRQn 7 /* 0x17 0x005C 23: Timer 2 */ -#define EC_RSV02_IRQn 8 /* 0x18 0x0060 24: RSV02 */ -#define EC_RSV03_IRQn 9 /* 0x19 0x0064 25: RSV03 */ -#define EC_RSV04_IRQn 10 /* 0x1A 0x0068 26: RSV04 */ -#define EC_RSV05_IRQn 11 /* 0x1B 0x006C 27: RSV05 */ -#define EC_RSV06_IRQn 12 /* 0x1C 0x0070 28: RSV06 */ -#define EC_I2C0_IRQn 13 /* 0x1D 0x0074 29: I2C0 */ -#define EC_UART0_IRQn 14 /* 0x1E 0x0078 30: UART 0 */ -#define EC_UART1_IRQn 15 /* 0x1F 0x007C 31: UART 1 */ -#define EC_SPI17Y_IRQn 16 /* 0x20 0x0080 32: SPI17Y */ -#define EC_SPIMSS_IRQn 17 /* 0x21 0x0084 33: SPIMSS */ -#define EC_RSV07_IRQn 18 /* 0x22 0x0088 34: RSV07 */ -#define EC_RSV08_IRQn 19 /* 0x23 0x008C 35: RSV08 */ -#define EC_RSV09_IRQn 20 /* 0x24 0x0090 36: RSV09 */ -#define EC_RSV10_IRQn 21 /* 0x25 0x0094 37: RSV10 */ -#define EC_RSV11_IRQn 22 /* 0x26 0x0098 38: RSV11 */ -#define EC_FLC_IRQn 23 /* 0x27 0x009C 39: FLC */ -#define EC_GPIO0_IRQn 24 /* 0x28 0x00A0 40: GPIO0 */ -#define EC_RSV12_IRQn 25 /* 0x29 0x00A4 41: RSV12 */ -#define EC_RSV13_IRQn 26 /* 0x2A 0x00A8 42: RSV13 */ -#define EC_RSV14_IRQn 27 /* 0x2B 0x00AC 43: RSV14 */ -#define EC_DMA0_IRQn 28 /* 0x2C 0x00B0 44: DMA0 */ -#define EC_DMA1_IRQn 29 /* 0x2D 0x00B4 45: DMA1 */ -#define EC_DMA2_IRQn 30 /* 0x2E 0x00B8 46: DMA2 */ -#define EC_DMA3_IRQn 31 /* 0x2F 0x00BC 47: DMA3 */ -#define EC_RSV15_IRQn 32 /* 0x30 0x00C0 48: RSV15 */ -#define EC_RSV16_IRQn 33 /* 0x31 0x00C4 49: RSV16 */ -#define EC_RSV17_IRQn 34 /* 0x32 0x00C8 50: RSV17 */ -#define EC_RSV18_IRQn 35 /* 0x33 0x00CC 51: RSV18 */ -#define EC_I2C1_IRQn 36 /* 0x34 0x00D0 52: I2C1 */ -#define EC_RSV19_IRQn 37 /* 0x35 0x00D4 53: RSV19 */ -#define EC_RSV20_IRQn 38 /* 0x36 0x00D8 54: RSV20 */ -#define EC_RSV21_IRQn 39 /* 0x37 0x00DC 55: RSV21 */ -#define EC_RSV22_IRQn 40 /* 0x38 0x00E0 56: RSV22 */ -#define EC_RSV23_IRQn 41 /* 0x39 0x00E4 57: RSV23 */ -#define EC_RSV24_IRQn 42 /* 0x3A 0x00E8 58: RSV24 */ -#define EC_RSV25_IRQn 43 /* 0x3B 0x00EC 59: RSV25 */ -#define EC_RSV26_IRQn 44 /* 0x3C 0x00F0 60: RSV26 */ -#define EC_RSV27_IRQn 45 /* 0x3D 0x00F4 61: RSV27 */ -#define EC_RSV28_IRQn 46 /* 0x3E 0x00F8 62: RSV28 */ -#define EC_RSV29_IRQn 47 /* 0x3F 0x00FC 63: RSV29 */ -#define EC_RSV30_IRQn 48 /* 0x40 0x0100 64: RSV30 */ -#define EC_RSV31_IRQn 49 /* 0x41 0x0104 65: RSV31 */ -#define EC_RSV32_IRQn 50 /* 0x42 0x0108 66: RSV32 */ -#define EC_RSV33_IRQn 51 /* 0x43 0x010C 67: RSV33 */ -#define EC_RSV34_IRQn 52 /* 0x44 0x0110 68: RSV34 */ -#define EC_RSV35_IRQn 53 /* 0x45 0x0114 69: RSV35 */ -#define EC_GPIOWAKE_IRQn 54 /* 0x46 0x0118 70: GPIO Wakeup */ - -#ifndef HIRC96_FREQ -#define HIRC96_FREQ 96000000 -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -#ifndef PeripheralClock -#define PeripheralClock \ - (SystemCoreClock / \ - 2) /*!< Peripheral Clock Frequency \ - */ -#endif - -#define MXC_FLASH_MEM_BASE 0x00000000UL -#define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE 0x00040000UL -#define MXC_INFO_MEM_BASE 0x00040000UL -#define MXC_INFO_MEM_SIZE 0x00001000UL -#define MXC_SRAM_MEM_BASE 0x20000000UL -#define MXC_SRAM_MEM_SIZE 0x00018000UL - -/* - Base addresses and configuration settings for all MAX32660 peripheral - modules. -*/ - -/******************************************************************************/ -/* Global control */ -#define MXC_BASE_GCR ((uint32_t)0x40000000UL) -#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) - -/******************************************************************************/ -/* Non-battery backed SI Registers */ -#define MXC_BASE_SIR ((uint32_t)0x40000400UL) -#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) - -/******************************************************************************/ -/* Watchdog */ -#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) -#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) - -/******************************************************************************/ -/* Real Time Clock */ -#define MXC_BASE_RTC ((uint32_t)0x40006000UL) -#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) - -/******************************************************************************/ -/* Power Sequencer */ -#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) -#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) - -/******************************************************************************/ -/* GPIO */ -#define MXC_CFG_GPIO_INSTANCES (1) -#define MXC_CFG_GPIO_PINS_PORT (14) - -#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) -#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) - -#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) - -#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) - -#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) - -#define PORT_0 ((uint32_t)(0UL)) /**< Port 0 Define*/ -#define PORT_1 ((uint32_t)(1UL)) /**< Port 1 Define*/ -#define PORT_2 ((uint32_t)(2UL)) /**< Port 2 Define*/ -#define PORT_3 ((uint32_t)(3UL)) /**< Port 3 Define*/ -#define PORT_4 ((uint32_t)(4UL)) /**< Port 4 Define*/ - -#define GPIO_0 PORT_0 /**< Port 0 Define*/ -#define GPIO_1 PORT_1 /**< Port 1 Define*/ -#define GPIO_2 PORT_2 /**< Port 2 Define*/ -#define GPIO_3 PORT_3 /**< Port 3 Define*/ -#define GPIO_4 PORT_4 /**< Port 4 Define*/ - -#define DUMMY_GPIO_BANK GPIO_0 - -/******************************************************************************/ -/* I2C */ -#define MXC_I2C_INSTANCES (2) -#define MXC_I2C_FIFO_DEPTH (8) - -#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) -#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) -#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) -#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) - -#define MXC_I2C_GET_IRQ(i) \ - (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) - -#define MXC_I2C_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) - -#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0) - -#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1) - -#define MXC_CFG_TMR_INSTANCES (3) - -#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) -#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) -#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) -#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) -#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) -#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) - -#define MXC_TMR_GET_IRQ(i) \ - (IRQn_Type)((i) == 0 ? \ - TMR0_IRQn : \ - (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0) - -#define MXC_TMR_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0 : \ - (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0) - -#define MXC_TMR_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0) - -#define MXC_TMR_GET_IDX(p) \ - ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1) - -/******************************************************************************/ -/* FLC */ -#define MXC_BASE_FLC ((uint32_t)0x40029000UL) -#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) - -/******************************************************************************/ -/* Instruction Cache */ -#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) -#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) - -/******************************************************************************/ -/* UART / Serial Port Interface */ - -#define MXC_UART_INSTANCES (2) -#define MXC_UART_FIFO_DEPTH (8) - -#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) -#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) -#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) -#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) - -#define MXC_UART_GET_IRQ(i) \ - (IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0) - -#define MXC_UART_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0) - -#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0) - -#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : -1) - -#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask)) - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/max32660/system_chip.c b/chip/max32660/system_chip.c deleted file mode 100644 index 07127dc8c5..0000000000 --- a/chip/max32660/system_chip.c +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 System module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "host_command.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "registers.h" -#include "gcr_regs.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) - -void chip_pre_init(void) -{ -} - -void system_pre_init(void) -{ -} - -void system_reset(int flags) -{ - MXC_GCR->rstr0 = MXC_F_GCR_RSTR0_SYSTEM; - while (1) - ; -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ - /* chip specific standby mode */ - CPRINTS("TODO: implement %s()", __func__); -} - -const char *system_get_chip_vendor(void) -{ - return "maxim"; -} - -const char *system_get_chip_name(void) -{ - return "max32660"; -} - -const char *system_get_chip_revision(void) -{ - return "A1"; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - return EC_ERROR_UNIMPLEMENTED; -} diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h deleted file mode 100644 index 946cacbc50..0000000000 --- a/chip/max32660/tmr_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the TMR Peripheral */ - -#ifndef _TMR_REGS_H_ -#define _TMR_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/* **** Definitions **** */ - -/** - * 32-bit reloadable timer that can be used for timing and event - * counting. - */ - -/** - * Structure type to access the TMR Registers. - */ -typedef struct { - __IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */ - __IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */ - __IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */ - __IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */ - __IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */ - __IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */ -} mxc_tmr_regs_t; - -/** - * TMR Peripheral Register Offsets from the TMR Base Peripheral - * Address. - */ -#define MXC_R_TMR_CNT \ - ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_TMR_CMP \ - ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_TMR_PWM \ - ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \ - 0x0x008 */ -#define MXC_R_TMR_INTR \ - ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \ - 0x0x00C */ -#define MXC_R_TMR_CN \ - ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \ - 0x0x010 */ -#define MXC_R_TMR_NOLCMP \ - ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \ - 0x0x014 */ - -/** - * Clear Interrupt. Writing a value (0 or 1) to a bit in this register - * clears the associated interrupt. - */ -#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */ -#define MXC_F_TMR_INTR_IRQ_CLR \ - ((uint32_t)(0x1UL \ - << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */ - -/** - * Timer Control Register. - */ -#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ -#define MXC_F_TMR_CN_TMODE \ - ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ -#define MXC_V_TMR_CN_TMODE_ONESHOT \ - ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ -#define MXC_S_TMR_CN_TMODE_ONESHOT \ - (MXC_V_TMR_CN_TMODE_ONESHOT \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ -#define MXC_V_TMR_CN_TMODE_CONTINUOUS \ - ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ -#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ - (MXC_V_TMR_CN_TMODE_CONTINUOUS \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ -#define MXC_V_TMR_CN_TMODE_COUNTER \ - ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ -#define MXC_S_TMR_CN_TMODE_COUNTER \ - (MXC_V_TMR_CN_TMODE_COUNTER \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ -#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ -#define MXC_S_TMR_CN_TMODE_PWM \ - (MXC_V_TMR_CN_TMODE_PWM \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURE \ - ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURE \ - (MXC_V_TMR_CN_TMODE_CAPTURE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ -#define MXC_V_TMR_CN_TMODE_COMPARE \ - ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ -#define MXC_S_TMR_CN_TMODE_COMPARE \ - (MXC_V_TMR_CN_TMODE_COMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ -#define MXC_V_TMR_CN_TMODE_GATED \ - ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ - */ -#define MXC_S_TMR_CN_TMODE_GATED \ - (MXC_V_TMR_CN_TMODE_GATED \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ - ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ - (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ - -#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ -#define MXC_F_TMR_CN_PRES \ - ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ -#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ -#define MXC_S_TMR_CN_PRES_DIV1 \ - (MXC_V_TMR_CN_PRES_DIV1 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ -#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ -#define MXC_S_TMR_CN_PRES_DIV2 \ - (MXC_V_TMR_CN_PRES_DIV2 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ -#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ -#define MXC_S_TMR_CN_PRES_DIV4 \ - (MXC_V_TMR_CN_PRES_DIV4 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ -#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ -#define MXC_S_TMR_CN_PRES_DIV8 \ - (MXC_V_TMR_CN_PRES_DIV8 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ -#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ -#define MXC_S_TMR_CN_PRES_DIV16 \ - (MXC_V_TMR_CN_PRES_DIV16 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ -#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ -#define MXC_S_TMR_CN_PRES_DIV32 \ - (MXC_V_TMR_CN_PRES_DIV32 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ -#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ -#define MXC_S_TMR_CN_PRES_DIV64 \ - (MXC_V_TMR_CN_PRES_DIV64 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ -#define MXC_V_TMR_CN_PRES_DIV128 \ - ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \ - */ -#define MXC_S_TMR_CN_PRES_DIV128 \ - (MXC_V_TMR_CN_PRES_DIV128 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ - -#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ -#define MXC_F_TMR_CN_TPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ -#define MXC_V_TMR_CN_TPOL_ACTIVEHI \ - ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ - (MXC_V_TMR_CN_TPOL_ACTIVEHI \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ -#define MXC_V_TMR_CN_TPOL_ACTIVELO \ - ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVELO \ - (MXC_V_TMR_CN_TPOL_ACTIVELO \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ - -#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ -#define MXC_F_TMR_CN_TEN \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ -#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ -#define MXC_S_TMR_CN_TEN_DIS \ - (MXC_V_TMR_CN_TEN_DIS \ - << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ -#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ -#define MXC_S_TMR_CN_TEN_EN \ - (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \ - */ - -#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ -#define MXC_F_TMR_CN_PRES3 \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ - -#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ -#define MXC_F_TMR_CN_PWMSYNC \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \ - */ -#define MXC_V_TMR_CN_PWMSYNC_DIS \ - ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ - */ -#define MXC_S_TMR_CN_PWMSYNC_DIS \ - (MXC_V_TMR_CN_PWMSYNC_DIS \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ -#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ -#define MXC_S_TMR_CN_PWMSYNC_EN \ - (MXC_V_TMR_CN_PWMSYNC_EN \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ - -#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ -#define MXC_F_TMR_CN_NOLHPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \ - */ -#define MXC_V_TMR_CN_NOLHPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ - */ -#define MXC_S_TMR_CN_NOLHPOL_DIS \ - (MXC_V_TMR_CN_NOLHPOL_DIS \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */ -#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ -#define MXC_S_TMR_CN_NOLHPOL_EN \ - (MXC_V_TMR_CN_NOLHPOL_EN \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */ - -#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ -#define MXC_F_TMR_CN_NOLLPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \ - */ -#define MXC_V_TMR_CN_NOLLPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ - */ -#define MXC_S_TMR_CN_NOLLPOL_DIS \ - (MXC_V_TMR_CN_NOLLPOL_DIS \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */ -#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ -#define MXC_S_TMR_CN_NOLLPOL_EN \ - (MXC_V_TMR_CN_NOLLPOL_EN \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */ - -#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ -#define MXC_F_TMR_CN_PWMCKBD \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \ - */ -#define MXC_V_TMR_CN_PWMCKBD_DIS \ - ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ - */ -#define MXC_S_TMR_CN_PWMCKBD_DIS \ - (MXC_V_TMR_CN_PWMCKBD_DIS \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ -#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ -#define MXC_S_TMR_CN_PWMCKBD_EN \ - (MXC_V_TMR_CN_PWMCKBD_EN \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ - -/** - * Timer Non-Overlapping Compare Register. - */ -#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ -#define MXC_F_TMR_NOLCMP_NOLLCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ - -#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ -#define MXC_F_TMR_NOLCMP_NOLHCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ - -#ifdef __cplusplus -} -#endif - -#endif /* _TMR_REGS_H_ */ diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c deleted file mode 100644 index de8d467253..0000000000 --- a/chip/max32660/uart_chip.c +++ /dev/null @@ -1,289 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Console UART Module for Chrome EC */ - -#include <stdint.h> -#include "system.h" -#include "task.h" -#include "uart.h" -#include "registers.h" -#include "tmr_regs.h" -#include "gpio_regs.h" -#include "common.h" -#include "gcr_regs.h" -#include "uart_regs.h" - -static int done_uart_init_yet; - -#ifndef UARTN -#define UARTN CONFIG_UART_HOST -#endif - -#if (UARTN == 0) -#define MXC_UART MXC_UART0 -#define EC_UART_IRQn EC_UART0_IRQn -#elif (UARTN == 1) -#define MXC_UART MXC_UART1 -#define EC_UART_IRQn EC_UART1_IRQn -#else -#error "MAX32660 supports only UART 0 or 1 for EC console" -#endif - -#define UART_BAUD 115200 - -#define UART_ER_IF \ - (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \ - MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN) - -#define UART_ER_IE \ - (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \ - MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN) - -#define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH) - -#define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH) - -#define UART_TX_IF \ - (UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \ - MXC_F_UART_INT_FL_TX_FIFO_THRESH) - -#define UART_TX_IE \ - (UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \ - MXC_F_UART_INT_EN_TX_FIFO_THRESH) - -#define UART_RX_THRESHOLD_LEVEL 1 - -/** - * Alternate clock rate. (7.3728MHz) */ -#define UART_ALTERNATE_CLOCK_HZ 7372800 - -/* ************************************************************************* */ -unsigned uart_number_write_available(mxc_uart_regs_t *uart) -{ - return MXC_UART_FIFO_DEPTH - - ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >> - MXC_F_UART_STATUS_TX_FIFO_CNT_POS); -} - -/* ************************************************************************* */ -unsigned uart_number_read_available(mxc_uart_regs_t *uart) -{ - return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >> - MXC_F_UART_STATUS_RX_FIFO_CNT_POS); -} - -void uartn_enable_tx_interrupt(int uart_num) -{ - // Enable the interrupts - MXC_UART_GET_UART(uart_num)->int_en |= UART_TX_IE; -} - -void uartn_disable_tx_interrupt(int uart_num) -{ - // Disable the interrupts - MXC_UART_GET_UART(uart_num)->int_en &= ~UART_TX_IE; -} - -void uartn_enable_rx_interrupt(int uart_num) -{ - // Enable the interrupts - MXC_UART_GET_UART(uart_num)->int_en |= UART_RX_IE; -} - -void uartn_disable_rx_interrupt(int uart_num) -{ - // Enable the interrupts - MXC_UART_GET_UART(uart_num)->int_en &= ~UART_RX_IE; -} - -int uartn_tx_in_progress(int uart_num) -{ - return ((MXC_UART_GET_UART(uart_num)->status & - (MXC_F_UART_STATUS_TX_BUSY)) != 0); -} - -void uartn_tx_flush(int uart_num) -{ - while (uartn_tx_in_progress(uart_num)) { - } -} - -int uartn_tx_ready(int uart_num) -{ - int avail; - avail = uart_number_write_available(MXC_UART_GET_UART(uart_num)); - /* True if the TX buffer is not completely full */ - return (avail != 0); -} - -int uartn_rx_available(int uart_num) -{ - int avail; - /* True if the RX buffer is not completely empty. */ - avail = uart_number_read_available(MXC_UART_GET_UART(uart_num)); - return (avail != 0); -} - -void uartn_write_char(int uart_num, char c) -{ - int avail; - mxc_uart_regs_t *uart; - - uart = MXC_UART_GET_UART(uart_num); - /* Refill the TX FIFO */ - avail = uart_number_write_available(uart); - - /* wait until there is room in the fifo */ - while (avail == 0) { - avail = uart_number_write_available(uart); - } - - /* stuff the fifo with the character */ - uart->fifo = c; -} - -int uartn_read_char(int uart_num) -{ - int c; - c = MXC_UART_GET_UART(uart_num)->fifo; - return c; -} - -void uartn_clear_interrupt_flags(int uart_num) -{ - uint32_t flags; - // Read and clear interrupts - // intst = MXC_UART_GET_UART(uart_num)->int_fl; - // MXC_UART_GET_UART(uart_num)->int_fl = ~intst; - - flags = MXC_UART_GET_UART(uart_num)->int_fl; - MXC_UART_GET_UART(uart_num)->int_fl = flags; -} - -static inline int uartn_is_rx_interrupt(int uart_num) -{ - return MXC_UART_GET_UART(uart_num)->int_fl & UART_RX_IF; -} - -static inline int uartn_is_tx_interrupt(int uart_num) -{ - return MXC_UART_GET_UART(uart_num)->int_fl & UART_TX_IF; -} - -int uart_init_done(void) -{ - return done_uart_init_yet; -} - -void uart_tx_start(void) -{ - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - /* - * Re-enable the transmit interrupt, then forcibly trigger the - * interrupt. - */ - uartn_enable_tx_interrupt(UARTN); - task_trigger_irq(EC_UART_IRQn); -} - -void uart_tx_stop(void) -{ - uartn_disable_tx_interrupt(UARTN); - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); -} - -int uart_tx_in_progress(void) -{ - return uartn_tx_in_progress(UARTN); -} - -void uart_tx_flush(void) -{ - uartn_tx_flush(UARTN); -} - -int uart_tx_ready(void) -{ - /* True if the TX buffer is not completely full */ - return uartn_tx_ready(UARTN); -} - -int uart_rx_available(void) -{ - /* True if the RX buffer is not completely empty. */ - return uartn_rx_available(UARTN); -} - -void uart_write_char(char c) -{ - /* write a character to the UART */ - uartn_write_char(UARTN, c); -} - -int uart_read_char(void) -{ - return uartn_read_char(UARTN); -} - -/** - * Interrupt handlers for UART - */ -void uart_rxtx_interrupt(void) -{ - /* Process the Console Input */ - uart_process_input(); - /* Process the Buffered Console Output */ - uart_process_output(); - uartn_clear_interrupt_flags(UARTN); -} -DECLARE_IRQ(EC_UART_IRQn, uart_rxtx_interrupt, 1); - -void uart_init(void) -{ - uint32_t flags; - uint32_t baud0 = 0, baud1 = 0, div; - int32_t factor = -1; - - /* Init the GPIO Port Mapping */ - gpio_config_module(MODULE_UART, 1); - - /* Drain FIFOs and enable UART and set configuration */ - MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1); - - /* Set the baud rate */ - div = PeripheralClock / (UART_BAUD); // constant part of DIV (i.e. DIV - // * (Baudrate*factor_int)) - - do { - factor += 1; - baud0 = div >> (7 - factor); // divide by 128,64,32,16 to - // extract integer part - baud1 = ((div << factor) - - (baud0 << 7)); // subtract factor corrected div - - // integer parts - - } while ((baud0 == 0) && (factor < 4)); - - MXC_UART->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0); - MXC_UART->baud1 = baud1; - - MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL - << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS; - - /* Clear Interrupt Flags */ - flags = MXC_UART->int_fl; - MXC_UART->int_fl = flags; - - /* Enable the RX interrupts */ - MXC_UART->int_en |= UART_RX_IE; - - /* Enable the IRQ */ - task_enable_irq(EC_UART_IRQn); - /* Set a flag for the system that the UART has been initialized */ - done_uart_init_yet = 1; -} diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h deleted file mode 100644 index a2de0cc0a0..0000000000 --- a/chip/max32660/uart_regs.h +++ /dev/null @@ -1,677 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the UART Peripheral */ - -#ifndef _UART_REGS_H_ -#define _UART_REGS_H_ - -/* **** Includes **** */ -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/** - * Structure type to access the UART Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */ - __IO uint32_t - thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */ - __I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */ - __IO uint32_t int_en; /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */ - __IO uint32_t int_fl; /**< <tt>\b 0x10:<\tt> UART INT_FL Register */ - __IO uint32_t baud0; /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */ - __IO uint32_t baud1; /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */ - __IO uint32_t fifo; /**< <tt>\b 0x1C:<\tt> UART FIFO Register */ - __IO uint32_t dma; /**< <tt>\b 0x20:<\tt> UART DMA Register */ - __IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */ -} mxc_uart_regs_t; - -/** - * UART Peripheral Register Offsets from the UART Base Peripheral - * Address. - */ -#define MXC_R_UART_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_UART_THRESH_CTRL \ - ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> \ - 0x0x004 */ -#define MXC_R_UART_STATUS \ - ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> \ - 0x0x008 */ -#define MXC_R_UART_INT_EN \ - ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> \ - 0x0x00C */ -#define MXC_R_UART_INT_FL \ - ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> \ - 0x0x010 */ -#define MXC_R_UART_BAUD0 \ - ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> \ - 0x0x014 */ -#define MXC_R_UART_BAUD1 \ - ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> \ - 0x0x018 */ -#define MXC_R_UART_FIFO \ - ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> \ - 0x0x01C */ -#define MXC_R_UART_DMA \ - ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> \ - 0x0x020 */ -#define MXC_R_UART_TX_FIFO \ - ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> \ - 0x0x024 */ - -/** - * Control Register. - */ -#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ -#define MXC_F_UART_CTRL_ENABLE \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ -#define MXC_V_UART_CTRL_ENABLE_DIS \ - ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ -#define MXC_S_UART_CTRL_ENABLE_DIS \ - (MXC_V_UART_CTRL_ENABLE_DIS \ - << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ -#define MXC_V_UART_CTRL_ENABLE_EN \ - ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \ - */ -#define MXC_S_UART_CTRL_ENABLE_EN \ - (MXC_V_UART_CTRL_ENABLE_EN \ - << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ - -#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ -#define MXC_F_UART_CTRL_PARITY_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ -#define MXC_V_UART_CTRL_PARITY_EN_DIS \ - ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ -#define MXC_S_UART_CTRL_PARITY_EN_DIS \ - (MXC_V_UART_CTRL_PARITY_EN_DIS \ - << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */ -#define MXC_V_UART_CTRL_PARITY_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ -#define MXC_S_UART_CTRL_PARITY_EN_EN \ - (MXC_V_UART_CTRL_PARITY_EN_EN \ - << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */ - -#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ -#define MXC_F_UART_CTRL_PARITY \ - ((uint32_t)( \ - 0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ -#define MXC_V_UART_CTRL_PARITY_EVEN \ - ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ -#define MXC_S_UART_CTRL_PARITY_EVEN \ - (MXC_V_UART_CTRL_PARITY_EVEN \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ -#define MXC_V_UART_CTRL_PARITY_ODD \ - ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ -#define MXC_S_UART_CTRL_PARITY_ODD \ - (MXC_V_UART_CTRL_PARITY_ODD \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ -#define MXC_V_UART_CTRL_PARITY_MARK \ - ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ -#define MXC_S_UART_CTRL_PARITY_MARK \ - (MXC_V_UART_CTRL_PARITY_MARK \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ -#define MXC_V_UART_CTRL_PARITY_SPACE \ - ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ -#define MXC_S_UART_CTRL_PARITY_SPACE \ - (MXC_V_UART_CTRL_PARITY_SPACE \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ - -#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ -#define MXC_F_UART_CTRL_PARMD \ - ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \ - */ -#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */ -#define MXC_S_UART_CTRL_PARMD_1 \ - (MXC_V_UART_CTRL_PARMD_1 \ - << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */ -#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */ -#define MXC_S_UART_CTRL_PARMD_0 \ - (MXC_V_UART_CTRL_PARMD_0 \ - << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */ - -#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ -#define MXC_F_UART_CTRL_TX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ - -#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ -#define MXC_F_UART_CTRL_RX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ - -#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ -#define MXC_F_UART_CTRL_BITACC \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ -#define MXC_V_UART_CTRL_BITACC_FRAME \ - ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ -#define MXC_S_UART_CTRL_BITACC_FRAME \ - (MXC_V_UART_CTRL_BITACC_FRAME \ - << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */ -#define MXC_V_UART_CTRL_BITACC_BIT \ - ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ -#define MXC_S_UART_CTRL_BITACC_BIT \ - (MXC_V_UART_CTRL_BITACC_BIT \ - << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */ - -#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ -#define MXC_F_UART_CTRL_CHAR_SIZE \ - ((uint32_t)( \ - 0x3UL \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ -#define MXC_V_UART_CTRL_CHAR_SIZE_5 \ - ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_5 \ - (MXC_V_UART_CTRL_CHAR_SIZE_5 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_6 \ - ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_6 \ - (MXC_V_UART_CTRL_CHAR_SIZE_6 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_7 \ - ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_7 \ - (MXC_V_UART_CTRL_CHAR_SIZE_7 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_8 \ - ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_8 \ - (MXC_V_UART_CTRL_CHAR_SIZE_8 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ - -#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ -#define MXC_F_UART_CTRL_STOPBITS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ -#define MXC_V_UART_CTRL_STOPBITS_1 \ - ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1 \ - (MXC_V_UART_CTRL_STOPBITS_1 \ - << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */ -#define MXC_V_UART_CTRL_STOPBITS_1_5 \ - ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1_5 \ - (MXC_V_UART_CTRL_STOPBITS_1_5 \ - << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */ - -#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ -#define MXC_F_UART_CTRL_FLOW_CTRL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ -#define MXC_V_UART_CTRL_FLOW_CTRL_EN \ - ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_EN \ - (MXC_V_UART_CTRL_FLOW_CTRL_EN \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */ -#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \ - ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \ - (MXC_V_UART_CTRL_FLOW_CTRL_DIS \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */ - -#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ -#define MXC_F_UART_CTRL_FLOW_POL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ -#define MXC_V_UART_CTRL_FLOW_POL_0 \ - ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_0 \ - (MXC_V_UART_CTRL_FLOW_POL_0 \ - << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */ -#define MXC_V_UART_CTRL_FLOW_POL_1 \ - ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_1 \ - (MXC_V_UART_CTRL_FLOW_POL_1 \ - << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */ - -#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ -#define MXC_F_UART_CTRL_NULL_MODEM \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \ - Mask */ -#define MXC_V_UART_CTRL_NULL_MODEM_DIS \ - ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */ -#define MXC_S_UART_CTRL_NULL_MODEM_DIS \ - (MXC_V_UART_CTRL_NULL_MODEM_DIS \ - << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \ - */ -#define MXC_V_UART_CTRL_NULL_MODEM_EN \ - ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */ -#define MXC_S_UART_CTRL_NULL_MODEM_EN \ - (MXC_V_UART_CTRL_NULL_MODEM_EN \ - << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */ - -#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ -#define MXC_F_UART_CTRL_BREAK \ - ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \ - */ -#define MXC_V_UART_CTRL_BREAK_DIS \ - ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \ - */ -#define MXC_S_UART_CTRL_BREAK_DIS \ - (MXC_V_UART_CTRL_BREAK_DIS \ - << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */ -#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ -#define MXC_S_UART_CTRL_BREAK_EN \ - (MXC_V_UART_CTRL_BREAK_EN \ - << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */ - -#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ -#define MXC_F_UART_CTRL_CLKSEL \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ -#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \ - ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ -#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \ - (MXC_V_UART_CTRL_CLKSEL_SYSTEM \ - << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */ -#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ - ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ -#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \ - (MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ - << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */ - -#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ -#define MXC_F_UART_CTRL_RX_TO \ - ((uint32_t)( \ - 0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ - -/** - * Threshold Control register. - */ -#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \ - 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_RX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \ - 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_TX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \ - 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_RTS_FIFO_THRESH \ - Mask */ - -/** - * Status Register. - */ -#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ -#define MXC_F_UART_STATUS_TX_BUSY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ - -#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ -#define MXC_F_UART_STATUS_RX_BUSY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ - -#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ -#define MXC_F_UART_STATUS_PARITY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ - -#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ -#define MXC_F_UART_STATUS_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ - -#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ -#define MXC_F_UART_STATUS_RX_EMPTY \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \ - Mask */ - -#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ -#define MXC_F_UART_STATUS_RX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - -#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ -#define MXC_F_UART_STATUS_TX_EMPTY \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \ - Mask */ - -#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ -#define MXC_F_UART_STATUS_TX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - -#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS \ - 8 /**< STATUS_RX_FIFO_CNT Position \ - */ -#define MXC_F_UART_STATUS_RX_FIFO_CNT \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \ - Mask */ - -#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS \ - 16 /**< STATUS_TX_FIFO_CNT Position \ - */ -#define MXC_F_UART_STATUS_TX_FIFO_CNT \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \ - Mask */ - -#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */ -#define MXC_F_UART_STATUS_RX_TO \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */ - -/** - * Interrupt Enable Register. - */ -#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \ - 0 /**< INT_EN_RX_FRAME_ERROR Position */ -#define MXC_F_UART_INT_EN_RX_FRAME_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< \ - INT_EN_RX_FRAME_ERROR \ - Mask */ - -#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \ - 1 /**< INT_EN_RX_PARITY_ERROR Position */ -#define MXC_F_UART_INT_EN_RX_PARITY_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< \ - INT_EN_RX_PARITY_ERROR \ - Mask */ - -#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ -#define MXC_F_UART_INT_EN_CTS_CHANGE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE \ - Mask */ - -#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ -#define MXC_F_UART_INT_EN_RX_OVERRUN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN \ - Mask */ - -#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \ - 4 /**< INT_EN_RX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_EN_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< \ - INT_EN_RX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \ - 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ -#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ - INT_EN_TX_FIFO_ALMOST_EMPTY \ - Mask */ - -#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \ - 6 /**< INT_EN_TX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_EN_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< \ - INT_EN_TX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ -#define MXC_F_UART_INT_EN_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ - -#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ -#define MXC_F_UART_INT_EN_RX_TIMEOUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT \ - Mask */ - -#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ -#define MXC_F_UART_INT_EN_LAST_BREAK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK \ - Mask */ - -/** - * Interrupt Status Flags. - */ -#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \ - 0 /**< INT_FL_RX_FRAME_ERROR Position */ -#define MXC_F_UART_INT_FL_RX_FRAME_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< \ - INT_FL_RX_FRAME_ERROR \ - Mask */ - -#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \ - 1 /**< INT_FL_RX_PARITY_ERROR Position */ -#define MXC_F_UART_INT_FL_RX_PARITY_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< \ - INT_FL_RX_PARITY_ERROR \ - Mask */ - -#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ -#define MXC_F_UART_INT_FL_CTS_CHANGE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE \ - Mask */ - -#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ -#define MXC_F_UART_INT_FL_RX_OVERRUN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN \ - Mask */ - -#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \ - 4 /**< INT_FL_RX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_FL_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< \ - INT_FL_RX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \ - 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ -#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ - INT_FL_TX_FIFO_ALMOST_EMPTY \ - Mask */ - -#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \ - 6 /**< INT_FL_TX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_FL_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< \ - INT_FL_TX_FIFO_THRESH \ - Mask */ - -#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ -#define MXC_F_UART_INT_FL_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ - -#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ -#define MXC_F_UART_INT_FL_RX_TIMEOUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT \ - Mask */ - -#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ -#define MXC_F_UART_INT_FL_LAST_BREAK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK \ - Mask */ - -/** - * Baud rate register. Integer portion. - */ -#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ -#define MXC_F_UART_BAUD0_IBAUD \ - ((uint32_t)(0xFFFUL \ - << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ - -#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ -#define MXC_F_UART_BAUD0_FACTOR \ - ((uint32_t)(0x3UL \ - << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ -#define MXC_V_UART_BAUD0_FACTOR_128 \ - ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ -#define MXC_S_UART_BAUD0_FACTOR_128 \ - (MXC_V_UART_BAUD0_FACTOR_128 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_64 \ - ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ -#define MXC_S_UART_BAUD0_FACTOR_64 \ - (MXC_V_UART_BAUD0_FACTOR_64 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_32 \ - ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ -#define MXC_S_UART_BAUD0_FACTOR_32 \ - (MXC_V_UART_BAUD0_FACTOR_32 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_16 \ - ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ -#define MXC_S_UART_BAUD0_FACTOR_16 \ - (MXC_V_UART_BAUD0_FACTOR_16 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ - -/** - * Baud rate register. Decimal Setting. - */ -#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ -#define MXC_F_UART_BAUD1_DBAUD \ - ((uint32_t)(0xFFFUL \ - << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ - -/** - * FIFO Data buffer. - */ -#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ -#define MXC_F_UART_FIFO_FIFO \ - ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \ - */ - - -/** - * DMA Configuration. - */ -#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */ -#define MXC_F_UART_DMA_TDMA_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */ -#define MXC_V_UART_DMA_TDMA_EN_DIS \ - ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_TDMA_EN_DIS \ - (MXC_V_UART_DMA_TDMA_EN_DIS \ - << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */ -#define MXC_V_UART_DMA_TDMA_EN_EN \ - ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \ - */ -#define MXC_S_UART_DMA_TDMA_EN_EN \ - (MXC_V_UART_DMA_TDMA_EN_EN \ - << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */ - -#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ -#define MXC_F_UART_DMA_RXDMA_EN \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ -#define MXC_V_UART_DMA_RXDMA_EN_DIS \ - ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_RXDMA_EN_DIS \ - (MXC_V_UART_DMA_RXDMA_EN_DIS \ - << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ -#define MXC_V_UART_DMA_RXDMA_EN_EN \ - ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ -#define MXC_S_UART_DMA_RXDMA_EN_EN \ - (MXC_V_UART_DMA_RXDMA_EN_EN \ - << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ - -#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ -#define MXC_F_UART_DMA_TXDMA_LEVEL \ - ((uint32_t)(0x3FUL \ - << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \ - Mask */ - -#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ -#define MXC_F_UART_DMA_RXDMA_LEVEL \ - ((uint32_t)(0x3FUL \ - << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \ - Mask */ - -/** - * Transmit FIFO Status register. - */ -#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ -#define MXC_F_UART_TX_FIFO_DATA \ - ((uint32_t)(0x7FUL \ - << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ - -#endif /* _UART_REGS_H_ */ diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c deleted file mode 100644 index 1c99c798fc..0000000000 --- a/chip/max32660/wdt_chip.c +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Watchdog Module */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "task.h" -#include "util.h" -#include "watchdog.h" -#include "console.h" -#include "registers.h" -#include "board.h" -#include "wdt_regs.h" - -#define CPUTS(outstr) cputs(CC_COMMAND, outstr) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) - -/* For a System clock of 96MHz, - * Time in seconds = 96000000 / 2 * 2^power - * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 - * Time in seconds = 96000000 / 2 * 2^29 - * = 11.1 Seconds - */ -#define WATCHDOG_TIMER_PERIOD MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 - -volatile int starve_dog = 0; - -void watchdog_reload(void) -{ - if (!starve_dog) { - /* Reset the watchdog */ - MXC_WDT0->rst = 0x00A5; - MXC_WDT0->rst = 0x005A; - } -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - /* Set the Watchdog period */ - MXC_SETFIELD(MXC_WDT0->ctrl, MXC_F_WDT_CTRL_RST_PERIOD, - (WATCHDOG_TIMER_PERIOD << 4)); - - /* We want the WD to reset us if it is not fed in time. */ - MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_RST_EN; - /* Enable the watchdog */ - MXC_WDT0->ctrl |= MXC_F_WDT_CTRL_WDT_EN; - /* Reset the watchdog */ - MXC_WDT0->rst = 0x00A5; - MXC_WDT0->rst = 0x005A; - return EC_SUCCESS; -} - -static int command_watchdog_test(int argc, char **argv) -{ - starve_dog = 1; - - CPRINTS("done command_watchdog_test."); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(wdttest, command_watchdog_test, "wdttest", - "Force a WDT reset."); diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h deleted file mode 100644 index 32d6fe0925..0000000000 --- a/chip/max32660/wdt_regs.h +++ /dev/null @@ -1,355 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MAX32660 Registers, Bit Masks and Bit Positions for the WDT Peripheral */ - -#ifndef _WDT_REGS_H_ -#define _WDT_REGS_H_ - -#include <stdint.h> - -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif - -/** - * Structure type to access the WDT Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> WDT CTRL Register */ - __O uint32_t rst; /**< <tt>\b 0x04:<\tt> WDT RST Register */ -} mxc_wdt_regs_t; - -/** - * WDT Peripheral Register Offsets from the WDT Base Peripheral - * Address. - */ -#define MXC_R_WDT_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> \ - 0x0x000 */ -#define MXC_R_WDT_RST \ - ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> \ - 0x0x004 */ - -/** - * Watchdog Timer Control Register. - */ -#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ -#define MXC_F_WDT_CTRL_INT_PERIOD \ - ((uint32_t)( \ - 0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD \ - Mask */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ - ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ - ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ - ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ - ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ - ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ - ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ - ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ - ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ - ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ - ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ - ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ - ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ - ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ - ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ - ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 \ - Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ - ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 \ - Setting */ - -#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ -#define MXC_F_WDT_CTRL_RST_PERIOD \ - ((uint32_t)( \ - 0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD \ - Mask */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ - ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ - ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ - ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ - ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ - ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ - ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ - ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ - ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ - ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ - ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ - ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ - ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ - ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ - ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ - ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 \ - Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ - ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 \ - Setting */ - -#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ -#define MXC_F_WDT_CTRL_WDT_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ -#define MXC_V_WDT_CTRL_WDT_EN_DIS \ - ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_WDT_EN_DIS \ - (MXC_V_WDT_CTRL_WDT_EN_DIS \ - << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_WDT_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \ - */ -#define MXC_S_WDT_CTRL_WDT_EN_EN \ - (MXC_V_WDT_CTRL_WDT_EN_EN \ - << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */ - -#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ -#define MXC_F_WDT_CTRL_INT_FLAG \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ -#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ - ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */ -#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE \ - (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ - << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting \ - */ -#define MXC_V_WDT_CTRL_INT_FLAG_PENDING \ - ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */ -#define MXC_S_WDT_CTRL_INT_FLAG_PENDING \ - (MXC_V_WDT_CTRL_INT_FLAG_PENDING \ - << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */ - -#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ -#define MXC_F_WDT_CTRL_INT_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ -#define MXC_V_WDT_CTRL_INT_EN_DIS \ - ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_INT_EN_DIS \ - (MXC_V_WDT_CTRL_INT_EN_DIS \ - << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_INT_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \ - */ -#define MXC_S_WDT_CTRL_INT_EN_EN \ - (MXC_V_WDT_CTRL_INT_EN_EN \ - << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */ - -#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ -#define MXC_F_WDT_CTRL_RST_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ -#define MXC_V_WDT_CTRL_RST_EN_DIS \ - ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */ -#define MXC_S_WDT_CTRL_RST_EN_DIS \ - (MXC_V_WDT_CTRL_RST_EN_DIS \ - << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_RST_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \ - */ -#define MXC_S_WDT_CTRL_RST_EN_EN \ - (MXC_V_WDT_CTRL_RST_EN_EN \ - << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */ - -#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ -#define MXC_F_WDT_CTRL_RST_FLAG \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ -#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ - ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */ -#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT \ - (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ - << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */ -#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ - ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */ -#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED \ - (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ - << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting \ - */ - -/** - * Watchdog Timer Reset Register. - */ -#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ -#define MXC_F_WDT_RST_WDT_RST \ - ((uint32_t)( \ - 0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ -#define MXC_V_WDT_RST_WDT_RST_SEQ0 \ - ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ0 \ - (MXC_V_WDT_RST_WDT_RST_SEQ0 \ - << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ -#define MXC_V_WDT_RST_WDT_RST_SEQ1 \ - ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ1 \ - (MXC_V_WDT_RST_WDT_RST_SEQ1 \ - << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ - -#endif /* _WDT_REGS_H_ */ diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c deleted file mode 100644 index e8ec10a0e5..0000000000 --- a/chip/mchp/adc.c +++ /dev/null @@ -1,158 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "adc_chip.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "tfdp_chip.h" - -/* - * Conversion on a single channel takes less than 12 ms. Set timeout to - * 15 ms so that we have a 3-ms margin. - */ -#define ADC_SINGLE_READ_TIME 15000 - -struct mutex adc_lock; - -/* - * Volatile should not be needed. - * ADC ISR only reads task_waiting. - * Two other non-ISR routines only write task_waiting when - * interrupt is disabled or before starting ADC. - */ -static task_id_t task_waiting; - -/* - * Start ADC single-shot conversion. - * 1. Disable ADC interrupt. - * 2. Clear sticky hardware status. - * 3. Start conversion. - * 4. Enable interrupt. - * 5. Wait with timeout for ADC ISR to - * to set TASK_EVENT_TIMER. - */ -static int start_single_and_wait(int timeout) -{ - int event; - - MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - task_waiting = task_get_current(); - - /* clear all R/W1C channel status */ - MCHP_ADC_STS = 0xffffu; - /* clear R/W1C single done status */ - MCHP_ADC_CTRL |= BIT(7); - /* clear GIRQ single status */ - MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - /* make sure all writes are issued before starting conversion */ - asm volatile ("dsb"); - - /* Start conversion */ - MCHP_ADC_CTRL |= BIT(1); - - MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - - /* Wait for interrupt, ISR disables interrupt */ - event = task_wait_event(timeout); - task_waiting = TASK_ID_INVALID; - return event != TASK_EVENT_TIMER; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - - mutex_lock(&adc_lock); - - MCHP_ADC_SINGLE = 1 << adc->channel; - - if (start_single_and_wait(ADC_SINGLE_READ_TIME)) - value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) / - adc->factor_div + adc->shift; - else - value = ADC_READ_ERROR; - - mutex_unlock(&adc_lock); - return value; -} - -int adc_read_all_channels(int *data) -{ - int i; - int ret = EC_SUCCESS; - const struct adc_t *adc; - - mutex_lock(&adc_lock); - - MCHP_ADC_SINGLE = 0; - for (i = 0; i < ADC_CH_COUNT; ++i) - MCHP_ADC_SINGLE |= 1 << adc_channels[i].channel; - - if (!start_single_and_wait(ADC_SINGLE_READ_TIME * ADC_CH_COUNT)) { - ret = EC_ERROR_TIMEOUT; - goto exit_all_channels; - } - - for (i = 0; i < ADC_CH_COUNT; ++i) { - adc = adc_channels + i; - data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) / - adc->factor_div + adc->shift; - } - -exit_all_channels: - mutex_unlock(&adc_lock); - - return ret; -} - -/* - * Enable GPIO pins. - * Using MEC17xx direct mode interrupts. Do not - * set Interrupt Aggregator Block Enable bit - * for GIRQ containing ADC. - */ -static void adc_init(void) -{ - trace0(0, ADC, 0, "adc_init"); - - gpio_config_module(MODULE_ADC, 1); - - /* clear ADC sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC); - - /* Activate ADC module */ - MCHP_ADC_CTRL |= BIT(0); - - /* Enable interrupt */ - task_waiting = TASK_ID_INVALID; - MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - task_enable_irq(MCHP_IRQ_ADC_SNGL); -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); - -void adc_interrupt(void) -{ - MCHP_INT_DISABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - - /* clear individual chan conversion status */ - MCHP_ADC_STS = 0xffffu; - - /* Clear interrupt status bit */ - MCHP_ADC_CTRL |= BIT(7); - - MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; - - if (task_waiting != TASK_ID_INVALID) - task_wake(task_waiting); -} -DECLARE_IRQ(MCHP_IRQ_ADC_SNGL, adc_interrupt, 2); diff --git a/chip/mchp/adc_chip.h b/chip/mchp/adc_chip.h deleted file mode 100644 index 4b1f8df8f1..0000000000 --- a/chip/mchp/adc_chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MCHP MEC specific ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - int channel; -}; - -/* - * Boards must provide this list of ADC channel definitions. - * This must match the enum adc_channel list provided by the board. - */ -extern const struct adc_t adc_channels[]; - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 1023 - -/* Just plain id mapping for code readability */ -#define MCHP_ADC_CH(x) (x) - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk deleted file mode 100644 index cea514ec43..0000000000 --- a/chip/mchp/build.mk +++ /dev/null @@ -1,100 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Microchip(MCHP) MEC chip specific files build -# - -# pass verbose build setting to SPI image generation script -SCRIPTVERBOSE= -ifeq ($(V),1) -SCRIPTVERBOSE=--verbose -endif - -# MCHP MEC SoC's have a Cortex-M4 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 - -# JTAG debug with Keil ARM MDK debugger -# do not allow GCC dwarf debug extensions -#CFLAGS_DEBUG_EXTRA=-gdwarf-3 -gstrict-dwarf - -LDFLAGS_EXTRA= - -ifeq ($(CONFIG_LTO),y) -# Re-include the core's build.mk file so we can remove the lto flag. -include core/$(CORE)/build.mk -endif - -# Required chip modules -chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o -chip-$(CONFIG_ADC)+=adc.o -chip-$(CONFIG_DMA)+=dma.o -chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o -chip-$(CONFIG_FANS)+=fan.o -chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o -chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_MEC_GPIO_EC_CMDS)+=gpio_cmds.o -chip-$(CONFIG_HOSTCMD_X86)+=lpc.o -chip-$(CONFIG_MCHP_GPSPI)+=gpspi.o -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_SPI)+=spi.o qmspi.o -chip-$(CONFIG_TFDP)+=tfdp.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif - -# location of the scripts and keys used to pack the SPI flash image -SCRIPTDIR:=./chip/${CHIP}/util - -# Allow SPI size to be overridden by board specific size, default to 512KB -CHIP_SPI_SIZE_KB?=512 - -TEST_SPI= -ifeq ($(CONFIG_MCHP_LFW_DEBUG),y) - TEST_SPI=--test_spi -endif - -# pack_ec.py creates SPI flash image for MEC -# _rw_size is CONFIG_RW_SIZE -# Commands to convert $^ to $@.tmp -cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \ - ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \ - --loader_file $(chip-lfw-flat) ${TEST_SPI} \ - --spi_size ${CHIP_SPI_SIZE_KB} \ - --image_size $(_rw_size) ${SCRIPTVERBOSE}; rm -f $@.tmp1 - -chip-lfw = chip/${CHIP}/lfw/ec_lfw -chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat - -# build these specifically for lfw with -lfw suffix -objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \ - $(addprefix common/, util gpio) \ - $(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \ - core/$(CORE)/cpu $(chip-lfw)) - -# reuse version.o (and its dependencies) from main board -objs_lfw += $(out)/RW/common/version.o - -dirs-y+=chip/$(CHIP)/lfw - -# objs with -lfw suffix are to include lfw's gpio -$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY) -# Remove the lto flag for the loader. It actually causes it to bloat in size. -ifeq ($(CONFIG_LTO),y) -$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU)) -endif -$(out)/RW/%-lfw.o: %.c - $(call quiet,c_to_o,CC ) - -# let lfw's elf link only with selected objects -$(out)/RW/%-lfw.elf: private objs = $(objs_lfw) -$(out)/RW/%-lfw.elf: override shlib := -$(out)/RW/%-lfw.elf: %.ld $(objs_lfw) - $(call quiet,elf,LD ) - -# final image needs lfw loader -$(out)/$(PROJECT).bin: $(chip-lfw-flat) diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c deleted file mode 100644 index ad8c47d38e..0000000000 --- a/chip/mchp/clock.c +++ /dev/null @@ -1,763 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" -#include "tfdp_chip.h" -#include "vboot_hash.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -#ifdef CONFIG_LOW_POWER_IDLE - -#define HTIMER_DIV_1_US_MAX (1998848) -#define HTIMER_DIV_1_1SEC (0x8012) - -/* Recovery time for HvySlp2 is 0 usec */ -#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 - -#define SET_HTIMER_DELAY_USEC 200 - -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t total_idle_dsleep_time_us; - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG -static uint32_t pcr_slp_en[MCHP_PCR_SLP_RST_REG_MAX]; -static uint32_t pcr_clk_req[MCHP_PCR_SLP_RST_REG_MAX]; -static uint32_t ecia_result[MCHP_INT_GIRQ_NUM]; -#endif - -/* - * Fixed amount of time to keep the console in use flag true after - * boot in order to give a permanent window in which the heavy sleep - * mode is not used. - */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) -static int console_in_use_timeout_sec = 60; -static timestamp_t console_expire_time; -#endif /*CONFIG_LOW_POWER_IDLE */ - -static int freq = 48000000; - -void clock_wait_cycles(uint32_t cycles) -{ - asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); -} - -int clock_get_freq(void) -{ - return freq; -} - -/** clock_init - * @note - * MCHP MEC implements 4 control bits in the VBAT Clock Enable register. - * It also implements an internal silicon 32KHz +/- 2% oscillator powered - * by VBAT. - * b[3] = XOSEL 0=parallel, 1=single-ended - * b[2] = 32KHZ_SOURCE specifies source of always-on clock domain - * 0=internal silicon oscillator - * 1=crystal XOSEL pin(s) - * b[1] = EXT_32K use always-on clock domain or external 32KHZ_IN pin - * 0=32K source is always-on clock domain - * 1=32K source is 32KHZ_IN pin (GPIO 0165) - * b[0] = 32K_SUPPRESS - * 0=32K clock domain stays enabled if VTR is off. Powered by VBAT - * 1=32K clock domain is disabled if VTR is off. - * Set b[3] based on CONFIG_CLOCK_CRYSTAL - * Set b[2:0] = 100b - * b[0]=0 32K clock domain always on (requires VBAT if VTR is off) - * b[1]=0 32K source is the 32K clock domain NOT the 32KHZ_IN pin - * b[2]=1 If activity detected on crystal pins switch 32K input from - * internal silicon oscillator to XOSEL pin(s) based on b[3]. - */ -void clock_init(void) -{ - int __attribute__((unused)) dummy; - - trace0(0, MEC, 0, "Clock Init"); - -#ifdef CONFIG_CLOCK_CRYSTAL - /* XOSEL: 0 = Parallel resonant crystal */ - MCHP_VBAT_CE &= ~(1ul << 3); - -#else - /* XOSEL: 1 = Single ended clock source */ - MCHP_VBAT_CE |= (1ul << 3); -#endif - - /* 32K clock enable */ - MCHP_VBAT_CE = (MCHP_VBAT_CE & ~(0x03)) | (1ul << 2); - -#ifdef CONFIG_CLOCK_CRYSTAL - /* Wait for crystal to stabilize (OSC_LOCK == 1) */ - while (!(MCHP_PCR_CHIP_OSC_ID & 0x100)) - ; -#endif - trace0(0, MEC, 0, "PLL OSC is Locked"); -#ifndef LFW - dummy = shared_mem_size(); - trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)dummy); -#endif -} - -/** - * Speed through boot + vboot hash calculation, dropping our processor - * clock only after vboot hashing is completed. - */ -static void clock_turbo_disable(void); -DECLARE_DEFERRED(clock_turbo_disable); - -static void clock_turbo_disable(void) -{ -#ifdef CONFIG_VBOOT_HASH - if (vboot_hash_in_progress()) - hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC); - else -#endif - /* Use 12 MHz processor clock for power savings */ - MCHP_PCR_PROC_CLK_CTL = 4; -} -DECLARE_HOOK(HOOK_INIT, - clock_turbo_disable, - HOOK_PRIO_INIT_VBOOT_HASH + 1); - -/** - * initialization of Hibernation timer0 - * Clear PCR sleep enable. - * GIRQ=21, aggregator bit = 1, Direct NVIC = 112 - * NVIC direct connect interrupts are used for all peripherals - * (exception GPIO's) then the MCHP_INT_BLK_EN GIRQ bit should not be - * set. - */ -void htimer_init(void) -{ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_HTMR0); - MCHP_HTIMER_PRELOAD(0) = 0; /* disable at beginning */ - MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = - MCHP_HTIMER_GIRQ_BIT(0); - MCHP_INT_ENABLE(MCHP_HTIMER_GIRQ) = - MCHP_HTIMER_GIRQ_BIT(0); - - task_enable_irq(MCHP_IRQ_HTIMER0); -} - -/** - * Use hibernate module to set up an htimer interrupt at a given - * time from now - * - * @param seconds Number of seconds before htimer interrupt - * @param microseconds Number of microseconds before htimer interrupt - * @note hibernation timer input clock is 32.768KHz. - * Control register bit[0] selects the divider. - * 0 is divide by 1 for 30.5us per LSB for a maximum of - * 65535 * 30.5us = 1998817.5 us or 32.786 counts per second - * 1 is divide by 4096 for 0.125s per LSB for a maximum of ~2 hours. - * 65535 * 0.125s ~ 8192 s = 2.27 hours - */ -void system_set_htimer_alarm(uint32_t seconds, - uint32_t microseconds) -{ - uint32_t hcnt, ns; - uint8_t hctrl; - - MCHP_HTIMER_PRELOAD(0) = 0; /* disable */ - - trace12(0, SLP, 0, "sys set htimer: sec=%d us=%d", - seconds, microseconds); - - if (microseconds > 1000000ul) { - ns = (microseconds / 1000000ul); - microseconds %= 1000000ul; - if ((0xfffffffful - seconds) > ns) - seconds += ns; - else - seconds = 0xfffffffful; - } - - if (seconds > 1) { - hcnt = (seconds << 3); /* divide by 0.125 */ - if (hcnt > 0xfffful) - hcnt = 0xfffful; - hctrl = 1; - } else { - /* - * approximate(~2% error) as seconds is 0 or 1 - * seconds / 30.5e-6 + microseonds / 30.5 - */ - hcnt = (seconds << 15) + (microseconds >> 5) + - (microseconds >> 10); - hctrl = 0; - } - - trace12(0, SLP, 0, - "sys set htimer: ctrl=0x%0x preload=0x%0x", - hctrl, hcnt); - MCHP_HTIMER_CONTROL(0) = hctrl; - MCHP_HTIMER_PRELOAD(0) = hcnt; -} - -#ifdef CONFIG_LOW_POWER_IDLE - -/** - * return time slept in micro-seconds - */ -static timestamp_t system_get_htimer(void) -{ - uint16_t count; - timestamp_t time; - - count = MCHP_HTIMER_COUNT(0); - - - if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */ - /* 0.125 sec per count */ - time.le.lo = (uint32_t)(count * 125000); - else /* if < 2 sec */ - /* 30.5(=61/2)usec per count */ - time.le.lo = (uint32_t)(count * 61 / 2); - - time.le.hi = 0; - - return time; /* in uSec */ -} - -/** - * Disable and clear hibernation timer interrupt - */ -static void system_reset_htimer_alarm(void) -{ - MCHP_HTIMER_PRELOAD(0) = 0; - MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = - MCHP_HTIMER_GIRQ_BIT(0); -} - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG -static void print_pcr_regs(void) -{ - int i; - - trace0(0, MEC, 0, "Current PCR registers"); - for (i = 0; i < 5; i++) { - trace12(0, MEC, 0, "REG SLP_EN[%d] = 0x%08X", - i, MCHP_PCR_SLP_EN(i)); - trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X", - i, MCHP_PCR_CLK_REQ(i)); - } -} - -static void print_ecia_regs(void) -{ - int i; - - trace0(0, MEC, 0, "Current GIRQn.Result registers"); - for (i = MCHP_INT_GIRQ_FIRST; - i <= MCHP_INT_GIRQ_LAST; i++) - trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X", - i, MCHP_INT_RESULT(i)); -} - -static void save_regs(void) -{ - int i; - - for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) { - pcr_slp_en[i] = MCHP_PCR_SLP_EN(i); - pcr_clk_req[i] = MCHP_PCR_CLK_REQ(i); - } - - for (i = 0; i < MCHP_INT_GIRQ_NUM; i++) - ecia_result[i] = - MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i); -} - -static void print_saved_regs(void) -{ - int i; - - trace0(0, BRD, 0, "Before sleep saved registers"); - for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) { - trace12(0, BRD, 0, "PCR_SLP_EN[%d] = 0x%08X", - i, pcr_slp_en[i]); - trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X", - i, pcr_clk_req[i]); - } - - for (i = 0; i < MCHP_INT_GIRQ_NUM; i++) - trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X", - (i+MCHP_INT_GIRQ_FIRST), ecia_result[i]); -} -#endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */ - -/** - * This is MCHP specific and equivalent to ARM Cortex's - * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL - * MCHP has new SLP_ALL feature. - * When SLP_ALL is enabled and HW sees sleep entry trigger from CPU. - * 1. HW saves PCR.SLP_EN registers - * 2. HW sets all PCR.SLP_EN bits to 1. - * 3. System sleeps - * 4. wake event wakes system - * 5. HW restores original values of all PCR.SLP_EN registers - * NOTE1: Current RTOS core (Cortex-Mx) does not use SysTick timer. - * We can leave code to disable it but do not re-enable on wake. - * NOTE2: Some peripherals will not sleep until outstanding transactions - * are complete: I2C, DMA, GPSPI, QMSPI, etc. - * NOTE3: Security blocks do not fully implement HW sleep therefore their - * sleep enables must be manually set/restored. - * - */ -static void prepare_for_deep_sleep(void) -{ - trace0(0, MEC, 0, "Prepare for Deep Sleep"); - - /* sysTick timer */ - CPU_NVIC_ST_CTRL &= ~ST_ENABLE; - CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG; - - CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */ - - /* Enable assertion of DeepSleep signals - * from the core when core enters sleep. - */ - CPU_SCB_SYSCTRL |= BIT(2); - - /* Stop timers */ - MCHP_TMR32_CTL(0) &= ~1; - MCHP_TMR32_CTL(1) &= ~1; -#ifdef CONFIG_WATCHDOG_HELP - MCHP_TMR16_CTL(0) &= ~1; - MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); - MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); -#endif - MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); - MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); - -#ifdef CONFIG_WATCHDOG - /* Stop watchdog */ - MCHP_WDG_CTL &= ~1; -#endif - - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; - MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; -#else - MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC; - MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_LPC; -#endif - -#ifdef CONFIG_ADC - /* - * Clear ADC activate bit. If a conversion is in progress the - * ADC block will not enter low power until the converstion is - * complete. - */ - MCHP_ADC_CTRL &= ~1; -#endif - - /* stop Port80 capture timer */ - MCHP_P80_ACTIVATE(0) = 0; - - /* - * Clear SLP_EN bit(s) for wake sources. - * Currently only Hibernation timer 0. - * GPIO pins can always wake. - */ - MCHP_PCR_SLP_EN3 &= ~(MCHP_PCR_SLP_EN3_HTMR0); - -#ifdef CONFIG_PWM - pwm_keep_awake(); /* clear sleep enables of active PWM's */ -#else - /* Disable 100 Khz clock */ - MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; -#endif - -#ifdef CONFIG_CHIPSET_DEBUG - /* Disable JTAG and preserve mode */ - MCHP_EC_JTAG_EN &= ~(MCHP_JTAG_ENABLE); -#endif - - /* call board level */ -#ifdef CONFIG_BOARD_DEEP_SLEEP - board_prepare_for_deep_sleep(); -#endif - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG - save_regs(); -#endif -} - -static void resume_from_deep_sleep(void) -{ - trace0(0, MEC, 0, "resume_from_deep_sleep"); - - MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */ - - /* Disable assertion of DeepSleep signal when core executes WFI */ - CPU_SCB_SYSCTRL &= ~BIT(2); - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG - print_saved_regs(); - print_pcr_regs(); - print_ecia_regs(); -#endif - -#ifdef CONFIG_CHIPSET_DEBUG - MCHP_EC_JTAG_EN |= (MCHP_JTAG_ENABLE); -#endif - - MCHP_PCR_SLOW_CLK_CTL |= 0x1e0; - - /* call board level */ -#ifdef CONFIG_BOARD_DEEP_SLEEP - board_resume_from_deep_sleep(); -#endif - /* - * re-enable hibernation timer 0 PCR.SLP_EN to - * reduce power. - */ - MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0); - -#ifdef CONFIG_HOSTCMD_ESPI - #ifdef CONFIG_POWER_S0IX - MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; - MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; - #else - MCHP_ESPI_ACTIVATE |= 1; - #endif -#else - #ifdef CONFIG_POWER_S0IX - MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC; - MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC; - #else - MCHP_LPC_ACT |= 1; - #endif -#endif - - /* re-enable Port80 capture */ - MCHP_P80_ACTIVATE(0) = 1; - -#ifdef CONFIG_ADC - MCHP_ADC_CTRL |= 1; -#endif - - /* Enable timer */ - MCHP_TMR32_CTL(0) |= 1; - MCHP_TMR32_CTL(1) |= 1; - MCHP_TMR16_CTL(0) |= 1; - MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); - MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); - - /* Enable watchdog */ -#ifdef CONFIG_WATCHDOG -#ifdef CONFIG_CHIPSET_DEBUG - /* enable WDG stall on active JTAG and do not start */ - MCHP_WDG_CTL = BIT(4); -#else - MCHP_WDG_CTL |= 1; -#endif -#endif -} - - -void clock_refresh_console_in_use(void) -{ - disable_sleep(SLEEP_MASK_CONSOLE); - - /* Set console in use expire time. */ - console_expire_time = get_time(); - console_expire_time.val += console_in_use_timeout_sec * SECOND; -} - -/** - * Low power idle task. Executed when no tasks are ready to be scheduled. - */ -void __idle(void) -{ - timestamp_t t0; - timestamp_t t1; - timestamp_t ht_t1; - uint32_t next_delay; - uint32_t max_sleep_time; - int time_for_dsleep; - int uart_ready_for_deepsleep; - - htimer_init(); /* hibernation timer initialize */ - - disable_sleep(SLEEP_MASK_CONSOLE); - console_expire_time.val = get_time().val + - CONSOLE_IN_USE_ON_BOOT_TIME; - - - /* - * Print when the idle task starts. This is the lowest priority - * task, so this only starts once all other tasks have gotten a - * chance to do their task inits and have gone to sleep. - */ - CPRINTS("MEC1701 low power idle task started"); - - while (1) { - /* Disable interrupts */ - interrupt_disable(); - - t0 = get_time(); /* uSec */ - - /* __hw_clock_event_get() is next programmed timer event */ - next_delay = __hw_clock_event_get() - t0.le.lo; - - time_for_dsleep = next_delay > - (HEAVY_SLEEP_RECOVER_TIME_USEC + - SET_HTIMER_DELAY_USEC); - - max_sleep_time = next_delay - - HEAVY_SLEEP_RECOVER_TIME_USEC; - - /* check if there enough time for deep sleep */ - if (DEEP_SLEEP_ALLOWED && time_for_dsleep) { - trace0(0, MEC, 0, "Enough time for Deep Sleep"); - /* - * Check if the console use has expired and - * console sleep is masked by GPIO(UART-RX) - * interrupt. - */ - if ((sleep_mask & SLEEP_MASK_CONSOLE) && - t0.val > console_expire_time.val) { - /* allow console to sleep. */ - enable_sleep(SLEEP_MASK_CONSOLE); - - /* - * Wait one clock before checking if - * heavy sleep is allowed to give time - * for sleep mask to be updated. - */ - clock_wait_cycles(1); - - if (LOW_SPEED_DEEP_SLEEP_ALLOWED) - CPRINTS("MEC1701 Disable console " - "in deepsleep"); - } - - - /* UART is not being used */ - uart_ready_for_deepsleep = - LOW_SPEED_DEEP_SLEEP_ALLOWED && - !uart_tx_in_progress() && - uart_buffer_empty(); - - /* - * Since MCHP's heavy sleep mode requires all - * blocks to be sleepable, UART/console's - * readiness is final decision factor of - * heavy sleep of EC. - */ - if (uart_ready_for_deepsleep) { - - idle_dsleep_cnt++; - - /* - * config UART Rx as GPIO wakeup - * interrupt source - */ - uart_enter_dsleep(); - - /* MCHP specific deep-sleep mode */ - prepare_for_deep_sleep(); - - /* - * 'max_sleep_time' value should be big - * enough so that hibernation timer's - * interrupt triggers only after 'wfi' - * completes its excution. - */ - max_sleep_time -= - (get_time().le.lo - t0.le.lo); - - /* setup/enable htimer wakeup interrupt */ - system_set_htimer_alarm(0, - max_sleep_time); - - /* set sleep all just before WFI */ - MCHP_PCR_SYS_SLP_CTL |= - MCHP_PCR_SYS_SLP_HEAVY; - MCHP_PCR_SYS_SLP_CTL |= - MCHP_PCR_SYS_SLP_ALL; - - } else { - idle_sleep_cnt++; - } - - /* Wait for interrupt: goes into deep sleep. */ - asm("dsb"); - asm("wfi"); - asm("isb"); - asm("nop"); - - if (uart_ready_for_deepsleep) { - - resume_from_deep_sleep(); - - /* - * Fast forward timer according to htimer - * counter: - * Since all blocks including timers - * will be in sleep mode, timers stops - * except hibernate timer. - * And system schedule timer should be - * corrected after wakeup by either - * hibernate timer or GPIO_UART_RX - * interrupt. - */ - ht_t1 = system_get_htimer(); - - /* disable/clear htimer wakeup interrupt */ - system_reset_htimer_alarm(); - - t1.val = t0.val + - (uint64_t)(max_sleep_time - - ht_t1.le.lo); - - force_time(t1); - - /* re-eanble UART */ - uart_exit_dsleep(); - - /* Record time spent in deep sleep. */ - total_idle_dsleep_time_us += - (uint64_t)(max_sleep_time - - ht_t1.le.lo); - } - - } else { /* CPU 'Sleep' mode */ - - idle_sleep_cnt++; - - asm("wfi"); - - } - - interrupt_enable(); - } /* while(1) */ -} - -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG -static void print_pcr_regs(void) -{ - int i; - - ccprintf("PCR regs before WFI\n"); - for (i = 0; i < 5; i++) { - ccprintf("PCR SLP_EN[%d] = 0x%08X\n", pcr_slp_en[i]); - ccprintf("PCR CLK_REQ[%d] = 0x%08X\n", pcr_clk_req[i]); - } -} -#endif - -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", - idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", - idle_dsleep_cnt); - - ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n", - total_idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n\n", - ts.val); - -#ifdef CONFIG_MCHP_DEEP_SLP_DEBUG - print_pcr_regs(); /* debug */ -#endif - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* defined(CONFIG_CMD_IDLE_STATS) */ - -/** - * Configure deep sleep clock settings. - */ -static int command_dsleep(int argc, char **argv) -{ - int v; - - if (argc > 1) { - if (parse_bool(argv[1], &v)) { - /* - * Force deep sleep not to use heavy sleep mode or - * allow it to use the heavy sleep mode. - */ - if (v) /* 'on' */ - disable_sleep( - SLEEP_MASK_FORCE_NO_LOW_SPEED); - else /* 'off' */ - enable_sleep( - SLEEP_MASK_FORCE_NO_LOW_SPEED); - } else { - /* Set console in use timeout. */ - char *e; - - v = strtoi(argv[1], &e, 10); - if (*e) - return EC_ERROR_PARAM1; - - console_in_use_timeout_sec = v; - - /* Refresh console in use to use new timeout. */ - clock_refresh_console_in_use(); - } - } - - ccprintf("Sleep mask: %08x\n", sleep_mask); - ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | <timeout> sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep NOT to enter heavysleep mode.\nUse 'off' to " - "allow deepsleep to use heavysleep whenever conditions " - "allow.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleepmask'."); -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h deleted file mode 100644 index 2e7de60358..0000000000 --- a/chip/mchp/clock_chip.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Microchip MEC1701 specific module for Chrome EC */ - -#ifndef __CROS_EC_CLOCK_CHIP_H -#define __CROS_EC_CLOCK_CHIP_H - -#include <stdint.h> - -void htimer_init(void); -void system_set_htimer_alarm(uint32_t seconds, - uint32_t microseconds); - -#endif /* __CROS_EC_I2C_CLOCK_H */ diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h deleted file mode 100644 index 7a0008958c..0000000000 --- a/chip/mchp/config_chip.h +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 157 - -/* Use a bigger console output buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 1024 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* - * Enable chip_pre_init called from main - * Used for configuring peripheral block - * sleep enables. - */ -#define CONFIG_CHIP_PRE_INIT - -/* - * MCHP EC's have I2C master/slave - * controllers and multiple I2C ports. Any - * port may be mapped to any controller. - * Enable multi-port controller feature. - * Board level configuration determines - * how many controllers/ports are used and - * the mapping of port(s) to controller(s). - * NOTE: Some MCHP reduced pin packages - * may not implement all 11 I2C ports. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER - -/* - * MCHP I2C controller is master-slave capable and requires - * a slave address be programmed even if used as master only. - * Each I2C controller can respond to two slave address. - * Define dummy slave addresses that aren't used on the I2C port(s) - * connected to each controller. - */ -#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1 - - -/************************************************************************/ -/* Memory mapping */ - -/* - * MEC1701H has a total of 256KB SRAM. - * CODE at 0xE0000 - 0x117FFF, DATA at 0x118000 - 0x11FFFF - * MCHP MEC can fetch code from data or data from code. - */ - -/************************************************************************/ -/* Define our RAM layout. */ - -#define CONFIG_MEC_SRAM_BASE_START 0x000E0000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 -#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_MEC_SRAM_BASE_START) - -/* 64k Data RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00010000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_RAM_SIZE) - -/* System stack size */ -/* was 1024, temporarily expanded to 2048 for debug */ -#define CONFIG_STACK_SIZE 2048 - -/* non-standard task stack sizes */ -/* temporarily expanded for debug */ -#define IDLE_TASK_STACK_SIZE 1024 /* 512 */ -#define LARGER_TASK_STACK_SIZE 1024 /* 640 */ -#define VENTI_TASK_STACK_SIZE 1024 /* 768 */ - -#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */ -#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */ -#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */ -#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */ - -/* - * TODO: Large stack consumption - * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 - */ -/* dsw original = 800, if stack exceptions expand to 1024 for debug */ -#define PD_TASK_STACK_SIZE 2048 - -/* Default task stack size */ -#define TASK_STACK_SIZE 1024 /* 512 */ - -/************************************************************************/ -/* Define our flash layout. */ - -/* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 -/* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 -/* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 - -/* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 - -/* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000 - -#include "config_flash_layout.h" - -/************************************************************************/ -/* Customize the build */ -/* Optional features present on this chip */ -#define CONFIG_ADC -#define CONFIG_DMA -#define CONFIG_HOSTCMD_X86 -#define CONFIG_SPI -#define CONFIG_SWITCH - -/* - * Enable configuration after ESPI_RESET# de-asserts - */ -#undef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT - -/* - * Enable CPRINT in chip eSPI module - * Define at board level. - */ -#undef CONFIG_MCHP_ESPI_DEBUG - -/* - * Enable EC UART commands in eSPI module useful for debugging. - */ -#undef CONFIG_MCHP_ESPI_EC_CMD - -/* - * Enable CPRINT debug messages in LPC module - */ -#undef CONFIG_MCHP_DEBUG_LPC - -/* - * Define this to use MEC1701 ROM SPI read API - * in little firmware module instead of SPI code - * from this module - */ -#undef CONFIG_CHIP_LFW_USE_ROM_SPI - -/* - * Use DMA when transmitting commands & data - * with GPSPI controllers. - */ -#define CONFIG_MCHP_GPSPI_TX_DMA - -/* - * Use DMA when transmitting command & data of length - * greater than QMSPI TX FIFO size. - */ -#define CONFIG_MCHP_QMSPI_TX_DMA - -/* - * Board level gpio.inc is using MCHP data sheet GPIO pin - * numbers which are octal. - * MCHP has 6 banks/ports each containing 32 GPIO's. - * Each bank/port is connected to a GIRQ. - * Port numbering: - * GPIO_015 = 13 decimal. Port = 13/32 = 0, bit = 13 % 32 = 13 - * GPIO_0123 = 83 decimal. Port 83/32 = 2, bit = 83 % 32 = 19 - * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal. - * You must use octal GPIO numbers in PIN(gpio_num) macro in - * gpio.inc files. - * Example: GPIO 211 in documentation 0211 = 137 = 0x89 - * GPIO(PCH_SLP_S0_L, PIN(0211), GPIO_INPUT | GPIO_PULL_DOWN) - * OR - * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN) - */ -#define GPIO_BANK(index) ((index) >> 5) -#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F)) - -#define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) - -#ifndef __ASSEMBLER__ - - -#endif /* #ifndef __ASSEMBLER__ */ - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h deleted file mode 100644 index b25ab02b06..0000000000 --- a/chip/mchp/config_flash_layout.h +++ /dev/null @@ -1,117 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H -#define __CROS_EC_CONFIG_FLASH_LAYOUT_H - -/* - * mec17xx flash layout: - * - Non memory-mapped, external SPI. - * - RW image at the beginning of writable region. - * - Bootloader at the beginning of protected region, followed by RO image. - * - Loader + (RO | RW) loaded into program memory. - */ - -/* Non-memmapped, external SPI */ -#define CONFIG_EXTERNAL_STORAGE -#undef CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE -#define CONFIG_SPI_FLASH - -/* - * MEC17xx BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04. - * One valid TAG must be present. - * TAG's point to a Header which must be located on a 256 byte - * boundary anywhere in the flash (24-bit addressing). - * Locate BootROM load Header + LFW + EC_RO at start of second - * 4KB sector (offset 0x1000). - * Locate BootROM load Header + EC_RW at start of second half of - * SPI flash. - * LFW size is 4KB - * EC_RO and EC_RW padded sizes from the build are 188KB each. - * Storage size is 1/2 flash size. - */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -/* Lower 256KB of flash is protected region */ -#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -/* Writable storage for EC_RW starts at 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -/* Writeable storage is 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 - - -/* Loader resides at the beginning of program memory */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0x1000 - -/* Write protect Loader and RO Image */ -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -/* - * Write protect LFW + EC_RO - */ -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* - * RO / RW images follow the loader in program memory. Either RO or RW - * image will be loaded -- both cannot be loaded at the same time. - */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -/* - * Total SRAM and the amount allocated for data are specified - * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h - * The little firmware (lfw) loader is resident in first 4KB of Code SRAM. - * EC_RO/RW size = Total SRAM - Data SRAM - LFW size. - * !!! EC_RO/RW size MUST be a multiple of flash erase block size. - * defined by CONFIG_FLASH_ERASE_SIZE in chip/config_chip.h - * and must be located on a erase block boundary. !!! - */ -#define CONFIG_RO_SIZE (CONFIG_MEC_SRAM_SIZE - \ - CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -/* - * NOTE: CONFIG_RW_SIZE is passed to chip/mchp/util/pack_ec.py - */ -#define CONFIG_RW_SIZE CONFIG_RO_SIZE - -/* - * WP region consists of first half of SPI containing TAGs at beginning - * of SPI flash and header + binary(LFW+EC_RO) an offset aligned on - * a 256 byte boundary. - * NOTE: Changing CONFIG_BOOT_HEADER_STORAGE_OFF requires changing - * parameter --payload_offset of pack_ec.py in build.mk! - * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device. - * We only use first TAG pointing to LFW + EC_RO. - * Header size is 128 bytes. Firmware binary is located immediately - * after the header. - * Second half of SPI flash contains: - * Header(128 bytes) + EC_RW - * EC flash erase/write commands check alginment base on - * CONFIG_FLASH_ERASE_SIZE defined in config_chip.h - * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or - * greater aligned boundaries. - */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 -#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 -#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0 - -/* Loader / lfw image immediately follows the boot header on SPI */ -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) - -/* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) - -/* - * RW image starts at offset 0 of second half of SPI. - * RW Header not needed. - */ -#define CONFIG_RW_STORAGE_OFF (CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_RW_BOOT_HEADER_STORAGE_SIZE) - - -#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c deleted file mode 100644 index 6c9ed8dd47..0000000000 --- a/chip/mchp/dma.c +++ /dev/null @@ -1,393 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "tfdp_chip.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) - -dma_chan_t *dma_get_channel(enum dma_channel channel) -{ - dma_chan_t *pd = NULL; - - if (channel < MCHP_DMAC_COUNT) { - pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS + - (channel << MCHP_DMA_CH_OFS_BITPOS)); - } - - return pd; -} - -void dma_disable(enum dma_channel channel) -{ - if (channel < MCHP_DMAC_COUNT) { - if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN) - MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN); - - if (MCHP_DMA_CH_ACT(channel) & MCHP_DMA_ACT_EN) - MCHP_DMA_CH_ACT(channel) = 0; - } -} - -void dma_disable_all(void) -{ - uint16_t ch; - uint32_t dummy = 0; - - for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) { - /* Abort any current transfer. */ - MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_ABORT; - /* Disable the channel. */ - MCHP_DMA_CH_CTRL(ch) &= ~(MCHP_DMA_RUN); - MCHP_DMA_CH_ACT(ch) = 0; - } - - /* Soft-reset the block. */ - MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST; - dummy += MCHP_DMA_MAIN_CTRL; - MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT; -} - -/** - * Prepare a channel for use and start it - * - * @param chan Channel to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register, normally: - * MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV for tx - * MCHP_DMA_INC_MEM for rx - * Plus transfer unit length(1, 2, or 4) in bits[22:20] - * @note MCHP DMA does not require address aliasing. Because count - * is the number of bytes to transfer memory start - memory end = count. - */ -static void prepare_channel(enum dma_channel ch, unsigned int count, - void *periph, void *memory, unsigned int flags) -{ - if (ch < MCHP_DMAC_COUNT) { - - MCHP_DMA_CH_CTRL(ch) = 0; - MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory; - MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count; - - MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)periph; - - MCHP_DMA_CH_CTRL(ch) = flags; - MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN; - } -} - -void dma_go(dma_chan_t *chan) -{ - /* Flush data in write buffer so that DMA can get the - * latest data. - */ - asm volatile("dsb;"); - - if (chan != NULL) - chan->ctrl |= MCHP_DMA_RUN; -} - -void dma_go_chan(enum dma_channel ch) -{ - asm volatile("dsb;"); - if (ch < MCHP_DMAC_COUNT) - MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - if (option != NULL) - /* - * Cast away const for memory pointer; this is ok because - * we know we're preparing the channel for transmit. - */ - prepare_channel(option->channel, count, option->periph, - (void *)memory, - MCHP_DMA_INC_MEM | - MCHP_DMA_TO_DEV | - MCHP_DMA_DEV(option->channel) | - option->flags); -} - -void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count, - const void *memory, uint32_t dma_xfr_units) -{ - uint32_t nflags; - - if (option != NULL) { - nflags = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK); - nflags |= MCHP_DMA_XFER_SIZE(dma_xfr_units & 0x07); - /* - * Cast away const for memory pointer; this is ok because - * we know we're preparing the channel for transmit. - */ - prepare_channel(option->channel, count, option->periph, - (void *)memory, - MCHP_DMA_INC_MEM | - MCHP_DMA_TO_DEV | - MCHP_DMA_DEV(option->channel) | - nflags); - } -} - -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) -{ - if (option != NULL) { - prepare_channel(option->channel, count, option->periph, - memory, - MCHP_DMA_INC_MEM | - MCHP_DMA_DEV(option->channel) | - option->flags); - dma_go_chan(option->channel); - } -} - -/* - * Configure and start DMA channel for read from device and write to - * memory. Allow caller to override DMA transfer unit length. - */ -void dma_xfr_start_rx(const struct dma_option *option, - uint32_t dma_xfr_ulen, - uint32_t count, void *memory) -{ - uint32_t ch, ctrl; - - if (option != NULL) { - ch = option->channel; - if (ch < MCHP_DMAC_COUNT) { - - MCHP_DMA_CH_CTRL(ch) = 0; - MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory; - MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + - count; - - MCHP_DMA_CH_DEV_ADDR(ch) = - (uint32_t)option->periph; - - ctrl = option->flags & - ~(MCHP_DMA_XFER_SIZE_MASK); - ctrl |= MCHP_DMA_INC_MEM; - ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen); - ctrl |= MCHP_DMA_DEV(option->channel); - MCHP_DMA_CH_CTRL(ch) = ctrl; - MCHP_DMA_CH_ACT(ch) = MCHP_DMA_ACT_EN; - } - - dma_go_chan(option->channel); - } -} - -/* - * Return the number of bytes transferred. - * The number of bytes transferred can be easily determined - * from the difference in DMA memory start address register - * and memory end address register. No need to look at DMA - * transfer size field because the hardware increments memory - * start address by unit size on each unit transferred. - * Why is a signed integer being used for a count value? - */ -int dma_bytes_done(dma_chan_t *chan, int orig_count) -{ - int bcnt; - - if (chan == NULL) - return 0; - - bcnt = (int)chan->mem_end; - bcnt -= (int)chan->mem_start; - bcnt = orig_count - bcnt; - - return bcnt; -} - -bool dma_is_enabled(dma_chan_t *chan) -{ - return (chan->ctrl & MCHP_DMA_RUN); -} - -int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count) -{ - uint32_t cnt; - - cnt = 0; - if (ch < MCHP_DMAC_COUNT) - if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN) - cnt = (uint32_t)orig_count - - (MCHP_DMA_CH_MEM_END(ch) - - MCHP_DMA_CH_MEM_START(ch)); - - return (int)cnt; -} - -/* - * Initialize DMA block. - * Clear PCR DMA sleep enable. - * Soft-Reset block should clear after one clock but read-back to - * be safe. - * Set block activate bit after reset. - */ -void dma_init(void) -{ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_DMA); - MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST; - MCHP_DMA_MAIN_CTRL; - MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT; -} - -int dma_wait(enum dma_channel channel) -{ - timestamp_t deadline; - - if (channel < MCHP_DMAC_COUNT) { - if (MCHP_DMA_CH_ACT(channel) == 0) - return EC_SUCCESS; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - - while (!(MCHP_DMA_CH_ISTS(channel) & - MCHP_DMA_STS_DONE)) { - - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; - } - - return EC_ERROR_INVAL; -} - -/* - * Clear all interrupt status in specified DMA channel - */ -void dma_clear_isr(enum dma_channel channel) -{ - if (channel < MCHP_DMAC_COUNT) - MCHP_DMA_CH_ISTS(channel) = 0x0f; -} - -void dma_cfg_buffers(enum dma_channel ch, const void *membuf, - uint32_t nb, const void *pdev) -{ - if (ch < MCHP_DMAC_COUNT) { - MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf; - MCHP_DMA_CH_MEM_END(ch) = (uint32_t)membuf + nb; - MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)pdev; - } -} - -/* - * ch = zero based DMA channel number - * unit_len = DMA unit size 1, 2 or 4 bytes - * flags - * b[0] = direction, 0=device_to_memory, 1=memory_to_device - * b[1] = 1 increment memory address - * b[2] = 1 increment device address - * b[3] = disable HW flow control - */ -void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, - uint8_t dev_id, uint8_t flags) -{ - uint32_t ctrl; - - if (ch < MCHP_DMAC_COUNT) { - ctrl = MCHP_DMA_XFER_SIZE(unit_len & 0x07); - ctrl += MCHP_DMA_DEV(dev_id & MCHP_DMA_DEV_MASK0); - if (flags & 0x01) - ctrl |= MCHP_DMA_TO_DEV; - if (flags & 0x02) - ctrl |= MCHP_DMA_INC_MEM; - if (flags & 0x04) - ctrl |= MCHP_DMA_INC_DEV; - if (flags & 0x08) - ctrl |= MCHP_DMA_DIS_HW_FLOW; - MCHP_DMA_CH_CTRL(ch) = ctrl; - } -} - -void dma_clr_chan(enum dma_channel ch) -{ - if (ch < MCHP_DMAC_COUNT) { - MCHP_DMA_CH_ACT(ch) = 0; - MCHP_DMA_CH_CTRL(ch) = 0; - MCHP_DMA_CH_IEN(ch) = 0; - MCHP_DMA_CH_ISTS(ch) = 0xff; - MCHP_DMA_CH_FSM_RO(ch) = MCHP_DMA_CH_ISTS(ch); - MCHP_DMA_CH_ACT(ch) = 1; - } -} - -void dma_run(enum dma_channel ch) -{ - if (ch < MCHP_DMAC_COUNT) { - if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_DIS_HW_FLOW) - MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_SW_GO; - else - MCHP_DMA_CH_CTRL(ch) |= MCHP_DMA_RUN; - } -} - -/* - * Check if DMA channel is done or stopped on error - * Returns 0 not done or stopped on error - * Returns non-zero if done or stopped. - * Caller should check bit pattern for specific bit, - * done, flow control error, and bus error. - */ -uint32_t dma_is_done_chan(enum dma_channel ch) -{ - if (ch < MCHP_DMAC_COUNT) - return (uint32_t)(MCHP_DMA_CH_ISTS(ch) & 0x07); - - return 0; -} - -/* - * Use DMA Channel 0 CRC32 ALU to compute CRC32 of data. - * Hardware implements IEEE 802.3 CRC32. - * IEEE 802.3 CRC32 initial value = 0xffffffff. - * Data must be aligned >= 4-bytes and number of bytes must - * be a multiple of 4. - */ -int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien) -{ - if ((mstart == NULL) || (nbytes == 0)) - return EC_ERROR_INVAL; - - if ((((uint32_t)mstart | nbytes) & 0x03) != 0) - return EC_ERROR_INVAL; - - MCHP_DMA_CH_ACT(0) = 0; - MCHP_DMA_CH_CTRL(0) = 0; - MCHP_DMA_CH_IEN(0) = 0; - MCHP_DMA_CH_ISTS(0) = 0xff; - MCHP_DMA_CH0_CRC32_EN = 1; - MCHP_DMA_CH0_CRC32_DATA = 0xfffffffful; - /* program device address to point to read-only register */ - MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c); - MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart; - MCHP_DMA_CH_MEM_END(0) = (uint32_t)mstart + nbytes; - if (ien != 0) - MCHP_DMA_CH_IEN(0) = 0x07; - MCHP_DMA_CH_ACT(0) = 1; - MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM + - MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4); - MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO; - return EC_SUCCESS; -} diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h deleted file mode 100644 index 4784b2c922..0000000000 --- a/chip/mchp/dma_chip.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MCHP MEC DMA controller chip level API - */ -/** @file dma_chip.h - *MCHP MEC Direct Memory Access block - */ -/** @defgroup MEC dma - */ - -#ifndef _DMA_CHIP_H -#define _DMA_CHIP_H - -#include <stdint.h> -#include <stddef.h> - - -#ifdef __cplusplus -extern "C" { -#endif - -/* Place any C interfaces here */ - -void dma_xfr_start_rx(const struct dma_option *option, - uint32_t dma_xfr_ulen, - uint32_t count, void *memory); - -void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count, - const void *memory, uint32_t dma_xfr_units); - -void dma_clr_chan(enum dma_channel ch); - -void dma_cfg_buffers(enum dma_channel ch, const void *membuf, - uint32_t nb, const void *pdev); - -/* - * ch = zero based DMA channel number - * unit_len = DMA unit size 1, 2 or 4 bytes - * flags - * b[0] = direction, 0=device_to_memory, 1=memory_to_device - * b[1] = 1 increment memory address - * b[2] = 1 increment device address - * b[3] = disable HW flow control - */ -#define DMA_FLAG_D2M 0 -#define DMA_FLAG_M2D 1 -#define DMA_FLAG_INCR_MEM 2 -#define DMA_FLAG_INCR_DEV 4 -#define DMA_FLAG_SW_FLOW 8 -void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, - uint8_t dev_id, uint8_t flags); - -void dma_run(enum dma_channel ch); - -uint32_t dma_is_done_chan(enum dma_channel ch); - -int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien); - -#ifdef __cplusplus -} -#endif - -#endif /* #ifndef _DMA_CHIP_H */ -/** @} - */ - diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c deleted file mode 100644 index 1cc06d8f90..0000000000 --- a/chip/mchp/espi.c +++ /dev/null @@ -1,1552 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* ESPI module for Chrome EC */ - -#include "common.h" -#include "acpi.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "keyboard_protocol.h" -#include "port80.h" -#include "util.h" -#include "chipset.h" - -#include "registers.h" -#include "espi.h" -#include "lpc.h" -#include "lpc_chip.h" -#include "system.h" -#include "task.h" -#include "console.h" -#include "uart.h" -#include "util.h" -#include "power.h" -#include "timer.h" -#include "tfdp_chip.h" - -/* Console output macros */ -#ifdef CONFIG_MCHP_ESPI_DEBUG -#ifdef CONFIG_MCHP_TFDP -#define CPUTS(...) -#define CPRINTS(...) -#else -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#endif -#else -#define CPUTS(...) -#define CPRINTS(...) -#endif - -/* - * eSPI slave to master virtual wire pulse timeout. - */ -#define ESPI_S2M_VW_PULSE_LOOP_CNT 50 -#define ESPI_S2M_VW_PULSE_LOOP_DLY_US 10 - -/* - * eSPI master enable virtual wire channel timeout. - */ -#define ESPI_CHAN_READY_TIMEOUT_US (100 * MSEC) -#define ESPI_CHAN_READY_POLL_INTERVAL_US 100 - -static uint32_t espi_channels_ready; - -/* - * eSPI Virtual Wire reset values - * VWire name used by chip independent code. - * Host eSPI Master VWire index containing signal - * Reset value of VWire. Note, each Host VWire index may - * have a different reset source: - * EC Power-on/chip reset - * ESPI_RESET# assertion by Host eSPI master - * eSPI Platform Reset assertion by Host eSPI master - * MEC1701H allows eSPI Platform reset to - * be a VWire or side band signal. - * - * NOTE MEC1701H Boot-ROM will restore VWires ... from - * VBAT power register MCHP_VBAT_VWIRE_BACKUP. - * bits[3:0] = Master-to-Slave Index 02h SRC3:SRC0 values - * MSVW00 register - * SRC0 = SLP_S3# - * SRC1 = SLP_S4# - * SRC2 = SLP_S5# - * SRC3 = reserved - * bits[7:4] = Master-to-Slave Index 42h SRC3:SRC0 values - * MSVW04 register - * SRC0 = SLP_LAN# - * SRC1 = SLP_WLAN# - * SRC2 = reserved - * SRC3 = reserved - * - */ -struct vw_info_t { - uint16_t name; /* signal name */ - uint8_t host_idx; /* Host VWire index of signal */ - uint8_t reset_val; /* reset value of VWire */ - uint8_t flags; /* b[0]=0(MSVW), =1(SMVW) */ - uint8_t reg_idx; /* MSVW or SMVW index */ - uint8_t src_num; /* SRC number */ - uint8_t rsvd; -}; - - -/* VW signals used in eSPI */ -/* - * MEC1701H VWire mapping based on eSPI Spec 1.0, - * eSPI Compatibility spec 0.96, - * MCHP HW defaults and ec/include/espi.h - * - * MSVW00 index=02h PORValue=00000000_04040404_00000102 reset=RESET_SYS - * SRC0 = VW_SLP_S3_L, IntrDis - * SRC1 = VW_SLP_S4_L, IntrDis - * SRC2 = VW_SLP_S5_L, IntrDis - * SRC3 = reserved, IntrDis - * MSVW01 index=03h PORValue=00000000_04040404_00000003 reset=RESET_ESPI - * SRC0 = VW_SUS_STAT_L, IntrDis - * SRC1 = VW_PLTRST_L, IntrDis - * SRC2 = VW_OOB_RST_WARN, IntrDis - * SRC3 = reserved, IntrDis - * MSVW02 index=07h PORValue=00000000_04040404_00000307 reset=PLTRST - * SRC0 = VW_HOST_RST_WARN - * SRC1 = 0 reserved - * SRC2 = 0 reserved - * SRC3 = 0 reserved - * MSVW03 index=41h PORValue=00000000_04040404_00000041 reset=RESET_ESPI - * SRC0 = VW_SUS_WARN_L, IntrDis - * SRC1 = VW_SUS_PWRDN_ACK_L, IntrDis - * SRC2 = 0 reserved, IntrDis - * SRC3 = VW_SLP_A_L, IntrDis - * MSVW04 index=42h PORValue=00000000_04040404_00000141 reset=RESET_SYS - * SRC0 = VW_SLP_LAN, IntrDis - * SRC1 = VW_SLP_WLAN, IntrDis - * SRC2 = reserved, IntrDis - * SRC3 = reserved, IntrDis - * - * SMVW00 index=04h PORValue=01010000_0000C004 STOM=1100 reset=RESET_ESPI - * SRC0 = VW_OOB_RST_ACK - * SRC1 = 0 reserved - * SRC2 = VW_WAKE_L - * SRC3 = VW_PME_L - * SMVW01 index=05h PORValue=00000000_00000005 STOM=0000 reset=RESET_ESPI - * SRC0 = SLAVE_BOOT_LOAD_DONE !!! NOTE: Google combines SRC0 & SRC3 - * SRC1 = VW_ERROR_FATAL - * SRC2 = VW_ERROR_NON_FATAL - * SRC3 = SLAVE_BOOT_LOAD_STATUS !!! into VW_SLAVE_BTLD_STATUS_DONE - * SMVW02 index=06h PORValue=00010101_00007306 STOM=0111 reset=PLTRST - * SRC0 = VW_SCI_L - * SRC1 = VW_SMI_L - * SRC2 = VW_RCIN_L - * SRC3 = VW_HOST_RST_ACK - * SMVW03 index=40h PORValue=00000000_00000040 STOM=0000 reset=RESET_ESPI - * SRC0 = assign VW_SUS_ACK - * SRC1 = 0 - * SRC2 = 0 - * SRC3 = 0 - * - * table of vwire structures - * MSVW00 at 0x400F9C00 offset = 0x000 - * MSVW01 at 0x400F9C0C offset = 0x00C - * - * SMVW00 at 0x400F9E00 offset = 0x200 - * SMVW01 at 0x400F9E08 offset = 0x208 - * - */ - -/* - * Virtual Wire table - * Each entry contains: - * Signal name from include/espi.h - * Host chipset VWire index number - * Reset value of VWire - * flags where bit[0]==0 Wire is Master-to-Slave or 1 Slave-to-Master - * MEC1701 register index into MSVW or SMVW register banks - * MEC1701 source number in MSVW or SMVW bank - * Reserved - * Pointer to name string for debug - */ -static const struct vw_info_t vw_info_tbl[] = { - /* name host reset reg SRC - * index value flags index num rsvd - */ - /* MSVW00 Host index 02h (In) */ - {VW_SLP_S3_L, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00}, - {VW_SLP_S4_L, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00}, - {VW_SLP_S5_L, 0x02, 0x00, 0x10, 0x00, 0x02, 0x00}, - /* MSVW01 Host index 03h (In) */ - {VW_SUS_STAT_L, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00}, - {VW_PLTRST_L, 0x03, 0x00, 0x10, 0x01, 0x01, 0x00}, - {VW_OOB_RST_WARN, 0x03, 0x00, 0x10, 0x01, 0x02, 0x00}, - /* SMVW00 Host Index 04h (Out) */ - {VW_OOB_RST_ACK, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00}, - {VW_WAKE_L, 0x04, 0x01, 0x01, 0x00, 0x02, 0x00}, - {VW_PME_L, 0x04, 0x01, 0x01, 0x00, 0x03, 0x00}, - /* SMVW01 Host index 05h (Out) */ - {VW_ERROR_FATAL, 0x05, 0x00, 0x01, 0x01, 0x01, 0x00}, - {VW_ERROR_NON_FATAL, 0x05, 0x00, 0x01, 0x01, 0x02, 0x00}, - {VW_SLAVE_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00}, - /* SMVW02 Host index 06h (Out) */ - {VW_SCI_L, 0x06, 0x01, 0x01, 0x02, 0x00, 0x00}, - {VW_SMI_L, 0x06, 0x01, 0x01, 0x02, 0x01, 0x00}, - {VW_RCIN_L, 0x06, 0x01, 0x01, 0x02, 0x02, 0x00}, - {VW_HOST_RST_ACK, 0x06, 0x00, 0x01, 0x02, 0x03, 0x00}, - /* MSVW02 Host index 07h (In) */ - {VW_HOST_RST_WARN, 0x07, 0x00, 0x10, 0x02, 0x00, 0x00}, - /* SMVW03 Host Index 40h (Out) */ - {VW_SUS_ACK, 0x40, 0x00, 0x01, 0x03, 0x00, 0x00}, - /* MSVW03 Host Index 41h (In) */ - {VW_SUS_WARN_L, 0x41, 0x00, 0x10, 0x03, 0x00, 0x00}, - {VW_SUS_PWRDN_ACK_L, 0x41, 0x00, 0x10, 0x03, 0x01, 0x00}, - {VW_SLP_A_L, 0x41, 0x00, 0x10, 0x03, 0x03, 0x00}, - /* MSVW04 Host index 42h (In) */ - {VW_SLP_LAN, 0x42, 0x00, 0x10, 0x04, 0x00, 0x00}, - {VW_SLP_WLAN, 0x42, 0x00, 0x10, 0x04, 0x01, 0x00} -}; -BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT); - - -/************************************************************************/ -/* eSPI internal utilities */ - -static int espi_vw_get_signal_index(enum espi_vw_signal event) -{ - int i; - - /* Search table by signal name */ - for (i = 0; i < ARRAY_SIZE(vw_info_tbl); i++) { - if (vw_info_tbl[i].name == event) - return i; - } - - return -1; -} - - -/* - * Initialize eSPI hardware upon ESPI_RESET# de-assertion - */ -#ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT -static void espi_reset_deassert_init(void) -{ - -} -#endif - -/* Call this on entry to deepest sleep state with EC turned off. - * May not be required in future host eSPI chipsets. - * - * Save Master-to-Slave VWire Index 02h & 42h before - * entering a deep sleep state where EC power is shut off. - * PCH requires we restore these VWires on wake. - * SLP_S3#, SLP_S4#, SLP_S5# in index 02h - * SLP_LAN#, SLP_WLAN# in index 42h - * Current VWire states are saved to a battery backed 8-bit - * register in MEC1701H. - * If a VBAT POR occurs the value of this register = 0 which - * is the default state of the above VWires on a hardware - * POR. - * VBAT byte bit definitions - * Host Index 02h -> MSVW00 - * Host Index 42h -> MSVW04 - * 0 Host Index 02h SRC0 - * 1 Host Index 02h SRC1 - * 2 Host Index 02h SRC2 - * 3 Host Index 02h SRC3 - * 4 Host Index 42h SRC0 - * 5 Host Index 42h SRC1 - * 6 Host Index 42h SRC2 - * 7 Host Index 42h SRC3 - */ -#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP -static void espi_vw_save(void) -{ - uint32_t i, r; - uint8_t vb; - - vb = 0; - r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42); - for (i = 0; i < 4; i++) { - if (r & (1ul << (i << 3))) - vb |= (1u << i); - } - - vb <<= 4; - r = MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02); - for (i = 0; i < 4; i++) { - if (r & (1ul << (i << 3))) - vb |= (1u << i); - } - - r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP); - r = (r & 0xFFFFFF00) | vb; - MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r; -} - -/* - * Update MEC1701H VBAT powered VWire backup values restored on - * MCHP chip reset. MCHP Boot-ROM loads these values into - * MSVW00 SRC[0:3](Index 02h) and MSVW04 SRC[0:3](Index 42h) - * on chip reset(POR, WDT reset, chip reset, wake from EC off). - * Always clear backup value after restore. - */ -static void espi_vw_restore(void) -{ - uint32_t i, r; - uint8_t vb; - -#ifdef EVB_NO_ESPI_TEST_MODE - vb = 0xff; /* force SLP_Sx# signals to 1 */ -#else - vb = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) & 0xff; -#endif - r = 0; - for (i = 0; i < 4; i++) { - if (vb & (1u << i)) - r |= (1ul << (i << 3)); - } - MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H02) = r; - CPRINTS("eSPI restore MSVW00(Index 02h) = 0x%08x", r); - trace11(0, ESPI, 0, "eSPI restore MSVW00(Index 02h) = 0x%08x", r); - - vb >>= 4; - r = 0; - for (i = 0; i < 4; i++) { - if (vb & (1u << i)) - r |= (1ul << (i << 3)); - } - MCHP_ESPI_VW_M2S_SRC_ALL(MSVW_H42) = r; - CPRINTS("eSPI restore MSVW00(Index 42h) = 0x%08x", r); - trace11(0, ESPI, 0, "eSPI restore MSVW04(Index 42h) = 0x%08x", r); - - r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP); - MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00; - -} -#endif - -static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id) -{ - uint8_t msvw; - - msvw = 0; - if (msvw_id < MSVW_MAX) { - uint32_t r = MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id); - - msvw = (r & 0x01); - msvw |= ((r >> 7) & 0x02); - msvw |= ((r >> 14) & 0x04); - msvw |= ((r >> 21) & 0x08); - } - - return msvw; -} - -static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id, - uint8_t src_bitmap) -{ - if (msvw_id < MSVW_MAX) { - uint32_t r = (src_bitmap & 0x08) << 21; - - r |= (src_bitmap & 0x04) << 14; - r |= (src_bitmap & 0x02) << 7; - r |= (src_bitmap & 0x01); - MCHP_ESPI_VW_M2S_SRC_ALL(msvw_id) = r; - } -} - -static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id) -{ - uint8_t smvw; - - smvw = 0; - if (smvw_id < SMVW_MAX) { - uint32_t r = MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id); - - smvw = (r & 0x01); - smvw |= ((r >> 7) & 0x02); - smvw |= ((r >> 14) & 0x04); - smvw |= ((r >> 21) & 0x08); - } - - return smvw; -} - -static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id, - uint8_t src_bitmap) -{ - if (smvw_id < SMVW_MAX) { - uint32_t r = (src_bitmap & 0x08) << 21; - - r |= (src_bitmap & 0x04) << 14; - r |= (src_bitmap & 0x02) << 7; - r |= (src_bitmap & 0x01); - MCHP_ESPI_VW_S2M_SRC_ALL(smvw_id) = r; - } -} - - -/* - * Called before releasing RSMRST# - * ESPI_RESET# is asserted - * PLATFORM_RESET# is asserted - */ -static void espi_bar_pre_init(void) -{ - /* Configuration IO BAR set to 0x2E/0x2F */ - MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E; - MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00; - MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1; -} - -/* - * Called before releasing RSMRST# - * ESPI_RESET# is asserted - * PLATFORM_RESET# is asserted - * Set all MSVW to either edge interrupt - * IRQ_SELECT fields are reset on RESET_SYS not ESPI_RESET or PLTRST - * - */ -static void espi_vw_pre_init(void) -{ - uint32_t i; - - CPRINTS("eSPI VW Pre-Init"); - trace0(0, ESPI, 0, "eSPI VW Pre-Init"); - -#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP - espi_vw_restore(); -#endif - - /* disable all */ - for (i = 0; i < MSVW_MAX; i++) - MCHP_ESPI_VW_M2S_IRQSEL_ALL(i) = 0x0f0f0f0ful; - - /* clear spurious status */ - MCHP_INT_SOURCE(24) = 0xfffffffful; - MCHP_INT_SOURCE(25) = 0xfffffffful; - - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H02) = 0x040f0f0ful; - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H03) = 0x040f0f0ful; - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H07) = 0x0404040ful; - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H41) = 0x0f040f0ful; - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H42) = 0x04040f0ful; - MCHP_ESPI_VW_M2S_IRQSEL_ALL(MSVW_H47) = 0x0404040ful; - - MCHP_INT_ENABLE(24) = 0xfff3b177ul; - MCHP_INT_ENABLE(25) = 0x01ul; - - MCHP_INT_SOURCE(24) = 0xfffffffful; - MCHP_INT_SOURCE(25) = 0xfffffffful; - - MCHP_INT_BLK_EN = (1ul << 24) + (1ul << 25); - - task_enable_irq(MCHP_IRQ_GIRQ24); - task_enable_irq(MCHP_IRQ_GIRQ25); - - CPRINTS("eSPI VW Pre-Init Done"); - trace0(0, ESPI, 0, "eSPI VW Pre-Init Done"); -} - - -/* - * If VWire, Flash, and OOB channels have been enabled - * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1 - * SLAVE_BOOT_LOAD_STATUS = SRC3 of Slave-to-Master Index 05h - * SLAVE_BOOT_LOAD_DONE = SRC0 of Slave-to-Master Index 05h - * Note, if set individually then set status first then done. - * We set both simultaneously. ESPI_ALERT# will assert only if one - * or both bits change. - * SRC0 is bit[32] of SMVW01 - * SRC3 is bit[56] of SMVW01 - */ -static void espi_send_boot_load_done(void) -{ - /* First set SLAVE_BOOT_LOAD_STATUS = 1 */ - MCHP_ESPI_VW_S2M_SRC3(SMVW_H05) = 1; - /* Next set SLAVE_BOOT_LOAD_DONE = 1 */ - MCHP_ESPI_VW_S2M_SRC0(SMVW_H05) = 1; - - CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1"); - trace0(0, ESPI, 0, "VW SLAVE_BOOT_LOAD_STATUS/DONE = 1"); -} - - -/* - * Called when eSPI PLTRST# VWire de-asserts - * Re-initialize any hardware that was reset while PLTRST# was - * asserted. - * Logical Device BAR's, etc. - * Each BAR requires address, mask, and valid bit - * mask = bit map of address[7:0] to mask out - * 0 = no masking, match exact address - * 0x01 = mask bit[0], match two consecutive addresses - * 0xff = mask bits[7:0], match 256 consecutive bytes - * eSPI has two registers for each BAR - * Host visible register - * base address in bits[31:16] - * valid = bit[0] - * EC only register - * mask = bits[7:0] - * Logical device number = bits[13:8] - * Virtualized = bit[16] Not Implemented - */ -static void espi_host_init(void) -{ - CPRINTS("eSPI - espi_host_init"); - trace0(0, ESPI, 0, "eSPI Host Init"); - - /* BAR's */ - - /* Configuration IO BAR set to 0x2E/0x2F */ - MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x01; - MCHP_ESPI_IO_BAR_ADDR_LSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x2E; - MCHP_ESPI_IO_BAR_ADDR_MSB(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 0x00; - MCHP_ESPI_IO_BAR_VALID(MCHP_ESPI_IO_BAR_ID_CFG_PORT) = 1; - - /* Set up ACPI0 for 0x62/0x66 */ - chip_acpi_ec_config(0, 0x62, 0x04); - - /* Set up ACPI1 for 0x200-0x203, 0x204-0x207 */ - chip_acpi_ec_config(1, 0x200, 0x07); - - /* Set up 8042 interface at 0x60/0x64 */ - chip_8042_config(0x60); - - /* EMI at 0x800 for accessing shared memory */ - chip_emi0_config(0x800); - - /* Setup Port80 Debug Hardware for I/O 80h */ - chip_port80_config(0x80); - - lpc_mem_mapped_init(); - - MCHP_ESPI_PC_STATUS = 0xfffffffful; - /* PC enable & Mastering enable changes */ - MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28); - - - /* Sufficiently initialized */ - lpc_set_init_done(1); - - /* last set eSPI Peripheral Channel Ready = 1 */ - /* Done in ISR for PC Channel */ - MCHP_ESPI_IO_PC_READY = 1; - - /* Update host events now that we can copy them to memmap */ - /* NOTE: This routine may pulse SCI# and/or SMI# - * For eSPI these are virtual wires. VWire channel should be - * enabled before PLTRST# is de-asserted so its safe BUT has - * PC Channel(I/O) Enable occurred? - */ - lpc_update_host_event_status(); - - CPRINTS("eSPI - espi_host_init Done"); - trace0(0, ESPI, 0, "eSPI Host Init Done"); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST); - - -/* - * Called in response to VWire OOB_RST_WARN==1 from - * espi_vw_evt_oob_rst_warn. - * Host chipset eSPI documentation states eSPI slave should - * if necessary flush any OOB upstream (OOB TX) data before the slave - * sends OOB_RST_ACK=1 to the Host. - */ -static void espi_oob_flush(void) -{ -} - - -/* - * Called in response to VWire HOST_RST_WARN==1 from - * espi_vw_evt_host_rst_warn. - * Host chipset eSPI documentation states assertion of HOST_RST_WARN - * can be used if necessary to flush any Peripheral Channel data - * before slave sends HOST_RST_ACK to Host. - */ -static void espi_pc_flush(void) -{ -} - -/* The ISRs of VW signals which used for power sequences */ -void espi_vw_power_signal_interrupt(enum espi_vw_signal signal) -{ - CPRINTS("eSPI power signal interrupt for VW %d", signal); - trace1(0, ESPI, 0, "eSPI pwr intr VW %d", (signal - VW_SIGNAL_START)); - power_signal_interrupt((enum gpio_signal) signal); -} - -/************************************************************************/ -/* IC specific low-level driver */ - - -/** - * Set eSPI Virtual-Wire signal to Host - * - * @param signal vw signal needs to set - * @param level level of vw signal - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level) -{ - int tidx; - uint8_t ridx, src_num; - - tidx = espi_vw_get_signal_index(signal); - - if (tidx < 0) - return EC_ERROR_PARAM1; - - if (0 == (vw_info_tbl[tidx].flags & (1u << 0))) - return EC_ERROR_PARAM1; /* signal is Master-to-Slave */ - - ridx = vw_info_tbl[tidx].reg_idx; - src_num = vw_info_tbl[tidx].src_num; - - if (level) - level = 1; - - if (signal == VW_SLAVE_BTLD_STATUS_DONE) { - /* SLAVE_BOOT_LOAD_STATUS */ - MCHP_ESPI_VW_S2M_SRC3(ridx) = level; - /* SLAVE_BOOT_LOAD_DONE after status */ - MCHP_ESPI_VW_S2M_SRC0(ridx) = level; - } else { - MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level; - } - -#ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("eSPI VW Set Wire %s = %d", - espi_vw_get_wire_name(signal), level); - trace2(0, ESPI, 0, "VW SetWire[%d] = %d", - ((uint32_t)signal - VW_SIGNAL_START), level); -#endif - - return EC_SUCCESS; -} - -/* - * Set Slave to Master virtual wire to level and wait for hardware - * to process virtual wire. - * If virtual wire written to same value then hardware change bit - * is 0 and routine returns success. - * If virtual wire written to different value then hardware change bit - * goes to 1 until bit is transmitted upstream to the master. This may - * happen quickly is bus is idle. Poll for hardware clearing change bit - * until timeout. - */ -static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num, - uint8_t level) -{ - uint32_t i; - - MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01; - - for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) { - if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) & - (1u << src_num)) == 0) - return EC_SUCCESS; - udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US); - } - - return EC_ERROR_TIMEOUT; -} - -/* - * Create a pulse on a Slave-to-Master VWire - * Use case is generate low pulse on SCI# virtual wire. - * Should a timeout mechanism be added because we are - * waiting on Host eSPI Master to respond to eSPI Alert and - * then read the VWires. If the eSPI Master is OK the maximum - * time will still be variable depending upon link frequency and - * other activity on the link. Other activity is currently bounded by - * Host chipset eSPI maximum payload length of 64 bytes + packet overhead. - * Lowest eSPI transfer rate is 1x at 20 MHz, assume 30% packet overhead. - * (64 * 1.3) * 8 = 666 bits is roughly 34 us. Pad to 100 us. - */ -int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level) -{ - int rc, tidx; - uint8_t ridx, src_num, level; - - tidx = espi_vw_get_signal_index(signal); - - if (tidx < 0) - return EC_ERROR_PARAM1; - - if (0 == (vw_info_tbl[tidx].flags & (1u << 0))) - return EC_ERROR_PARAM1; /* signal is Master-to-Slave */ - - ridx = vw_info_tbl[tidx].reg_idx; - src_num = vw_info_tbl[tidx].src_num; - - level = 0; - if (pulse_level) - level = 1; - -#ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("eSPI VW Pulse Wire %s to %d", - espi_vw_get_wire_name(signal), level); - trace2(0, ESPI, 0, "eSPI pulse VW[%d] = %d", signal, level); - trace2(0, ESPI, 0, " S2M index=%d src=%d", ridx, src_num); -#endif - - /* set requested inactive state */ - rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level); - if (rc != EC_SUCCESS) - return rc; - - /* drive to requested active state */ - rc = espi_vw_s2m_set_w4m(ridx, src_num, level); - if (rc != EC_SUCCESS) - return rc; - - /* set to requested inactive state */ - rc = espi_vw_s2m_set_w4m(ridx, src_num, ~level); - - return rc; -} - -/** - * Get eSPI Virtual-Wire signal from host - * - * @param signal vw signal needs to get - * @return 1: set by host, otherwise: no signal - */ -int espi_vw_get_wire(enum espi_vw_signal signal) -{ - int vw, tidx; - uint8_t ridx, src_num; - - vw = 0; - tidx = espi_vw_get_signal_index(signal); - - if (tidx >= 0 && (0 == (vw_info_tbl[tidx].flags & (1u << 0)))) { - ridx = vw_info_tbl[tidx].reg_idx; - src_num = vw_info_tbl[tidx].src_num; - vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01; -#ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW GetWire %s = %d", - espi_vw_get_wire_name(signal), vw); - trace2(0, ESPI, 0, "VW GetWire[%d] = %d", - ((uint32_t)signal - VW_SIGNAL_START), vw); -#endif - } - - return vw; -} - -/** - * Enable VW interrupt of power sequence signal - * - * @param signal vw signal needs to enable interrupt - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_enable_wire_int(enum espi_vw_signal signal) -{ - int tidx; - uint8_t ridx, src_num, girq_num, bpos; - - tidx = espi_vw_get_signal_index(signal); - - if (tidx < 0) - return EC_ERROR_PARAM1; - - if (0 != (vw_info_tbl[tidx].flags & (1u << 0))) - return EC_ERROR_PARAM1; /* signal is Slave-to-Master */ - -#ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW IntrEn for VW[%s]", - espi_vw_get_wire_name(signal)); - trace1(0, ESPI, 0, "VW IntrEn for VW[%d]", - ((uint32_t)signal - VW_SIGNAL_START)); -#endif - - ridx = vw_info_tbl[tidx].reg_idx; - src_num = vw_info_tbl[tidx].src_num; - - /* - * Set SRCn_IRQ_SELECT field for VWire to either edge - * Write enable set bit in GIRQ24 or GIRQ25 - * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27]) - * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25]) - */ - MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = - MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES; - - girq_num = 24; - if (ridx > 6) { - girq_num++; - ridx -= 7; - } - bpos = (ridx << 2) + src_num; - - MCHP_INT_SOURCE(girq_num) = (1ul << bpos); - MCHP_INT_ENABLE(girq_num) = (1ul << bpos); - - return EC_SUCCESS; -} - -/** - * Disable VW interrupt of power sequence signal - * - * @param signal vw signal needs to disable interrupt - * @return EC_SUCCESS, or non-zero if error. - */ -int espi_vw_disable_wire_int(enum espi_vw_signal signal) -{ - int tidx; - uint8_t ridx, src_num, bpos; - - tidx = espi_vw_get_signal_index(signal); - - if (tidx < 0) - return EC_ERROR_PARAM1; - - if (0 != (vw_info_tbl[tidx].flags & (1u << 0))) - return EC_ERROR_PARAM1; /* signal is Slave-to-Master */ - -#ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW IntrDis for VW[%s]", - espi_vw_get_wire_name(signal)); - trace1(0, ESPI, 0, "VW IntrDis for VW[%d]", - (signal - VW_SIGNAL_START)); -#endif - - ridx = vw_info_tbl[tidx].reg_idx; - src_num = vw_info_tbl[tidx].src_num; - - /* - * Set SRCn_IRQ_SELECT field for VWire to disabled - * Write enable set bit in GIRQ24 or GIRQ25 - * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27]) - * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25]) - */ - MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = - MCHP_ESPI_MSVW_IRQSEL_DISABLED; - - if (ridx < 7) { - bpos = (ridx << 2) + src_num; - MCHP_INT_DISABLE(24) = (1ul << bpos); - - } else { - bpos = ((ridx - 7) << 2) + src_num; - MCHP_INT_DISABLE(25) = (1ul << bpos); - } - - return EC_SUCCESS; -} - -/************************************************************************/ -/* VW event handlers */ - -#ifdef CONFIG_CHIPSET_RESET_HOOK -static void espi_chipset_reset(void) -{ - hook_notify(HOOK_CHIPSET_RESET); -} -DECLARE_DEFERRED(espi_chipset_reset); -#endif - - -/* SLP_Sx event handler */ -void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_S3: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_S3_L change to %d", wire_state); - espi_vw_power_signal_interrupt(VW_SLP_S3_L); -} - -void espi_vw_evt_slp_s4_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_S4: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_S4_L change to %d", wire_state); - espi_vw_power_signal_interrupt(VW_SLP_S4_L); -} - -void espi_vw_evt_slp_s5_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_S5: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_S5_L change to %d", wire_state); - espi_vw_power_signal_interrupt(VW_SLP_S5_L); -} - -void espi_vw_evt_sus_stat_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SUS_STAT: %d", wire_state); - trace1(0, ESPI, 0, "VW_SUS_STAT change to %d", wire_state); - espi_vw_power_signal_interrupt(VW_SUS_STAT_L); -} - -/* PLTRST# event handler */ -void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW PLTRST#: %d", wire_state); - trace1(0, ESPI, 0, "VW_PLTRST# change to %d", wire_state); - - if (wire_state) /* Platform Reset de-assertion */ - espi_host_init(); - else /* assertion */ -#ifdef CONFIG_CHIPSET_RESET_HOOK - hook_call_deferred(&espi_chipset_reset_data, MSEC); -#endif - -} - -/* OOB Reset Warn event handler */ -void espi_vw_evt_oob_rst_warn(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW OOB_RST_WARN: %d", wire_state); - trace1(0, ESPI, 0, "VW_OOB_RST_WARN change to %d", wire_state); - - espi_oob_flush(); - - espi_vw_set_wire(VW_OOB_RST_ACK, wire_state); -} - -/* SUS_WARN# event handler */ -void espi_vw_evt_sus_warn_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SUS_WARN#: %d", wire_state); - trace1(0, ESPI, 0, "VW_SUS_WARN# change to %d", wire_state); - - udelay(100); - - /* - * Add any Deep Sx prep here - * NOTE: we could schedule a deferred function and have - * it send ACK to host after preparing for Deep Sx - */ -#ifdef CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP - espi_vw_save(); -#endif - /* Send ACK to host by WARN#'s wire */ - espi_vw_set_wire(VW_SUS_ACK, wire_state); -} - -/* - * SUS_PWRDN_ACK - * PCH is informing us it does not need suspend power well. - * if SUS_PWRDN_ACK == 1 we can turn off suspend power well assuming - * hardware design allow. - */ -void espi_vw_evt_sus_pwrdn_ack(uint32_t wire_state, uint32_t bpos) -{ - trace1(0, ESPI, 0, "VW_SUS_PWRDN_ACK change to %d", wire_state); - CPRINTS("VW SUS_PWRDN_ACK: %d", wire_state); -} - -/* SLP_A#(SLP_M#) */ -void espi_vw_evt_slp_a_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_A: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_A# change to %d", wire_state); - - /* Put handling of ASW well devices here, if any */ -} - -/* HOST_RST WARN event handler */ -void espi_vw_evt_host_rst_warn(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW HOST_RST_WARN: %d", wire_state); - trace1(0, ESPI, 0, "VW_HOST_RST_WARN change to %d", wire_state); - - espi_pc_flush(); - - /* Send HOST_RST_ACK to host */ - espi_vw_set_wire(VW_HOST_RST_ACK, wire_state); -} - -/* SLP_LAN# */ -void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_LAN: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_LAN# change to %d", wire_state); -} - -/* SLP_WLAN# */ -void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW SLP_WLAN: %d", wire_state); - trace1(0, ESPI, 0, "VW_SLP_WLAN# change to %d", wire_state); -} - -void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("VW HOST_C10: %d", wire_state); - trace1(0, ESPI, 0, "VW_HOST_C10 change to %d", wire_state); -} - -void espi_vw_evt1_dflt(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("Unknown M2S VW: state=%d GIRQ24 bitpos=%d", wire_state, bpos); - MCHP_INT_DISABLE(24) = (1ul << bpos); -} - -void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos) -{ - CPRINTS("Unknown M2S VW: state=%d GIRQ25 bitpos=%d", wire_state, bpos); - MCHP_INT_DISABLE(25) = (1ul << bpos); -} - -/************************************************************************/ -/* Interrupt handlers */ - -/* MEC1701H - * GIRQ19 all direct connect capable, none wake capable - * b[0] = Peripheral Channel (PC) - * b[1] = Bus Master 1 (BM1) - * b[2] = Bus Master 2 (BM2) - * b[3] = LTR - * b[4] = OOB_UP - * b[5] = OOB_DN - * b[6] = Flash Channel (FC) - * b[7] = ESPI_RESET# change - * b[8] = VWire Channel (VW) enable assertion - * b[9:31] = 0 reserved - * - * GIRQ22 b[9]=ESPI interface wake peripheral logic only, not EC. - * Not direct connect capable - * - * GIRQ24 - * b[0:3] = MSVW00_SRC[0:3] - * b[4:7] = MSVW01_SRC[0:3] - * b[8:11] = MSVW02_SRC[0:3] - * b[12:15] = MSVW03_SRC[0:3] - * b[16:19] = MSVW04_SRC[0:3] - * b[20:23] = MSVW05_SRC[0:3] - * b[24:27] = MSVW06_SRC[0:3] - * b[28:31] = 0 reserved - * - * GIRQ25 - * b[0:3] = MSVW07_SRC[0:3] - * b[4:7] = MSVW08_SRC[0:3] - * b[8:11] = MSVW09_SRC[0:3] - * b[12:15] = MSVW10_SRC[0:3] - * b[16:31] = 0 reserved - * - */ - -typedef void (*FPVW)(uint32_t, uint32_t); - -#define MCHP_GIRQ24_NUM_M2S (7 * 4) -const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = { - espi_vw_evt_slp_s3_n, /* MSVW00, Host M2S 02h */ - espi_vw_evt_slp_s4_n, - espi_vw_evt_slp_s5_n, - espi_vw_evt1_dflt, - espi_vw_evt_sus_stat_n, /* MSVW01, Host M2S 03h */ - espi_vw_evt_pltrst_n, - espi_vw_evt_oob_rst_warn, - espi_vw_evt1_dflt, - espi_vw_evt_host_rst_warn, /* MSVW02, Host M2S 07h */ - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt_sus_warn_n, /* MSVW03, Host M2S 41h */ - espi_vw_evt_sus_pwrdn_ack, - espi_vw_evt1_dflt, - espi_vw_evt_slp_a_n, - espi_vw_evt_slp_lan_n, /* MSVW04, Host M2S 42h */ - espi_vw_evt_slp_wlan_n, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, /* MSVW05, Host M2S 43h */ - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, /* MSVW06, Host M2S 44h */ - espi_vw_evt1_dflt, - espi_vw_evt1_dflt, - espi_vw_evt1_dflt -}; - -#define MCHP_GIRQ25_NUM_M2S (4 * 4) -const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = { - espi_vw_evt_host_c10, /* MSVW07, Host M2S 47h */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW08 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW09 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW10 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, -}; - -/* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */ -void espi_mswv1_interrupt(void) -{ - uint32_t d, girq24_result, bpos; - - d = MCHP_INT_ENABLE(24); - girq24_result = MCHP_INT_RESULT(24); - MCHP_INT_SOURCE(24) = girq24_result; - - bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */ - while (bpos != 32) { - d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 + - (12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01; - (girq24_vw_handlers[bpos])(d, bpos); - girq24_result &= ~(1ul << bpos); - bpos = __builtin_ctz(girq24_result); - } -} -DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2); - - -/* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */ -void espi_msvw2_interrupt(void) -{ - uint32_t d, girq25_result, bpos; - - d = MCHP_INT_ENABLE(25); - girq25_result = MCHP_INT_RESULT(25); - MCHP_INT_SOURCE(25) = girq25_result; - - bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */ - while (bpos != 32) { - d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 + - (12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01; - (girq25_vw_handlers[bpos])(d, bpos); - girq25_result &= ~(1ul << bpos); - bpos = __builtin_ctz(girq25_result); - } -} -DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2); - - - -/* - * NOTES: - * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and - * their registers can't be programmed. All channel Enable and Ready bits - * are cleared. The only operational logic is the ESPI_RESET# change - * detection logic. - * Once ESPI_RESET# de-asserts, firmware can enable interrupts on all - * other eSPI channels/components. - * Implications are: - * ESPI_RESET# assertion - - * All channel ready bits are cleared stopping all outstanding - * transactions and clearing registers and internal FIFO's. - * ESPI_RESET# de-assertion - - * All channels/components can now be programmed and can detect - * reception of channel enable messages from the eSPI Master. - */ - -/* - * eSPI Reset change handler - * Multiple scenarios must be handled. - * eSPI Link initialization from de-assertion of RSMRST# - * Upon RSMRST# de-assertion, the PCH may drive ESPI_RESET# low - * and then back high. If the platform has a pull-down on ESPI_RESET# - * then we will not see both edges. We must handle the scenario where - * ESPI_RESET# has only a rising edge or is pulsed low once RSMRST# - * has been released. - * eSPI Link is operational and PCH asserts ESPI_RESET# due to - * global reset event or some other system problem. - * eSPI link is operational and the system generates a global reset - * event to the PCH. EC is unaware of global reset and sees PCH - * activate ESPI_RESET#. - * - * ESPI_RESET# assertion will disable all MCHP eSPI channel ready - * bits and place all channels is reset state. Any hardware affected by - * ESPI_RESET# must be re-initialized after ESPI_RESET# de-asserts. - * - * Note ESPI_RESET# is not equivalent to LPC LRESET#. LRESET# is - * equivalent to eSPI Platform Reset. - * - */ -void espi_reset_isr(void) -{ - uint8_t erst; - - erst = MCHP_ESPI_IO_RESET_STATUS; - MCHP_ESPI_IO_RESET_STATUS = erst; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT; - if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */ - MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); - MCHP_ESPI_OOB_TX_IEN = (1ul << 1); - MCHP_ESPI_FC_IEN = (1ul << 1); - MCHP_ESPI_PC_IEN = (1ul << 25); - CPRINTS("eSPI Reset de-assert"); - trace0(0, ESPI, 0, "eSPI Reset de-assert"); - - } else { /* falling edge - reset asserted */ - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); - espi_channels_ready = 0; - - chipset_handle_espi_reset_assert(); - - CPRINTS("eSPI Reset assert"); - trace0(0, ESPI, 0, "eSPI Reset assert"); - } -} -DECLARE_IRQ(MCHP_IRQ_ESPI_RESET, espi_reset_isr, 3); - -/* - * eSPI Virtual Wire channel enable handler - * Must disable once VW Enable is set by eSPI Master - */ -void espi_vw_en_isr(void) -{ - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_VW_EN_GIRQ_BIT; - - MCHP_ESPI_IO_VW_READY = 1; - - espi_channels_ready |= (1ul << 0); - - CPRINTS("eSPI VW Enable received, set VW Ready"); - trace0(0, ESPI, 0, "VW Enable. Set VW Ready"); - - if (0x03 == (espi_channels_ready & 0x03)) - espi_send_boot_load_done(); -} -DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2); - - -/* - * eSPI OOB TX and OOB channel enable change interrupt handler - */ -void espi_oob_tx_isr(void) -{ - uint32_t sts; - - sts = MCHP_ESPI_OOB_TX_STATUS; - MCHP_ESPI_OOB_TX_STATUS = sts; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_TX_GIRQ_BIT; - if (sts & (1ul << 1)) { - /* Channel Enable change */ - if (sts & (1ul << 9)) { /* enable? */ - MCHP_ESPI_OOB_RX_LEN = 73; - MCHP_ESPI_IO_OOB_READY = 1; - espi_channels_ready |= (1ul << 2); - CPRINTS("eSPI OOB_UP ISR: OOB Channel Enable"); - trace0(0, ESPI, 0, "OOB_TX OOB Enable"); - } else { /* no, disabled by Master */ - espi_channels_ready &= ~(1ul << 2); - CPRINTS("eSPI OOB_UP ISR: OOB Channel Disable"); - trace0(0, ESPI, 0, "eSPI OOB_TX OOB Disable"); - } - } else { - /* Handle OOB Up transmit status: done and/or errors, here */ - CPRINTS("eSPI OOB_UP status = 0x%x", sts); - trace11(0, ESPI, 0, "eSPI OOB_TX Status = 0x%08x", sts); - } -} -DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2); - - -/* eSPI OOB RX interrupt handler */ -void espi_oob_rx_isr(void) -{ - uint32_t sts; - - sts = MCHP_ESPI_OOB_RX_STATUS; - MCHP_ESPI_OOB_RX_STATUS = sts; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_OOB_RX_GIRQ_BIT; - /* Handle OOB Up transmit status: done and/or errors, if any */ - CPRINTS("eSPI OOB_DN status = 0x%x", sts); - trace11(0, ESPI, 0, "eSPI OOB_RX Status = 0x%08x", sts); -} -DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2); - - -/* - * eSPI Flash Channel enable change and data transfer - * interrupt handler - */ -void espi_fc_isr(void) -{ - uint32_t sts; - - sts = MCHP_ESPI_FC_STATUS; - MCHP_ESPI_FC_STATUS = sts; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_FC_GIRQ_BIT; - if (sts & (1ul << 1)) { - /* Channel Enable change */ - if (sts & (1ul << 0)) { /* enable? */ - MCHP_ESPI_IO_FC_READY = 1; - espi_channels_ready |= (1ul << 1); - CPRINTS("eSPI FC ISR: Enable"); - trace0(0, ESPI, 0, "eSPI FC Enable"); - if (0x03 == (espi_channels_ready & 0x03)) - espi_send_boot_load_done(); - } else { /* no, disabled by Master */ - espi_channels_ready &= ~(1ul << 1); - CPRINTS("eSPI FC ISR: Disable"); - trace0(0, ESPI, 0, "eSPI FC Disable"); - } - } else { - /* Handle FC command status: done and/or errors */ - CPRINTS("eSPI FC status = 0x%x", sts); - trace11(0, ESPI, 0, "eSPI FC Status = 0x%08x", sts); - } -} -DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2); - - -/* eSPI Peripheral Channel interrupt handler */ -void espi_pc_isr(void) -{ - uint32_t sts; - - sts = MCHP_ESPI_PC_STATUS; - MCHP_ESPI_PC_STATUS = sts; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_PC_GIRQ_BIT; - if (sts & (1ul << 25)) { - if (sts & (1ul << 24)) { - MCHP_ESPI_IO_PC_READY = 1; - espi_channels_ready |= (1ul << 3); - CPRINTS("eSPI PC Channel Enable"); - trace0(0, ESPI, 0, "eSPI PC Enable"); - } else { - espi_channels_ready &= ~(1ul << 3); - CPRINTS("eSPI PC Channel Disable"); - trace0(0, ESPI, 0, "eSPI PC Disable"); - } - - } else { - /* Handler PC channel errors here */ - CPRINTS("eSPI PC status = 0x%x", sts); - trace11(0, ESPI, 0, "eSPI PC Status = 0x%08x", sts); - } -} -DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2); - - -/************************************************************************/ - -/* - * Enable/disable direct mode interrupt for ESPI_RESET# change. - * Optionally clear status before enable or after disable. - */ -static void espi_reset_ictrl(int enable, int clr_status) -{ - if (enable) { - if (clr_status) { - MCHP_ESPI_IO_RESET_STATUS = - MCHP_ESPI_RST_CHG_STS; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; - } - MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN; - MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; - task_enable_irq(MCHP_IRQ_ESPI_RESET); - } else { - task_disable_irq(MCHP_IRQ_ESPI_RESET); - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; - MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN); - if (clr_status) { - MCHP_ESPI_IO_RESET_STATUS = - MCHP_ESPI_RST_CHG_STS; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; - } - } -} - -/* eSPI Initialization functions */ - -/* MEC1701H */ -void espi_init(void) -{ - espi_channels_ready = 0; - - CPRINTS("eSPI - espi_init"); - trace0(0, ESPI, 0, "eSPI Init"); - - /* Clear PCR eSPI sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ESPI); - - /* - * b[8]=0(eSPI PLTRST# VWire is platform reset), b[0]=0 - * VCC_PWRGD is asserted when PLTRST# VWire is 1(inactive) - */ - MCHP_PCR_PWR_RST_CTL = 0; - - /* - * There is no MODULE_ESPI in include/module_id.h - * eSPI pins marked as MODULE_LPC in board/myboard/board.h - * eSPI pins are on VTR3. - * Make sure VTR3 chip knows VTR3 is 1.8V - * This is done in system_pre_init() - */ - gpio_config_module(MODULE_LPC, 1); - - /* Override Boot-ROM configuration */ -#ifdef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP - MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP; -#endif - -#ifdef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ - MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_MAX_FREQ_MASK); -#if CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 25 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_25M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 33 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_33M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 50 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_50M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 66 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_66M; -#else - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_20M; -#endif -#endif - -#ifdef CONFIG_HOSTCMD_ESPI_EC_MODE - MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_IO_MASK); - MCHP_ESPI_IO_CAP1 |= ((CONFIG_HOSTCMD_ESPI_EC_MODE) - << MCHP_ESPI_CAP1_IO_BITPOS); -#endif - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW; -#else - MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN; -#endif - - MCHP_PCR_PWR_RST_CTL &= - ~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS); - - MCHP_ESPI_ACTIVATE = 1; - - espi_bar_pre_init(); - - /* - * VWires are configured to be reset by different events. - * Default configuration has: - * RESET_SYS (chip reset) MSVW00, MSVW04 - * RESET_ESPI MSVW01, MSVW03, SMVW00, SMVW01 - * PLTRST MSVW02, SMVW02 - */ - espi_vw_pre_init(); - - /* - * Configure MSVW00 & MSVW04 - * Any change to default values (SRCn bits) - * Any change to interrupt enable, SRCn_IRQ_SELECT bit fields - * Should interrupt bits in MSVWyx and GIRQ24/25 be touched - * before ESPI_RESET# de-asserts? - */ - - MCHP_ESPI_PC_STATUS = 0xfffffffful; - MCHP_ESPI_OOB_RX_STATUS = 0xfffffffful; - MCHP_ESPI_FC_STATUS = 0xfffffffful; - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = 0x1FFul; - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = 0x1FFul; - - task_enable_irq(MCHP_IRQ_ESPI_PC); - task_enable_irq(MCHP_IRQ_ESPI_OOB_UP); - task_enable_irq(MCHP_IRQ_ESPI_OOB_DN); - task_enable_irq(MCHP_IRQ_ESPI_FC); - task_enable_irq(MCHP_IRQ_ESPI_VW_EN); - - /* Enable eSPI Master-to-Slave Virtual wire NVIC inputs - * VWire block interrupts are all disabled by default - * and will be controlled by espi_vw_enable/disable_wire_in - */ - CPRINTS("eSPI - enable ESPI_RESET# interrupt"); - trace0(0, ESPI, 0, "Enable ESPI_RESET# interrupt"); - - /* Enable ESPI_RESET# interrupt and clear status */ - espi_reset_ictrl(1, 1); - - CPRINTS("eSPI - espi_init - done"); - trace0(0, ESPI, 0, "eSPI Init Done"); - -} - - -#ifdef CONFIG_MCHP_ESPI_EC_CMD -/* TODO */ -static int command_espi(int argc, char **argv) -{ - uint32_t chan, w0, w1, w2; - char *e; - - if (argc == 1) { - return EC_ERROR_INVAL; - /* Get value of eSPI registers */ - } else if (argc == 2) { - int i; - - if (strcasecmp(argv[1], "cfg") == 0) { - ccprintf("eSPI Reg32A [0x%08x]\n", - MCHP_ESPI_IO_REG32_A); - ccprintf("eSPI Reg32B [0x%08x]\n", - MCHP_ESPI_IO_REG32_B); - ccprintf("eSPI Reg32C [0x%08x]\n", - MCHP_ESPI_IO_REG32_C); - ccprintf("eSPI Reg32D [0x%08x]\n", - MCHP_ESPI_IO_REG32_D); - } else if (strcasecmp(argv[1], "vsm") == 0) { - for (i = 0; i < MSVW_MAX; i++) { - w0 = MSVW(i, 0); - w1 = MSVW(i, 1); - w2 = MSVW(i, 2); - ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i, - w2, w1, w0); - } - } else if (strcasecmp(argv[1], "vms") == 0) { - for (i = 0; i < SMVW_MAX; i++) { - w0 = SMVW(i, 0); - w1 = SMVW(i, 1); - ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0); - } - } - /* Enable/Disable the channels of eSPI */ - } else if (argc == 3) { - uint32_t m = (uint32_t) strtoi(argv[2], &e, 0); - - if (*e) - return EC_ERROR_PARAM2; - if (m < 0 || m > 4) - return EC_ERROR_PARAM2; - else if (m == 4) - chan = 0x0F; - else - chan = 0x01 << m; - if (strcasecmp(argv[1], "en") == 0) - MCHP_ESPI_IO_CAP0 |= chan; - else if (strcasecmp(argv[1], "dis") == 0) - MCHP_ESPI_IO_CAP0 &= ~chan; - else - return EC_ERROR_PARAM1; - ccprintf("eSPI IO Cap0 [0x%02x]\n", MCHP_ESPI_IO_CAP0); - } - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(espi, command_espi, - "cfg/vms/vsm/en/dis [channel]", - "eSPI configurations"); -#endif diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c deleted file mode 100644 index dc939bb58f..0000000000 --- a/chip/mchp/fan.c +++ /dev/null @@ -1,164 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MCHP MEC fan control module. */ - -/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */ - -#include "fan.h" -#include "registers.h" -#include "util.h" -#include "tfdp_chip.h" - -/* Maximum tach reading/target value */ -#define MAX_TACH 0x1fff - -/* Tach target value for disable fan */ -#define FAN_OFF_TACH 0xfff8 - -/* - * RPM = (n - 1) * m * f * 60 / poles / TACH - * n = number of edges = 5 - * m = multiplier defined by RANGE = 2 in our case - * f = 32.768K - * poles = 2 - */ -#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH) -#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1)) - -static int rpm_setting; -static int duty_setting; -static int in_rpm_mode = 1; - - -static void clear_status(void) -{ - /* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */ - MCHP_FAN_STATUS(0) = 0x23; -} - -void fan_set_enabled(int ch, int enabled) -{ - if (in_rpm_mode) { - if (enabled) - fan_set_rpm_target(ch, rpm_setting); - else - MCHP_FAN_TARGET(0) = FAN_OFF_TACH; - } else { - if (enabled) - fan_set_duty(ch, duty_setting); - else - MCHP_FAN_SETTING(0) = 0; - } - clear_status(); -} - -int fan_get_enabled(int ch) -{ - if (in_rpm_mode) - return (MCHP_FAN_TARGET(0) & 0xff00) != 0xff00; - else - return !!MCHP_FAN_SETTING(0); -} - -void fan_set_duty(int ch, int percent) -{ - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - duty_setting = percent; - MCHP_FAN_SETTING(0) = percent * 255 / 100; - clear_status(); -} - -int fan_get_duty(int ch) -{ - return duty_setting; -} - -int fan_get_rpm_mode(int ch) -{ - return !!(MCHP_FAN_CFG1(0) & BIT(7)); -} - -void fan_set_rpm_mode(int ch, int rpm_mode) -{ - if (rpm_mode) - MCHP_FAN_CFG1(0) |= BIT(7); - else - MCHP_FAN_CFG1(0) &= ~BIT(7); - clear_status(); -} - -int fan_get_rpm_actual(int ch) -{ - if ((MCHP_FAN_READING(0) >> 8) == 0xff) - return 0; - else - return TACH_TO_RPM(MCHP_FAN_READING(0) >> 3); -} - -int fan_get_rpm_target(int ch) -{ - return rpm_setting; -} - -void fan_set_rpm_target(int ch, int rpm) -{ - rpm_setting = rpm; - MCHP_FAN_TARGET(0) = RPM_TO_TACH(rpm) << 3; - clear_status(); -} - -enum fan_status fan_get_status(int ch) -{ - uint8_t sts = MCHP_FAN_STATUS(0); - - if (sts & (BIT(5) | BIT(1))) - return FAN_STATUS_FRUSTRATED; - if (fan_get_rpm_actual(ch) == 0) - return FAN_STATUS_STOPPED; - return FAN_STATUS_LOCKED; -} - -int fan_is_stalled(int ch) -{ - uint8_t sts = MCHP_FAN_STATUS(0); - - if (fan_get_rpm_actual(ch)) { - MCHP_FAN_STATUS(0) = 0x1; - return 0; - } - return sts & 0x1; -} - -void fan_channel_setup(int ch, unsigned int flags) -{ - /* Clear PCR sleep enable for RPM2FAN0 */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_RPMPWM0); - - /* - * Fan configuration 1 register: - * 0x80 = bit 7 = RPM mode (0x00 if FAN_USE_RPM_MODE not set) - * 0x20 = bits 6:5 = min 1000 RPM, multiplier = 2 - * 0x08 = bits 4:3 = 5 edges, 2 poles - * 0x03 = bits 2:0 = 400 ms update time - * - * Fan configuration 2 register: - * 0x00 = bit 6 = Ramp control disabled - * 0x00 = bit 5 = Glitch filter enabled - * 0x18 = bits 4:3 = Using both derivative options - * 0x02 = bits 2:1 = error range is 50 RPM - * 0x00 = bits 0 = normal polarity - */ - if (flags & FAN_USE_RPM_MODE) - MCHP_FAN_CFG1(0) = 0xab; - else - MCHP_FAN_CFG1(0) = 0x2b; - MCHP_FAN_CFG2(0) = 0x1a; - clear_status(); -} diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c deleted file mode 100644 index 043e2b268f..0000000000 --- a/chip/mchp/flash.c +++ /dev/null @@ -1,278 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "host_command.h" -#include "shared_mem.h" -#include "spi.h" -#include "spi_flash.h" -#include "system.h" -#include "util.h" -#include "hooks.h" -#include "tfdp_chip.h" - -#define PAGE_SIZE 256 - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -static int entire_flash_locked; - -/* The previous write protect state before sys jump */ - -struct flash_wp_state { - int entire_flash_locked; -}; - -/** - * Read from physical flash. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Destination buffer for data. - */ -int flash_physical_read(int offset, int size, char *data) -{ - trace13(0, FLASH, 0, - "flash_phys_read: offset=0x%08X size=0x%08X dataptr=0x%08X", - offset, size, (uint32_t)data); - return spi_flash_read(data, offset, size); -} - -/** - * Write to physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Data to write to flash. Must be 32-bit aligned. - */ -int flash_physical_write(int offset, int size, const char *data) -{ - int ret = EC_SUCCESS; - int i, write_size; - - trace13(0, FLASH, 0, - "flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X", - offset, size, (uint32_t)data); - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size | (uint32_t)(uintptr_t)data) & 3) - return EC_ERROR_INVAL; - - for (i = 0; i < size; i += write_size) { - write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE); - ret = spi_flash_write(offset + i, - write_size, - (uint8_t *)data + i); - if (ret != EC_SUCCESS) - break; - } - return ret; -} - -/** - * Erase physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE. - * - * @param offset Flash offset to erase. - * @param size Number of bytes to erase. - */ -int flash_physical_erase(int offset, int size) -{ - int ret; - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - trace12(0, FLASH, 0, - "flash_phys_erase: offset=0x%08X size=0x%08X", - offset, size); - ret = spi_flash_erase(offset, size); - return ret; -} - -/** - * Read physical write protect setting for a flash bank. - * - * @param bank Bank index to check. - * @return non-zero if bank is protected until reboot. - */ -int flash_physical_get_protect(int bank) -{ - return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE, - CONFIG_FLASH_BANK_SIZE); -} - -/** - * Protect flash now. - * - * This is always successful, and only emulates "now" protection - * - * @param all Protect all (=1) or just read-only - * @return non-zero if error. - */ -int flash_physical_protect_now(int all) -{ - if (all) - entire_flash_locked = 1; - - /* - * RO "now" protection is not currently implemented. If needed, it - * can be added by splitting the entire_flash_locked variable into - * and RO and RW vars, and setting + checking the appropriate var - * as required. - */ - return EC_SUCCESS; -} - -/** - * Return flash protect state flags from the physical layer. - * - * This should only be called by flash_get_protect(). - * - * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF, - CONFIG_WP_STORAGE_SIZE)) { - flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - } - - if (entire_flash_locked) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - return flags; -} - -/** - * Return the valid flash protect flags. - * - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -/** - * Return the writable flash protect flags. - * - * @param cur_flags The current flash protect flags. - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - enum spi_flash_wp wp_status = SPI_WP_NONE; - - wp_status = spi_flash_check_wp(); - - if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE && - !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) - ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - - if (!entire_flash_locked) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -/** - * Enable write protect for the specified range. - * - * Once write protect is enabled, it will stay enabled until HW PIN is - * de-asserted and SRP register is unset. - * - * However, this implementation treats FLASH_WP_ALL as FLASH_WP_RO but - * tries to remember if "all" region is protected. - * - * @param range The range to protect. - * @return EC_SUCCESS, or nonzero if error. - */ -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - int offset, size, ret; - enum spi_flash_wp flashwp = SPI_WP_NONE; - - if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) { - /* Clear protection */ - offset = size = 0; - flashwp = SPI_WP_NONE; - } else { - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - entire_flash_locked = 1; - - offset = CONFIG_WP_STORAGE_OFF; - size = CONFIG_WP_STORAGE_SIZE; - flashwp = SPI_WP_HARDWARE; - } - - ret = spi_flash_set_protect(offset, size); - if (ret == EC_SUCCESS) - ret = spi_flash_set_wp(flashwp); - return ret; -} - -/** - * Initialize the module. - * - * Applies at-boot protection settings if necessary. - */ -int flash_pre_init(void) -{ - flash_physical_restore_state(); - return EC_SUCCESS; -} - -int flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image - * could have applied write protection. Nothing additional needs - * to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) - entire_flash_locked = prev->entire_flash_locked; - return 1; - } - - return 0; -} - -/************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - struct flash_wp_state state; - - state.entire_flash_locked = entire_flash_locked; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c deleted file mode 100644 index 1de74dafcc..0000000000 --- a/chip/mchp/gpio.c +++ /dev/null @@ -1,435 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for MCHP MEC */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "lpc_chip.h" -#include "tfdp_chip.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - - -struct gpio_int_mapping { - int8_t girq_id; - int8_t port_offset; -}; - -/* - * Mapping from GPIO port to GIRQ info - * MEC17xx each bank contains 32 GPIO's. - * Pin Id is the bit position [0:31] - * Bank GPIO's GIRQ - * 0 0000 - 0036 11 - * 1 0040 - 0076 10 - * 2 0100 - 0135 9 - * 3 0140 - 0175 8 - * 4 0200 - 0235 12 - * 5 0240 - 0276 26 - */ -static const struct gpio_int_mapping int_map[6] = { - { 11, 0 }, { 10, 1 }, { 9, 2 }, - { 8, 3 }, { 12, 4 }, { 26, 5 } -}; - - - -/* - * NOTE: GCC __builtin_ffs(val) returns (index + 1) of least significant - * 1-bit of val or if val == 0 returns 0 - */ -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - int i; - uint32_t val; - - while (mask) { - i = __builtin_ffs(mask) - 1; - val = MCHP_GPIO_CTL(port, i); - val &= ~(BIT(12) | BIT(13)); - /* mux_control = DEFAULT, indicates GPIO */ - if (func > GPIO_ALT_FUNC_DEFAULT) - val |= (func & 0x3) << 12; - MCHP_GPIO_CTL(port, i) = val; - mask &= ~BIT(i); - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - uint32_t val; - - if (mask == 0) - return 0; - i = GPIO_MASK_TO_NUM(mask); - val = MCHP_GPIO_CTL(gpio_list[signal].port, i); - - return (val & BIT(24)) ? 1 : 0; -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - - if (mask == 0) - return; - i = GPIO_MASK_TO_NUM(mask); - - if (value) - MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); - else - MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); -} - -/* - * Add support for new #ifdef CONFIG_CMD_GPIO_POWER_DOWN. - * If GPIO_POWER_DONW flag is set force GPIO Control to - * GPIO input, interrupt detect disabled, power control field - * in bits[3:2]=10b. - * NOTE: if interrupt detect is enabled when pin is powered down - * then a false edge may be detected. - * - */ -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - int i; - uint32_t val; - - while (mask) { - i = GPIO_MASK_TO_NUM(mask); - mask &= ~BIT(i); - val = MCHP_GPIO_CTL(port, i); - -#ifdef CONFIG_GPIO_POWER_DOWN - if (flags & GPIO_POWER_DOWN) { - val = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); - MCHP_GPIO_CTL(port, i) = val; - continue; - } -#endif - val &= ~(MCHP_GPIO_CTRL_PWR_MASK); - val |= MCHP_GPIO_CTRL_PWR_VTR; - - /* - * Select open drain first, so that we don't - * glitch the signal when changing the line to - * an output. - */ - if (flags & GPIO_OPEN_DRAIN) - val |= (MCHP_GPIO_OPEN_DRAIN); - else - val &= ~(MCHP_GPIO_OPEN_DRAIN); - - if (flags & GPIO_OUTPUT) { - val |= (MCHP_GPIO_OUTPUT); - val &= ~(MCHP_GPIO_OUTSEL_PAR); - } else { - val &= ~(MCHP_GPIO_OUTPUT); - val |= (MCHP_GPIO_OUTSEL_PAR); - } - - /* Handle pull-up / pull-down */ - val &= ~(MCHP_GPIO_CTRL_PUD_MASK); - if (flags & GPIO_PULL_UP) - val |= MCHP_GPIO_CTRL_PUD_PU; - else if (flags & GPIO_PULL_DOWN) - val |= MCHP_GPIO_CTRL_PUD_PD; - else - val |= MCHP_GPIO_CTRL_PUD_NONE; - - /* Set up interrupt */ - val &= ~(MCHP_GPIO_INTDET_MASK); - switch (flags & GPIO_INT_ANY) { - case GPIO_INT_F_RISING: - val |= MCHP_GPIO_INTDET_EDGE_RIS; - break; - case GPIO_INT_F_FALLING: - val |= MCHP_GPIO_INTDET_EDGE_FALL; - break; - case GPIO_INT_BOTH: /* both edges */ - val |= MCHP_GPIO_INTDET_EDGE_BOTH; - break; - case GPIO_INT_F_LOW: - val |= MCHP_GPIO_INTDET_LVL_LO; - break; - case GPIO_INT_F_HIGH: - val |= MCHP_GPIO_INTDET_LVL_HI; - break; - default: - val |= MCHP_GPIO_INTDET_DISABLED; - break; - } - - /* Set up level */ - if (flags & GPIO_HIGH) - val |= (MCHP_GPIO_CTRL_OUT_LVL); - else if (flags & GPIO_LOW) - val &= ~(MCHP_GPIO_CTRL_OUT_LVL); - - MCHP_GPIO_CTL(port, i) = val; - } -} - -void gpio_power_off_by_mask(uint32_t port, uint32_t mask) -{ - int i; - - while (mask) { - i = GPIO_MASK_TO_NUM(mask); - mask &= ~BIT(i); - - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); - } -} - -int gpio_power_off(enum gpio_signal signal) -{ - int i, port; - - if (gpio_list[signal].mask == 0) - return EC_ERROR_INVAL; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + - MCHP_GPIO_INTDET_DISABLED); - - return EC_SUCCESS; -} - -/* - * gpio_list[signal].port = [0, 6] each port contains up to 32 pins - * gpio_list[signal].mask = bit mask in 32-bit port - * NOTE: MCHP GPIO are always aggregated not direct connected to NVIC. - * GPIO's are aggregated into banks of 32 pins. - * Each bank/port are connected to a GIRQ. - * int_map[port].girq_id is the GIRQ ID - * The bit number in the GIRQ registers is the same as the bit number - * in the GPIO bank. - */ -int gpio_enable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - - MCHP_INT_ENABLE(girq_id) = BIT(i); - MCHP_INT_BLK_EN |= BIT(girq_id); - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - - - MCHP_INT_DISABLE(girq_id) = BIT(i); - - return EC_SUCCESS; -} - -/* - * MCHP Interrupt Source is R/W1C no need for read-modify-write. - * GPIO's are aggregated meaning the NVIC Pending bit may be - * set for another GPIO in the GIRQ. You can clear NVIC pending - * and the hardware should re-assert it within one Cortex-M4 clock. - * If the Cortex-M4 is clocked slower than AHB then the Cortex-M4 - * will take longer to register the interrupt. Not clearing NVIC - * pending leave a pending status if only the GPIO this routine - * clears is pending. - * NVIC (system control) register space is strongly-ordered - * Interrupt Aggregator is in Device space (system bus connected - * to AHB) with the Cortex-M4 write buffer. - * We need to insure the write to aggregator register in device - * AHB space completes before NVIC pending is cleared. - * The Cortex-M4 memory ordering rules imply Device access - * comes before strongly ordered access. Cortex-M4 will not re-order - * the writes. Due to the presence of the write buffer a DSB will - * not guarantee the clearing of the device status completes. Add - * a read back before clearing NVIC pending. - * GIRQ 8, 9, 10, 11, 12, 26 map to NVIC inputs 0, 1, 2, 3, 4, and 18. - */ -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - - /* Clear interrupt source sticky status bit even if not enabled */ - MCHP_INT_SOURCE(girq_id) = BIT(i); - i = MCHP_INT_SOURCE(girq_id); - task_clear_pending_irq(girq_id - 8); - - return EC_SUCCESS; -} - -/* - * MCHP NOTE - called from main before scheduler started - */ -void gpio_pre_init(void) -{ - int i; - int flags; - int is_warm = system_is_reboot_warm(); - const struct gpio_info *g = gpio_list; - - - for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - - /* Use as GPIO, not alternate function */ - gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); - } -} - -/* Clear any interrupt flags before enabling GPIO interrupt - * Original code has flaws. - * Writing result register to source only clears bits that have their - * enable and sources bits set. - * We must clear the NVIC pending R/W bit before setting NVIC enable. - * NVIC Pending is only cleared by the NVIC HW on ISR entry. - * Modifications are: - * 1. Clear all status bits in each GPIO GIRQ. This assumes any edges - * will occur after gpio_init. The old code is also making this - * assumption for the GPIO's that have been enabled. - * 2. Clear NVIC pending to prevent ISR firing on false edge. - */ -#define ENABLE_GPIO_GIRQ(x) \ - do { \ - MCHP_INT_SOURCE(x) = 0xfffffffful; \ - task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \ - task_enable_irq(MCHP_IRQ_GIRQ ## x); \ - } while (0) - - -static void gpio_init(void) -{ - ENABLE_GPIO_GIRQ(8); - ENABLE_GPIO_GIRQ(9); - ENABLE_GPIO_GIRQ(10); - ENABLE_GPIO_GIRQ(11); - ENABLE_GPIO_GIRQ(12); - ENABLE_GPIO_GIRQ(26); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/************************************************************************/ -/* Interrupt handlers */ - - -/** - * Handler for each GIRQ interrupt. This reads and clears the interrupt - * bits for the GIRQ interrupt, then finds and calls the corresponding - * GPIO interrupt handlers. - * - * @param girq GIRQ index - * @param port zero based GPIO port number [0, 5] - * @note __builtin_ffs(x) returns bitpos+1 of least significant 1-bit - * in x or 0 if no bits are set. - */ -static void gpio_interrupt(int girq, int port) -{ - int i, bit; - const struct gpio_info *g = gpio_list; - uint32_t sts = MCHP_INT_RESULT(girq); - - /* RW1C, no need for read-modify-write */ - MCHP_INT_SOURCE(girq) = sts; - - trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts); - trace12(0, GPIO, 0, "GPIO ParIn[%d] = 0x%08x", - port, MCHP_GPIO_PARIN(port)); - - for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) { - if (g->port != port) - continue; - - bit = __builtin_ffs(g->mask); - if (bit) { - bit--; - if (sts & BIT(bit)) { - trace12(0, GPIO, 0, - "Bit[%d]: handler @ 0x%08x", bit, - (uint32_t)gpio_irq_handlers[i]); - gpio_irq_handlers[i](i); - } - sts &= ~BIT(bit); - } - } -} - -#define GPIO_IRQ_FUNC(irqfunc, girq, port)\ - void irqfunc(void) \ - { \ - gpio_interrupt(girq, port);\ - } - -GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3); -GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 2); -GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 1); -GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0); -GPIO_IRQ_FUNC(__girq_12_interrupt, 12, 4); -GPIO_IRQ_FUNC(__girq_26_interrupt, 26, 5); - -#undef GPIO_IRQ_FUNC - -/* - * Declare IRQs. Nesting this macro inside the GPIO_IRQ_FUNC macro works - * poorly because DECLARE_IRQ() stringizes its inputs. - */ -DECLARE_IRQ(MCHP_IRQ_GIRQ8, __girq_8_interrupt, 1); -DECLARE_IRQ(MCHP_IRQ_GIRQ9, __girq_9_interrupt, 1); -DECLARE_IRQ(MCHP_IRQ_GIRQ10, __girq_10_interrupt, 1); -DECLARE_IRQ(MCHP_IRQ_GIRQ11, __girq_11_interrupt, 1); -DECLARE_IRQ(MCHP_IRQ_GIRQ12, __girq_12_interrupt, 1); -DECLARE_IRQ(MCHP_IRQ_GIRQ26, __girq_26_interrupt, 1); - diff --git a/chip/mchp/gpio_chip.h b/chip/mchp/gpio_chip.h deleted file mode 100644 index 7baaa76fa2..0000000000 --- a/chip/mchp/gpio_chip.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MCHP MEC processor - */ -/** @file gpio_chip.h - *MEC GPIO module - */ -/** @defgroup MEC gpio - */ - -#ifndef _GPIO_CHIP_H -#define _GPIO_CHIP_H - -#include <stdint.h> -#include <stddef.h> - -#include "gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Place any C interfaces here */ - -int gpio_power_off(enum gpio_signal signal); - -void gpio_power_off_by_mask(uint32_t port, uint32_t mask); - -#ifdef __cplusplus -} -#endif - -#endif /* #ifndef _GPIO_CHIP_H */ -/** @} - */ - diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c deleted file mode 100644 index cbf5f4c462..0000000000 --- a/chip/mchp/gpio_cmds.c +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MCHP MEC GPIO module EC UART commands */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "util.h" -#include "gpio_chip.h" -#include "tfdp_chip.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - - - -static int cmd_gp_get_config(int argc, char **argv) -{ - char *e; - int i; - uint32_t gctrl; - - /* If a signal is specified, print only that one */ - if (argc == 2) { - i = strtoi(argv[1], &e, 0); - if (*e) - return EC_ERROR_PARAM1; - - if (!gpio_is_implemented(i)) - return EC_ERROR_PARAM1; - - gctrl = MCHP_GPIO_CTRL(i); - - ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl); - - } else { /* Otherwise print them all */ - for (i = 0; i < GPIO_COUNT; i++) { - if (!gpio_is_implemented(i)) - continue; /* Skip unsupported signals */ - - gctrl = MCHP_GPIO_CTRL(i); - - ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl); - } - } - - /* Flush console to avoid truncating output */ - cflush(); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config, - "[number]", - "Read GPIO config"); - -static int cmd_gp_set_config(int argc, char **argv) -{ - char *e; - int i; - uint32_t gctrl; - - /* If a signal is specified, print only that one */ - if (argc > 2) { - i = strtoi(argv[1], &e, 0); - if (*e) - return EC_ERROR_PARAM1; - - if (!gpio_is_implemented(i)) - return EC_ERROR_PARAM1; - - gctrl = (uint32_t)strtoi(argv[2], &e, 0); - if (*e) - return EC_ERROR_PARAM2; - - MCHP_GPIO_CTRL(i) = gctrl; - gctrl = MCHP_GPIO_CTRL(i); - ccprintf(" GPIO[0x%X].Ctrl = 0x%08X\n", i, gctrl); - - } else { - ccprintf(" Requires two parameters: GPIO num and new config"); - } - /* Flush console to avoid truncating output */ - cflush(); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config, - "gp_num val", - "Set GPIO config"); - diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c deleted file mode 100644 index f8b556d389..0000000000 --- a/chip/mchp/gpspi.c +++ /dev/null @@ -1,267 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* General Purpose SPI master module for MCHP MEC */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "timer.h" -#include "util.h" -#include "hooks.h" -#include "task.h" -#include "spi_chip.h" -#include "gpspi_chip.h" -#include "tfdp_chip.h" - -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) -/* One byte at 12 MHz full duplex = 0.67 us */ -#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 20 - -/* - * GP-SPI - */ - -/** - * Return zero based GPSPI controller index given hardware port. - * @param hw_port b[7:4]==1 (GPSPI), b[3:0]=0(GPSPI0), 1(GPSPI1) - * @return 0(GPSPI0) or 1(GPSPI1) - */ -static uint8_t gpspi_port_to_ctrl_id(uint8_t hw_port) -{ - return (hw_port & 0x01); -} - -static int gpspi_wait_byte(const int ctrl) -{ - timestamp_t deadline; - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - while ((MCHP_SPI_SR(ctrl) & 0x3) != 0x3) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - return EC_SUCCESS; -} - -/* NOTE: auto-read must be disabled before calling this routine! */ -static void gpspi_rx_fifo_clean(const int ctrl) -{ - uint8_t dummy = 0; - - /* If ACTIVE and/or RXFF then clean it */ - if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4) - dummy += MCHP_SPI_RD(ctrl); - - if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2) - dummy += MCHP_SPI_RD(ctrl); -} -/* - * NOTE: auto-read must be disabled before calling this routine! - */ -#ifndef CONFIG_MCHP_GPSPI_TX_DMA -static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) -{ - int i; - int ret; - uint8_t dummy = 0; - - gpspi_rx_fifo_clean(ctrl); - - ret = EC_SUCCESS; - for (i = 0; i < txlen; ++i) { - MCHP_SPI_TD(ctrl) = txdata[i]; - ret = gpspi_wait_byte(ctrl); - if (ret != EC_SUCCESS) - break; - dummy += MCHP_SPI_RD(ctrl); - } - - return ret; -} -#endif - -int gpspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int hw_port, ctrl; - int ret = EC_SUCCESS; - int cs_asserted = 0; - const struct dma_option *opdma; -#ifdef CONFIG_MCHP_GPSPI_TX_DMA - dma_chan_t *chan; -#endif - if (spi_device == NULL) - return EC_ERROR_PARAM1; - - hw_port = spi_device->port; - - ctrl = gpspi_port_to_ctrl_id(hw_port); - - /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~BIT(5); - - if ((txdata != NULL) && (txdata != 0)) { -#ifdef CONFIG_MCHP_GPSPI_TX_DMA - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR); - if (opdma == NULL) - return EC_ERROR_INVAL; - - gpspi_rx_fifo_clean(ctrl); - - dma_prepare_tx(opdma, txlen, txdata); - - chan = dma_get_channel(opdma->channel); - - gpio_set_level(spi_device->gpio_cs, 0); - cs_asserted = 1; - - dma_go(chan); - ret = dma_wait(opdma->channel); - if (ret == EC_SUCCESS) - ret = gpspi_wait_byte(ctrl); - - dma_disable(opdma->channel); - dma_clear_isr(opdma->channel); - - gpspi_rx_fifo_clean(ctrl); -#else - gpio_set_level(spi_device->gpio_cs, 0); - cs_asserted = 1; - - ret = gpspi_tx(ctrl, txdata, txlen); -#endif - } - - if (ret == EC_SUCCESS) - if ((rxlen != 0) && (rxdata != NULL)) { - ret = EC_ERROR_INVAL; - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - if (opdma != NULL) { - if (!cs_asserted) - gpio_set_level(spi_device->gpio_cs, 0); - /* Enable auto read */ - MCHP_SPI_CR(ctrl) |= BIT(5); - dma_start_rx(opdma, rxlen, rxdata); - MCHP_SPI_TD(ctrl) = 0; - ret = EC_SUCCESS; - } - } - - return ret; -} - -int gpspi_transaction_flush(const struct spi_device_t *spi_device) -{ - int ctrl, hw_port; - int ret; - enum dma_channel chan; - const struct dma_option *opdma; - timestamp_t deadline; - - if (spi_device == NULL) - return EC_ERROR_PARAM1; - - hw_port = spi_device->port; - ctrl = gpspi_port_to_ctrl_id(hw_port); - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - chan = opdma->channel; - - ret = dma_wait(chan); - - /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~BIT(5); - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - /* Wait for FIFO empty SPISR_TXBE */ - while ((MCHP_SPI_SR(ctrl) & 0x01) != 0x1) { - if (timestamp_expired(deadline, NULL)) { - ret = EC_ERROR_TIMEOUT; - break; - } - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - - dma_disable(chan); - dma_clear_isr(chan); - if (MCHP_SPI_SR(ctrl) & 0x2) - hw_port = MCHP_SPI_RD(ctrl); - - gpio_set_level(spi_device->gpio_cs, 1); - - return ret; -} - -int gpspi_transaction_wait(const struct spi_device_t *spi_device) -{ - const struct dma_option *opdma; - - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - - return dma_wait(opdma->channel); -} - -/** - * Enable GPSPI controller and MODULE_SPI_MASTER pins - * - * @param hw_port b[7:4]=1 b[3:0]=0(GPSPI0), 1(GPSPI1) - * @param enable - * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized - * @note called from mec1701/spi.c - * - */ -int gpspi_enable(int hw_port, int enable) -{ - uint32_t ctrl; - - if ((hw_port != GPSPI0_PORT) && (hw_port != GPSPI1_PORT)) - return EC_ERROR_INVAL; - - gpio_config_module(MODULE_SPI_MASTER, (enable > 0)); - - ctrl = (uint32_t)hw_port & 0x0f; - - if (enable) { - - if (ctrl) - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1); - else - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI0); - - /* Set enable bit in SPI_AR */ - MCHP_SPI_AR(ctrl) |= 0x1; - - /* Set SPDIN to 0 -> Full duplex */ - MCHP_SPI_CR(ctrl) &= ~(0x3 << 2); - - /* Set CLKPOL, TCLKPH, RCLKPH to 0 */ - MCHP_SPI_CC(ctrl) &= ~0x7; - - /* Set LSBF to 0 -> MSB first */ - MCHP_SPI_CR(ctrl) &= ~0x1; - } else { - /* soft reset */ - MCHP_SPI_CR(ctrl) |= (1u << 4); - - /* Clear enable bit in SPI_AR */ - MCHP_SPI_AR(ctrl) &= ~0x1; - - if (ctrl) - MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI1); - else - MCHP_PCR_SLP_EN_DEV(MCHP_PCR_GPSPI0); - } - - return EC_SUCCESS; -} - diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h deleted file mode 100644 index 529a727e36..0000000000 --- a/chip/mchp/gpspi_chip.h +++ /dev/null @@ -1,35 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MCHP MEC processor - */ -/** @file gpspi_chip.h - *MCHP MEC General Purpose SPI Master - */ -/** @defgroup MCHP MEC gpspi - */ - -#ifndef _GPSPI_CHIP_H -#define _GPSPI_CHIP_H - -#include <stdint.h> -#include <stddef.h> - -/* struct spi_device_t */ -#include "spi.h" - -int gpspi_transaction_flush(const struct spi_device_t *spi_device); - -int gpspi_transaction_wait(const struct spi_device_t *spi_device); - -int gpspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); - -int gpspi_enable(int port, int enable); - -#endif /* #ifndef _GPSPI_CHIP_H */ -/** @} - */ - diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c deleted file mode 100644 index e84f278f4a..0000000000 --- a/chip/mchp/hwtimer.c +++ /dev/null @@ -1,121 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "clock.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "tfdp_chip.h" - -void __hw_clock_event_set(uint32_t deadline) -{ - MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - - (0xffffffff - deadline); - MCHP_TMR32_CTL(1) |= BIT(5); -} - -uint32_t __hw_clock_event_get(void) -{ - return MCHP_TMR32_CNT(1) - MCHP_TMR32_CNT(0) + 0xffffffff; -} - -void __hw_clock_event_clear(void) -{ - MCHP_TMR32_CTL(1) &= ~BIT(5); -} - -uint32_t __hw_clock_source_read(void) -{ - return 0xffffffff - MCHP_TMR32_CNT(0); -} - -void __hw_clock_source_set(uint32_t ts) -{ - MCHP_TMR32_CTL(0) &= ~BIT(5); - MCHP_TMR32_CNT(0) = 0xffffffff - ts; - MCHP_TMR32_CTL(0) |= BIT(5); -} - -/* - * Always clear both timer and aggregator status - */ -static void __hw_clock_source_irq(int timer_id) -{ - MCHP_TMR32_STS(timer_id & 0x01) |= 1; - MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(timer_id & 0x01); - - /* If IRQ is from timer 0, 32-bit timer overflowed */ - process_timers(timer_id == 0); -} - -void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); } -DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1); -void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); } -DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1); - -static void configure_timer(int timer_id) -{ - uint32_t val; - - /* Ensure timer is not running */ - MCHP_TMR32_CTL(timer_id) &= ~BIT(5); - - /* Enable timer */ - MCHP_TMR32_CTL(timer_id) |= BIT(0); - - val = MCHP_TMR32_CTL(timer_id); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MCHP_TMR32_CTL(timer_id) = val; - - /* Set preload to use the full 32 bits of the timer */ - MCHP_TMR32_PRE(timer_id) = 0xffffffff; - - /* Enable interrupt */ - MCHP_TMR32_IEN(timer_id) |= 1; -} - -int __hw_clock_source_init(uint32_t start_t) -{ - MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 + - MCHP_PCR_SLP_EN3_BTMR32_1); - - /* - * The timer can only fire interrupt when its value reaches zero. - * Therefore we need two timers: - * - Timer 0 as free running timer - * - Timer 1 as event timer - */ - configure_timer(0); - configure_timer(1); - - /* Override the count */ - MCHP_TMR32_CNT(0) = 0xffffffff - start_t; - - /* Auto restart */ - MCHP_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= BIT(5); - - /* Enable interrupt */ - task_enable_irq(MCHP_IRQ_TIMER32_0); - task_enable_irq(MCHP_IRQ_TIMER32_1); - MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); - /* - * Not needed when using direct mode interrupts - * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ); - */ - return MCHP_IRQ_TIMER32_1; -} diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c deleted file mode 100644 index ab2c75c754..0000000000 --- a/chip/mchp/i2c.c +++ /dev/null @@ -1,964 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C port module for MCHP MEC - * TODO handle chip variants - */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "tfdp_chip.h" - -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* - * MCHP I2C BAUD clock source is 16 MHz. - */ -#define I2C_CLOCK 16000000 /* 16 MHz */ - -/* SMBus Timing values for 1MHz Speed */ -#define SPEED_1MHZ_BUS_CLOCK 0x0509 -#define SPEED_1MHZ_DATA_TIMING 0x06060601 -#define SPEED_1MHZ_DATA_TIMING_2 0x06 -#define SPEED_1MHZ_IDLE_SCALING 0x01000050 -#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7 -/* SMBus Timing values for 400kHz speed */ -#define SPEED_400KHZ_BUS_CLOCK 0x0F17 -#define SPEED_400KHZ_DATA_TIMING 0x040A0F01 -#define SPEED_400KHZ_DATA_TIMING_2 0x0A -#define SPEED_400KHZ_IDLE_SCALING 0x01000050 -#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7 -/* SMBus Timing values for 100kHz speed */ -#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful -#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul -#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul -#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul -#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul -/* Status */ -#define STS_NBB BIT(0) /* Bus busy */ -#define STS_LAB BIT(1) /* Arbitration lost */ -#define STS_LRB BIT(3) /* Last received bit */ -#define STS_BER BIT(4) /* Bus error */ -#define STS_PIN BIT(7) /* Pending interrupt */ -/* Control */ -#define CTRL_ACK BIT(0) /* Acknowledge */ -#define CTRL_STO BIT(1) /* STOP */ -#define CTRL_STA BIT(2) /* START */ -#define CTRL_ENI BIT(3) /* Enable interrupt */ -#define CTRL_ESO BIT(6) /* Enable serial output */ -#define CTRL_PIN BIT(7) /* Pending interrupt not */ -/* Completion */ -#define COMP_DTEN BIT(2) /* enable device timeouts */ -#define COMP_MCEN BIT(3) /* enable master cumulative timeouts */ -#define COMP_SCEN BIT(4) /* enable slave cumulative timeouts */ -#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */ -#define COMP_IDLE BIT(29) /* i2c bus is idle */ -#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ -/* Configuration */ -#define CFG_PORT_MASK (0x0F) /* port selection field */ -#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */ -#define CFG_FEN BIT(8) /* enable input filtering */ -#define CFG_RESET BIT(9) /* reset controller */ -#define CFG_ENABLE BIT(10) /* enable controller */ -#define CFG_GC_DIS BIT(14) /* disable general call address */ -#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */ -/* Enable network layer master done interrupt */ -#define CFG_ENMI BIT(30) -/* Enable network layer slave done interrupt */ -#define CFG_ENSI BIT(31) -/* Master Command */ -#define MCMD_MRUN BIT(0) -#define MCMD_MPROCEED BIT(1) -#define MCMD_START0 BIT(8) -#define MCMD_STARTN BIT(9) -#define MCMD_STOP BIT(10) -#define MCMD_READM BIT(12) -#define MCMD_WCNT_BITPOS (16) -#define MCMD_WCNT_MASK0 (0xFF) -#define MCMD_WCNT_MASK (0xFF << 16) -#define MCMD_RCNT_BITPOS (24) -#define MCMD_RCNT_MASK0 (0xFF) -#define MCMD_RCNT_MASK (0xFF << 24) - -/* Maximum transfer of a SMBUS block transfer */ -#define SMBUS_MAX_BLOCK_SIZE 32 -/* - * Amount of time to blocking wait for i2c bus to finish. After this - * blocking timeout, if the bus is still not finished, then allow other - * tasks to run. - * Note: this is just long enough for a 400kHz bus to finish transmitting - * one byte assuming the bus isn't being held. - */ -#define I2C_WAIT_BLOCKING_TIMEOUT_US 25 - -enum i2c_transaction_state { - /* Stop condition was sent in previous transaction */ - I2C_TRANSACTION_STOPPED, - /* Stop condition was not sent in previous transaction */ - I2C_TRANSACTION_OPEN, -}; - -/* I2C controller state data - * NOTE: I2C_CONTROLLER_COUNT is defined at board level. - */ -static struct { - /* Transaction timeout, or 0 to use default. */ - uint32_t timeout_us; - /* Task waiting on port, or TASK_ID_INVALID if none. */ - /* - * MCHP Remove volatile. - * ISR only reads. - * Non-ISR only writes when interrupt is disabled. - */ - task_id_t task_waiting; - enum i2c_transaction_state transaction_state; - /* transaction context */ - int out_size; - const uint8_t *outp; - int in_size; - uint8_t *inp; - int xflags; - uint32_t i2c_complete; /* ISR write */ - uint32_t flags; - uint8_t port; - uint8_t slv_addr_8bit; - uint8_t ctrl; - uint8_t hwsts; - uint8_t hwsts2; - uint8_t hwsts3; /* ISR write */ - uint8_t hwsts4; - uint8_t lines; -} cdata[I2C_CONTROLLER_COUNT]; - -static const uint16_t i2c_controller_pcr[MCHP_I2C_CTRL_MAX] = { - MCHP_PCR_I2C0, - MCHP_PCR_I2C1, - MCHP_PCR_I2C2, - MCHP_PCR_I2C3 -}; - -static int chip_i2c_is_controller_valid(int controller) -{ - if ((controller < 0) || (controller >= MCHP_I2C_CTRL_MAX)) - return 0; - return 1; -} - -static void i2c_ctrl_slp_en(int controller, int sleep_en) -{ - if (!chip_i2c_is_controller_valid(controller)) - return; - if (sleep_en) - MCHP_PCR_SLP_EN_DEV(i2c_controller_pcr[controller]); - else - MCHP_PCR_SLP_DIS_DEV(i2c_controller_pcr[controller]); -} - -uint32_t chip_i2c_get_ctx_flags(int port) -{ - int controller = i2c_port_to_controller(port); - - if (!chip_i2c_is_controller_valid(controller)) - return 0; - return cdata[controller].flags; -} - -/* - * MCHP I2C controller tuned bus clock values. - * MCHP I2C_SMB_Controller_3.6.pdf Table 6-3 - */ -struct i2c_bus_clk { - int freq_khz; - int bus_clk; -}; - -const struct i2c_bus_clk i2c_freq_tbl[] = { - { 40, 0xC7C7 }, - { 80, 0x6363 }, - { 100, 0x4F4F }, - { 333, 0x0F1F }, - { 400, 0x0F17 }, - { 1000, 0x0509 }, -}; - -static int get_closest(int lesser, int greater, int target) -{ - if (target - i2c_freq_tbl[lesser].freq_khz >= - i2c_freq_tbl[greater].freq_khz - target) - return greater; - else - return lesser; -} - -/* - * Return index in i2c_freq_tbl of supported frequeny - * closest to requested frequency. - */ -static const struct i2c_bus_clk *get_supported_speed_idx(int req_kbps) -{ - int i, limit, m, imax; - - ASSERT(ARRAY_SIZE(i2c_freq_tbl) != 0); - - if (req_kbps <= i2c_freq_tbl[0].freq_khz) - return &i2c_freq_tbl[0]; - - imax = ARRAY_SIZE(i2c_freq_tbl); - if (req_kbps >= i2c_freq_tbl[imax-1].freq_khz) - return &i2c_freq_tbl[imax-1]; - - /* we only get here if ARRAY_SIZE(...) > 1 - * and req_kbps is in range. - */ - i = 0; - limit = imax; - while (i < limit) { - m = (i + limit) / 2; - if (i2c_freq_tbl[m].freq_khz == req_kbps) - break; - - if (req_kbps < i2c_freq_tbl[m].freq_khz) { - if (m > 0 && req_kbps > i2c_freq_tbl[m-1].freq_khz) { - m = get_closest(m-1, m, req_kbps); - break; - } - limit = m; - } else { - if (m < imax-1 && - req_kbps < i2c_freq_tbl[m+1].freq_khz) { - m = get_closest(m, m+1, req_kbps); - break; - } - i = m + 1; - } - } - - return &i2c_freq_tbl[m]; -} - -/* - * Refer to NXP UM10204 for minimum timing requirement of T_Low and T_High. - * http://www.nxp.com/documents/user_manual/UM10204.pdf - * I2C spec. timing value are used in recommended registers values - * in MCHP I2C_SMB_Controller_3.6.pdf - * Restrict frequencies to those in the above MCHP spec. - * 40, 80, 100, 333, 400, and 1000 kHz. - */ -static void configure_controller_speed(int controller, int kbps) -{ - const struct i2c_bus_clk *p; - - p = get_supported_speed_idx(kbps); - MCHP_I2C_BUS_CLK(controller) = p->bus_clk; - - if (p->freq_khz > 400) { /* Fast mode plus */ - MCHP_I2C_DATA_TIM(controller) = SPEED_1MHZ_DATA_TIMING; - MCHP_I2C_DATA_TIM_2(controller) = SPEED_1MHZ_DATA_TIMING_2; - MCHP_I2C_IDLE_SCALE(controller) = SPEED_1MHZ_IDLE_SCALING; - MCHP_I2C_TOUT_SCALE(controller) = SPEED_1MHZ_TIMEOUT_SCALING; - } else if (p->freq_khz > 100) { /* Fast mode */ - MCHP_I2C_DATA_TIM(controller) = SPEED_400KHZ_DATA_TIMING; - MCHP_I2C_DATA_TIM_2(controller) = SPEED_400KHZ_DATA_TIMING_2; - MCHP_I2C_IDLE_SCALE(controller) = SPEED_400KHZ_IDLE_SCALING; - MCHP_I2C_TOUT_SCALE(controller) = SPEED_400KHZ_TIMEOUT_SCALING; - } else { /* Standard mode */ - MCHP_I2C_DATA_TIM(controller) = SPEED_100KHZ_DATA_TIMING; - MCHP_I2C_DATA_TIM_2(controller) = SPEED_100KHZ_DATA_TIMING_2; - MCHP_I2C_IDLE_SCALE(controller) = SPEED_100KHZ_IDLE_SCALING; - MCHP_I2C_TOUT_SCALE(controller) = SPEED_100KHZ_TIMEOUT_SCALING; - } -} - -/* - * NOTE: direct mode interrupts do not need GIRQn bit - * set in aggregator block enable register. - */ -static void enable_controller_irq(int controller) -{ - MCHP_INT_ENABLE(MCHP_I2C_GIRQ) = - MCHP_I2C_GIRQ_BIT(controller); - task_enable_irq(MCHP_IRQ_I2C_0 + controller); -} - -static void disable_controller_irq(int controller) -{ - MCHP_INT_DISABLE(MCHP_I2C_GIRQ) = - MCHP_I2C_GIRQ_BIT(controller); - /* read back into read-only reg. to insure disable takes effect */ - MCHP_INT_BLK_IRQ = MCHP_INT_DISABLE(MCHP_I2C_GIRQ); - task_disable_irq(MCHP_IRQ_I2C_0 + controller); - task_clear_pending_irq(MCHP_IRQ_I2C_0 + controller); -} - -/* - * Do NOT enable controller's IDLE interrupt in the configuration - * register. IDLE is meant for mult-master and controller as slave. - */ -static void configure_controller(int controller, int port, int kbps) -{ - if (!chip_i2c_is_controller_valid(controller)) - return; - - disable_controller_irq(controller); - MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = - MCHP_I2C_GIRQ_BIT(controller); - - /* set to default except for port select field b[3:0] */ - MCHP_I2C_CONFIG(controller) = (uint32_t)(port & 0xf); - MCHP_I2C_CTRL(controller) = CTRL_PIN; - - /* Set both controller slave addresses to 0 the - * general call address. We disable general call - * below. - */ - MCHP_I2C_OWN_ADDR(controller) = 0; - - configure_controller_speed(controller, kbps); - - /* Controller timings done, clear RO status, enable - * output, and ACK generation. - */ - MCHP_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK; - - /* filter enable, disable General Call */ - MCHP_I2C_CONFIG(controller) |= CFG_FEN + CFG_GC_DIS; - /* enable controller */ - MCHP_I2C_CONFIG(controller) |= CFG_ENABLE; -} - -static void reset_controller(int controller) -{ - int i; - - /* Reset asserted for at least one AHB clock */ - MCHP_I2C_CONFIG(controller) |= BIT(9); - MCHP_EC_ID_RO = 0; - MCHP_I2C_CONFIG(controller) &= ~BIT(9); - - for (i = 0; i < i2c_ports_used; ++i) - if (controller == i2c_port_to_controller(i2c_ports[i].port)) { - configure_controller(controller, i2c_ports[i].port, - i2c_ports[i].kbps); - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - break; - } -} - -/* - * !!! WARNING !!! - * We have observed task_wait_event_mask() returning 0 if the I2C - * controller IDLE interrupt is enabled. We believe it is due to the ISR - * post multiple events too quickly but don't have absolute proof. - */ -static int wait_for_interrupt(int controller, int timeout) -{ - int event; - - if (timeout <= 0) - return EC_ERROR_TIMEOUT; - - cdata[controller].task_waiting = task_get_current(); - enable_controller_irq(controller); - - /* Wait until I2C interrupt or timeout. */ - event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout); - - disable_controller_irq(controller); - cdata[controller].task_waiting = TASK_ID_INVALID; - - return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS; -} - -static int wait_idle(int controller) -{ - uint8_t sts = MCHP_I2C_STATUS(controller); - uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - uint64_t task_timeout = block_timeout + cdata[controller].timeout_us; - int rv = 0; - - while (!(sts & STS_NBB)) { - if (rv) - return rv; - if (get_time().val > block_timeout) - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - sts = MCHP_I2C_STATUS(controller); - } - - if (sts & (STS_BER | STS_LAB)) - return EC_ERROR_UNKNOWN; - return EC_SUCCESS; -} - -/* - * Return EC_SUCCESS on ACK of byte else EC_ERROR_UNKNOWN. - * Record I2C.Status in cdata[controller] structure. - * Byte transmit finished with no I2C bus error or lost arbitration. - * PIN -> 0. LRB bit contains slave ACK/NACK bit. - * Slave ACK: I2C.Status == 0x00 - * Slave NACK: I2C.Status == 0x08 - * Byte transmit finished with I2C bus errors or lost arbitration. - * PIN -> 0 and BER and/or LAB set. - * - * Byte receive finished with no I2C bus errors or lost arbitration. - * PIN -> 0. LRB=0/1 based on ACK bit in I2C.Control. - * Master receiver must NACK last byte it wants to receive. - * How do we handle this if we don't know direction of transfer? - * I2C.Control is write-only so we can't see Master's ACK control bit. - * - */ -static int wait_byte_done(int controller, uint8_t mask, uint8_t expected) -{ - uint64_t block_timeout; - uint64_t task_timeout; - int rv; - uint8_t sts; - - rv = 0; - block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - task_timeout = block_timeout + cdata[controller].timeout_us; - sts = MCHP_I2C_STATUS(controller); - cdata[controller].hwsts = sts; - while (sts & STS_PIN) { - if (rv) - return rv; - if (get_time().val > block_timeout) { - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - } - sts = MCHP_I2C_STATUS(controller); - cdata[controller].hwsts = sts; - } - - rv = EC_SUCCESS; - if ((sts & mask) != expected) - rv = EC_ERROR_UNKNOWN; - return rv; -} - -/* - * Select port on controller. If controller configured - * for port do nothing. - * Switch port by reset and reconfigure to handle cases where - * the slave on current port is driving line(s) low. - * NOTE: I2C hardware reset only requires one AHB clock, back to back - * writes is OK but we added a dummy write as insurance. - */ -static void select_port(int port, int controller) -{ - uint32_t port_sel; - - port_sel = (uint32_t)(port & 0x0f); - if ((MCHP_I2C_CONFIG(controller) & 0x0f) == port_sel) - return; - - MCHP_I2C_CONFIG(controller) |= BIT(9); - MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */ - MCHP_I2C_CONFIG(controller) &= ~BIT(9); - configure_controller(controller, port_sel, i2c_ports[port].kbps); -} - -/* - * Use safe method (reading GPIO.Control PAD input bit) - * to obtain SCL line state in bit[0] and SDA line state in bit[1]. - * NOTE: I2C controller bit-bang register is not safe. Using - * bit-bang requires timeouts be disabled and the controller in an - * idle state. Switching controller to bit-bang mode when the controller - * is not idle will cause problems. - */ -static uint32_t get_line_level(int port) -{ - uint32_t lines; - - lines = i2c_raw_get_scl(port) & 0x01; - lines |= (i2c_raw_get_sda(port) & 0x01) << 1; - return lines; -} - -/* - * Check if I2C port connected to controller has bus error or - * other signalling issues such as stuck clock/data lines. - */ -static int i2c_check_recover(int port, int controller) -{ - uint32_t lines; - uint8_t reg; - lines = get_line_level(port); - reg = MCHP_I2C_STATUS(controller); - - if ((((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) || - (lines != I2C_LINE_IDLE))) { - cdata[controller].flags |= (1ul << 16); - CPRINTS("I2C%d port%d recov status 0x%02x, SDA:SCL=0x%0x", - controller, port, reg, lines); - /* Attempt to unwedge the port. */ - if (lines != I2C_LINE_IDLE) - if (i2c_unwedge(port)) - return EC_ERROR_UNKNOWN; - - /* Bus error, bus busy, or arbitration lost. Try reset. */ - reset_controller(controller); - select_port(port, controller); - /* - * We don't know what edges the slave saw, so sleep long enough - * that the slave will see the new start condition below. - */ - usleep(1000); - reg = MCHP_I2C_STATUS(controller); - lines = get_line_level(port); - if ((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB) || - (lines != I2C_LINE_IDLE)) - return EC_ERROR_UNKNOWN; - } - return EC_SUCCESS; -} - -static inline void push_in_buf(uint8_t **in, uint8_t val, int skip) -{ - if (!skip) { - **in = val; - (*in)++; - } -} - -/* - * I2C Master transmit - * Caller has filled in cdata[ctrl] parameters - */ -static int i2c_mtx(int ctrl) -{ - int i, rv; - - rv = EC_SUCCESS; - cdata[ctrl].flags |= (1ul << 1); - if (cdata[ctrl].xflags & I2C_XFER_START) { - cdata[ctrl].flags |= (1ul << 2); - MCHP_I2C_DATA(ctrl) = cdata[ctrl].slv_addr_8bit; - /* Clock out the slave address, sending START bit */ - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI | - CTRL_ACK | CTRL_STA; - cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN; - } - - for (i = 0; i < cdata[ctrl].out_size; ++i) { - rv = wait_byte_done(ctrl, 0xff, 0x00); - if (rv) { - cdata[ctrl].flags |= (1ul << 17); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_ENI | CTRL_STO | CTRL_ACK; - return rv; - } - cdata[ctrl].flags |= (1ul << 15); - MCHP_I2C_DATA(ctrl) = cdata[ctrl].outp[i]; - } - - rv = wait_byte_done(ctrl, 0xff, 0x00); - if (rv) { - cdata[ctrl].flags |= (1ul << 18); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | CTRL_ENI | - CTRL_STO | CTRL_ACK; - return rv; - } - - /* - * Send STOP bit if the stop flag is on, and caller - * doesn't expect to receive data. - */ - if ((cdata[ctrl].xflags & I2C_XFER_STOP) && - (cdata[ctrl].in_size == 0)) { - cdata[ctrl].flags |= (1ul << 3); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED; - } - return rv; -} - -/* - * I2C Master-Receive helper routine for sending START or - * Repeated-START. - * This routine should only be called if a (Repeated-)START - * is required. - * If I2C controller is Idle or Stopped - * Send START by: - * Write read address to I2C.Data - * Write PIN=ESO=STA=ACK=1, STO=0 to I2C.Ctrl. This - * will trigger controller to output 8-bits of data. - * Else if I2C controller is Open (previous START sent) - * Send Repeated-START by: - * Write ESO=STA=ACK=1, PIN=STO=0 to I2C.Ctrl. Controller - * will generate START but not transmit data. - * Write read address to I2C.Data. Controller will transmit - * 8-bits of data - * Endif - * NOTE: Controller clocks in address on SDA as its transmitting. - * Therefore 1-byte RX-FIFO will contain address plus R/nW bit. - * Controller will wait for slave to release SCL before transmitting - * 9th clock and latching (N)ACK on SDA. - * Spin on I2C.Status PIN -> 0. Enable I2C interrupt if spin time - * exceeds threshold. If a timeout occurs generate STOP and return - * an error. - * - * Because I2C generates clocks for next byte when reading I2C.Data - * register we must prepare control logic. - * If the caller requests STOP and read length is 1 then set - * clear ACK bit in I2C.Ctrl. Set ESO=ENI=1, PIN=STA=STO=ACK=0 - * in I2C.Ctrl. Master must NACK last byte. - */ -static int i2c_mrx_start(int ctrl) -{ - uint8_t u8; - int rv; - - cdata[ctrl].flags |= (1ul << 4); - u8 = CTRL_ESO | CTRL_ENI | CTRL_STA | CTRL_ACK; - if (cdata[ctrl].transaction_state == I2C_TRANSACTION_OPEN) { - cdata[ctrl].flags |= (1ul << 5); - /* Repeated-START then address */ - MCHP_I2C_CTRL(ctrl) = u8; - } - MCHP_I2C_DATA(ctrl) = cdata[ctrl].slv_addr_8bit | 0x01; - if (cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) { - cdata[ctrl].flags |= (1ul << 6); - /* address then START */ - MCHP_I2C_CTRL(ctrl) = u8 | CTRL_PIN; - } - cdata[ctrl].transaction_state = I2C_TRANSACTION_OPEN; - /* Controller generates START, transmits data(address) capturing - * 9-bits from SDA (8-bit address + (N)Ack bit). - * We leave captured address in I2C.Data register. - * Master Receive data read routine assumes data is pending - * in I2C.Data - */ - cdata[ctrl].flags |= (1ul << 7); - rv = wait_byte_done(ctrl, 0xff, 0x00); - if (rv) { - cdata[ctrl].flags |= (1ul << 19); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - return rv; - } - /* if STOP requested and last 1 or 2 bytes prepare controller - * to NACK last byte. Do this before read of dummy data so - * controller is setup to NACK last byte. - */ - cdata[ctrl].flags |= (1ul << 8); - if (cdata[ctrl].xflags & I2C_XFER_STOP && - (cdata[ctrl].in_size < 2)) { - cdata[ctrl].flags |= (1ul << 9); - MCHP_I2C_CTRL(ctrl) = CTRL_ESO | CTRL_ENI; - } - /* - * Read & discard slave address. - * Generates clocks for next data - */ - cdata[ctrl].flags |= (1ul << 10); - u8 = MCHP_I2C_DATA(ctrl); - return rv; -} -/* - * I2C Master-Receive data read helper. - * Assumes I2C is in use, (Rpt-)START was previously sent. - * Reading I2C.Data generates clocks for the next byte. If caller - * requests STOP then we must clear I2C.Ctrl ACK before reading - * second to last byte from RX-FIFO data register. Before reading - * the last byte we must set I2C.Ctrl to generate a stop after - * the read from RX-FIFO register. - * NOTE: I2C.Status.LRB only records the (N)ACK bit in master - * transmit mode, not in master receive mode. - * NOTE2: Do not set ENI bit in I2C.Ctrl for STOP generation. - */ -static int i2c_mrx_data(int ctrl) -{ - uint32_t nrx = (uint32_t)cdata[ctrl].in_size; - uint32_t stop = (uint32_t)cdata[ctrl].xflags & I2C_XFER_STOP; - uint8_t *pdest = cdata[ctrl].inp; - int rv; - - cdata[ctrl].flags |= (1ul << 11); - while (nrx) { - rv = wait_byte_done(ctrl, 0xff, 0x00); - if (rv) { - cdata[ctrl].flags |= (1ul << 20); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - return rv; - } - if (stop) { - if (nrx == 2) { - cdata[ctrl].flags |= (1ul << 12); - MCHP_I2C_CTRL(ctrl) = CTRL_ESO | CTRL_ENI; - } else if (nrx == 1) { - cdata[ctrl].flags |= (1ul << 13); - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - } - } - *pdest++ = MCHP_I2C_DATA(ctrl); - nrx--; - } - cdata[ctrl].flags |= (1ul << 14); - return EC_SUCCESS; -} - -/* - * Called from common/i2c_master - */ -int chip_i2c_xfer(int port, uint16_t slave_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) -{ - int ctrl; - int ret_done; - - if (out_size == 0 && in_size == 0) - return EC_SUCCESS; - - ctrl = i2c_port_to_controller(port); - if (ctrl < 0) - return EC_ERROR_INVAL; - - cdata[ctrl].flags = (1ul << 0); - disable_controller_irq(ctrl); - select_port(port, ctrl); - - /* store transfer context */ - cdata[ctrl].i2c_complete = 0; - cdata[ctrl].hwsts = 0; - cdata[ctrl].hwsts2 = 0; - cdata[ctrl].hwsts3 = 0; - cdata[ctrl].hwsts4 = 0; - cdata[ctrl].port = port & 0xff; - cdata[ctrl].slv_addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - cdata[ctrl].out_size = out_size; - cdata[ctrl].outp = out; - cdata[ctrl].in_size = in_size; - cdata[ctrl].inp = in; - cdata[ctrl].xflags = flags; - - if ((flags & I2C_XFER_START) && - cdata[ctrl].transaction_state == I2C_TRANSACTION_STOPPED) { - wait_idle(ctrl); - ret_done = i2c_check_recover(port, ctrl); - if (ret_done) - goto err_chip_i2c_xfer; - } - - ret_done = EC_SUCCESS; - if (out_size) { - ret_done = i2c_mtx(ctrl); - if (ret_done) - goto err_chip_i2c_xfer; - } - - if (in_size) { - if (cdata[ctrl].xflags & I2C_XFER_START) { - ret_done = i2c_mrx_start(ctrl); - if (ret_done) - goto err_chip_i2c_xfer; - } - ret_done = i2c_mrx_data(ctrl); - if (ret_done) - goto err_chip_i2c_xfer; - } - - cdata[ctrl].flags |= (1ul << 15); - /* MCHP wait for STOP to complete */ - if (cdata[ctrl].xflags & I2C_XFER_STOP) - wait_idle(ctrl); - - /* Check for error conditions */ - if (MCHP_I2C_STATUS(ctrl) & (STS_LAB | STS_BER)) { - cdata[ctrl].flags |= (1ul << 21); - goto err_chip_i2c_xfer; - } - cdata[ctrl].flags |= (1ul << 14); - return EC_SUCCESS; - -err_chip_i2c_xfer: - cdata[ctrl].flags |= (1ul << 22); - cdata[ctrl].hwsts2 = MCHP_I2C_STATUS(ctrl); /* record status */ - /* NOTE: writing I2C.Ctrl.PIN=1 will clear all bits - * except NBB in I2C.Status - */ - MCHP_I2C_CTRL(ctrl) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - cdata[ctrl].transaction_state = I2C_TRANSACTION_STOPPED; - /* record status after STOP */ - cdata[ctrl].hwsts4 = MCHP_I2C_STATUS(ctrl); - - /* record line levels. - * Note line levels may reflect STOP condition - */ - cdata[ctrl].lines = (uint8_t)get_line_level(cdata[ctrl].port); - if (cdata[ctrl].hwsts2 & STS_BER) { - cdata[ctrl].flags |= (1ul << 23); - reset_controller(ctrl); - } - return EC_ERROR_UNKNOWN; -} -/* - * A safe method of reading port's SCL pin level. - */ -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - /* If no SCL pin defined for this port, - * then return 1 to appear idle. - */ - if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - return gpio_get_level(g); -} - -/* - * A safe method of reading port's SDA pin level. - */ -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - /* If no SDA pin defined for this port, - * then return 1 to appear idle. - */ - if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - return gpio_get_level(g); -} - -/* - * Caller is responsible for locking the port. - */ -int i2c_get_line_levels(int port) -{ - int rv, controller; - - controller = i2c_port_to_controller(port); - if (controller < 0) - return 0x03; /* No controller, return high line levels */ - - select_port(port, controller); - rv = get_line_level(port); - return rv; -} - -/* - * I2C port must be a zero based number. - * MCHP I2C can map any port to any of the 4 controllers. - * Call board level function as board designs may choose - * to wire up and group ports differently. - */ -int i2c_port_to_controller(int port) -{ - return board_i2c_p2c(port); -} - -void i2c_set_timeout(int port, uint32_t timeout) -{ - /* Param is port, but timeout is stored by-controller. */ - cdata[i2c_port_to_controller(port)].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; -} - -/* - * Initialize I2C controllers specified by the board configuration. - * If multiple ports are mapped to the same controller choose the - * lowest speed. - */ -void i2c_init(void) -{ - int i, controller, kbps; - int controller_kbps[MCHP_I2C_CTRL_MAX]; - const struct i2c_bus_clk *pbc; - - for (i = 0; i < MCHP_I2C_CTRL_MAX; i++) - controller_kbps[i] = 0; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - memset(cdata, 0, sizeof(cdata)); - - for (i = 0; i < i2c_ports_used; ++i) { - controller = i2c_port_to_controller(i2c_ports[i].port); - kbps = i2c_ports[i].kbps; - - /* Clear PCR sleep enable for controller */ - i2c_ctrl_slp_en(controller, 0); - - if (controller_kbps[controller] && - (controller_kbps[controller] != kbps)) { - CPRINTF("I2C[%d] init speed conflict: %d != %d\n", - controller, kbps, - controller_kbps[controller]); - kbps = MIN(kbps, controller_kbps[controller]); - } - - /* controller speed hardware limits */ - pbc = get_supported_speed_idx(kbps); - if (pbc->freq_khz != kbps) - CPRINTF("I2C[%d] init requested speed %d" - " using closest supported speed %d\n", - controller, kbps, pbc->freq_khz); - - controller_kbps[controller] = pbc->freq_khz; - configure_controller(controller, i2c_ports[i].port, - controller_kbps[controller]); - cdata[controller].task_waiting = TASK_ID_INVALID; - cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; - /* Use default timeout. */ - i2c_set_timeout(i2c_ports[i].port, 0); - } -} - -/* - * Handle I2C interrupts. - * I2C controller is configured to fire interrupts on - * anything causing PIN 1->0 and I2C IDLE (NBB -> 1). - * NVIC interrupt disable must clear NVIC pending bit. - */ -static void handle_interrupt(int controller) -{ - uint32_t r; - int id = cdata[controller].task_waiting; - - /* - * Write to control register interferes with I2C transaction. - * Instead, let's disable IRQ from the core until the next time - * we want to wait for STS_PIN/STS_NBB. - */ - disable_controller_irq(controller); - cdata[controller].hwsts3 = MCHP_I2C_STATUS(controller); - /* Clear all interrupt status */ - r = MCHP_I2C_COMPLETE(controller); - MCHP_I2C_COMPLETE(controller) = r; - cdata[controller].i2c_complete = r; - MCHP_INT_SOURCE(MCHP_I2C_GIRQ) = MCHP_I2C_GIRQ_BIT(controller); - - /* Wake up the task which was waiting on the I2C interrupt, if any. */ - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_I2C_IDLE, 0); -} - -void i2c0_interrupt(void) { handle_interrupt(0); } -void i2c1_interrupt(void) { handle_interrupt(1); } -void i2c2_interrupt(void) { handle_interrupt(2); } -void i2c3_interrupt(void) { handle_interrupt(3); } - -DECLARE_IRQ(MCHP_IRQ_I2C_0, i2c0_interrupt, 2); -DECLARE_IRQ(MCHP_IRQ_I2C_1, i2c1_interrupt, 2); -DECLARE_IRQ(MCHP_IRQ_I2C_2, i2c2_interrupt, 2); -DECLARE_IRQ(MCHP_IRQ_I2C_3, i2c3_interrupt, 2); diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c deleted file mode 100644 index 946ea1ca90..0000000000 --- a/chip/mchp/keyboard_raw.c +++ /dev/null @@ -1,104 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for MCHP MEC - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" -#include "tfdp_chip.h" - -/* - * Using direct mode interrupt, do not enable - * GIRQ bit in aggregator block enable register. - */ -void keyboard_raw_init(void) -{ - /* clear key scan PCR sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_KEYSCAN); - - keyboard_raw_enable_interrupt(0); - gpio_config_module(MODULE_KEYBOARD_SCAN, 1); - - /* Enable keyboard scan interrupt */ - MCHP_INT_ENABLE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT; - MCHP_KS_KSI_INT_EN = 0xff; -} - -void keyboard_raw_task_start(void) -{ - task_enable_irq(MCHP_IRQ_KSC_INT); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - if (out == KEYBOARD_COLUMN_ALL) { - MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 1); -#endif - } else if (out == KEYBOARD_COLUMN_NONE) { - MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 0); -#endif - } else { -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - if (out == 2) { - MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ - gpio_set_level(GPIO_KBD_KSO2, 1); - } else { - MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; - gpio_set_level(GPIO_KBD_KSO2, 0); - } -#else - MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; -#endif - } -} - -test_mockable int keyboard_raw_read_rows(void) -{ - uint8_t b1, b2; - - b1 = MCHP_KS_KSI_INPUT; - b2 = (b1 & 0xff) ^ 0xff; - - /* Invert it so 0=not pressed, 1=pressed */ - /* return (MCHP_KS_KSI_INPUT & 0xff) ^ 0xff; */ - return b2; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT; - task_clear_pending_irq(MCHP_IRQ_KSC_INT); - task_enable_irq(MCHP_IRQ_KSC_INT); - } else { - task_disable_irq(MCHP_IRQ_KSC_INT); - } -} - -void keyboard_raw_interrupt(void) -{ - /* Clear interrupt status bits */ - MCHP_KS_KSI_STATUS = 0xff; - - MCHP_INT_SOURCE(MCHP_KS_GIRQ) = MCHP_KS_GIRQ_BIT; - - /* Wake keyboard scan task to handle interrupt */ - task_wake(TASK_ID_KEYSCAN); -} -DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1); - -int keyboard_raw_is_input_low(int port, int id) -{ - return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0; -} diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c deleted file mode 100644 index 111e753d3b..0000000000 --- a/chip/mchp/lfw/ec_lfw.c +++ /dev/null @@ -1,425 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MCHP MEC SoC little FW - * - */ - -#include <stdint.h> - -#include "config.h" -#include "gpio.h" -#include "spi.h" -#include "spi_flash.h" -#include "util.h" -#include "timer.h" -#include "dma.h" -#include "registers.h" -#include "cpu.h" -#include "clock.h" -#include "system.h" -#include "version.h" -#include "hwtimer.h" -#include "gpio_list.h" -#include "tfdp_chip.h" - -#ifdef CONFIG_MCHP_LFW_DEBUG -#include "dma_chip.h" -#endif - -#include "ec_lfw.h" - -/* - * Check if LFW build is pulling in GPSPI which is not - * used for EC firmware SPI flash access. - */ -#ifdef CONFIG_MCHP_GPSPI -#error "FORCED BUILD ERROR: CONFIG_MCHP_CMX_GPSPI is defined" -#endif - -#define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC) -#define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 - -__attribute__ ((section(".intvector"))) -const struct int_vector_t hdr_int_vect = { - /* init sp, unused. set by MEC ROM loader */ - (void *)lfw_stack_top, /* preserve ROM log. was (void *)0x11FA00, */ - &lfw_main, /* was &lfw_main, */ /* reset vector */ - &fault_handler, /* NMI handler */ - &fault_handler, /* HardFault handler */ - &fault_handler, /* MPU fault handler */ - &fault_handler /* Bus fault handler */ -}; - -/* SPI devices - from board.c */ -const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 4, GPIO_QMSPI_CS0 }, -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - -/* - * At POR or EC reset MCHP Boot-ROM should only load LFW and jumps - * into LFW entry point located at offset 0x04 of LFW. - * Entry point is programmed into SPI Header by Python SPI image - * builder at chip/mec1701/util/pack_ec.py - * - * EC_RO/RW calling LFW should enter through this routine if you - * want the vector table updated. The stack should be set to - * LFW linker file parameter lfw_stack_top because we do not - * know if the callers stack is OK. - * - * Make sure lfw_stack_top will not overwrite panic data! - * from include/panic.h - * Panic data goes at the end of RAM. This is safe because we don't - * context switch away from the panic handler before rebooting, - * and stacks and data start at the beginning of RAM. - * - * chip level config_chip.h - * #define CONFIG_RAM_SIZE 0x00008000 - * #define CONFIG_RAM_BASE 0x120000 - 0x8000 = 0x118000 - * - * #define PANIC_DATA_PTR ((struct panic_data *)\ - * (CONFIG_RAM_BASE + CONFIG_RAM_SIZE - sizeof(struct panic_data))) - * - * LFW stack located by ec_lfw.ld linker file 256 bytes below top of - * data SRAM. - * PROVIDE( lfw_stack_top = 0x11F000 ); - * - * !!!WARNING!!! - * Current MEC BootROM's zeros all memory therefore any chip reset - * will destroy panic data. - */ - -/* - * Configure 32-bit basic timer 0 for 1MHz, auto-reload and - * no interrupt. - */ -void timer_init(void) -{ - uint32_t val = 0; - - /* Ensure timer is not running */ - MCHP_TMR32_CTL(0) &= ~BIT(5); - - /* Enable timer */ - MCHP_TMR32_CTL(0) |= BIT(0); - - val = MCHP_TMR32_CTL(0); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MCHP_TMR32_CTL(0) = val; - - /* Set preload to use the full 32 bits of the timer */ - MCHP_TMR32_PRE(0) = 0xffffffff; - - /* Override the count */ - MCHP_TMR32_CNT(0) = 0xffffffff; - - /* Auto restart */ - MCHP_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= BIT(5); - -} - -/* - * Use copy of SPI flash read compiled for LFW (no semaphores). - * LFW timeout code does not use interrupts so reset timer - * before starting SPI read to minimize probability of - * timer wrap. - */ -static int spi_flash_readloc(uint8_t *buf_usr, - unsigned int offset, - unsigned int bytes) -{ - uint8_t cmd[4] = {SPI_FLASH_READ, - (offset >> 16) & 0xFF, - (offset >> 8) & 0xFF, - offset & 0xFF}; - - if (offset + bytes > CONFIG_FLASH_SIZE) - return EC_ERROR_INVAL; - - __hw_clock_source_set(0); /* restart free run timer */ - return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes); -} - -/* - * Load EC_RO/RW image from local SPI flash. - * If CONFIG_MEC_TEST_EC_RORW_CRC was define the last 4 bytes - * of the binary is IEEE 802.3 CRC32 of the previous bytes. - * Use DMA channel 0 CRC32 HW to check data integrity. - */ -int spi_image_load(uint32_t offset) -{ - uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + - CONFIG_PROGRAM_MEMORY_BASE); - uint32_t i; -#ifdef CONFIG_MCHP_LFW_DEBUG - uint32_t crc_calc, crc_exp; - int rc; -#endif - - BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE); - - /* Why fill all but last 4-bytes? */ - memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4)); - - for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE) -#ifdef CONFIG_MCHP_LFW_DEBUG - rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); - if (rc != EC_SUCCESS) { - trace2(0, LFW, 0, - "spi_flash_readloc block %d ret = %d", - i, rc); - while (MCHP_PCR_PROC_CLK_CTL) - MCHP_PCR_CHIP_OSC_ID &= 0x1FE; - } -#else - spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); -#endif - -#ifdef CONFIG_MCHP_LFW_DEBUG - dma_crc32_start(buf, (CONFIG_RO_SIZE - 4), 0); - do { - MCHP_USEC_DELAY(31); /* delay(stall) CPU by 32 us */ - i = dma_is_done_chan(0); - } while (i == 0); - crc_calc = MCHP_DMA_CH0_CRC32_DATA; - crc_exp = *((uint32_t *)&buf[CONFIG_RO_SIZE - 4]); - trace12(0, LFW, 0, "EC image CRC32 = 0x%08x expected = 0x%08x", - crc_calc, crc_exp); -#endif - - return 0; -} - -void udelay(unsigned int us) -{ - uint32_t t0 = __hw_clock_source_read(); - - while (__hw_clock_source_read() - t0 < us) - ; -} - -void usleep(unsigned int us) -{ - udelay(us); -} - -int timestamp_expired(timestamp_t deadline, const timestamp_t *now) -{ - timestamp_t now_val; - - if (!now) { - now_val = get_time(); - now = &now_val; - } - - return ((int64_t)(now->val - deadline.val) >= 0); -} - -/* - * LFW does not use interrupts so no ISR will fire to - * increment high 32-bits of timestap_t. Force high - * word to zero. NOTE: There is a risk of false timeout - * errors due to timer wrap. We will reset timer before - * each SPI transaction. - */ -timestamp_t get_time(void) -{ - timestamp_t ts; - - ts.le.hi = 0; /* clksrc_high; */ - ts.le.lo = __hw_clock_source_read(); - return ts; -} - -void uart_write_c(char c) -{ - /* Put in carriage return prior to newline to mimic uart_vprintf() */ - if (c == '\n') - uart_write_c('\r'); - - /* Wait for space in transmit FIFO. */ - while (!(MCHP_UART_LSR(0) & BIT(5))) - ; - MCHP_UART_TB(0) = c; -} - -void uart_puts(const char *str) -{ - if (!str || !*str) - return; - - do { - uart_write_c(*str++); - } while (*str); -} - -void fault_handler(void) -{ - uart_puts("EXCEPTION!\nTriggering watchdog reset\n"); - /* trigger reset in 1 ms */ - usleep(1000); - MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET; - while (1) - ; - -} - -void jump_to_image(uintptr_t init_addr) -{ - void (*resetvec)(void) = (void(*)(void))init_addr; - - resetvec(); -} - -void uart_init(void) -{ - /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~BIT(0); - - /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= BIT(7); - - /* PBRG0/PBRG1 */ - MCHP_UART_PBRG0(0) = 1; - MCHP_UART_PBRG1(0) = 0; - - /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~BIT(7); - - /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MCHP_UART_FCR(0) = BIT(0); - - /* Activate UART */ - MCHP_UART_ACT(0) |= BIT(0); - - gpio_config_module(MODULE_UART, 1); -} - -/* - * If any of VTR POR, VBAT POR, chip resets, or WDT reset are active - * force VBAT image type to none causing load of EC_RO. - */ -void system_init(void) -{ - uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST; - uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & - MCHP_PWR_RST_STS_VTR; - - trace12(0, LFW, 0, - "VBAT_STS = 0x%08x PCR_PWR_RST_STS = 0x%08x", - wdt_sts, rst_sts); - - if (rst_sts || wdt_sts) - MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) - = SYSTEM_IMAGE_UNKNOWN; -} - -enum system_image_copy_t system_get_image_copy(void) -{ - return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX); -} - - -/* - * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly. - * NOTE: Based on LFW from MEC1322 - * Upon chip reset, BootROM loads image = LFW+EC_RO and enters LFW. - * LFW checks reset type: - * VTR POR, chip reset, WDT reset then set VBAT Load type to Unknown. - * LFW reads VBAT Load type: - * SYSTEM_IMAGE_RO then read EC_RO from SPI flash and jump into it. - * SYSTEM_IMAGE_RO then read EC_RW from SPI flash and jump into it. - * Other then jump into EC image loaded by Boot-ROM. - */ -void lfw_main(void) -{ - - uintptr_t init_addr; - - /* install vector table */ - *((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect; - - /* Use 48 MHz processor clock to power through boot */ - MCHP_PCR_PROC_CLK_CTL = 1; - -#ifdef CONFIG_WATCHDOG - /* Reload watchdog which may be running in case of sysjump */ - MCHP_WDG_KICK = 1; -#ifdef CONFIG_WATCHDOG_HELP - /* Stop aux timer */ - MCHP_TMR16_CTL(0) &= ~1; -#endif -#endif - /* - * TFDP functions will compile to nothing if CONFIG_MEC1701_TFDP - * is not defined. - */ - tfdp_power(1); - tfdp_enable(1, 1); - trace0(0, LFW, 0, "LFW first trace"); - - timer_init(); - clock_init(); - cpu_init(); - dma_init(); - uart_init(); - system_init(); - - spi_enable(CONFIG_SPI_FLASH_PORT, 1); - - uart_puts("littlefw "); - uart_puts(current_image_data.version); - uart_puts("\n"); - - switch (system_get_image_copy()) { - case SYSTEM_IMAGE_RW: - trace0(0, LFW, 0, "LFW EC_RW Load"); - uart_puts("lfw-RW load\n"); - - init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF); - break; - case SYSTEM_IMAGE_RO: - trace0(0, LFW, 0, "LFW EC_RO Load"); - uart_puts("lfw-RO load\n"); - - init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF); - break; - default: - trace0(0, LFW, 0, "LFW default: use EC_RO loaded by BootROM"); - uart_puts("lfw-default case\n"); - - MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = - SYSTEM_IMAGE_RO; - - init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - } - - trace11(0, LFW, 0, "Get EC reset handler from 0x%08x", (init_addr + 4)); - trace11(0, LFW, 0, "Jump to EC @ 0x%08x", - *((uint32_t *)(init_addr + 4))); - jump_to_image(*(uintptr_t *)(init_addr + 4)); - - /* should never get here */ - while (1) - ; -} diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h deleted file mode 100644 index 8d9da760a7..0000000000 --- a/chip/mchp/lfw/ec_lfw.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MCHP MEC SoC little FW - * - */ - -/* Why naked? This is dangerous except for - * function/ISR wrappers using inline assembly. - * lfw_main() makes many calls and has one local variable. - * Naked C functions should not use local data unless the local - * data can fit in CPU registers. - * Note other C functions called by lfw_main() are not marked naked and - * do include compiler generated prolog and epilog code. - * We also do not know how much stack space is available when - * EC_RO calls lfw_main(). - * -void lfw_main(void) __attribute__ ((noreturn, naked)); -*/ -void lfw_main(void) __attribute__ ((noreturn)); -void fault_handler(void) __attribute__((naked)); - -/* - * Defined in linker file ec_lfw.ld - */ -extern uint32_t lfw_stack_top[]; - -struct int_vector_t { - void *stack_ptr; - void *reset_vector; - void *nmi; - void *hard_fault; - void *bus_fault; - void *usage_fault; -}; - -#define SPI_CHUNK_SIZE 1024 diff --git a/chip/mchp/lfw/ec_lfw.ld b/chip/mchp/lfw/ec_lfw.ld deleted file mode 100644 index 8e8601a5ee..0000000000 --- a/chip/mchp/lfw/ec_lfw.ld +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MCHP MEC parts with 256KB SRAM SoC little FW - * - */ - -/* - * Memory Spaces Definitions - * LFW occupies first 4KB of CODE SRAM. - * First 24 bytes contain a minimal Cortex-M4 - * vector table. - */ -MEMORY -{ - VECTOR(r ) : ORIGIN = 0x0E0000, LENGTH = 0x18 - SRAM (xrw) : ORIGIN = 0x0E0018, LENGTH = 0xFE8 -} - -/* - * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the - * values here. - */ -ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.") -ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0x1000, "Invalid VECTOR+SRAM length.") - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ -ENTRY(lfw_main) - -/* - * MEC 256KB SRAM 0xE0000 - 0x11FFFF - * Data Top 32KB at 0x118000 - 0x11FFFF - * Boot-ROM log is 0x11FF00 - 0x11FFFF - * Set top of LFW stack 1KB below top of SRAM - * because EC panic and jump data live at - * top of SRAM. - * !!!WARNING!!! - * POR or any chip reset will cause MEC BootROM - * to run. BootROM will clear all CODE & DATA SRAM. - * Panic data will be lost. - * - */ -PROVIDE( lfw_stack_top = 0x11F000 ); - -/* Sections Definitions */ - -SECTIONS -{ - - /* - * The vector table goes first - */ - .intvector : - { - . = ALIGN(4); - KEEP(*(.intvector)) - } > VECTOR - - /* - * The program code is stored in the .text section, - * which goes to FLASH. - */ - - .text : - { - *(.text .text.*) /* all remaining code */ - *(.rodata .rodata.*) /* read-only data (constants) */ - } >SRAM - - . = ALIGN(4); - - /* Padding */ - - .fill : { - FILL(0xFF); - . = ORIGIN(SRAM) + LENGTH(SRAM) - 1; - BYTE(0xFF); /* emit at least a byte to make linker happy */ - } - - __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR); -} diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c deleted file mode 100644 index 91adb7f17c..0000000000 --- a/chip/mchp/lpc.c +++ /dev/null @@ -1,979 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* LPC module for MCHP MEC family */ - -#include "common.h" -#include "acpi.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "keyboard_protocol.h" -#include "lpc.h" -#include "lpc_chip.h" -#include "espi.h" -#include "port80.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "chipset.h" -#include "tfdp_chip.h" - -/* Console output macros */ -#ifdef CONFIG_MCHP_DEBUG_LPC -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#else -#define CPUTS(...) -#define CPRINTS(...) -#endif - -static uint8_t -mem_mapped[0x200] __attribute__((section(".bss.big_align"))); - -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ - -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); -static int init_done; - -static struct ec_lpc_host_args * const lpc_host_args = - (struct ec_lpc_host_args *)mem_mapped; - -#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1 -static uint8_t custom_acpi_cmd; -static uint8_t custom_acpi_ec2os_cnt; -static uint8_t custom_apci_ec2os[4]; -#endif - - -static void keyboard_irq_assert(void) -{ -#ifdef CONFIG_KEYBOARD_IRQ_GPIO - /* - * Enforce signal-high for long enough for the signal to be - * pulled high by the external pullup resistor. This ensures the - * host will see the following falling edge, regardless of the - * line state before this function call. - */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); - udelay(4); - /* Generate a falling edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0); - udelay(4); - - /* Set signal high, now that we've generated the edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); -#else - /* - * SERIRQ is automatically sent by KBC - */ -#endif -} - -/** - * Generate SMI pulse to the host chipset via GPIO. - * - * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length - * is 60ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need - * pulse length >61us. Both are short enough and events are infrequent, - * so just delay for 65us. - */ -static void lpc_generate_smi(void) -{ - CPUTS("LPC Pulse SMI"); -#ifdef CONFIG_HOSTCMD_ESPI - /* eSPI: pulse SMI# Virtual Wire low */ - espi_vw_pulse_wire(VW_SMI_L, 0); -#else - gpio_set_level(GPIO_PCH_SMI_L, 0); - udelay(65); - gpio_set_level(GPIO_PCH_SMI_L, 1); -#endif -} - -static void lpc_generate_sci(void) -{ - CPUTS("LPC Pulse SCI"); -#ifdef CONFIG_SCI_GPIO - gpio_set_level(CONFIG_SCI_GPIO, 0); - udelay(65); - gpio_set_level(CONFIG_SCI_GPIO, 1); -#else -#ifdef CONFIG_HOSTCMD_ESPI - espi_vw_pulse_wire(VW_SCI_L, 0); -#else - MCHP_ACPI_PM_STS |= 1; - udelay(65); - MCHP_ACPI_PM_STS &= ~1; -#endif -#endif -} - -/** - * Update the level-sensitive wake signal to the AP. - * - * @param wake_events Currently asserted wake events - */ -static void lpc_update_wake(host_event_t wake_events) -{ - /* - * Mask off power button event, since the AP gets that - * through a separate dedicated GPIO. - */ - wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); - -#ifdef CONFIG_HOSTCMD_ESPI - espi_vw_set_wire(VW_WAKE_L, !wake_events); -#else - /* Signal is asserted low when wake events is non-zero */ - gpio_set_level(GPIO_PCH_WAKE_L, !wake_events); -#endif -} - -static uint8_t *lpc_get_hostcmd_data_range(void) -{ - return mem_mapped; -} - - -/** - * Update the host event status. - * - * Sends a pulse if masked event status becomes non-zero: - * - SMI pulse via PCH_SMI_L GPIO - * - SCI pulse via PCH_SCI_L GPIO - */ -void lpc_update_host_event_status(void) -{ - int need_sci = 0; - int need_smi = 0; - - CPUTS("LPC update_host_event_status"); - - if (!init_done) - return; - - /* Disable LPC interrupt while updating status register */ - task_disable_irq(MCHP_IRQ_ACPIEC0_IBF); - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) { - /* Only generate SMI for first event */ - if (!(MCHP_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING)) - need_smi = 1; - MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING; - } else { - MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING; - } - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) { - /* Generate SCI for every event */ - need_sci = 1; - MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING; - } else { - MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING; - } - - /* Copy host events to mapped memory */ - *(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); - - task_enable_irq(MCHP_IRQ_ACPIEC0_IBF); - - /* Process the wake events. */ - lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE)); - - /* Send pulse on SMI signal if needed */ - if (need_smi) - lpc_generate_smi(); - - /* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */ - if (need_sci) - lpc_generate_sci(); -} - -static void lpc_send_response(struct host_cmd_handler_args *args) -{ - uint8_t *out; - int size = args->response_size; - int csum; - int i; - - /* Ignore in-progress on LPC since interface is synchronous anyway */ - if (args->result == EC_RES_IN_PROGRESS) - return; - - /* Handle negative size */ - if (size < 0) { - args->result = EC_RES_INVALID_RESPONSE; - size = 0; - } - - /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; - - lpc_host_args->data_size = size; - - csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; - - for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) - csum += *out; - - lpc_host_args->checksum = (uint8_t)csum; - - /* Fail if response doesn't fit in the param buffer */ - if (size > EC_PROTO2_MAX_PARAM_SIZE) - args->result = EC_RES_INVALID_RESPONSE; - - /* Write result to the data byte. */ - MCHP_ACPI_EC_EC2OS(1, 0) = args->result; - - /* - * Clear processing flag in hardware and - * sticky status in interrupt aggregator. - */ - MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(1); - -} - -static void lpc_send_response_packet(struct host_packet *pkt) -{ - /* Ignore in-progress on LPC since interface is - * synchronous anyway - */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) { - /* CPRINTS("LPC EC_RES_IN_PROGRESS"); */ - return; - } - - CPRINTS("LPC Set EC2OS(1,0)=0x%02x", pkt->driver_result); - - /* Write result to the data byte. */ - MCHP_ACPI_EC_EC2OS(1, 0) = pkt->driver_result; - - /* Clear the busy bit, so the host knows the EC is done. */ - MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(1); -} - -uint8_t *lpc_get_memmap_range(void) -{ - return mem_mapped + 0x100; -} - -void lpc_mem_mapped_init(void) -{ - /* We support LPC args and version 3 protocol */ - *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; -} - -const int acpi_ec_pcr_slp[MCHP_ACPI_EC_MAX] = { - MCHP_PCR_ACPI_EC0, - MCHP_PCR_ACPI_EC1, - MCHP_PCR_ACPI_EC2, - MCHP_PCR_ACPI_EC3, - MCHP_PCR_ACPI_EC4, -}; - -const int acpi_ec_nvic_ibf[MCHP_ACPI_EC_MAX] = { - MCHP_IRQ_ACPIEC0_IBF, - MCHP_IRQ_ACPIEC1_IBF, - MCHP_IRQ_ACPIEC2_IBF, - MCHP_IRQ_ACPIEC3_IBF, - MCHP_IRQ_ACPIEC4_IBF, -}; - -#ifdef CONFIG_HOSTCMD_ESPI -const int acpi_ec_espi_bar_id[MCHP_ACPI_EC_MAX] = { - MCHP_ESPI_IO_BAR_ID_ACPI_EC0, - MCHP_ESPI_IO_BAR_ID_ACPI_EC1, - MCHP_ESPI_IO_BAR_ID_ACPI_EC2, - MCHP_ESPI_IO_BAR_ID_ACPI_EC3, - MCHP_ESPI_IO_BAR_ID_ACPI_EC4, -}; -#endif - -void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask) -{ - if (instance >= MCHP_ACPI_EC_MAX) - CPUTS("ACPI EC CFG invalid"); - - MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]); - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = - mask; - MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) = - (io_base << 16) + 0x01ul; -#else - MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) + - (1ul << 15) + mask; -#endif - MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING; - MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(instance); - task_enable_irq(acpi_ec_nvic_ibf[instance]); -} - -/* - * 8042EM hardware decodes with fixed mask of 0x04 - * Example: io_base == 0x60 -> decodes 0x60/0x64 - * Enable both IBF and OBE interrupts. - */ -void chip_8042_config(uint32_t io_base) -{ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042); - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = - (io_base << 16) + 0x01ul; -#else - /* Set up 8042 interface at 0x60/0x64 */ - MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15); -#endif - /* Set up indication of Auxiliary sts */ - MCHP_8042_KB_CTRL |= BIT(7); - - MCHP_8042_ACT |= 1; - - MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT + - MCHP_8042_IBF_GIRQ_BIT; - - task_enable_irq(MCHP_IRQ_8042EM_IBF); - task_enable_irq(MCHP_IRQ_8042EM_OBE); - -#ifndef CONFIG_KEYBOARD_IRQ_GPIO - /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= BIT(5); - MCHP_LPC_SIRQ(1) = 0x01; -#endif -} - -/* - * Access data RAM - * MCHP EMI Base address register = physical address of buffer - * in SRAM. EMI hardware adds 16-bit offset Host programs into - * EC_Address_LSB/MSB registers. - * Limit EMI read / write range. First 256 bytes are RW for host - * commands. Second 256 bytes are RO for mem-mapped data. - * Hardware decodes a fixed 16 byte IO range. - */ -void chip_emi0_config(uint32_t io_base) -{ -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = - (io_base << 16) + 0x01ul; -#else - MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15); -#endif - - MCHP_EMI_MBA0(0) = (uint32_t)mem_mapped; - - MCHP_EMI_MRL0(0) = 0x200; - MCHP_EMI_MWL0(0) = 0x100; - - MCHP_INT_ENABLE(MCHP_EMI_GIRQ) = MCHP_EMI_GIRQ_BIT(0); - task_enable_irq(MCHP_IRQ_EMI0); -} - -/* Setup Port80 Debug Hardware ports. - * First instance for I/O 80h only. - * Clear FIFO's and timestamp. - * Set FIFO interrupt threshold to maximum of 14 bytes. - */ -void chip_port80_config(uint32_t io_base) -{ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0); - - MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + - MCHP_P80_RESET_TIMESTAMP_WO; - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = - (io_base << 16) + 0x01ul; -#else - MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15); -#endif - MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 + - MCHP_P80_TIMEBASE_1500KHZ + - MCHP_P80_TIMER_ENABLE; - - MCHP_P80_ACTIVATE(0) = 1; - - MCHP_INT_SOURCE(15) = MCHP_INT15_P80(0); - MCHP_INT_ENABLE(15) = MCHP_INT15_P80(0); - task_enable_irq(MCHP_IRQ_PORT80DBG0); -} - -#ifdef CONFIG_MCHP_DEBUG_LPC -static void chip_lpc_iobar_debug(void) -{ - CPRINTS("LPC ACPI EC0 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(0)); - CPRINTS("LPC ACPI EC1 IO BAR = 0x%08x", MCHP_LPC_ACPI_EC_BAR(1)); - CPRINTS("LPC 8042EM IO BAR = 0x%08x", MCHP_LPC_8042_BAR); - CPRINTS("LPC EMI0 IO BAR = 0x%08x", MCHP_LPC_EMI0_BAR); - CPRINTS("LPC Port80Dbg0 IO BAR = 0x%08x", MCHP_LPC_P80DBG0_BAR); -} -#endif - -/* - * Most registers in LPC module are reset when the host is off. - * We need to set up LPC again when the host is starting up. - * MCHP LRESET# can be one of two pins - * GPIO_0052 Func 2 - * GPIO_0064 Func 1 - * Use GPIO interrupt to detect LRESET# changes. - * Use GPIO_0064 for LRESET#. Must update board/board_name/gpio.inc - * - * For eSPI PLATFORM_RESET# virtual wire is used as LRESET# - * - */ -#ifndef CONFIG_HOSTCMD_ESPI -static void setup_lpc(void) -{ - TRACE0(55, LPC, 0, "setup_lpc"); - - MCHP_LPC_CFG_BAR |= (1ul << 15); - - /* Set up ACPI0 for 0x62/0x66 */ - chip_acpi_ec_config(0, 0x62, 0x04); - - /* Set up ACPI1 for 0x200 - 0x207 */ - chip_acpi_ec_config(1, 0x200, 0x07); - - /* Set up 8042 interface at 0x60/0x64 */ - chip_8042_config(0x60); - -#ifndef CONFIG_KEYBOARD_IRQ_GPIO - /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= BIT(5); - MCHP_LPC_SIRQ(1) = 0x01; -#endif - /* EMI0 at IO 0x800 */ - chip_emi0_config(0x800); - - chip_port80_config(0x80); - - lpc_mem_mapped_init(); - - /* Activate LPC interface */ - MCHP_LPC_ACT |= 1; - - /* Sufficiently initialized */ - init_done = 1; - - /* Update host events now that we can copy them to memmap */ - lpc_update_host_event_status(); - -#ifdef CONFIG_MCHP_DEBUG_LPC - chip_lpc_iobar_debug(); -#endif -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST); -#endif - -static void lpc_init(void) -{ - CPUTS("LPC HOOK_INIT"); - - /* Initialize host args and memory map to all zero */ - memset(lpc_host_args, 0, sizeof(*lpc_host_args)); - memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE); - - /* - * Clear PCR sleep enables for peripherals we are using for - * both LPC and eSPI. - * Global Config, ACPI EC0/1, 8042 Keyboard controller, - * Port80 Capture0, and EMI. - * NOTE: EMI doesn't have a sleep enable. - */ - MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG + - MCHP_PCR_SLP_EN2_ACPI_EC0 + - MCHP_PCR_SLP_EN2_ACPI_EC0 + - MCHP_PCR_SLP_EN2_MIF8042); - - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0); - -#ifdef CONFIG_HOSTCMD_ESPI - - espi_init(); - -#else - /* Clear PCR LPC sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_LPC); - - /* configure pins */ - gpio_config_module(MODULE_LPC, 1); - - /* - * MCHP LRESET# interrupt is GPIO interrupt - * and configured by GPIO table in board level gpio.inc - * Refer to lpcrst_interrupt() in this file. - */ - gpio_enable_interrupt(GPIO_PCH_PLTRST_L); - - /* - * b[8]=1(LRESET# is platform reset), b[0]=0 VCC_PWRGD is - * asserted when LRESET# is 1(inactive) - */ - MCHP_PCR_PWR_RST_CTL = 0x100ul; - - /* - * Allow LPC sleep if Host CLKRUN# signals - * clock stop and there are no pending SERIRQ - * or LPC DMA. - */ - MCHP_LPC_EC_CLK_CTRL = - (MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul; - - setup_lpc(); -#endif -} -/* - * Set priority to higher than default; this way LPC memory mapped - * data is ready before other inits try to initialize their - * memmap data. - */ -DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); - -#ifdef CONFIG_CHIPSET_RESET_HOOK -static void lpc_chipset_reset(void) -{ - hook_notify(HOOK_CHIPSET_RESET); -} -DECLARE_DEFERRED(lpc_chipset_reset); -#endif - -void lpc_set_init_done(int val) -{ - init_done = val; -} - -/* - * MCHP MCHP family allows selecting one of two GPIO pins alternate - * functions as LRESET#. - * LRESET# can be monitored as bit[1](read-only) of the - * LPC Bus Monitor register. NOTE: Bus Monitor is synchronized with - * LPC clock. We have observed APL configurations where LRESET# - * changes while LPC clock is not running! - * bit[1]==0 -> LRESET# is high - * bit[1]==1 -> LRESET# is low (active) - * LRESET# active causes the EC to activate internal signal RESET_HOST. - * MCHP_PCR_PWR_RST_STS bit[3](read-only) = RESET_HOST_STATUS = - * 0 = Reset active - * 1 = Reset not active - * MCHP is different than MEC1322 in that LRESET# is not connected - * to a separate interrupt source. - * If using LPC the board design must select on of the two GPIO pins - * dedicated for LRESET# and this pin must be configured in the - * board level gpio.inc - */ -void lpcrst_interrupt(enum gpio_signal signal) -{ -#ifndef CONFIG_HOSTCMD_ESPI - /* Initialize LPC module when LRESET# is deasserted */ - if (!lpc_get_pltrst_asserted()) { - setup_lpc(); - } else { - /* Store port 80 reset event */ - port_80_write(PORT_80_EVENT_RESET); - -#ifdef CONFIG_CHIPSET_RESET_HOOK - /* Notify HOOK_CHIPSET_RESET */ - hook_call_deferred(&lpc_chipset_reset_data, MSEC); -#endif - } -#ifdef CONFIG_MCHP_DEBUG_LPC - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); -#endif -#endif -} - -/* - * TODO - Is this only for debug of EMI host communication - * or logging of EMI host communication? We don't observe - * this ISR so Host is not writing to MCHP_EMI_H2E_MBX(0). - */ -void emi0_interrupt(void) -{ - uint8_t h2e; - - h2e = MCHP_EMI_H2E_MBX(0); - CPRINTS("LPC Host 0x%02x -> EMI0 H2E(0)", h2e); - port_80_write(h2e); -} -DECLARE_IRQ(MCHP_IRQ_EMI0, emi0_interrupt, 1); - -/* - * ISR empties BIOS Debug 0 FIFO and - * writes data to circular buffer. How can we be - * sure this routine can read the last Port 80h byte? - */ -int port_80_read(void) -{ - int data; - - data = PORT_80_IGNORE; - if (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) - data = MCHP_P80_CAP(0) & 0xFF; - - return data; -} - -#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1 -/* - * Handle custom ACPI EC0 commands. - * Some chipset's CoreBoot will send read board ID command expecting - * a two byte response. - */ -static int acpi_ec0_custom(int is_cmd, uint8_t value, - uint8_t *resultptr) -{ - int rval; - - rval = 0; - custom_acpi_ec2os_cnt = 0; - *resultptr = 0x00; - - if (is_cmd && (value == 0x0d)) { - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); - /* Write two bytes sequence 0xC2, 0x04 to Host */ - if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) { - /* Host enabled 4-byte mode */ - MCHP_ACPI_EC_EC2OS(0, 0) = 0x02; - MCHP_ACPI_EC_EC2OS(0, 1) = 0x04; - MCHP_ACPI_EC_EC2OS(0, 2) = 0x00; - /* Sets OBF */ - MCHP_ACPI_EC_EC2OS(0, 3) = 0x00; - } else { - /* single byte mode */ - *resultptr = 0x02; - custom_acpi_ec2os_cnt = 1; - custom_apci_ec2os[0] = 0x04; - MCHP_ACPI_EC_EC2OS(0, 0) = 0x02; - MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); - task_enable_irq(MCHP_IRQ_ACPIEC0_OBE); - } - custom_acpi_cmd = 0; - rval = 1; - } - - return rval; -} -#endif - -void acpi_0_interrupt(void) -{ - uint8_t value, result, is_cmd; - - is_cmd = MCHP_ACPI_EC_STATUS(0); - - /* Set the bust bi */ - MCHP_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING; - - result = MCHP_ACPI_EC_BYTE_CTL(0); - - /* Read command/data; this clears the FRMH bit. */ - value = MCHP_ACPI_EC_OS2EC(0, 0); - - is_cmd &= EC_LPC_STATUS_LAST_CMD; - - /* Handle whatever this was. */ - result = 0; - if (acpi_ap_to_ec(is_cmd, value, &result)) - MCHP_ACPI_EC_EC2OS(0, 0) = result; -#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1 - else - acpi_ec0_custom(is_cmd, value, &result); -#endif - /* Clear the busy bit */ - MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; - - /* Clear R/W1C status bit in Aggregator */ - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(0); - - /* - * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / - * Output Buffer Full condition on the kernel channel/ - */ - lpc_generate_sci(); -} -DECLARE_IRQ(MCHP_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1); - -#ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1 -/* - * ACPI EC0 output buffer empty ISR. - * Used to handle custom ACPI EC0 command requiring - * two byte response. - */ -void acpi_0_obe_isr(void) -{ - uint8_t sts, data; - - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); - - sts = MCHP_ACPI_EC_STATUS(0); - data = MCHP_ACPI_EC_BYTE_CTL(0); - data = sts; - if (custom_acpi_ec2os_cnt) { - custom_acpi_ec2os_cnt--; - data = custom_apci_ec2os[custom_acpi_ec2os_cnt]; - } - - if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */ - MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); - } - - lpc_generate_sci(); -} -DECLARE_IRQ(MCHP_IRQ_ACPIEC0_OBE, acpi_0_obe_isr, 1); -#endif - -void acpi_1_interrupt(void) -{ - uint8_t st = MCHP_ACPI_EC_STATUS(1); - - if (!(st & EC_LPC_STATUS_FROM_HOST) || - !(st & EC_LPC_STATUS_LAST_CMD)) - return; - - /* Set the busy bit */ - MCHP_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING; - - /* - * Read the command byte. This clears the FRMH bit in - * the status byte. - */ - host_cmd_args.command = MCHP_ACPI_EC_OS2EC(1, 0); - - host_cmd_args.result = EC_RES_SUCCESS; - host_cmd_args.send_response = lpc_send_response; - host_cmd_flags = lpc_host_args->flags; - - /* We only support new style command (v3) now */ - if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) { - lpc_packet.send_response = lpc_send_response_packet; - - lpc_packet.request = - (const void *)lpc_get_hostcmd_data_range(); - lpc_packet.request_temp = params_copy; - lpc_packet.request_max = sizeof(params_copy); - /* Don't know the request size so - * pass in the entire buffer - */ - lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE; - - lpc_packet.response = - (void *)lpc_get_hostcmd_data_range(); - lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE; - lpc_packet.response_size = 0; - - lpc_packet.driver_result = EC_RES_SUCCESS; - - host_packet_receive(&lpc_packet); - - } else { - /* Old style command unsupported */ - host_cmd_args.result = EC_RES_INVALID_COMMAND; - - /* Hand off to host command handler */ - host_command_received(&host_cmd_args); - } -} -DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1); - -#ifdef HAS_TASK_KEYPROTO -/* - * Reading data out of input buffer clears read-only status - * in 8042EM. Next, we must clear aggregator status. - */ -void kb_ibf_interrupt(void) -{ - if (lpc_keyboard_input_pending()) - keyboard_host_write(MCHP_8042_H2E, - MCHP_8042_STS & BIT(3)); - - MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT; - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MCHP_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); - -/* - * Interrupt generated when Host reads data byte from 8042EM - * output buffer. The 8042EM STATUS.OBF bit will clear when the - * Host reads the data and assert its OBE signal to interrupt - * aggregator. Clear aggregator 8042EM OBE R/WC status bit before - * invoking task. - */ -void kb_obe_interrupt(void) -{ - MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT; - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1); -#endif - -/* - * Bit 0 of 8042EM STATUS register is OBF meaning EC has written - * data to EC2HOST data register. OBF is cleared when the host - * reads the data. - */ -int lpc_keyboard_has_char(void) -{ - return (MCHP_8042_STS & BIT(0)) ? 1 : 0; -} - -int lpc_keyboard_input_pending(void) -{ - return (MCHP_8042_STS & BIT(1)) ? 1 : 0; -} - -/* - * called from common/keyboard_8042.c - */ -void lpc_keyboard_put_char(uint8_t chr, int send_irq) -{ - MCHP_8042_E2H = chr; - if (send_irq) - keyboard_irq_assert(); -} - -/* - * Read 8042 register and write to read-only register - * insuring compiler does not optimize out the read. - */ -void lpc_keyboard_clear_buffer(void) -{ - MCHP_PCR_CHIP_OSC_ID = MCHP_8042_OBF_CLR; -} - -void lpc_keyboard_resume_irq(void) -{ - if (lpc_keyboard_has_char()) - keyboard_irq_assert(); -} - -void lpc_set_acpi_status_mask(uint8_t mask) -{ - MCHP_ACPI_EC_STATUS(0) |= mask; -} - -void lpc_clear_acpi_status_mask(uint8_t mask) -{ - MCHP_ACPI_EC_STATUS(0) &= ~mask; -} - -/* - * Read hardware to determine state of platform reset signal. - * LPC issue: Observed APL chipset changing LRESET# while LPC - * clock is not running. This violates original LPC specification. - * Unable to find information in APL chipset documentation - * stating APL can change LRESET# with LPC clock not running. - * Could this be a CoreBoot issue during CB LPC configuration? - * We work-around this issue by reading the GPIO state. - */ -int lpc_get_pltrst_asserted(void) -{ -#ifdef CONFIG_HOSTCMD_ESPI - /* - * eSPI PLTRST# a VWire or side-band signal - * Controlled by CONFIG_HOSTCMD_ESPI - */ - return !espi_vw_get_wire(VW_PLTRST_L); -#else - /* returns 1 if LRESET# pin is asserted(low) else 0 */ -#ifdef CONFIG_CHIPSET_APL_GLK - /* Use GPIO */ - return !gpio_get_level(GPIO_PCH_PLTRST_L); -#else - /* assumes LPC clock is running when host changes LRESET# */ - return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0; -#endif -#endif -} - -/* Enable LPC ACPI-EC0 interrupts */ -void lpc_enable_acpi_interrupts(void) -{ - task_enable_irq(MCHP_IRQ_ACPIEC0_IBF); -} - -/* Disable LPC ACPI-EC0 interrupts */ -void lpc_disable_acpi_interrupts(void) -{ - task_disable_irq(MCHP_IRQ_ACPIEC0_IBF); -} - -/* On boards without a host, this command is used to set up LPC */ -static int lpc_command_init(int argc, char **argv) -{ - lpc_init(); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL); - -/* Get protocol information */ -static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO"); - - memset(r, 0, sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->flags = 0; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); - -#ifdef CONFIG_MCHP_DEBUG_LPC -static int command_lpc(int argc, char **argv) -{ - if (argc == 1) - return EC_ERROR_PARAM1; - - if (!strcasecmp(argv[1], "sci")) - lpc_generate_sci(); - else if (!strcasecmp(argv[1], "smi")) - lpc_generate_smi(); - else if (!strcasecmp(argv[1], "wake")) - lpc_update_wake(-1); - else - return EC_ERROR_PARAM1; - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", - "Trigger SCI/SMI"); -#endif - diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h deleted file mode 100644 index dcb5577fc1..0000000000 --- a/chip/mchp/lpc_chip.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Microchip MEC1701 specific module for Chrome EC */ - -#ifndef __CROS_EC_LPC_CHIP_H -#define __CROS_EC_LPC_CHIP_H - -#ifdef CONFIG_HOSTCMD_ESPI - -#include "espi.h" - -#define MCHP_HOST_IF_LPC (0) -#define MCHP_HOST_IF_ESPI (1) - -/* eSPI Initialization functions */ -void espi_init(void); - -/* eSPI ESPI_RESET# interrupt handler */ -void espi_reset_handler(void); - -/* - * - */ -int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level); - -void lpc_update_host_event_status(void); - -#endif - -/* LPC LRESET interrupt handler */ -void lpcrst_interrupt(enum gpio_signal signal); - -void lpc_set_init_done(int val); - -void lpc_mem_mapped_init(void); - -#ifndef CONFIG_HOSTCMD_ESPI -void lpcrst_interrupt(enum gpio_signal signal); -#endif - -void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask); -void chip_8042_config(uint32_t io_base); -void chip_emi0_config(uint32_t io_base); -void chip_port80_config(uint32_t io_base); - -#endif /* __CROS_EC_LPC_CHIP_H */ diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c deleted file mode 100644 index 8be91e9d3d..0000000000 --- a/chip/mchp/port80.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Port 80 Timer Interrupt for MCHP MEC family */ - -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "lpc.h" -#include "port80.h" -#include "registers.h" -#include "task.h" -#include "tfdp_chip.h" - - -/* - * Interrupt fires when number of bytes written - * to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level - * Issues: - * 1. eSPI will not break 16-bit I/O into two 8-bit writes - * as LPC does. This means Port80 hardware will capture - * only bits[7:0] of data. - * 2. If Host performs write of 16-bit code as consecutive - * byte writes the Port80 hardware will capture both but - * we do not know the order it was written. - * 3. If Host sometimes writes one byte code to I/O 80h and - * sometimes two byte code to I/O 80h/81h how do we determine - * what to do? - * - * An alternative is to document Host must write 16-bit codes - * to I/O 80h and 90h. LSB to 0x80 and MSB to 0x90. - * - */ -void port_80_interrupt(void) -{ - int d; - - while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) { - /* this masks off time stamp d = port_80_read(); */ - d = MCHP_P80_CAP(0); /* b[7:0] = data, b[31:8] = timestamp */ - trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff)); - port_80_write(d & 0xff); - } - - MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0); -} -DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3); - - diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c deleted file mode 100644 index 53a8c15806..0000000000 --- a/chip/mchp/pwm.c +++ /dev/null @@ -1,155 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for MCHP MEC family */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "util.h" -#include "tfdp_chip.h" - -#define CPUTS(outstr) cputs(CC_PWM, outstr) -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) - -/* - * PWMs that must remain active in low-power idle - - * PWM 0,1-8 are b[4,20:27] of MCHP_PCR_SLP_EN1 - * PWM 9 is b[31] of MCHP_PCR_SLP_EN3 - * PWM 10 - 11 are b[0:1] of MCHP_PCR_SLP_EN4 - * store 32-bit word with - * b[0:1] = PWM 10-11 - * b[4,20:27] = PWM 0, 1-8 - * b[31] = PWM 9 - */ -static uint32_t pwm_keep_awake_mask; - -const uint8_t pwm_slp_bitpos[12] = { - 4, 20, 21, 22, 23, 24, 25, 26, 27, 31, 0, 1 -}; - -static uint32_t pwm_get_sleep_mask(int id) -{ - uint32_t bitpos = 32; - - if (id < 12) - bitpos = (uint32_t)pwm_slp_bitpos[id]; - - return (1ul << bitpos); -} - - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - int id = pwm_channels[ch].channel; - uint32_t pwm_slp_mask; - - pwm_slp_mask = pwm_get_sleep_mask(id); - - if (enabled) { - MCHP_PWM_CFG(id) |= 0x1; - if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) - pwm_keep_awake_mask |= pwm_slp_mask; - } else { - MCHP_PWM_CFG(id) &= ~0x1; - pwm_keep_awake_mask &= ~pwm_slp_mask; - } -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - return MCHP_PWM_CFG(pwm_channels[ch].channel) & 0x1; -} - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - int id = pwm_channels[ch].channel; - - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - MCHP_PWM_ON(id) = percent; - MCHP_PWM_OFF(id) = 100 - percent; -} - -int pwm_get_duty(enum pwm_channel ch) -{ - return MCHP_PWM_ON(pwm_channels[ch].channel); -} - -void pwm_keep_awake(void) -{ - if (pwm_keep_awake_mask) { - /* b[4,20:27] */ - MCHP_PCR_SLP_EN1 &= ~(pwm_keep_awake_mask & - (MCHP_PCR_SLP_EN1_PWM_ALL)); - /* b[31] */ - MCHP_PCR_SLP_EN3 &= ~(pwm_keep_awake_mask & - (MCHP_PCR_SLP_EN3_PWM_ALL)); - /* b[1:0] */ - MCHP_PCR_SLP_EN4 &= ~(pwm_keep_awake_mask & - (MCHP_PCR_SLP_EN4_PWM_ALL)); - } else { - MCHP_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; - } -} - - -static void pwm_configure(int ch, int active_low, int clock_low) -{ - /* - * clock_low=0 selects the 48MHz Ring Oscillator source - * clock_low=1 selects the 100kHz_Clk source - */ - MCHP_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? BIT(2) : 0) | - (clock_low ? BIT(1) : 0); -} - -static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = { - MCHP_PCR_PWM0, - MCHP_PCR_PWM1, - MCHP_PCR_PWM2, - MCHP_PCR_PWM3, - MCHP_PCR_PWM4, - MCHP_PCR_PWM5, - MCHP_PCR_PWM6, - MCHP_PCR_PWM7, - MCHP_PCR_PWM8, - MCHP_PCR_PWM9, - MCHP_PCR_PWM10, - MCHP_PCR_PWM11, -}; - -static void pwm_slp_en(int pwm_id, int sleep_en) -{ - if ((pwm_id < 0) || (pwm_id > MCHP_PWM_ID_MAX)) - return; - - if (sleep_en) - MCHP_PCR_SLP_EN_DEV(pwm_pcr[pwm_id]); - else - MCHP_PCR_SLP_DIS_DEV(pwm_pcr[pwm_id]); -} - -static void pwm_init(void) -{ - int i; - - for (i = 0; i < PWM_CH_COUNT; ++i) { - pwm_slp_en(pwm_channels[i].channel, 0); - pwm_configure(pwm_channels[i].channel, - pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW, - pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK); - pwm_set_duty(i, 0); - } -} -DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_DEFAULT); diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h deleted file mode 100644 index 85ff484f86..0000000000 --- a/chip/mchp/pwm_chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1701H-specific PWM module for Chrome EC */ -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* PWM Channel ID */ - int channel; - - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; -}; - -extern const struct pwm_t pwm_channels[]; - -void pwm_keep_awake(void); - -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c deleted file mode 100644 index 1a5f9576b8..0000000000 --- a/chip/mchp/qmspi.c +++ /dev/null @@ -1,700 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* QMSPI master module for MCHP MEC family */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "timer.h" -#include "util.h" -#include "hooks.h" -#include "task.h" -#include "dma_chip.h" -#include "spi_chip.h" -#include "qmspi_chip.h" -#include "tfdp_chip.h" - -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -#define QMSPI_TRANSFER_TIMEOUT (100 * MSEC) -#define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) -#define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20 - - - -#ifndef CONFIG_MCHP_QMSPI_TX_DMA -#ifdef LFW -/* - * MCHP 32-bit timer 0 configured for 1us count down mode and no - * interrupt in the LFW environment. Don't need to sleep CPU in LFW. - */ -static int qmspi_wait(uint32_t mask, uint32_t mval) -{ - uint32_t t1, t2, td; - - t1 = MCHP_TMR32_CNT(0); - - while ((MCHP_QMSPI0_STS & mask) != mval) { - t2 = MCHP_TMR32_CNT(0); - if (t1 >= t2) - td = t1 - t2; - else - td = t1 + (0xfffffffful - t2); - if (td > QMSPI_BYTE_TRANSFER_TIMEOUT_US) - return EC_ERROR_TIMEOUT; - } - return EC_SUCCESS; -} -#else -/* - * This version uses the full EC_RO/RW timer infrastructure and it needs - * a timer ISR to handle timer underflow. Without the ISR we observe false - * timeouts when debugging with JTAG. - * QMSPI_BYTE_TRANSFER_TIMEOUT_US currently 3ms - * QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US currently 100 us - */ - -static int qmspi_wait(uint32_t mask, uint32_t mval) -{ - timestamp_t deadline; - - deadline.val = get_time().val + (QMSPI_BYTE_TRANSFER_TIMEOUT_US); - - while ((MCHP_QMSPI0_STS & mask) != mval) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - - usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - return EC_SUCCESS; -} -#endif /* #ifdef LFW */ -#endif /* #ifndef CONFIG_MCHP_QMSPI_TX_DMA */ - -/* - * Wait for QMSPI read using DMA to finish. - * DMA subsystem has 100 ms timeout - */ -int qmspi_transaction_wait(const struct spi_device_t *spi_device) -{ - const struct dma_option *opdma; - - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - if (opdma != NULL) - return dma_wait(opdma->channel); - - return EC_ERROR_INVAL; -} - -/* - * Create QMSPI transmit data descriptor not using DMA. - * Transmit on MOSI pin (single/full-duplex) from TX FIFO. - * TX FIFO filled by CPU. - * Caller will apply close and last flags if applicable. - */ -#ifndef CONFIG_MCHP_QMSPI_TX_DMA -static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid) -{ - uint32_t d; - - d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_TX_DATA; - d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); - - if (ntx <= MCHP_QMSPI_C_MAX_UNITS) - d |= MCHP_QMSPI_C_XFRU_1B; - else { - if ((ntx & 0x0f) == 0) { - ntx >>= 4; - d |= MCHP_QMSPI_C_XFRU_16B; - } else if ((ntx & 0x03) == 0) { - ntx >>= 2; - d |= MCHP_QMSPI_C_XFRU_4B; - } else - d |= MCHP_QMSPI_C_XFRU_1B; - - if (ntx > MCHP_QMSPI_C_MAX_UNITS) - return 0; /* overflow unit count field */ - } - - d |= (ntx << MCHP_QMSPI_C_NUM_UNITS_BITPOS); - - return d; -} - -/* - * Create QMSPI receive data descriptor using DMA. - * Receive data on MISO pin (single/full-duplex) and store in QMSPI - * RX FIFO. QMSPI triggers DMA channel to read from RX FIFO and write - * to memory. Return value is an uint64_t where low 32-bit word is the - * descriptor and upper 32-bit word is DMA channel unit length with - * value (1, 2, or 4). - * Caller will apply close and last flags if applicable. - */ -static uint64_t qmspi_build_rx_descr(uint32_t raddr, - uint32_t nrx, uint32_t ndid) -{ - uint32_t d, dmau, na; - uint64_t u; - - d = MCHP_QMSPI_C_1X + MCHP_QMSPI_C_RX_EN; - d |= ((ndid & 0x0F) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); - - dmau = 1; - na = (raddr | nrx) & 0x03; - if (na == 0) { - d |= MCHP_QMSPI_C_RX_DMA_4B; - dmau <<= 2; - } else if (na == 0x02) { - d |= MCHP_QMSPI_C_RX_DMA_2B; - dmau <<= 1; - } else { - d |= MCHP_QMSPI_C_RX_DMA_1B; - } - - if ((nrx & 0x0f) == 0) { - nrx >>= 4; - d |= MCHP_QMSPI_C_XFRU_16B; - } else if ((nrx & 0x03) == 0) { - nrx >>= 2; - d |= MCHP_QMSPI_C_XFRU_4B; - } else { - d |= MCHP_QMSPI_C_XFRU_1B; - } - - u = 0; - if (nrx <= MCHP_QMSPI_C_MAX_UNITS) { - d |= (nrx << MCHP_QMSPI_C_NUM_UNITS_BITPOS); - u = dmau; - u <<= 32; - u |= d; - } - - return u; -} -#endif - -#ifdef CONFIG_MCHP_QMSPI_TX_DMA - -#define QMSPI_ERR_ANY 0x80 -#define QMSPI_ERR_BAD_PTR 0x81 -#define QMSPI_ERR_OUT_OF_DESCR 0x85 - -/* - * bits[1:0] of word - * 1 -> 0 - * 2 -> 1 - * 4 -> 2 - */ -static uint32_t qmspi_pins_encoding(uint8_t npins) -{ - return (uint32_t)(npins >> 1) & 0x03; -} - -/* - * Clear status, FIFO's, and all descriptors. - * Enable descriptor mode. - */ -static void qmspi_descr_mode_ready(void) -{ - int i; - - MCHP_QMSPI0_CTRL = 0; - MCHP_QMSPI0_IEN = 0; - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS; - MCHP_QMSPI0_STS = 0xfffffffful; - MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN; - /* clear all descriptors */ - for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++) - MCHP_QMSPI0_DESCR(i) = 0; -} - -/* - * helper - * did = zero based index of start descriptor - * descr = descriptor configuration - * nb = number of bytes to transfer - * Return index of last descriptor allocated or 0xffff - * if out of descriptors. - * Algorithm: - * If requested number of bytes will fit in one descriptor then - * configure descriptor for QMSPI byte units and return. - * Otherwise allocate multiple descriptor using QMSPI 16-byte mode - * and remaining < 16 bytes in byte unit descriptor until all bytes - * exhausted or out of descriptors error. - */ -static uint32_t qmspi_descr_alloc(uint32_t did, - uint32_t descr, uint32_t nb) -{ - uint32_t nu; - - while (nb) { - if (did >= MCHP_QMSPI_MAX_DESCR) - return 0xffff; - - descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK + - MCHP_QMSPI_C_XFRU_MASK); - - if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) { - descr |= MCHP_QMSPI_C_XFRU_1B; - descr += (nb << MCHP_QMSPI_C_NUM_UNITS_BITPOS); - nb = 0; - } else { - descr |= MCHP_QMSPI_C_XFRU_16B; - nu = (nb >> 4) & MCHP_QMSPI_C_NUM_UNITS_MASK0; - descr += (nu << MCHP_QMSPI_C_NUM_UNITS_BITPOS); - nb -= (nu << 4); - } - - descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); - MCHP_QMSPI0_DESCR(did) = descr; - if (nb) - did++; - } - - return did; -} - -/* - * Build one or more descriptors for command/data transmit. - * cfg b[7:0] = start descriptor index - * cfg b[15:8] = number of pins for transmit. - * If bytes to transmit will fit in TX FIFO then fill TX FIFO and build - * one descriptor. - * Otherwise build one or more descriptors to fill TX FIFO using DMA - * channel and configure the DMA channel for memory to device transfer. - */ -static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma, - uint32_t cfg, - const uint8_t *data, - uint32_t ndata) -{ - uint32_t d, d2, did, dma_cfg; - - did = cfg & 0x0f; - d = qmspi_pins_encoding((cfg >> 8) & 0x07); - - if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) { - d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) + - MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA; - d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); - MCHP_QMSPI0_DESCR(did) = d2; - while (ndata--) - MCHP_QMSPI0_TX_FIFO8 = *data++; - } else { // TX DMA - if (((uint32_t)data | ndata) & 0x03) { - dma_cfg = 1; - d |= (MCHP_QMSPI_C_TX_DATA + - MCHP_QMSPI_C_TX_DMA_1B); - } else { - dma_cfg = 4; - d |= (MCHP_QMSPI_C_TX_DATA + - MCHP_QMSPI_C_TX_DMA_4B); - } - did = qmspi_descr_alloc(did, d, ndata); - if (did == 0xffff) - return QMSPI_ERR_OUT_OF_DESCR; - - dma_clr_chan(opdma->channel); - dma_cfg_buffers(opdma->channel, data, ndata, - (void *)MCHP_QMSPI0_TX_FIFO_ADDR); - dma_cfg_xfr(opdma->channel, dma_cfg, - MCHP_DMA_QMSPI0_TX_REQ_ID, - (DMA_FLAG_M2D + DMA_FLAG_INCR_MEM)); - dma_run(opdma->channel); - } - - return did; -} - -/* - * QMSPI0 Start - * flags - * b[0] = 1 de-assert chip select when done - * b[1] = 1 enable QMSPI interrupts - * b[2] = 1 start - */ -void qmspi_cfg_irq_start(uint8_t flags) -{ - MCHP_INT_DISABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT; - MCHP_INT_SOURCE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT; - MCHP_QMSPI0_IEN = 0; - - if (flags & (1u << 1)) { - MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE + - MCHP_QMSPI_STS_PROG_ERR); - MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT; - } - - if (flags & (1u << 2)) - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START; -} - -/* - * QMSPI transmit and/or receive - * np_flags - * b[7:0] = flags - * b[0] = close(de-assert chip select when done) - * b[1] = enable Done and ProgError interrupt - * b[2] = start - * b[15:8] = number of tx pins - * b[24:16] = number of rx pins - * - * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR - * or error (bit[7]==1) - */ -uint8_t qmspi_xfr(const struct spi_device_t *spi_device, - uint32_t np_flags, - const uint8_t *txdata, uint32_t ntx, - uint8_t *rxdata, uint32_t nrx) -{ - uint32_t d, did, dma_cfg; - const struct dma_option *opdma; - - qmspi_descr_mode_ready(); - - did = 0; - if (ntx) { - if (txdata == NULL) - return QMSPI_ERR_BAD_PTR; - - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR); - - d = qmspi_pins_encoding((np_flags >> 8) & 0xff); - dma_cfg = (np_flags & 0xFF00) + did; - did = qmspi_xmit_data_descr(opdma, dma_cfg, txdata, ntx); - if (did & QMSPI_ERR_ANY) - return (uint8_t)(did & 0xff); - - if (nrx) - did++; /* point to next descriptor */ - } - - if (nrx) { - if (rxdata == NULL) - return QMSPI_ERR_BAD_PTR; - - if (did >= MCHP_QMSPI_MAX_DESCR) - return QMSPI_ERR_OUT_OF_DESCR; - - d = qmspi_pins_encoding((np_flags >> 16) & 0xff); - /* compute DMA units: 1 or 4 */ - if (((uint32_t)rxdata | nrx) & 0x03) { - dma_cfg = 1; - d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_1B); - } else { - dma_cfg = 4; - d |= (MCHP_QMSPI_C_RX_EN + MCHP_QMSPI_C_RX_DMA_4B); - } - did = qmspi_descr_alloc(did, d, nrx); - if (did & QMSPI_ERR_ANY) - return (uint8_t)(did & 0xff); - - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - dma_clr_chan(opdma->channel); - dma_cfg_buffers(opdma->channel, rxdata, nrx, - (void *)MCHP_QMSPI0_RX_FIFO_ADDR); - dma_cfg_xfr(opdma->channel, dma_cfg, - MCHP_DMA_QMSPI0_RX_REQ_ID, - (DMA_FLAG_D2M + DMA_FLAG_INCR_MEM)); - dma_run(opdma->channel); - } - - if (ntx || nrx) { - d = MCHP_QMSPI0_DESCR(did); - d |= MCHP_QMSPI_C_DESCR_LAST; - if (np_flags & 0x01) - d |= MCHP_QMSPI_C_CLOSE; - MCHP_QMSPI0_DESCR(did) = d; - qmspi_cfg_irq_start(np_flags & 0xFF); - } - - return (uint8_t)(did & 0xFF); -} -#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */ - -/* - * QMSPI controller must control chip select therefore this routine - * configures QMSPI to assert SPI CS# and de-assert when done. - * Transmit using QMSPI TX FIFO only when tx data fits in TX FIFO else - * use TX DMA. - * Transmit and receive will allocate as many QMSPI descriptors as - * needed for data size. This could result in an error if the maximum - * number of descriptors is exceeded. - * Descriptors are limited to 0x7FFF units where unit size is 1, 4, or - * 16 bytes. Code determines unit size based upon number of bytes and - * alignment of data buffer. - * DMA channel will move data in units of 1 or 4 bytes also based upon - * the number of data bytes and buffer alignment. - * The most efficient transfers are those where TX and RX buffers are - * aligned >= 4 bytes and the number of bytes is a multiple of 4. - * NOTE on SPI flash commands: - * This routine does NOT handle SPI flash commands requiring - * dummy clocks or special mode bytes. Dummy clocks and special mode - * bytes require additional descriptors. For example the flash read - * dual command (0x3B): - * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on - * one pin (IO0). - * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When - * this descriptor is executed QMSPI will tri-state IO0 & IO1 and - * output 8 clocks (dual mode 4 clocks per byte). The SPI flash may - * turn on its output drivers on the first dummy clock. - * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit - * size and DMA unit size based on number of bytes to read and - * alignment of destination buffer. - * The common SPI API will be required to supply more information about - * SPI flash read commands. A further complication is some larger SPI - * flash devices support a 4-byte address mode. 4-byte address mode can - * be implemented as separate command code or a configuration bit in - * the SPI flash that changes the default 24-bit address command to - * require a 32-bit address. - * 0x03 is 1-1-1 - * 0x3B is 1-1-2 with 8 dummy clocks - * 0x6B is 1-1-4 with 8 dummy clocks - * 0xBB is 1-2-2 with 4 dummy clocks - * Number of IO pins for command - * Number of IO pins for address - * Number of IO pins for data - * Number of bit/bytes for address (3 or 4) - * Number of dummy clocks after address phase - */ -#ifdef CONFIG_MCHP_QMSPI_TX_DMA -int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - uint32_t np_flags, ntx, nrx; - int ret; - uint8_t rc; - - ntx = 0; - if (txlen >= 0) - ntx = (uint32_t)txlen; - - nrx = 0; - if (rxlen >= 0) - nrx = (uint32_t)rxlen; - - np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */ - rc = qmspi_xfr(spi_device, np_flags, - txdata, ntx, - rxdata, nrx); - - if (rc & QMSPI_ERR_ANY) - return EC_ERROR_INVAL; - - ret = EC_SUCCESS; - return ret; -} -#else -/* - * Transmit using CPU and QMSPI TX FIFO(no DMA). - * Receive using DMA as above. - */ -int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - const struct dma_option *opdma; - uint32_t d, did, dmau; - uint64_t u; - - if (spi_device == NULL) - return EC_ERROR_PARAM1; - - /* soft reset the controller */ - MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - d = spi_device->div; - d <<= MCHP_QMSPI_M_CLKDIV_BITPOS; - d += (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0); - MCHP_QMSPI0_MODE = d; - MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN; - - d = did = 0; - - if (txlen > 0) { - if (txdata == NULL) - return EC_ERROR_PARAM2; - - d = qmspi_build_tx_descr((uint32_t)txlen, 1); - if (d == 0) /* txlen too large */ - return EC_ERROR_OVERFLOW; - - MCHP_QMSPI0_DESCR(did) = d; - } - - if (rxlen > 0) { - if (rxdata == NULL) - return EC_ERROR_PARAM4; - - u = qmspi_build_rx_descr((uint32_t)rxdata, - (uint32_t)rxlen, 2); - - d = (uint32_t)u; - dmau = u >> 32; - - if (txlen > 0) - did++; - MCHP_QMSPI0_DESCR(did) = d; - - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata); - } - - MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE + - MCHP_QMSPI_C_DESCR_LAST); - - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START; - - while (txlen--) { - if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) { - if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY, - MCHP_QMSPI_STS_TX_BUFF_EMPTY) != - EC_SUCCESS) { - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP; - return EC_ERROR_TIMEOUT; - } - } else - MCHP_QMSPI0_TX_FIFO8 = *txdata++; - } - - return EC_SUCCESS; -} -#endif /* #ifdef CONFIG_MCHP_QMSPI_TX_DMA */ - -/* - * Wait for QMSPI descriptor mode transfer to finish. - * QMSPI is configured to perform a complete transaction. - * Assert CS# - * optional transmit - * CPU keeps filling TX FIFO until all bytes are transmitted. - * optional receive - * QMSPI is configured to read rxlen bytes and uses a DMA channel - * to move data from its RX FIFO to memory. - * De-assert CS# - * This routine can be called with QMSPI hardware in four states: - * 1. Transmit only and QMSPI has finished (empty TX FIFO) by the time - * this routine is called. QMSPI.Status transfer done status will be - * set and QMSPI HW has de-asserted SPI CS#. - * 2. Transmit only and QMSPI TX FIFO is still transmitting. - * QMSPI transfer done status is not asserted and CS# is still - * asserted. QMSPI HW will de-assert CS# when done or firmware - * manually stops QMSPI. - * 3. Receive was enabled and DMA channel is moving data from - * QMSPI RX FIFO to memory. QMSPI.Status transfer done and DMA done - * status bits are not set. QMSPI SPI CS# will stay asserted until - * transaction finishes or firmware manually stops QMSPI. - * 4. Receive was enabled and DMA channel is finished. QMSPI RX FIFO - * should be empty and DMA channel is done. QMSPI.Status transfer - * done and DMA done status bits will be set. QMSPI HW has de-asserted - * SPI CS#. - * We are using QMSPI in descriptor mode. The definition of QMSPI.Status - * transfer complete bit in this mode is: complete will be set to 1 only - * when the last buffer completes its transfer. - * TX only sets complete when transfer unit count is matched and all units - * have been clocked out of the TX FIFO. - * RX DMA transfer complete will be set when the last transfer unit - * is out of the RX FIFO but DMA may not be complete until it finishes - * moving the transfer unit to memory. - * If TX only spin on QMSPI.Status Transfer_Complete bit. - * If RX used spin on QMsPI.Status Transfer_Complete and DMA_Complete. - * Search descriptors looking for RX DMA enabled. - * If RX DMA is enabled add DMA complete flag to status mask. - * Spin while QMSPI.Status & mask != mask or timeout. - * If timeout force QMSPI to stop and exit spin loop. - * if DMA was enabled disable DMA channel. - * Clear QMSPI.Status and FIFO's - */ -int qmspi_transaction_flush(const struct spi_device_t *spi_device) -{ - int ret; - uint32_t qsts, mask; - const struct dma_option *opdma; - timestamp_t deadline; - - if (spi_device == NULL) - return EC_ERROR_PARAM1; - - mask = MCHP_QMSPI_STS_DONE; - - ret = EC_SUCCESS; - deadline.val = get_time().val + QMSPI_TRANSFER_TIMEOUT; - - qsts = MCHP_QMSPI0_STS; - while ((qsts & mask) != mask) { - if (timestamp_expired(deadline, NULL)) { - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP; - ret = EC_ERROR_TIMEOUT; - break; - } - usleep(QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US); - qsts = MCHP_QMSPI0_STS; - } - - /* clear transmit DMA channel */ - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_WR); - if (opdma == NULL) - return EC_ERROR_INVAL; - - dma_disable(opdma->channel); - dma_clear_isr(opdma->channel); - - /* clear receive DMA channel */ - opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); - if (opdma == NULL) - return EC_ERROR_INVAL; - - dma_disable(opdma->channel); - dma_clear_isr(opdma->channel); - - /* clear QMSPI FIFO's */ - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS; - MCHP_QMSPI0_STS = 0xffffffff; - - return ret; -} - -/** - * Enable QMSPI controller and MODULE_SPI_FLASH pins. - * - * @param hw_port b[3:0]=0 and b[7:4]=0 - * @param enable - * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized - * @note called by spi_enable in mec1701/spi.c - * - */ -int qmspi_enable(int hw_port, int enable) -{ - uint8_t dummy __attribute__((unused)) = 0; - - trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", - hw_port, enable); - - if (hw_port != QMSPI0_PORT) - return EC_ERROR_INVAL; - - gpio_config_module(MODULE_SPI_FLASH, (enable > 0)); - - if (enable) { - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI); - MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; - MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE + - MCHP_QMSPI_M_SPI_MODE0 + - MCHP_QMSPI_M_CLKDIV_12M); - } else { - MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; - MCHP_QMSPI0_MODE_ACT_SRST = 0; - MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI); - } - - return EC_SUCCESS; -} - diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h deleted file mode 100644 index 1a1d764267..0000000000 --- a/chip/mchp/qmspi_chip.h +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MEC17xx processor - */ -/** @file qmspi_chip.h - *MEC17xx Quad SPI Master - */ -/** @defgroup MCHP MEC qmspi - */ - -#ifndef _QMSPI_CHIP_H -#define _QMSPI_CHIP_H - -#include <stdint.h> -#include <stddef.h> - -/* struct spi_device_t */ -#include "spi.h" - - -int qmspi_transaction_flush(const struct spi_device_t *spi_device); - -int qmspi_transaction_wait(const struct spi_device_t *spi_device); - -int qmspi_transaction_sync(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); - -int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); - -int qmspi_enable(int port, int enable); - -/* - * QMSPI0 Start - * flags - * b[0] = ignored - * b[1] = 1 enable QMSPI interrupts - * b[2] = 1 start - */ -void qmspi_cfg_irq_start(uint8_t flags); - -/* - * QMSPI transmit and/or receive - * np_flags - * b[7:0] = flags - * b[0] = close(de-assert chip select when done) - * b[1] = enable Done and ProgError interrupt - * b[2] = start - * b[15:8] = number of tx pins - * b[24:16] = number of rx pins - * - * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR - * or error (bit[7]==1) - */ -uint8_t qmspi_xfr(const struct spi_device_t *spi_device, - uint32_t np_flags, - const uint8_t *txdata, uint32_t ntx, - uint8_t *rxdata, uint32_t nrx); - -#endif /* #ifndef _QMSPI_CHIP_H */ -/** @} - */ - diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h deleted file mode 100644 index f7ef36e68c..0000000000 --- a/chip/mchp/registers.h +++ /dev/null @@ -1,2244 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for Microchip MEC family processors - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" - -/* - * Helper function for RAM address aliasing - * NOTE: MCHP AHB masters do NOT require aliasing. - * Cortex-M4 bit-banding does require aliasing of the - * DATA SRAM region. - */ -#define MCHP_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) - -/* EC Chip Configuration */ -#define MCHP_CHIP_BASE 0x400fff00 -#define MCHP_CHIP_DEV_ID REG8(MCHP_CHIP_BASE + 0x20) -#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x21) - - -/* Power/Clocks/Resets */ -#define MCHP_PCR_BASE 0x40080100 - -#define MCHP_PCR_SYS_SLP_CTL REG32(MCHP_PCR_BASE + 0x00) -#define MCHP_PCR_PROC_CLK_CTL REG32(MCHP_PCR_BASE + 0x04) -#define MCHP_PCR_SLOW_CLK_CTL REG32(MCHP_PCR_BASE + 0x08) -#define MCHP_PCR_CHIP_OSC_ID REG32(MCHP_PCR_BASE + 0x0C) -#define MCHP_PCR_PWR_RST_STS REG32(MCHP_PCR_BASE + 0x10) -#define MCHP_PCR_PWR_RST_CTL REG32(MCHP_PCR_BASE + 0x14) -#define MCHP_PCR_SYS_RST REG32(MCHP_PCR_BASE + 0x18) -#define MCHP_PCR_SLP_EN0 REG32(MCHP_PCR_BASE + 0x30) -#define MCHP_PCR_SLP_EN1 REG32(MCHP_PCR_BASE + 0x34) -#define MCHP_PCR_SLP_EN2 REG32(MCHP_PCR_BASE + 0x38) -#define MCHP_PCR_SLP_EN3 REG32(MCHP_PCR_BASE + 0x3C) -#define MCHP_PCR_SLP_EN4 REG32(MCHP_PCR_BASE + 0x40) -#define MCHP_PCR_CLK_REQ0 REG32(MCHP_PCR_BASE + 0x50) -#define MCHP_PCR_CLK_REQ1 REG32(MCHP_PCR_BASE + 0x54) -#define MCHP_PCR_CLK_REQ2 REG32(MCHP_PCR_BASE + 0x58) -#define MCHP_PCR_CLK_REQ3 REG32(MCHP_PCR_BASE + 0x5C) -#define MCHP_PCR_CLK_REQ4 REG32(MCHP_PCR_BASE + 0x60) -#define MCHP_PCR_RST_EN0 REG32(MCHP_PCR_BASE + 0x70) -#define MCHP_PCR_RST_EN1 REG32(MCHP_PCR_BASE + 0x74) -#define MCHP_PCR_RST_EN2 REG32(MCHP_PCR_BASE + 0x78) -#define MCHP_PCR_RST_EN3 REG32(MCHP_PCR_BASE + 0x7C) -#define MCHP_PCR_RST_EN4 REG32(MCHP_PCR_BASE + 0x80) - -#define MCHP_PCR_SLP_EN(x) REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2)) -#define MCHP_PCR_CLK_REQ(x) REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2)) -#define MCHP_PCR_RST_EN(x) REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2)) - -#define MCHP_PCR_SLP_RST_REG_MAX (5) - -/* Bit definitions for MCHP_PCR_SYS_SLP_CTL */ -#define MCHP_PCR_SYS_SLP_LIGHT (0ul << 0) -#define MCHP_PCR_SYS_SLP_HEAVY (1ul << 0) -#define MCHP_PCR_SYS_SLP_ALL (1ul << 3) - -/* - * Set/clear PCR sleep enable bit for single device - * d bits[10:8] = register 0 - 4 - * d bits[4:0] = register bit position - */ -#define MCHP_PCR_SLP_EN_DEV(d) (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |=\ - (1ul << ((d) & 0x1f))) -#define MCHP_PCR_SLP_DIS_DEV(d) (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &=\ - ~(1ul << ((d) & 0x1f))) - -/* - * Set/clear bit pattern specified by mask in a single PCR sleep enable - * register. - * id = zero based ID of sleep enable register (0-4) - * m = bit mask of bits to change - */ -#define MCHP_PCR_SLP_EN_DEV_MASK(id, m) MCHP_PCR_SLP_EN((id)) |= (m) -#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) MCHP_PCR_SLP_EN((id)) &= ~(m) - -/* Slow Clock Control Mask */ -#define MCHP_PCR_SLOW_CLK_CTL_MASK 0x03FFul - -/* Sleep Enable, Clock Required, Reset on Sleep 0 bits */ -#define MCHP_PCR_ISPI (0x0002) -#define MCHP_PCR_EFUSE (0x0001) -#define MCHP_PCR_JTAG (0x0000) - -/* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_ISPI BIT(2) -#define MCHP_PCR_SLP_EN0_EFUSE BIT(1) -#define MCHP_PCR_SLP_EN0_JTAG BIT(0) -#define MCHP_PCR_SLP_EN0_SLEEP 0x07ul - -/* Sleep Enable, Clock Required, Reset on Sleep 1 bits */ -#define MCHP_PCR_BTMR16_1 (BIT(8) + 31) -#define MCHP_PCR_BTMR16_0 (BIT(8) + 30) -#define MCHP_PCR_ECS (BIT(8) + 29) -#define MCHP_PCR_PWM8 (BIT(8) + 27) -#define MCHP_PCR_PWM7 (BIT(8) + 26) -#define MCHP_PCR_PWM6 (BIT(8) + 25) -#define MCHP_PCR_PWM5 (BIT(8) + 24) -#define MCHP_PCR_PWM4 (BIT(8) + 23) -#define MCHP_PCR_PWM3 (BIT(8) + 22) -#define MCHP_PCR_PWM2 (BIT(8) + 21) -#define MCHP_PCR_PWM1 (BIT(8) + 20) -#define MCHP_PCR_TACH2 (BIT(8) + 12) -#define MCHP_PCR_TACH1 (BIT(8) + 11) -#define MCHP_PCR_I2C0 (BIT(8) + 10) -#define MCHP_PCR_WDT (BIT(8) + 9) -#define MCHP_PCR_CPU (BIT(8) + 8) -#define MCHP_PCR_TFDP (BIT(8) + 7) -#define MCHP_PCR_DMA (BIT(8) + 6) -#define MCHP_PCR_PMC (BIT(8) + 5) -#define MCHP_PCR_PWM0 (BIT(8) + 4) -#define MCHP_PCR_TACH0 (BIT(8) + 2) -#define MCHP_PCR_PECI (BIT(8) + 1) -#define MCHP_PCR_ECIA (BIT(8) + 0) - -/* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) -#define MCHP_PCR_SLP_EN1_ECS BIT(29) -/* bit[28] reserved */ -#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) -#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) -#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) -#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) -#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) -#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) -#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) -#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) -#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) -/* bits[19:13] reserved */ -#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) -#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) -#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) -#define MCHP_PCR_SLP_EN1_WDT BIT(9) -#define MCHP_PCR_SLP_EN1_CPU BIT(8) -#define MCHP_PCR_SLP_EN1_TFDP BIT(7) -#define MCHP_PCR_SLP_EN1_DMA BIT(6) -#define MCHP_PCR_SLP_EN1_PMC BIT(5) -#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) -/* bit[3] reserved */ -#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) -#define MCHP_PCR_SLP_EN1_PECI BIT(1) -#define MCHP_PCR_SLP_EN1_ECIA BIT(0) -/* all sleep enable 1 bits */ -#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff -/* - * block not used by default - * Always use ECIA, PMC, CPU and ECS - */ -#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede - -/* Sleep Enable2, Clock Required2, Reset on Sleep2 bits */ -#define MCHP_PCR_P80CAP1 ((2 << 8) + 26) -#define MCHP_PCR_P80CAP0 ((2 << 8) + 25) -#define MCHP_PCR_ACPI_EC4 ((2 << 8) + 23) -#define MCHP_PCR_ACPI_EC3 ((2 << 8) + 22) -#define MCHP_PCR_ACPI_EC2 ((2 << 8) + 21) -#define MCHP_PCR_ESPI ((2 << 8) + 19) -#define MCHP_PCR_RTC ((2 << 8) + 18) -#define MCHP_PCR_MBOX ((2 << 8) + 17) -#define MCHP_PCR_8042 ((2 << 8) + 16) -#define MCHP_PCR_ACPI_PM1 ((2 << 8) + 15) -#define MCHP_PCR_ACPI_EC1 ((2 << 8) + 14) -#define MCHP_PCR_ACPI_EC0 ((2 << 8) + 13) -#define MCHP_PCR_GCFG ((2 << 8) + 12) -#define MCHP_PCR_UART1 ((2 << 8) + 2) -#define MCHP_PCR_UART0 ((2 << 8) + 1) -#define MCHP_PCR_LPC ((2 << 8) + 0) - -/* Command all blocks to sleep */ -/* bits[31:27] reserved */ -#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) -#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) -/* bit[24] reserved */ -#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) -/* bit[20] reserved */ -#define MCHP_PCR_SLP_EN2_ESPI BIT(19) -#define MCHP_PCR_SLP_EN2_RTC BIT(18) -#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) -#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) -#define MCHP_PCR_SLP_EN2_GCFG BIT(12) -/* bits[11:3] reserved */ -#define MCHP_PCR_SLP_EN2_UART1 BIT(2) -#define MCHP_PCR_SLP_EN2_UART0 BIT(1) -#define MCHP_PCR_SLP_EN2_LPC BIT(0) -/* all sleep enable 2 bits */ -#define MCHP_PCR_SLP_EN2_SLEEP 0x07ffffff - -/* Sleep Enable3, Clock Required3, Reset on Sleep3 bits */ -#define MCHP_PCR_PWM9 ((3 << 8) + 31) -#define MCHP_PCR_CCT0 ((3 << 8) + 30) -#define MCHP_PCR_HTMR1 ((3 << 8) + 29) -#define MCHP_PCR_AESHASH ((3 << 8) + 28) -#define MCHP_PCR_RNG ((3 << 8) + 27) -#define MCHP_PCR_PKE ((3 << 8) + 26) -#define MCHP_PCR_LED3 ((3 << 8) + 25) -#define MCHP_PCR_BTMR32_1 ((3 << 8) + 24) -#define MCHP_PCR_BTMR32_0 ((3 << 8) + 23) -#define MCHP_PCR_BTMR16_3 ((3 << 8) + 22) -#define MCHP_PCR_BTMR16_2 ((3 << 8) + 21) -#define MCHP_PCR_GPSPI1 ((3 << 8) + 20) -#define MCHP_PCR_BCM0 ((3 << 8) + 19) -#define MCHP_PCR_LED2 ((3 << 8) + 18) -#define MCHP_PCR_LED1 ((3 << 8) + 17) -#define MCHP_PCR_LED0 ((3 << 8) + 16) -#define MCHP_PCR_I2C3 ((3 << 8) + 15) -#define MCHP_PCR_I2C2 ((3 << 8) + 14) -#define MCHP_PCR_I2C1 ((3 << 8) + 13) -#define MCHP_PCR_RPMPWM0 ((3 << 8) + 12) -#define MCHP_PCR_KEYSCAN ((3 << 8) + 11) -#define MCHP_PCR_HTMR0 ((3 << 8) + 10) -#define MCHP_PCR_GPSPI0 ((3 << 8) + 9) -#define MCHP_PCR_PS2_2 ((3 << 8) + 7) -#define MCHP_PCR_PS2_1 ((3 << 8) + 6) -#define MCHP_PCR_PS2_0 ((3 << 8) + 5) -#define MCHP_PCR_ADC ((3 << 8) + 3) - -/* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) -#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) -#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) -#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) -#define MCHP_PCR_SLP_EN3_RNG BIT(27) -#define MCHP_PCR_SLP_EN3_PKE BIT(26) -#define MCHP_PCR_SLP_EN3_LED3 BIT(25) -#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) -#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) -#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) -#define MCHP_PCR_SLP_EN3_GPSPI1 BIT(20) -#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) -#define MCHP_PCR_SLP_EN3_LED2 BIT(18) -#define MCHP_PCR_SLP_EN3_LED1 BIT(17) -#define MCHP_PCR_SLP_EN3_LED0 BIT(16) -#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) -#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) -#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) -#define MCHP_PCR_SLP_EN3_RPMPWM0 BIT(12) -#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) -#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) -#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) -/* bit[8] reserved */ -#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7) -#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) -#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) -/* bit[4] reserved */ -#define MCHP_PCR_SLP_EN3_ADC BIT(3) -/* bits[2:0] reserved */ -/* all sleep enable 3 bits */ -#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffeed -#define MCHP_PCR_SLP_EN3_PWM_ALL (1ul << 31) - -/* Sleep Enable4, Clock Required4, Reset on Sleep4 bits */ -#define MCHP_PCR_FJCL ((4 << 8) + 15) -#define MCHP_PCR_PSPI ((4 << 8) + 14) -#define MCHP_PCR_PROCHOT ((4 << 8) + 13) -#define MCHP_PCR_RCID2 ((4 << 8) + 12) -#define MCHP_PCR_RCID1 ((4 << 8) + 11) -#define MCHP_PCR_RCID0 ((4 << 8) + 10) -#define MCHP_PCR_BCM1 ((4 << 8) + 9) -#define MCHP_PCR_QMSPI ((4 << 8) + 8) -#define MCHP_PCR_RPMPWM1 ((4 << 8) + 7) -#define MCHP_PCR_RTMR ((4 << 8) + 6) -#define MCHP_PCR_CNT16_3 ((4 << 8) + 5) -#define MCHP_PCR_CNT16_2 ((4 << 8) + 4) -#define MCHP_PCR_CNT16_1 ((4 << 8) + 3) -#define MCHP_PCR_CNT16_0 ((4 << 8) + 2) -#define MCHP_PCR_PWM11 ((4 << 8) + 1) -#define MCHP_PCR_PWM10 ((4 << 8) + 0) - -/* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN4_FJCL BIT(15) -#define MCHP_PCR_SLP_EN4_PSPI BIT(14) -#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) -#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) -#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) -#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) -#define MCHP_PCR_SLP_EN4_BCM1 BIT(9) -#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) -#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) -#define MCHP_PCR_SLP_EN4_RTMR BIT(6) -#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) -#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) -#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) -#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) -#define MCHP_PCR_SLP_EN4_PWM_ALL (3 << 0) -#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) -#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) -/* all sleep enable 4 bits */ -#define MCHP_PCR_SLP_EN4_SLEEP 0x0000ffff - -/* Allow all blocks to request clocks */ -#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP)) -#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP)) -#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP)) -#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP)) -#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP)) - - -/* Bit definitions for MCHP_PCR_SLP_EN1/CLK_REQ1/RST_EN1 */ - -/* Bit definitions for MCHP_PCR_SLP_EN2/CLK_REQ2/RST_EN2 */ - -/* Bit definitions for MCHP_PCR_SLP_EN3/CLK_REQ3/RST_EN3 */ -#define MCHP_PCR_SLP_EN1_PKE BIT(26) -#define MCHP_PCR_SLP_EN1_NDRNG BIT(27) -#define MCHP_PCR_SLP_EN1_AES_SHA BIT(28) -#define MCHP_PCR_SLP_EN1_ALL_CRYPTO (0x07 << 26) - -/* Bit definitions for MCHP_PCR_SLP_EN4/CLK_REQ4/RST_EN4 */ - - -/* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_VTR BIT(6) -#define MCHP_PWR_RST_STS_VBAT BIT(5) - -/* Bit defines for MCHP_PCR_PWR_RST_CTL */ -#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 -#define MCHP_PCR_PWR_HOST_RST_LRESET 1 -#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST 0 - - -/* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET BIT(8) - - -/* TFDP */ -#define MCHP_TFDP_BASE 0x40008c00 -#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) -#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) - - -/* EC Subsystem */ -#define MCHP_EC_BASE 0x4000fc00 -#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) -#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) -#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) -#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) -#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) -#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) -#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) -#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c) -#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c) -#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64) - -/* MCHP_EC_JTAG_EN bit definitions */ -#define MCHP_JTAG_ENABLE 0x01 -/* bits [2:1] */ -#define MCHP_JTAG_MODE_4PIN 0x00 -/* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */ -#define MCHP_JTAG_MODE_SWD_SWV 0x02 -/* ARM 2-pin SWD with no SWV */ -#define MCHP_JTAG_MODE_SWD 0x04 - - -/* MCHP_EC_CRYPTO_SRESET bit definitions */ -#define MCHP_CRYPTO_NDRNG_SRST 0x01 -#define MCHP_CRYPTO_PKE_SRST 0x02 -#define MCHP_CRYPTO_AES_SHA_SRST 0x04 -#define MCHP_CRYPTO_ALL_SRST 0x07 - -/* MCHP_GPIO_BANK_PWR bit definitions */ -#define MCHP_EC_GPIO_BANK_PWR_VTR1_18 (0x01) -#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 (0x02) -#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 (0x04) - - -/* AHB ERR Enable */ -#define MCHP_EC_AHB_ERROR_ENABLE 0 -#define MCHP_EC_AHB_ERROR_DISABLE 1 - - -/* Interrupt aggregator */ -#define MCHP_INT_BASE 0x4000e000 -#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + ((x)<<4) + ((x)<<2) - 160) -#define MCHP_INT_SOURCE(x) REG32(MCHP_INTx_BASE(x) + 0x0) -#define MCHP_INT_ENABLE(x) REG32(MCHP_INTx_BASE(x) + 0x4) -#define MCHP_INT_RESULT(x) REG32(MCHP_INTx_BASE(x) + 0x8) -#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc) -#define MCHP_INT_BLK_EN REG32(MCHP_INT_BASE + 0x200) -#define MCHP_INT_BLK_DIS REG32(MCHP_INT_BASE + 0x204) -#define MCHP_INT_BLK_IRQ REG32(MCHP_INT_BASE + 0x208) -#define MCHP_INT_GIRQ_FIRST 8 -#define MCHP_INT_GIRQ_LAST 26 -#define MCHP_INT_GIRQ_NUM (26-8+1) - -/* - * Bits for INT=13(GIRQ13) registers - * SMBus[0:3] = bits[0:3] - */ -#define MCHP_INT13_SMB(x) (1ul << (x)) - - -/* - * Bits for INT=14(GIRQ14) registers - * DMA channels 0 - 13 - */ -#define MCHP_INT14_DMA(x) (1ul << (x)) - - -/* Bits for INT=15(GIRQ15) registers - * UART[0:1] = bits[0:1] - * EMI[0:2] = bits[2:4] - */ -#define MCHP_INT15_UART(x) (1ul << ((x) & 0x01)) -#define MCHP_INT15_EMI(x) (1ul << (2 + (x))) -/* - * ACPI_EC[0:4] IBF = bits[5,7,9,11,13] - * ACPI_EC[0:4] OBE = bits[6,8,10,12,14] - */ -#define MCHP_INT15_ACPI_EC_IBF(x) (1ul << (5 + ((x) << 1))) -#define MCHP_INT15_ACPI_EC_OBE(x) (1ul << (6 + ((x) << 1))) -#define MCHP_INT15_ACPI_PM1_CTL (1ul << 15) -#define MCHP_INT15_ACPI_PM1_EN (1ul << 16) -#define MCHP_INT15_ACPI_PM1_STS (1ul << 17) -#define MCHP_INT15_8042_OBE (1ul << 18) -#define MCHP_INT15_8042_IBF (1ul << 19) -#define MCHP_INT15_MAILBOX (1ul << 20) -#define MCHP_INT15_P80(x) (1ul << (22 + ((x) & 0x01))) - - -/* Bits for INT=16(GIRQ16) registers */ -#define MCHP_INT16_PKE_ERR (1ul << 0) -#define MCHP_INT16_PKE_DONE (1ul << 1) -#define MCHP_INT16_RNG_DONE (1ul << 2) -#define MCHP_INT16_AES_DONE (1ul << 3) -#define MCHP_INT16_HASH_DONE (1ul << 4) - - -/* Bits for INT=17(GIRQ17) registers */ -#define MCHP_INT17_PECI (1ul << 0) -/* TACH[0:2] = bits[1:3] */ -#define MCHP_INT17_TACH(x) (1ul << (1 + (x))) -/* RPMFAN_FAIL[0:1] = bits[4,6] */ -#define MCHP_INT17_RPMFAN_FAIL(x) (1ul << (4 + ((x) << 1))) -/* RPMFAN_STALL[0:1] = bits[5,7] */ -#define MCHP_INT17_RPMFAN_STALL(x) (1ul << (5 + ((x) << 1))) -#define MCHP_INT17_ADC_SINGLE (1ul << 8) -#define MCHP_INT17_ADC_REPEAT (1ul << 9) -/* RCIC[0:2] = bits[10:12] */ -#define MCHP_INT17_RCID(x) (1ul << (10 + (x))) -#define MCHP_INT17_LED_WDT(x) (1ul << (13 + (x))) - - -/* Bits for INT=18(GIRQ18) registers */ -#define MCHP_INT18_LPC (1ul << 0) -#define MCHP_INT18_QMSPI0 (1ul << 1) -/* SPI_TX[0:1] = bits[2,4] */ -#define MCHP_INT18_SPI_TX(x) (1ul << (2 + ((x) << 1))) -/* SPI_RX[0:1] = bits[3,5] */ -#define MCHP_INT18_SPI_RX(x) (1ul << (3 + ((x) << 1))) - - -/* Bits for INT=19(GIRQ19) registers */ -#define MCHP_INT19_ESPI_PC (1ul << 0) -#define MCHP_INT19_ESPI_BM1 (1ul << 1) -#define MCHP_INT19_ESPI_BM2 (1ul << 2) -#define MCHP_INT19_ESPI_LTR (1ul << 3) -#define MCHP_INT19_ESPI_OOB_TX (1ul << 4) -#define MCHP_INT19_ESPI_OOB_RX (1ul << 5) -#define MCHP_INT19_ESPI_FC (1ul << 6) -#define MCHP_INT19_ESPI_RESET (1ul << 7) -#define MCHP_INT19_ESPI_VW_EN (1ul << 8) - - -/* Bits for INT=21(GIRQ21) registers */ -#define MCHP_INT21_RTOS_TMR (1ul << 0) -/* HibernationTimer[0:1] = bits[1:2] */ -#define MCHP_INT21_HIB_TMR(x) (1ul << (1 + (x))) -#define MCHP_INT21_WEEK_ALARM (1ul << 3) -#define MCHP_INT21_WEEK_SUB (1ul << 4) -#define MCHP_INT21_WEEK_1SEC (1ul << 5) -#define MCHP_INT21_WEEK_1SEC_SUB (1ul << 6) -#define MCHP_INT21_WEEK_PWR_PRES (1ul << 7) -#define MCHP_INT21_RTC (1ul << 8) -#define MCHP_INT21_RTC_ALARM (1ul << 9) -#define MCHP_INT21_VCI_OVRD (1ul << 10) -/* VCI_IN[0:6] = bits[11:17] */ -#define MCHP_INT21_VCI_IN(x) (1ul << (11 + (x))) -/* PS2 Port Wake[0:4] =[0A,0B,1A,1B,2] = bits[18:22] */ -#define MCHP_INT21_PS2_WAKE(x) (1ul << (18 + (x))) -#define MCHP_INT21_KEYSCAN (1ul << 25) - -/* Bits for INT=22(GIRQ22) wake only registers */ -#define MCHP_INT22_WAKE_ONLY_LPC (1ul << 0) -#define MCHP_INT22_WAKE_ONLY_I2C0 (1ul << 1) -#define MCHP_INT22_WAKE_ONLY_I2C1 (1ul << 2) -#define MCHP_INT22_WAKE_ONLY_I2C2 (1ul << 3) -#define MCHP_INT22_WAKE_ONLY_I2C3 (1ul << 4) -#define MCHP_INT22_WAKE_ONLY_ESPI (1ul << 9) - -/* Bits for INT=23(GIRQ23) registers */ -/* 16-bit Basic Timers[0:3] = bits[0:3] */ -#define MCHP_INT23_BASIC_TMR16(x) (1ul << (x)) -/* 32-bit Basic Timers[0:1] = bits[4:5] */ -#define MCHP_INT23_BASIC_TMR32(x) (1ul << (4 + (x))) -/* 16-bit Counter-Timer[0:3] = bits[6:9] */ -#define MCHP_INT23_CNT(x) (1ul << (6 + (x))) -#define MCHP_INT23_CCT_TMR (1ul << 10) -/* CCT Capture events[0:5] = bits[11:16] */ -#define MCHP_INT23_CCT_CAP(x) (1ul << (11 + (x))) -/* CCT Compare events[0:1] = bits[17:18] */ -#define MCHP_INT23_CCT_CMP(x) (1ul << (17 + (x))) - - -/* Bits for INT=24(GIRQ24) registers */ -/* Master-to-Slave v=[0:6], Source=[0:3] */ -#define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s))) - -/* Bits for INT25(GIRQ25) registers */ -/* Master-to-Slave v=[7:10], Source=[0:3] */ -#define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s))) - -/* End MCHP_INTxy bit definitions */ - -/* UART Peripheral */ -#define MCHP_UART_CONFIG_BASE(x) (0x400f2700 + ((x) * 0x400)) -#define MCHP_UART_RUNTIME_BASE(x) (0x400f2400 + ((x) * 0x400)) - -#define MCHP_UART_ACT(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0x30) -#define MCHP_UART_CFG(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0) - -/* DLAB=0 */ -#define MCHP_UART_RB(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_TB(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_IER(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) -/* DLAB=1 */ -#define MCHP_UART_PBRG0(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_PBRG1(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) - -#define MCHP_UART_FCR(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) -#define MCHP_UART_IIR(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) -#define MCHP_UART_LCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3) -#define MCHP_UART_MCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4) -#define MCHP_UART_LSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5) -#define MCHP_UART_MSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6) -#define MCHP_UART_SCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7) -/* - * UART[0:1] connected to GIRQ15 bits[0:1] - */ -#define MCHP_UART_GIRQ 15 -#define MCHP_UART_GIRQ_BIT(x) (1ul << (x)) - -/* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY BIT(5) - - -/* GPIO */ -#define MCHP_GPIO_BASE 0x40081000 - - -/* MCHP each Port contains 32 GPIO's. - * GPIO Control 1 registers are 32-bit registers starting at - * MCHP_GPIO_BASE. - * index = octal GPIO number from MCHP specification. - * port/bank = index >> 5 - * id = index & 0x1F - * - * The port/bank, id pair may also be used to access GPIO's via - * parallel I/O registers if GPIO control is configured for - * parallel I/O. - * - * From ec/chip/mec1701/config_chip.h - * #define GPIO_PIN(index) ((index) >> 5), ((index) & 0x1F) - * - * GPIO Control 1 Address = 0x40081000 + (((bank << 5) + id) << 2) - * - * Example: GPIO043, Control 1 register address = 0x4008108c - * port/bank = 0x23 >> 5 = 1 - * id = 0x23 & 0x1F = 0x03 - * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c - * - * Example: GPIO235, Control 1 register address = 0x40081274 - * port/bank = 0x9d >> 5 = 4 - * id = 0x9d & 0x1f = 0x1d - * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274 - * - */ -#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \ - (((port << 5) + id) << 2)) - -/* MCHP implements 6 GPIO ports */ -#define MCHP_GPIO_MAX_PORT (7) - -#define DUMMY_GPIO_BANK 0 - -/* - * MEC1701 documentation GPIO numbers are octal, each control - * register is located on a 32-bit boundary. - */ -#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \ - ((gpio_num) << 2)) - -/* - * GPIO control register bit fields - */ -#define MCHP_GPIO_CTRL_PUD_BITPOS 0 -#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 -#define MCHP_GPIO_CTRL_PUD_MASK 0x03 -#define MCHP_GPIO_CTRL_PUD_NONE 0x00 -#define MCHP_GPIO_CTRL_PUD_PU 0x01 -#define MCHP_GPIO_CTRL_PUD_PD 0x02 -#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 -#define MCHP_GPIO_CTRL_PWR_BITPOS 2 -#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 -#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2) -#define MCHP_GPIO_CTRL_PWR_VTR (0x00 << 2) -#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2) -#define MCHP_GPIO_INTDET_MASK (0xF0) -#define MCHP_GPIO_INTDET_LVL_LO (0x00) -#define MCHP_GPIO_INTDET_LVL_HI (0x10) -#define MCHP_GPIO_INTDET_DISABLED (0x40) -#define MCHP_GPIO_INTDET_EDGE_RIS (0xD0) -#define MCHP_GPIO_INTDET_EDGE_FALL (0xE0) -#define MCHP_GPIO_INTDET_EDGE_BOTH (0xF0) -#define MCHP_GPIO_INTDET_EDGE_EN (1u << 7) -#define MCHP_GPIO_PUSH_PULL (0u << 8) -#define MCHP_GPIO_OPEN_DRAIN (1u << 8) -#define MCHP_GPIO_INPUT (0u << 9) -#define MCHP_GPIO_OUTPUT (1u << 9) -#define MCHP_GPIO_OUTSET_CTRL (0u << 10) -#define MCHP_GPIO_OUTSEL_PAR (1u << 10) -#define MCHP_GPIO_POLARITY_NINV (0u << 11) -#define MCHP_GPIO_POLARITY_INV (1u << 11) -#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12) -#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12) -#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) -#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) -#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) -#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) - -/* GPIO Parallel Input and Output registers. - * gpio_bank in [0, 5] - */ -#define MCHP_GPIO_PARIN(gpio_bank) REG32(MCHP_GPIO_BASE + 0x0300 +\ - ((gpio_bank) << 2)) - -#define MCHP_GPIO_PAROUT(gpio_bank) REG32(MCHP_GPIO_BASE + 0x0380 +\ - ((gpio_bank) << 2)) - -/* Timer */ -#define MCHP_TMR16_MAX (4) -#define MCHP_TMR32_MAX (2) -#define MCHP_TMR16_BASE(x) (0x40000c00 + (x) * 0x20) -#define MCHP_TMR32_BASE(x) (0x40000c80 + (x) * 0x20) - -#define MCHP_TMR16_CNT(x) REG32(MCHP_TMR16_BASE(x) + 0x0) -#define MCHP_TMR16_PRE(x) REG32(MCHP_TMR16_BASE(x) + 0x4) -#define MCHP_TMR16_STS(x) REG32(MCHP_TMR16_BASE(x) + 0x8) -#define MCHP_TMR16_IEN(x) REG32(MCHP_TMR16_BASE(x) + 0xc) -#define MCHP_TMR16_CTL(x) REG32(MCHP_TMR16_BASE(x) + 0x10) -#define MCHP_TMR32_CNT(x) REG32(MCHP_TMR32_BASE(x) + 0x0) -#define MCHP_TMR32_PRE(x) REG32(MCHP_TMR32_BASE(x) + 0x4) -#define MCHP_TMR32_STS(x) REG32(MCHP_TMR32_BASE(x) + 0x8) -#define MCHP_TMR32_IEN(x) REG32(MCHP_TMR32_BASE(x) + 0xc) -#define MCHP_TMR32_CTL(x) REG32(MCHP_TMR32_BASE(x) + 0x10) -/* 16-bit Basic Timers[0:3] = GIRQ23 bits[0:3] */ -#define MCHP_TMR16_GIRQ 23 -#define MCHP_TMR16_GIRQ_BIT(x) (1ul << (x)) -/* 32-bit Basic Timers[0:1] = GIRQ23 bits[4:5] */ -#define MCHP_TMR32_GIRQ 23 -#define MCHP_TMR32_GIRQ_BIT(x) (1ul << ((x) + 4)) - -/* RTimer */ -#define MCHP_RTMR_BASE (0x40007400) -#define MCHP_RTMR_COUNTER REG32(MCHP_RTMR_BASE + 0x00) -#define MCHP_RTMR_PRELOAD REG32(MCHP_RTMR_BASE + 0x04) -#define MCHP_RTMR_CONTROL REG8(MCHP_RTMR_BASE + 0x08) -#define MCHP_RTMR_SOFT_INTR REG8(MCHP_RTMR_BASE + 0x0c) -/* RTimer GIRQ21 bit[0] */ -#define MCHP_RTMR_GIRQ 21 -#define MCHP_RTMR_GIRQ_BIT(x) (1ul << 0) - -/* Watchdog */ -#define MCHP_WDG_BASE 0x40000000 -#define MCHP_WDG_LOAD REG16(MCHP_WDG_BASE + 0x0) -#define MCHP_WDG_CTL REG8(MCHP_WDG_BASE + 0x4) -#define MCHP_WDG_KICK REG8(MCHP_WDG_BASE + 0x8) -#define MCHP_WDG_CNT REG16(MCHP_WDG_BASE + 0xc) - - -/* VBAT */ -#define MCHP_VBAT_BASE 0x4000a400 -#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) -#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8) -#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC) -#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) -#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) -/* read 32-bit word at 32-bit offset x where 0 <= x <= 31 */ -#define MCHP_VBAT_RAM(x) REG32(MCHP_VBAT_BASE + 0x400 + ((x) * 4)) -#define MCHP_VBAT_VWIRE_BACKUP 30 - -/* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET BIT(2) -#define MCHP_VBAT_STS_RESETI BIT(4) -#define MCHP_VBAT_STS_WDT BIT(5) -#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) -#define MCHP_VBAT_STS_VBAT_RST BIT(7) -#define MCHP_VBAT_STS_ANY_RST (0xF4u) - -/* Bit definitions for MCHP_VBAT_CE */ -#define MCHP_VBAT_CE_XOSEL_BITPOS (3) -#define MCHP_VBAT_CE_XOSEL_MASK (1ul << 3) -#define MCHP_VBAT_CE_XOSEL_PAR (0ul << 3) -#define MCHP_VBAT_CE_XOSEL_SE (1ul << 3) - -#define MCHP_VBAT_CE_32K_SRC_BITPOS (2) -#define MCHP_VBAT_CE_32K_SRC_MASK (1ul << 2) -#define MCHP_VBAT_CE_32K_SRC_INT (0ul << 2) -#define MCHP_VBAT_CE_32K_SRC_CRYS (1ul << 2) - -#define MCHP_VBAT_CE_EXT_32K_BITPOS (1) -#define MCHP_VBAT_CE_EXT_32K_MASK (1ul << 1) -#define MCHP_VBAT_CE_INT_32K (0ul << 1) -#define MCHP_VBAT_CE_EXT_32K (1ul << 1) - -#define MCHP_VBAT_CE_32K_VTR_BITPOS (0) -#define MCHP_VBAT_CE_32K_VTR_MASK (1ul << 0) -#define MCHP_VBAT_CE_32K_VTR_ON (0ul << 0) -#define MCHP_VBAT_CE_32K_VTR_OFF (1ul << 0) - - -/* - * Blinking-Breathing LED - * 4 instances - */ -#define MCHP_BBLED_BASE(x) (0x4000B800 + (((x) & 0x03) << 8)) -#define MCHP_BBLEN_INSTANCES 4 - -#define MCHP_BBLED_CONFIG(x) REG32(MCHP_BBLED_BASE(x) + 0x00) -#define MCHP_BBLED_LIMITS(x) REG32(MCHP_BBLED_BASE(x) + 0x04) -#define MCHP_BBLED_LIMIT_MIN(x) REG8(MCHP_BBLED_BASE(x) + 0x04) -#define MCHP_BBLED_LIMIT_MAX(x) REG8(MCHP_BBLED_BASE(x) + 0x06) -#define MCHP_BBLED_DELAY(x) REG32(MCHP_BBLED_BASE(x) + 0x08) -#define MCHP_BBLED_UPDATE_STEP(x) REG32(MCHP_BBLED_BASE(x) + 0x0C) -#define MCHP_BBLED_UPDATE_INTV(x) REG32(MCHP_BBLED_BASE(x) + 0x10) -#define MCHP_BBLED_OUTPUT_DLY(x) REG8(MCHP_BBLED_BASE(x) + 0x14) - -/* BBLED Configuration Register */ -#define MCHP_BBLED_ASYMMETRIC (1ul << 16) -#define MCHP_BBLED_WDT_RELOAD_BITPOS (8) -#define MCHP_BBLED_WDT_RELOAD_MASK0 (0xFFul) -#define MCHP_BBLED_WDT_RELOAD_MASK (0xFFul << 8) -#define MCHP_BBLED_RESET (1ul << 7) -#define MCHP_BBLED_EN_UPDATE (1ul << 6) -#define MCHP_BBLED_PWM_SIZE_BITPOS (4) -#define MCHP_BBLED_PWM_SIZE_MASK0 (0x03ul) -#define MCHP_BBLED_PWM_SIZE_MASK (0x03ul << 4) -#define MCHP_BBLED_PWM_SIZE_6BIT (0x02ul << 4) -#define MCHP_BBLED_PWM_SIZE_7BIT (0x01ul << 4) -#define MCHP_BBLED_PWM_SIZE_8BIT (0x00ul << 4) -#define MCHP_BBLED_SYNC (1ul << 3) -#define MCHP_BBLED_CLK_48M (1ul << 2) -#define MCHP_BBLED_CLK_32K (0ul << 2) -#define MCHP_BBLED_CTRL_MASK (0x03ul) -#define MCHP_BBLED_CTRL_ALWAYS_ON (0x03ul) -#define MCHP_BBLED_CTRL_BLINK (0x02ul) -#define MCHP_BBLED_CTRL_BREATHE (0x01ul) -#define MCHP_BBLED_CTRL_OFF (0x00ul) - -/* BBLED Delay Register */ -#define MCHP_BBLED_DLY_MASK (0x0FFFul) -#define MCHP_BBLED_DLY_LO_BITPOS (0) -#define MCHP_BBLED_DLY_LO_MASK (0x0FFFul << 0) -#define MCHP_BBLED_DLY_HI_BITPOS (12) -#define MCHP_BBLED_DLY_HI_MASK (0x0FFFul << 12) - -/* - * BBLED Update Step Register - * 8 update fields numbered 0 - 7 - */ -#define MCHP_BBLED_UPD_STEP_MASK0 (0x0Ful) -#define MCHP_BBLED_UPD_STEP_MASK(u) (0x0Ful << (((u) & 0x07) + 4)) - -/* - * BBLED Update Interval Register - * 8 interval fields numbered 0 - 7 - */ -#define MCHP_BBLED_UPD_INTV_MASK0 (0x0Ful) -#define MCHP_BBLED_UPD_INTV_MASK(i) (0x0Ful << (((i) & 0x07) + 4)) - - -/* Miscellaneous firmware control fields - * scratch pad index cannot be more than 32 as - * MCHP has 128 bytes = 32 indexes of scratchpad RAM - */ -#define MCHP_IMAGETYPE_IDX 31 - - -/* LPC */ -#define MCHP_LPC_CFG_BASE 0x400f3300 -#define MCHP_LPC_ACT REG8(MCHP_LPC_CFG_BASE + 0x30) -#define MCHP_LPC_SIRQ(x) REG8(MCHP_LPC_CFG_BASE + 0x40 + (x)) -#define MCHP_LPC_CFG_BAR REG32(MCHP_LPC_CFG_BASE + 0x60) -#define MCHP_LPC_MAILBOX_BAR REG32(MCHP_LPC_CFG_BASE + 0x64) -#define MCHP_LPC_8042_BAR REG32(MCHP_LPC_CFG_BASE + 0x68) -#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C) -#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70) -#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74) -#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78) -#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C) -#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80) -#define MCHP_LPC_PORT92_BAR REG32(MCHP_LPC_CFG_BASE + 0x84) -#define MCHP_LPC_UART0_BAR REG32(MCHP_LPC_CFG_BASE + 0x88) -#define MCHP_LPC_UART1_BAR REG32(MCHP_LPC_CFG_BASE + 0x8C) -#define MCHP_LPC_EMI0_BAR REG32(MCHP_LPC_CFG_BASE + 0x90) -#define MCHP_LPC_EMI1_BAR REG32(MCHP_LPC_CFG_BASE + 0x94) -#define MCHP_LPC_EMI2_BAR REG32(MCHP_LPC_CFG_BASE + 0x98) -#define MCHP_LPC_P80DBG0_BAR REG32(MCHP_LPC_CFG_BASE + 0x9C) -#define MCHP_LPC_P80DBG1_BAR REG32(MCHP_LPC_CFG_BASE + 0xA0) -#define MCHP_LPC_RTC_BAR REG32(MCHP_LPC_CFG_BASE + 0xA4) - -#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2)) - -/* LPC BAR bits */ -#define MCHP_LPC_IO_BAR_ADDR_BITPOS (16) -#define MCHP_LPC_IO_BAR_EN (1ul << 15) - -/* LPC Generic Memory BAR's, 64-bit registers */ -#define MCHP_LPC_SRAM0_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB0) -#define MCHP_LPC_SRAM0_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xB4) -#define MCHP_LPC_SRAM1_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB8) -#define MCHP_LPC_SRAM1_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xBC) - -/* - * LPC Logical Device Memory BAR's, 48-bit registers - * Use 16-bit aligned access - */ -#define MCHP_LPC_MAILBOX_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC0) -#define MCHP_LPC_MAILBOX_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC2) -#define MCHP_LPC_MAILBOX_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xC4) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4) - - -#define MCHP_LPC_RT_BASE 0x400f3100 -#define MCHP_LPC_BUS_MONITOR REG32(MCHP_LPC_RT_BASE + 0x4) -#define MCHP_LPC_HOST_ERROR REG32(MCHP_LPC_RT_BASE + 0x8) -#define MCHP_LPC_EC_SERIRQ REG32(MCHP_LPC_RT_BASE + 0xC) -#define MCHP_LPC_EC_CLK_CTRL REG32(MCHP_LPC_RT_BASE + 0x10) -#define MCHP_LPC_BAR_INHIBIT REG32(MCHP_LPC_RT_BASE + 0x20) -#define MCHP_LPC_BAR_INIT REG32(MCHP_LPC_RT_BASE + 0x30) -#define MCHP_LPC_SRAM0_BAR REG32(MCHP_LPC_RT_BASE + 0xf8) -#define MCHP_LPC_SRAM1_BAR REG32(MCHP_LPC_RT_BASE + 0xfc) - - -/* EMI */ -#define MCHP_EMI_BASE(x) (0x400F4100 + ((x) << 10)) -#define MCHP_EMI_H2E_MBX(x) REG8(MCHP_EMI_BASE(x) + 0x0) -#define MCHP_EMI_E2H_MBX(x) REG8(MCHP_EMI_BASE(x) + 0x1) -#define MCHP_EMI_MBA0(x) REG32(MCHP_EMI_BASE(x) + 0x4) -#define MCHP_EMI_MRL0(x) REG16(MCHP_EMI_BASE(x) + 0x8) -#define MCHP_EMI_MWL0(x) REG16(MCHP_EMI_BASE(x) + 0xa) -#define MCHP_EMI_MBA1(x) REG32(MCHP_EMI_BASE(x) + 0xc) -#define MCHP_EMI_MRL1(x) REG16(MCHP_EMI_BASE(x) + 0x10) -#define MCHP_EMI_MWL1(x) REG16(MCHP_EMI_BASE(x) + 0x12) -#define MCHP_EMI_ISR(x) REG16(MCHP_EMI_BASE(x) + 0x14) -#define MCHP_EMI_HCE(x) REG16(MCHP_EMI_BASE(x) + 0x16) - -#define MCHP_EMI_RT_BASE(x) (0x400F4000 + ((x) << 10)) -#define MCHP_EMI_ISR_B0(x) REG8(MCHP_EMI_RT_BASE(x) + 0x8) -#define MCHP_EMI_ISR_B1(x) REG8(MCHP_EMI_RT_BASE(x) + 0x9) -#define MCHP_EMI_IMR_B0(x) REG8(MCHP_EMI_RT_BASE(x) + 0xa) -#define MCHP_EMI_IMR_B1(x) REG8(MCHP_EMI_RT_BASE(x) + 0xb) -/* - * EMI[0:2] on GIRQ15 bits[2:4] - */ -#define MCHP_EMI_GIRQ 15 -#define MCHP_EMI_GIRQ_BIT(x) (1ul << ((x)+2)) - - -/* Mailbox */ -#define MCHP_MBX_RT_BASE 0x400f0000 -#define MCHP_MBX_INDEX REG8(MCHP_MBX_RT_BASE + 0x0) -#define MCHP_MBX_DATA REG8(MCHP_MBX_RT_BASE + 0x1) - -#define MCHP_MBX_BASE 0x400f0100 -#define MCHP_MBX_H2E_MBX REG8(MCHP_MBX_BASE + 0x0) -#define MCHP_MBX_E2H_MBX REG8(MCHP_MBX_BASE + 0x4) -#define MCHP_MBX_ISR REG8(MCHP_MBX_BASE + 0x8) -#define MCHP_MBX_IMR REG8(MCHP_MBX_BASE + 0xc) -#define MCHP_MBX_REG(x) REG8(MCHP_MBX_BASE + 0x10 + (x)) -/* - * Mailbox on GIRQ15 bit[20] - */ -#define MCHP_MBX_GIRQ 15 -#define MCHP_MBX_GIRQ_BIT (1ul << 20) - - -/* Port80 Capture */ -#define MCHP_P80_BASE(x) (0x400f8000 + ((x) << 10)) -#define MCHP_P80_HOST_DATA(x) REG8(MCHP_P80_BASE(x)) -/* Data catpure with timestamp register */ -#define MCHP_P80_CAP(x) REG32(MCHP_P80_BASE(x) + 0x100) -#define MCHP_P80_CFG(x) REG8(MCHP_P80_BASE(x) + 0x104) -#define MCHP_P80_STS(x) REG8(MCHP_P80_BASE(x) + 0x108) -#define MCHP_P80_CNT(x) REG32(MCHP_P80_BASE(x) + 0x10c) -#define MCHP_P80_CNT_GET(x) (REG32(MCHP_P80_BASE(x) + 0x10c) >> 8) -#define MCHP_P80_CNT_SET(x, c) (REG32(MCHP_P80_BASE(x) + 0x10c) = (c << 8)) -#define MCHP_P80_ACTIVATE(x) REG8(MCHP_P80_BASE(x) + 0x330) -/* - * Port80 [0:1] GIRQ15 bits[22:23] - */ -#define MCHP_P80_GIRQ 15 -#define MCHP_P80_GIRQ_BIT(x) (1ul << ((x) + 22)) - -/* Port80 Data register bits - * bits[7:0] = data captured on Host write - * bits[31:8] = optional time stamp - */ -#define MCHP_P80_CAP_DATA_MASK 0xFFul -#define MCHP_P80_CAP_TS_BITPOS 8 -#define MCHP_P80_CAP_TS_MASK0 0xfffffful -#define MCHP_P80_CAP_TS_MASK (\ - (MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS)) - -/* Port80 Configuration register bits */ -#define MCHP_P80_FLUSH_FIFO_WO (1u << 1) -#define MCHP_P80_RESET_TIMESTAMP_WO (1u << 2) -#define MCHP_P80_TIMEBASE_BITPOS 3 -#define MCHP_P80_TIMEBASE_MASK0 0x03 -#define MCHP_P80_TIMEBASE_MASK (\ - (MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_750KHZ (\ - 0x03 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_1500KHZ (\ - 0x02 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_3MHZ (\ - 0x01 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_6MHZ (\ - 0x00 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMER_ENABLE (1u << 5) -#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6) -#define MCHP_P80_FIFO_THRHOLD_1 (0u << 6) -#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6) -#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6) -#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6) -#define MCHP_P80_FIFO_LEN 16 - -/* Port80 Status register bits, read-only */ -#define MCHP_P80_STS_NOT_EMPTY 0x01 -#define MCHP_P80_STS_OVERRUN 0x02 - -/* Port80 Count register bits */ -#define MCHP_P80_CNT_BITPOS 8 -#define MCHP_P80_CNT_MASK0 0xfffffful -#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) <<\ - (MCHP_P80_CNT_BITPOS)) - - -/* PWM */ -#define MCHP_PWM_ID_MAX (12) -#define MCHP_PWM_BASE(x) (0x40005800 + ((x) << 4)) -#define MCHP_PWM_ON(x) REG32(MCHP_PWM_BASE(x) + 0x00) -#define MCHP_PWM_OFF(x) REG32(MCHP_PWM_BASE(x) + 0x04) -#define MCHP_PWM_CFG(x) REG32(MCHP_PWM_BASE(x) + 0x08) - -/* TACH */ -#define MCHP_TACH_BASE(x) (0x40006000 + (x) << 4) -#define MCHP_TACH_CTRL(x) REG32(MCHP_TACH_BASE(x)) -#define MCHP_TACH_CTRL_LO(x) REG16(MCHP_TACH_BASE(x) + 0x00) -#define MCHP_TACH_CTRL_CNT(x) REG16(MCHP_TACH_BASE(x) + 0x02) -#define MCHP_TACH_STATUS(x) REG8(MCHP_TACH_BASE(x) + 0x04) -#define MCHP_TACH_LIMIT_HI(x) REG16(MCHP_TACH_BASE(x) + 0x08) -#define MCHP_TACH_LIMIT_LO(x) REG16(MCHP_TACH_BASE(x) + 0x0C) -/* - * TACH [2:0] GIRQ17 bits[3:1] - */ -#define MCHP_TACH_GIRQ 17 -#define MCHP_TACH_GIRQ_BIT(x) (1ul << ((x) + 1)) - - -/* ACPI */ -#define MCHP_ACPI_EC_MAX (5) -#define MCHP_ACPI_EC_BASE(x) (0x400f0800 + ((x) << 10)) -#define MCHP_ACPI_EC_EC2OS(x, y) REG8(MCHP_ACPI_EC_BASE(x) +\ - 0x100 + (y)) -#define MCHP_ACPI_EC_STATUS(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x104) -#define MCHP_ACPI_EC_BYTE_CTL(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x105) -#define MCHP_ACPI_EC_OS2EC(x, y) REG8(MCHP_ACPI_EC_BASE(x) +\ - 0x108 + (y)) - -#define MCHP_ACPI_PM_RT_BASE 0x400f1c00 -#define MCHP_ACPI_PM1_STS1 REG8(MCHP_ACPI_PM_RT_BASE + 0x0) -#define MCHP_ACPI_PM1_STS2 REG8(MCHP_ACPI_PM_RT_BASE + 0x1) -#define MCHP_ACPI_PM1_EN1 REG8(MCHP_ACPI_PM_RT_BASE + 0x2) -#define MCHP_ACPI_PM1_EN2 REG8(MCHP_ACPI_PM_RT_BASE + 0x3) -#define MCHP_ACPI_PM1_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x4) -#define MCHP_ACPI_PM1_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x5) -#define MCHP_ACPI_PM2_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x6) -#define MCHP_ACPI_PM2_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x7) -#define MCHP_ACPI_PM_EC_BASE 0x400f1d00 -#define MCHP_ACPI_PM_STS REG8(MCHP_ACPI_PM_EC_BASE + 0x10) -/* - * All ACPI EC controllers connected to GIRQ15 - * ACPI EC[0:4] IBF = GIRQ15 bits[5,7,9,11,13] - * ACPI EC[0:4] OBE = GIRQ15 bits[6,8,10,12,14] - * ACPI PM1_CTL = GIRQ15 bit[15] - * ACPI PM1_EN = GIRQ15 bit[16] - * ACPI PM1_STS = GIRQ16 bit[17] - */ -#define MCHP_ACPI_EC_GIRQ 15 -#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) (1ul << (((x)<<1) + 5)) -#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) (1ul << (((x)<<1) + 6)) -#define MCHP_ACPI_PM1_CTL_GIRQ_BIT 15 -#define MCHP_ACPI_PM1_EN_GIRQ_BIT 16 -#define MCHP_ACPI_PM1_STS_GIRQ_BIT 17 - -/* 8042 */ -#define MCHP_8042_BASE 0x400f0400 -#define MCHP_8042_OBF_CLR REG8(MCHP_8042_BASE + 0x0) -#define MCHP_8042_H2E REG8(MCHP_8042_BASE + 0x100) -#define MCHP_8042_E2H REG8(MCHP_8042_BASE + 0x100) -#define MCHP_8042_STS REG8(MCHP_8042_BASE + 0x104) -#define MCHP_8042_KB_CTRL REG8(MCHP_8042_BASE + 0x108) -#define MCHP_8042_PCOBF REG8(MCHP_8042_BASE + 0x114) -#define MCHP_8042_ACT REG8(MCHP_8042_BASE + 0x330) -/* - * 8042 [OBE:IBF] = GIRQ15 bits[18:19] - */ -#define MCHP_8042_GIRQ 15 -#define MCHP_8042_OBE_GIRQ_BIT (1ul << 18) -#define MCHP_8042_IBF_GIRQ_BIT (1ul << 19) - -/* FAN */ -#define MCHP_FAN_BASE(x) (0x4000a000 + ((x) << 7)) -#define MCHP_FAN_SETTING(x) REG8(MCHP_FAN_BASE(x) + 0x0) -#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x1) -#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2) -#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3) -#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5) -#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6) -#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7) -#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8) -#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9) -#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa) -#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc) -#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe) -#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10) -#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11) -/* - * FAN(RPM2PWM) all instances on GIRQ17 - * FAN[0:1] Fail = GIRQ17 bits[4,6] - * FAN[0:1] Stall = GIRQ17 bits[5,7] - */ -#define MCHP_FAN_GIRQ 17 -#define MCHP_FAN_FAIL_GIRQ_BIT(x) (1ul << (((x)<<1)+4)) -#define MCHP_FAN_STALL_GIRQ_BIT(x) (1ul << (((x)<<1)+5)) - - -/* I2C */ -#define MCHP_I2C_CTRL0 (0) -#define MCHP_I2C_CTRL1 (1) -#define MCHP_I2C_CTRL2 (2) -#define MCHP_I2C_CTRL3 (3) -#define MCHP_I2C_CTRL_MAX (4) - -#define MCHP_I2C_BASE(x) (0x40004000 + ((x) << 10)) -#define MCHP_I2C0_BASE 0x40004000 -#define MCHP_I2C1_BASE 0x40004400 -#define MCHP_I2C2_BASE 0x40004800 -#define MCHP_I2C3_BASE 0x40004C00 -#define MCHP_I2C_BASESEP 0x00000400 -#define MCHP_I2C_ADDR(controller, offset) \ - (offset + MCHP_I2C_BASE(controller)) - -/* - * MEC1701H 144-pin package has four I2C controller and eleven ports. - * Any port can be mapped to any I2C controller. - * This package does not implement pins for I2C01 (Port 1). - * - * I2C port values must be zero based consecutive whole numbers due to - * port number used as an index for I2C mutex array, etc. - * - * Refer to chip i2c_port_to_controller function for mapping - * of port to controller. - * - * Locking must occur by-controller (not by-port). - */ -#define MCHP_I2C_PORT_MASK 0x07FDul - -enum MCHP_i2c_port { - MCHP_I2C_PORT0 = 0, - MCHP_I2C_PORT1, /* port 1, do not use. pins not present */ - MCHP_I2C_PORT2, - MCHP_I2C_PORT3, - MCHP_I2C_PORT4, - MCHP_I2C_PORT5, - MCHP_I2C_PORT6, - MCHP_I2C_PORT7, - MCHP_I2C_PORT8, - MCHP_I2C_PORT9, - MCHP_I2C_PORT10, - - MCHP_I2C_PORT_COUNT, -}; - -#define MCHP_I2C_CTRL(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x0)) -#define MCHP_I2C_STATUS(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x0)) -#define MCHP_I2C_OWN_ADDR(ctrl) REG16(MCHP_I2C_ADDR(ctrl, 0x4)) -#define MCHP_I2C_DATA(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x8)) -#define MCHP_I2C_MASTER_CMD(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0xc)) -#define MCHP_I2C_SLAVE_CMD(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x10)) -#define MCHP_I2C_PEC(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x14)) -#define MCHP_I2C_DATA_TIM_2(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x18)) -#define MCHP_I2C_COMPLETE(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x20)) -#define MCHP_I2C_IDLE_SCALE(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x24)) -#define MCHP_I2C_CONFIG(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x28)) -#define MCHP_I2C_BUS_CLK(ctrl) REG16(MCHP_I2C_ADDR(ctrl, 0x2c)) -#define MCHP_I2C_BLK_ID(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x30)) -#define MCHP_I2C_REV(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x34)) -#define MCHP_I2C_BB_CTRL(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x38)) -#define MCHP_I2C_DATA_TIM(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x40)) -#define MCHP_I2C_TOUT_SCALE(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x44)) -#define MCHP_I2C_SLAVE_TX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x48)) -#define MCHP_I2C_SLAVE_RX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x4c)) -#define MCHP_I2C_MASTER_TX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x50)) -#define MCHP_I2C_MASTER_RX_BUF(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x54)) -#define MCHP_I2C_WAKE_STS(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x60)) -#define MCHP_I2C_WAKE_EN(ctrl) REG8(MCHP_I2C_ADDR(ctrl, 0x64)) -/* All I2C controller connected to GIRQ13 */ -#define MCHP_I2C_GIRQ 13 -/* I2C[0:3] -> GIRQ13 bits[0:3] */ -#define MCHP_I2C_GIRQ_BIT(x) (1ul << (x)) - - -/* Keyboard scan matrix */ -#define MCHP_KS_BASE 0x40009c00 -#define MCHP_KS_KSO_SEL REG32(MCHP_KS_BASE + 0x4) -#define MCHP_KS_KSI_INPUT REG32(MCHP_KS_BASE + 0x8) -#define MCHP_KS_KSI_STATUS REG32(MCHP_KS_BASE + 0xc) -#define MCHP_KS_KSI_INT_EN REG32(MCHP_KS_BASE + 0x10) -#define MCHP_KS_EXT_CTRL REG32(MCHP_KS_BASE + 0x14) -#define MCHP_KS_GIRQ 21 -#define MCHP_KS_GIRQ_BIT (1ul << 25) - - -/* ADC */ -#define MCHP_ADC_BASE 0x40007c00 -#define MCHP_ADC_CTRL REG32(MCHP_ADC_BASE + 0x0) -#define MCHP_ADC_DELAY REG32(MCHP_ADC_BASE + 0x4) -#define MCHP_ADC_STS REG32(MCHP_ADC_BASE + 0x8) -#define MCHP_ADC_SINGLE REG32(MCHP_ADC_BASE + 0xc) -#define MCHP_ADC_REPEAT REG32(MCHP_ADC_BASE + 0x10) -#define MCHP_ADC_READ(x) REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4)) - -#define MCHP_ADC_GIRQ 17 -#define MCHP_ADC_GIRQ_SINGLE_BIT (1ul << 8) -#define MCHP_ADC_GIRQ_REPEAT_BIT (1ul << 9) - - -/* Hibernation timer */ -#define MCHP_HTIMER_BASE(x) (0x40009800 + ((x) << 5)) -#define MCHP_HTIMER_PRELOAD(x) REG16(MCHP_HTIMER_BASE(x) + 0x0) -#define MCHP_HTIMER_CONTROL(x) REG16(MCHP_HTIMER_BASE(x) + 0x4) -#define MCHP_HTIMER_COUNT(x) REG16(MCHP_HTIMER_BASE(x) + 0x8) -/* All Hibernation timers connected to GIRQ21 */ -#define MCHP_HTIMER_GIRQ 21 -/* HTIMER[0:1] -> GIRQ21 bits[1:2] */ -#define MCHP_HTIMER_GIRQ_BIT(x) (1ul << ((x) + 1)) - - -/* General Purpose SPI (GP-SPI) */ -#define MCHP_SPI_BASE(port) (0x40009400 + ((port) << 7)) -#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00) -#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04) -#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08) -#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c) -#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10) -#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14) -#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18) -/* Addresses of TX/RX register used in tables */ -#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c) -#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10) -/* All GP-SPI controllers connected to GIRQ18 */ -#define MCHP_SPI_GIRQ 18 -/* - * SPI[0:1] TXBE -> GIRQ18 bits[2,4] - * SPI[0:1] RXBF -> GIRQ18 bits[3,5] - */ -#define MCHP_SPI_GIRQ_TXBE_BIT(x) (1ul << (((x) << 1) + 2)) -#define MCHP_SPI_GIRQ_RXBF_BIT(x) (1ul << (((x) << 1) + 3)) - -#define MCHP_GPSPI0_ID 0 -#define MCHP_GPSPI1_ID 1 - -#ifdef CHIP_FAMILY_MEC17XX - -/* Quad Master SPI (QMSPI) */ -#define MCHP_QMSPI0_BASE 0x40005400 -#define MCHP_QMSPI0_MODE REG32(MCHP_QMSPI0_BASE + 0x00) -#define MCHP_QMSPI0_MODE_ACT_SRST REG8(MCHP_QMSPI0_BASE + 0x00) -#define MCHP_QMSPI0_MODE_SPI_MODE REG8(MCHP_QMSPI0_BASE + 0x01) -#define MCHP_QMSPI0_MODE_FDIV REG8(MCHP_QMSPI0_BASE + 0x02) -#define MCHP_QMSPI0_CTRL REG32(MCHP_QMSPI0_BASE + 0x04) -#define MCHP_QMSPI0_EXE REG8(MCHP_QMSPI0_BASE + 0x08) -#define MCHP_QMSPI0_IFCTRL REG8(MCHP_QMSPI0_BASE + 0x0C) -#define MCHP_QMSPI0_STS REG32(MCHP_QMSPI0_BASE + 0x10) -#define MCHP_QMSPI0_BUFCNT_STS REG32(MCHP_QMSPI0_BASE + 0x14) -#define MCHP_QMSPI0_IEN REG32(MCHP_QMSPI0_BASE + 0x18) -#define MCHP_QMSPI0_BUFCNT_TRIG REG32(MCHP_QMSPI0_BASE + 0x1C) -#define MCHP_QMSPI0_TX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_RX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_DESCR(x) REG32(MCHP_QMSPI0_BASE +\ - 0x30 + ((x)<<2)) -#define MCHP_QMSPI_GIRQ 18 -#define MCHP_QMSPI_GIRQ_BIT (1ul << 1) - -#define MCHP_QMSPI_MAX_DESCR 5 - -/* Bits in MCHP_QMSPI0_MODE */ -#define MCHP_QMSPI_M_ACTIVATE (1ul << 0) -#define MCHP_QMSPI_M_SOFT_RESET (1ul << 1) -#define MCHP_QMSPI_M_SPI_MODE_MASK (0x7ul << 8) -#define MCHP_QMSPI_M_SPI_MODE0 (0x0ul << 8) -#define MCHP_QMSPI_M_SPI_MODE3 (0x3ul << 8) -#define MCHP_QMSPI_M_SPI_MODE0_48M (0x4ul << 8) -#define MCHP_QMSPI_M_SPI_MODE3_48M (0x7ul << 8) -/* - * clock divider is 8-bit field in bits[23:16] - * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256 - */ -#define MCHP_QMSPI_M_CLKDIV_BITPOS 16 -#define MCHP_QMSPI_M_CLKDIV_48M (1ul << 16) -#define MCHP_QMSPI_M_CLKDIV_24M (2ul << 16) -#define MCHP_QMSPI_M_CLKDIV_16M (3ul << 16) -#define MCHP_QMSPI_M_CLKDIV_12M (4ul << 16) -#define MCHP_QMSPI_M_CLKDIV_8M (6ul << 16) -#define MCHP_QMSPI_M_CLKDIV_6M (8ul << 16) -#define MCHP_QMSPI_M_CLKDIV_1M (48ul << 16) -#define MCHP_QMSPI_M_CLKDIV_188K (0x100ul << 16) - -/* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */ -#define MCHP_QMSPI_C_1X (0ul << 0) /* Full Duplex */ -#define MCHP_QMSPI_C_2X (1ul << 0) /* Dual IO */ -#define MCHP_QMSPI_C_4X (2ul << 0) /* Quad IO */ -#define MCHP_QMSPI_C_TX_DIS (0ul << 2) -#define MCHP_QMSPI_C_TX_DATA (1ul << 2) -#define MCHP_QMSPI_C_TX_ZEROS (2ul << 2) -#define MCHP_QMSPI_C_TX_ONES (3ul << 2) -#define MCHP_QMSPI_C_TX_DMA_DIS (0ul << 4) -#define MCHP_QMSPI_C_TX_DMA_1B (1ul << 4) -#define MCHP_QMSPI_C_TX_DMA_2B (2ul << 4) -#define MCHP_QMSPI_C_TX_DMA_4B (3ul << 4) -#define MCHP_QMSPI_C_TX_DMA_MASK (3ul << 4) -#define MCHP_QMSPI_C_RX_DIS (0ul << 6) -#define MCHP_QMSPI_C_RX_EN (1ul << 6) -#define MCHP_QMSPI_C_RX_DMA_DIS (0ul << 7) -#define MCHP_QMSPI_C_RX_DMA_1B (1ul << 7) -#define MCHP_QMSPI_C_RX_DMA_2B (2ul << 7) -#define MCHP_QMSPI_C_RX_DMA_4B (3ul << 7) -#define MCHP_QMSPI_C_RX_DMA_MASK (3ul << 7) -#define MCHP_QMSPI_C_NO_CLOSE (0ul << 9) -#define MCHP_QMSPI_C_CLOSE (1ul << 9) -#define MCHP_QMSPI_C_XFRU_BITS (0ul << 10) -#define MCHP_QMSPI_C_XFRU_1B (1ul << 10) -#define MCHP_QMSPI_C_XFRU_4B (2ul << 10) -#define MCHP_QMSPI_C_XFRU_16B (3ul << 10) -#define MCHP_QMSPI_C_XFRU_MASK (3ul << 10) -/* Control */ -#define MCHP_QMSPI_C_START_DESCR_BITPOS (12) -#define MCHP_QMSPI_C_START_DESCR_MASK (0xFul << 12) -#define MCHP_QMSPI_C_DESCR_MODE_EN (1ul << 16) -/* Descriptors, indicates the current descriptor is the last */ -#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS 12 -#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0xFul -#define MCHP_QMSPI_C_NEXT_DESCR_MASK \ - ((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12) -#define MCHP_QMSPI_C_NXTD(n) (n << 12) -#define MCHP_QMSPI_C_NEXTD0 (0ul << 12) -#define MCHP_QMSPI_C_NEXTD1 (1ul << 12) -#define MCHP_QMSPI_C_NEXTD2 (2ul << 12) -#define MCHP_QMSPI_C_NEXTD3 (3ul << 12) -#define MCHP_QMSPI_C_NEXTD4 (4ul << 12) -#define MCHP_QMSPI_C_DESCR_LAST (1ul << 16) -/* - * Total transfer length is the count in this field - * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx - */ -#define MCHP_QMSPI_C_NUM_UNITS_BITPOS (17) -#define MCHP_QMSPI_C_MAX_UNITS (0x7ffful) -#define MCHP_QMSPI_C_NUM_UNITS_MASK0 (0x7ffful) -#define MCHP_QMSPI_C_NUM_UNITS_MASK \ - ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17) - -/* Bits in MCHP_QMSPI0_EXE */ -#define MCHP_QMSPI_EXE_START BIT(0) -#define MCHP_QMSPI_EXE_STOP BIT(1) -#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) - -/* MCHP QMSPI FIFO Sizes */ -#define MCHP_QMSPI_TX_FIFO_LEN 8 -#define MCHP_QMSPI_RX_FIFO_LEN 8 - -/* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */ -#define MCHP_QMSPI_STS_DONE (1ul << 0) -#define MCHP_QMSPI_STS_DMA_DONE (1ul << 1) -#define MCHP_QMSPI_STS_TX_BUFF_ERR (1ul << 2) -#define MCHP_QMSPI_STS_RX_BUFF_ERR (1ul << 3) -#define MCHP_QMSPI_STS_PROG_ERR (1ul << 4) -#define MCHP_QMSPI_STS_TX_BUFF_FULL (1ul << 8) -#define MCHP_QMSPI_STS_TX_BUFF_EMPTY (1ul << 9) -#define MCHP_QMSPI_STS_TX_BUFF_REQ (1ul << 10) -#define MCHP_QMSPI_STS_TX_BUFF_STALL (1ul << 11) /* status only */ -#define MCHP_QMSPI_STS_RX_BUFF_FULL (1ul << 12) -#define MCHP_QMSPI_STS_RX_BUFF_EMPTY (1ul << 13) -#define MCHP_QMSPI_STS_RX_BUFF_REQ (1ul << 14) -#define MCHP_QMSPI_STS_RX_BUFF_STALL (1ul << 15) /* status only */ -#define MCHP_QMSPI_STS_ACTIVE (1ul << 16) /* status only */ - -/* Bits in MCHP_QMSPI0_BUFCNT (read-only) */ -#define MCHP_QMSPI_BUFCNT_TX_BITPOS (0) -#define MCHP_QMSPI_BUFCNT_TX_MASK (0xFFFFul) -#define MCHP_QMSPI_BUFCNT_RX_BITPOS (16) -#define MCHP_QMSPI_BUFCNT_RX_MASK (0xFFFFul << 16) - -#define MCHP_QMSPI0_ID 0 - -#endif /* #ifdef CHIP_FAMILY_MEC17XX */ - -/* eSPI */ - -/* eSPI IO Component Base Address */ -#define MCHP_ESPI_IO_BASE 0x400f3400 - -/* Peripheral Channel Registers */ -#define MCHP_ESPI_PC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x114) -#define MCHP_ESPI_PC_IEN REG32(MCHP_ESPI_IO_BASE + 0x118) -#define MCHP_ESPI_PC_BAR_INHIBIT_LO REG32(MCHP_ESPI_IO_BASE + 0x120) -#define MCHP_ESPI_PC_BAR_INHIBIT_HI REG32(MCHP_ESPI_IO_BASE + 0x124) -#define MCHP_ESPI_PC_BAR_INIT_LD_0C REG16(MCHP_ESPI_IO_BASE + 0x128) -#define MCHP_ESPI_PC_EC_IRQ REG8(MCHP_ESPI_IO_BASE + 0x12C) - -/* LTR Registers */ -#define MCHP_ESPI_IO_LTR_STATUS REG16(MCHP_ESPI_IO_BASE + 0x220) -#define MCHP_ESPI_IO_LTR_IEN REG8(MCHP_ESPI_IO_BASE + 0x224) -#define MCHP_ESPI_IO_LTR_CTRL REG16(MCHP_ESPI_IO_BASE + 0x228) -#define MCHP_ESPI_IO_LTR_MSG REG16(MCHP_ESPI_IO_BASE + 0x22C) - -/* OOB Channel Registers */ -#define MCHP_ESPI_OOB_RX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x240) -#define MCHP_ESPI_OOB_RX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x244) -#define MCHP_ESPI_OOB_TX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x248) -#define MCHP_ESPI_OOB_TX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x24C) -#define MCHP_ESPI_OOB_RX_LEN REG32(MCHP_ESPI_IO_BASE + 0x250) -#define MCHP_ESPI_OOB_TX_LEN REG32(MCHP_ESPI_IO_BASE + 0x254) -#define MCHP_ESPI_OOB_RX_CTL REG32(MCHP_ESPI_IO_BASE + 0x258) -#define MCHP_ESPI_OOB_RX_IEN REG8(MCHP_ESPI_IO_BASE + 0x25C) -#define MCHP_ESPI_OOB_RX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x260) -#define MCHP_ESPI_OOB_TX_CTL REG32(MCHP_ESPI_IO_BASE + 0x264) -#define MCHP_ESPI_OOB_TX_IEN REG8(MCHP_ESPI_IO_BASE + 0x268) -#define MCHP_ESPI_OOB_TX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x26C) - -/* Flash Channel Registers */ -#define MCHP_ESPI_FC_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x280) -#define MCHP_ESPI_FC_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x284) -#define MCHP_ESPI_FC_BUF_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x288) -#define MCHP_ESPI_FC_BUF_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x28C) -#define MCHP_ESPI_FC_XFR_LEN REG32(MCHP_ESPI_IO_BASE + 0x290) -#define MCHP_ESPI_FC_CTL REG32(MCHP_ESPI_IO_BASE + 0x294) -#define MCHP_ESPI_FC_IEN REG8(MCHP_ESPI_IO_BASE + 0x298) -#define MCHP_ESPI_FC_CONFIG REG32(MCHP_ESPI_IO_BASE + 0x29C) -#define MCHP_ESPI_FC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x2A0) - -/* VWire Channel Registers */ -#define MCHP_ESPI_VW_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2B0) - -/* Global Registers */ -/* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */ -#define MCHP_ESPI_IO_REG32_A REG32(MCHP_ESPI_IO_BASE + 0x2E0) -#define MCHP_ESPI_IO_CAP_ID REG8(MCHP_ESPI_IO_BASE + 0x2E0) -#define MCHP_ESPI_IO_CAP0 REG8(MCHP_ESPI_IO_BASE + 0x2E1) -#define MCHP_ESPI_IO_CAP1 REG8(MCHP_ESPI_IO_BASE + 0x2E2) -#define MCHP_ESPI_IO_PC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E3) -/* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */ -#define MCHP_ESPI_IO_REG32_B REG32(MCHP_ESPI_IO_BASE + 0x2E4) -#define MCHP_ESPI_IO_VW_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E4) -#define MCHP_ESPI_IO_OOB_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E5) -#define MCHP_ESPI_IO_FC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E6) -#define MCHP_ESPI_IO_PC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E7) -/* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */ -#define MCHP_ESPI_IO_REG32_C REG32(MCHP_ESPI_IO_BASE + 0x2E8) -#define MCHP_ESPI_IO_OOB_READY REG8(MCHP_ESPI_IO_BASE + 0x2E8) -#define MCHP_ESPI_IO_FC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E9) -#define MCHP_ESPI_IO_RESET_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2EA) -#define MCHP_ESPI_IO_RESET_IEN REG8(MCHP_ESPI_IO_BASE + 0x2EB) -/* 32-bit register containing PLTRST_SRC/VW_READY */ -#define MCHP_ESPI_IO_REG32_D REG32(MCHP_ESPI_IO_BASE + 0x2EC) -#define MCHP_ESPI_IO_PLTRST_SRC REG8(MCHP_ESPI_IO_BASE + 0x2EC) -#define MCHP_ESPI_IO_VW_READY REG8(MCHP_ESPI_IO_BASE + 0x2ED) - - -/* Bits in MCHP_ESPI_IO_CAP0 */ -#define MCHP_ESPI_CAP0_PC_SUPP 0x01 -#define MCHP_ESPI_CAP0_VW_SUPP 0x02 -#define MCHP_ESPI_CAP0_OOB_SUPP 0x04 -#define MCHP_ESPI_CAP0_FC_SUPP 0x08 -#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP (MCHP_ESPI_CAP0_PC_SUPP | \ - MCHP_ESPI_CAP0_VW_SUPP | \ - MCHP_ESPI_CAP0_OOB_SUPP | \ - MCHP_ESPI_CAP0_FC_SUPP) - -/* Bits in MCHP_ESPI_IO_CAP1 */ -#define MCHP_ESPI_CAP1_RW_MASK 0x37 -#define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07 -#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0x00 -#define MCHP_ESPI_CAP1_MAX_FREQ_25M 0x01 -#define MCHP_ESPI_CAP1_MAX_FREQ_33M 0x02 -#define MCHP_ESPI_CAP1_MAX_FREQ_50M 0x03 -#define MCHP_ESPI_CAP1_MAX_FREQ_66M 0x04 -#define MCHP_ESPI_CAP1_IO_BITPOS 4 -#define MCHP_ESPI_CAP1_IO_MASK0 0x03 -#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << 4) -#define MCHP_ESPI_CAP1_IO1_VAL 0x00 -#define MCHP_ESPI_CAP1_IO12_VAL 0x01 -#define MCHP_ESPI_CAP1_IO24_VAL 0x02 -#define MCHP_ESPI_CAP1_IO124_VAL 0x03 -#define MCHP_ESPI_CAP1_IO1 (0x00 << 4) -#define MCHP_ESPI_CAP1_IO12 (0x01 << 4) -#define MCHP_ESPI_CAP1_IO24 (0x02 << 4) -#define MCHP_ESPI_CAP1_IO124 (0x03 << 4) - - -/* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */ -#define MCHP_ESPI_RST_PIN_MASK 0x02 -#define MCHP_ESPI_RST_CHG_STS 1 -#define MCHP_ESPI_RST_IEN 1 - - -/* Bits in MCHP_ESPI_IO_PLTRST_SRC */ -#define MCHP_ESPI_PLTRST_SRC_VW 0 -#define MCHP_ESPI_PLTRST_SRC_PIN 1 - - -/* - * eSPI Slave Activate Register - * bit[0] = 0 de-active block is clock-gates - * bit[0] = 1 block is powered and functional - */ -#define MCHP_ESPI_ACTIVATE REG8(MCHP_ESPI_IO_BASE + 0x330) - - -/* - * IO BAR's starting at offset 0x134 - * b[16]=virtualized R/W - * b[15:14]=0 reserved RO - * b[13:8]=Logical Device Number RO - * b[7:0]=mask - */ -#define MCHP_ESPI_IO_BAR_CTL(x) REG32(MCHP_ESPI_IO_BASE + \ - 0x134 + ((x) << 2)) -/* access mask field of eSPI IO BAR Control register */ -#define MCHP_ESPI_IO_BAR_CTL_MASK(x) REG8(MCHP_ESPI_IO_BASE + \ - 0x134 + ((x) << 2)) - -/* - * IO BAR's starting at offset 0x334 - * b[31:16] = I/O address - * b[15:1]=0 reserved - * b[0] = valid - */ -#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + 0x334 + ((x) << 2)) - -#define MCHP_ESPI_IO_BAR_VALID(x) REG8(MCHP_ESPI_IO_BASE + \ - 0x334 + ((x) << 2) + 0) -#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) REG8(MCHP_ESPI_IO_BASE + \ - 0x334 + ((x) << 2) + 2) -#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) REG8(MCHP_ESPI_IO_BASE + \ - 0x334 + ((x) << 2) + 3) -#define MCHP_ESPI_IO_BAR_ADDR(x) REG16(MCHP_ESPI_IO_BASE + \ - 0x334 + ((x) << 2) + 2) - -/* Indices for use in above macros */ -#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 -#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 -#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 -#define MCHP_ESPI_IO_BAR_ID_8042 3 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8 -#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 -#define MCHP_ESPI_IO_BAR_ID_P92 0xA -#define MCHP_ESPI_IO_BAR_ID_UART0 0xB -#define MCHP_ESPI_IO_BAR_ID_UART1 0xC -#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD -#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE -#define MCHP_ESPI_IO_BAR_ID_EMI 0xF -#define MCHP_ESPI_IO_BAR_P80_0 0x10 -#define MCHP_ESPI_IO_BAR_P80_1 0x11 -#define MCHP_ESPI_IO_BAR_RTC 0x12 - -/* eSPI Serial IRQ registers */ -#define MCHP_ESPI_IO_SERIRQ_REG(x) REG8(MCHP_ESPI_IO_BASE + \ - 0x3ac + (x)) -#define MCHP_ESPI_MBOX_SIRQ0 0 -#define MCHP_ESPI_MBOX_SIRQ1 1 -#define MCHP_ESPI_8042_SIRQ0 2 -#define MCHP_ESPI_8042_SIRQ1 3 -#define MCHP_ESPI_ACPI_EC0_SIRQ 4 -#define MCHP_ESPI_ACPI_EC1_SIRQ 5 -#define MCHP_ESPI_ACPI_EC2_SIRQ 6 -#define MCHP_ESPI_ACPI_EC3_SIRQ 7 -#define MCHP_ESPI_ACPI_EC4_SIRQ 8 -#define MCHP_ESPI_UART0_SIRQ 9 -#define MCHP_ESPI_UART1_SIRQ 10 -#define MCHP_ESPI_EMI0_SIRQ0 11 -#define MCHP_ESPI_EMI0_SIRQ1 12 -#define MCHP_ESPI_EMI1_SIRQ0 13 -#define MCHP_ESPI_EMI1_SIRQ1 14 -#define MCHP_ESPI_EMI2_SIRQ0 15 -#define MCHP_ESPI_EMI2_SIRQ1 16 -#define MCHP_ESPI_RTC_SIRQ 17 -#define MCHP_ESPI_EC_SIRQ 18 - -/* eSPI Virtual Wire Error Register */ -#define MCHP_ESPI_IO_VW_ERROR REG8(MCHP_ESPI_IO_BASE + 0x3f0) - - -/* eSPI Memory Component Base Address */ -#define MCHP_ESPI_MEM_BASE 0x400f3800 - -/* - * eSPI Logical Device Memory Host BAR's to specify Host memory - * base address and valid bit. - * Each Logical Device implementing memory access has an 80-bit register. - * b[0]=Valid - * b[15:1]=0(reserved) - * b[79:16]=eSPI bus memory address(Host address space) - */ -#define MCHP_ESPI_MBAR_MBOX_ID 0 -#define MCHP_ESPI_MBAR_ACPI_EC0_ID 1 -#define MCHP_ESPI_MBAR_ACPI_EC1_ID 2 -#define MCHP_ESPI_MBAR_ACPI_EC2_ID 3 -#define MCHP_ESPI_MBAR_ACPI_EC3_ID 4 -#define MCHP_ESPI_MBAR_ACPI_EC4_ID 5 -#define MCHP_ESPI_MBAR_EMI0_ID 6 -#define MCHP_ESPI_MBAR_EMI1_ID 7 -#define MCHP_ESPI_MBAR_EMI2_ID 8 - -#define MCHP_ESPI_MBAR_VALID(x) \ - REG8(MCHP_ESPI_MEM_BASE + 0x130 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x132 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x134 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x136 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x138 + ((x) << 3) + ((x) << 1)) - -/* - * eSPI SRAM BAR's - * b[0,3,8:15] = 0 reserved - * b[2:1] = access - * b[7:4] = size - * b[79:16] = Host address - */ -#define MCHP_ESPI_SRAM_BAR_CFG(x) \ - REG8(MCHP_ESPI_MEM_BASE + 0x1ac + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x1ae + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x1b0 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x1b2 + ((x) << 3) + ((x) << 1)) - -#define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x1b4 + ((x) << 3) + ((x) << 1)) - -/* eSPI Memory Bus Master Registers */ -#define MCHP_ESPI_BM_STATUS \ - REG32(MCHP_ESPI_MEM_BASE + 0x200) -#define MCHP_ESPI_BM_IEN \ - REG32(MCHP_ESPI_MEM_BASE + 0x204) -#define MCHP_ESPI_BM_CONFIG \ - REG32(MCHP_ESPI_MEM_BASE + 0x208) -#define MCHP_ESPI_BM1_CTL \ - REG32(MCHP_ESPI_MEM_BASE + 0x210) -#define MCHP_ESPI_BM1_HOST_ADDR_LO \ - REG32(MCHP_ESPI_MEM_BASE + 0x214) -#define MCHP_ESPI_BM1_HOST_ADDR_HI \ - REG32(MCHP_ESPI_MEM_BASE + 0x218) -#define MCHP_ESPI_BM1_EC_ADDR \ - REG32(MCHP_ESPI_MEM_BASE + 0x21c) -#define MCHP_ESPI_BM2_CTL \ - REG32(MCHP_ESPI_MEM_BASE + 0x224) -#define MCHP_ESPI_BM2_HOST_ADDR_LO \ - REG32(MCHP_ESPI_MEM_BASE + 0x228) -#define MCHP_ESPI_BM2_HOST_ADDR_HI \ - REG32(MCHP_ESPI_MEM_BASE + 0x22c) -#define MCHP_ESPI_BM2_EC_ADDR \ - REG32(MCHP_ESPI_MEM_BASE + 0x230) - -/* - * eSPI Memory BAR's for Logical Devices - * b[0] = Valid - * b[2:1] = access - * b[3] = 0 reserved - * b[7:4] = size - * b[15:8] = 0 reserved - * b[47:16] = EC SRAM Address where Host address is mapped - * b[79:48] = 0 reserved - * - * BAR's start at offset 0x330 - */ -#define MCHP_ESPI_MBAR_EC_VSIZE(x) \ - REG32(MCHP_ESPI_MEM_BASE + 0x330 + ((x) << 3) + ((x) << 1)) -#define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x332 + ((x) << 3) + ((x) << 1)) -#define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x334 + ((x) << 3) + ((x) << 1)) -#define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + 0x336 + ((x) << 3) + ((x) << 1)) - -/* eSPI Virtual Wire Component Base Address */ -#define MCHP_ESPI_VW_BASE 0x400f9c00 - -#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE) -#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul) - -#define MCHP_ESPI_MSVW_LEN 12 -#define MCHP_ESPI_SMVW_LEN 8 - -#define MCHP_ESPI_MSVW_ADDR(n) ((MCHP_ESPI_MSVW_BASE) + \ - ((n) * (MCHP_ESPI_MSVW_LEN))) - -#define MCHP_ESPI_MSVW_MTOS_BITPOS 4 - -#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO 0 -#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI 1 -#define MCHP_ESPI_MSVW_IRQSEL_DISABLED 4 -#define MCHP_ESPI_MSVW_IRQSEL_RISING 0x0d -#define MCHP_ESPI_MSVW_IRQSEL_FALLING 0x0e -#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES 0x0f - - - -/* - * Mapping of eSPI Master Host VWire group indices to - * MCHP eSPI Master to Slave 96-bit VWire registers. - * MSVW_xy where xy = PCH VWire number. - * Each PCH VWire number controls 4 virtual wires. - */ -#define MSVW_H02 0 -#define MSVW_H03 1 -#define MSVW_H07 2 -#define MSVW_H41 3 -#define MSVW_H42 4 -#define MSVW_H43 5 -#define MSVW_H44 6 -#define MSVW_H47 7 -#define MSVW_H4A 8 -#define MSVW_HSPARE0 9 -#define MSVW_HSPARE1 10 -#define MSVW_MAX 11 - - -/* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */ -#define MSVW(id, w) REG32(MCHP_ESPI_MSVW_BASE + ((id) << 3) + \ - ((id << 2)) + (((w) & 0x03) << 2)) - -/* Access index value in byte 0 */ -#define MCHP_ESPI_VW_M2S_INDEX(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) << 3) + ((id) << 2)) - -/* - * Access MTOS_SOURCE and MTOS_STATE in byte 1 - * MTOS_SOURCE = b[1:0] specifies reset source - * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event - */ -#define MCHP_ESPI_VW_M2S_MTOS(id) \ - REG8(MCHP_ESPI_VW_BASE + 1 + ((id) << 3) + ((id) << 2)) - -/* - * Access Index, MTOS Source, and MTOS State as 16-bit quantity. - * Index in b[7:0] - * MTOS Source in b[9:8] - * MTOS State in b[15:12] - */ -#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \ - REG16(MCHP_ESPI_VW_BASE + ((id) << 3) + ((id) << 2)) - -/* Access SRCn IRQ Select bit fields */ -#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \ - (REG8(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2))) - -#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \ - (REG8(MCHP_ESPI_VW_BASE + 5 + ((id) << 3) + ((id) << 2))) - -#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \ - (REG8(MCHP_ESPI_VW_BASE + 6 + ((id) << 3) + ((id) << 2))) - -#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \ - (REG8(MCHP_ESPI_VW_BASE + 7 + ((id) << 3) + ((id) << 2))) - -#define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \ - REG8(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2) + \ - ((src) & 0x03)) - -#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \ - (REG32(MCHP_ESPI_VW_BASE + 4 + ((id) << 3) + ((id) << 2))) - -/* Access individual source bits */ -#define MCHP_ESPI_VW_M2S_SRC0(id) \ - REG8(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((id) << 2)) - -#define MCHP_ESPI_VW_M2S_SRC1(id) \ - REG8(MCHP_ESPI_VW_BASE + 9 + ((id) << 3) + ((id) << 2)) - -#define MCHP_ESPI_VW_M2S_SRC2(id) \ - REG8(MCHP_ESPI_VW_BASE + 10 + ((id) << 3) + ((id) << 2)) - -#define MCHP_ESPI_VW_M2S_SRC3(id) \ - REG8(MCHP_ESPI_VW_BASE + 11 + ((id) << 3) + ((id) << 2)) - -/* - * Access all four Source bits as 32-bit value, Source bits are located - * at bits[0, 8, 16, 24] of 32-bit word. - */ -#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \ - REG32(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((id) << 2)) - -/* - * Access an individual Source bit as byte where - * bit[0] contains the source bit. - */ -#define MCHP_ESPI_VW_M2S_SRC(id, src) \ - REG8(MCHP_ESPI_VW_BASE + 8 + ((id) << 3) + ((src) & 0x03)) - - - -/* - * Indices of Slave to Master Virtual Wire registers. - * Registers are 64-bit. - * Host chipset groups VWires into groups of 4 with - * a spec. defined index. - * SMVW_Ixy where xy = eSPI Master defined index. - * MCHP maps Host indices into its Slave to Master - * 64-bit registers. - */ -#define SMVW_H04 0 -#define SMVW_H05 1 -#define SMVW_H06 2 -#define SMVW_H40 3 -#define SMVW_H45 4 -#define SMVW_H46 5 -#define SMVW_HSPARE6 6 -#define SMVW_HSPARE7 7 -#define SMVW_HSPARE8 8 -#define SMVW_HSPARE9 9 -#define SMVW_HSPARE10 10 -#define SMVW_MAX 11 - - -/* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */ -#define SMVW(id, w) REG32(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3) + \ - (((w) & 0x01) << 2)) - -/* Access Index in b[7:0] of byte 0 */ -#define MCHP_ESPI_VW_S2M_INDEX(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3)) - -/* Access STOM_SOURCE and STOM_STATE in byte 1 - * STOM_SOURCE = b[1:0] - * STOM_STATE = b[7:4] - */ -#define MCHP_ESPI_VW_S2M_STOM(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x201 + ((id) << 3)) - -/* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0] - * Index = b[7:0] - * STOM_SOURCE = b[9:8] - * STOM_STATE = [15:12] - */ -#define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \ - REG16(MCHP_ESPI_VW_BASE + 0x200 + ((id) << 3)) - -/* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */ -#define MCHP_ESPI_VW_S2M_CHANGE(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x202 + ((id) << 3)) - -/* Access individual SRC bits - * bit[0] = SRCn - */ -#define MCHP_ESPI_VW_S2M_SRC0(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3)) - -#define MCHP_ESPI_VW_S2M_SRC1(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x205 + ((id) << 3)) - -#define MCHP_ESPI_VW_S2M_SRC2(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x206 + ((id) << 3)) - -#define MCHP_ESPI_VW_S2M_SRC3(id) \ - REG8(MCHP_ESPI_VW_BASE + 0x206 + ((id) << 3)) - -/* - * Access specified source bit as byte read/write. - * Source bit is in bit[0] of byte. - */ -#define MCHP_ESPI_VW_S2M_SRC(id, src) \ - REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3) + ((src) & 0x03)) - - -/* Access SRC[0:3] as 32-bit word - * SRC0 = b[0] - * SRC1 = b[8] - * SRC2 = b[16] - * SRC3 = b[24] - */ -#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \ - REG32(MCHP_ESPI_VW_BASE + 0x204 + ((id) << 3)) - - -/* - * eSPI RESET, channel enables and operations except Master-to-Slave - * WWires are all on GIRQ19 - */ -#define MCHP_ESPI_GIRQ 19 -#define MCHP_ESPI_PC_GIRQ_BIT (1ul << 0) -#define MCHP_ESPI_BM1_GIRQ_BIT (1ul << 1) -#define MCHP_ESPI_BM2_GIRQ_BIT (1ul << 2) -#define MCHP_ESPI_LTR_GIRQ_BIT (1ul << 3) -#define MCHP_ESPI_OOB_TX_GIRQ_BIT (1ul << 4) -#define MCHP_ESPI_OOB_RX_GIRQ_BIT (1ul << 5) -#define MCHP_ESPI_FC_GIRQ_BIT (1ul << 6) -#define MCHP_ESPI_RESET_GIRQ_BIT (1ul << 7) -#define MCHP_ESPI_VW_EN_GIRQ_BIT (1ul << 8) - -/* - * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 - */ -#define MCHP_ESPI_MSVW_0_6_GIRQ 24 -#define MCHP_ESPI_MSVW_7_10_GIRQ 25 -/* - * Four source bits, SRC[0:3] per Master-to-Slave register - * v = MSVW [0:10] - * n = VWire SRC bit = [0:3] - */ -#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0)) - -#define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \ - (((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n)))) - - - -/* DMA */ -#define MCHP_DMA_BASE 0x40002400 -#define MCHP_DMA_CH_OFS 0x40 -#define MCHP_DMA_CH_OFS_BITPOS 6 -#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS) - -#define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00) -#define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04) -#define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08) - -/* DMA Channel Registers */ -#define MCHP_DMA_CH_ACT(n) \ - REG8(MCHP_DMA_CH_BASE + ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_MEM_START(n) \ - REG32(MCHP_DMA_CH_BASE + 0x04 + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_MEM_END(n) \ - REG32(MCHP_DMA_CH_BASE + 0x08 + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_DEV_ADDR(n) \ - REG32(MCHP_DMA_CH_BASE + 0x0c + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_CTRL(n) \ - REG32(MCHP_DMA_CH_BASE + 0x10 + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_ISTS(n) \ - REG8(MCHP_DMA_CH_BASE + 0x14 + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_IEN(n) \ - REG8(MCHP_DMA_CH_BASE + 0x18 + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -#define MCHP_DMA_CH_FSM_RO(n) \ - REG16(MCHP_DMA_CH_BASE + 0x1c + \ - ((n) << MCHP_DMA_CH_OFS_BITPOS)) - -/* - * DMA Channel 0 implements CRC-32 feature - */ -#define MCHP_DMA_CH0_CRC32_EN REG8(MCHP_DMA_CH_BASE + 0x20) -#define MCHP_DMA_CH0_CRC32_DATA REG32(MCHP_DMA_CH_BASE + 0x24) -#define MCHP_DMA_CH0_CRC32_POST_STS REG8(MCHP_DMA_CH_BASE + 0x28) - -/* - * DMA Channel 1 implements memory fill feature - */ -#define MCHP_DMA_CH1_FILL_EN \ - REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20) -#define MCHP_DMA_CH1_FILL_DATA \ - REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24) - - -/* - * Available DMA channels. - * - * On MCHP, any DMA channel may serve any device. Since we have - * 14 channels and 14 devices, we make each channel dedicated to the - * device of the same number. - */ -enum dma_channel { - /* Channel numbers */ - MCHP_DMAC_I2C0_SLAVE = 0, - MCHP_DMAC_I2C0_MASTER = 1, - MCHP_DMAC_I2C1_SLAVE = 2, - MCHP_DMAC_I2C1_MASTER = 3, - MCHP_DMAC_I2C2_SLAVE = 4, - MCHP_DMAC_I2C2_MASTER = 5, - MCHP_DMAC_I2C3_SLAVE = 6, - MCHP_DMAC_I2C3_MASTER = 7, - MCHP_DMAC_SPI0_TX = 8, - MCHP_DMAC_SPI0_RX = 9, - MCHP_DMAC_SPI1_TX = 10, - MCHP_DMAC_SPI1_RX = 11, - MCHP_DMAC_QMSPI0_TX = 12, - MCHP_DMAC_QMSPI0_RX = 13, - /* Channel count */ - MCHP_DMAC_COUNT = 14, -}; - - -/* Bits for DMA Main Control */ -#define MCHP_DMA_MAIN_CTRL_ACT BIT(0) -#define MCHP_DMA_MAIN_CTRL_SRST BIT(1) - -/* Bits for DMA channel regs */ -#define MCHP_DMA_ACT_EN BIT(0) -/* DMA Channel Control */ -#define MCHP_DMA_ABORT BIT(25) -#define MCHP_DMA_SW_GO BIT(24) -#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20) -#define MCHP_DMA_XFER_SIZE(x) ((x) << 20) -#define MCHP_DMA_DIS_HW_FLOW BIT(19) -#define MCHP_DMA_INC_DEV BIT(17) -#define MCHP_DMA_INC_MEM BIT(16) -#define MCHP_DMA_DEV(x) ((x) << 9) -#define MCHP_DMA_DEV_MASK0 (0x7f) -#define MCHP_DMA_DEV_MASK (0x7f << 9) -#define MCHP_DMA_TO_DEV BIT(8) -#define MCHP_DMA_DONE BIT(2) -#define MCHP_DMA_RUN BIT(0) -/* DMA Channel Status */ -#define MCHP_DMA_STS_ALU_DONE BIT(3) -#define MCHP_DMA_STS_DONE BIT(2) -#define MCHP_DMA_STS_HWFL_ERR BIT(1) -#define MCHP_DMA_STS_BUS_ERR BIT(0) - -/* - * Peripheral device DMA Device ID's for bits [15:9] - * in DMA channel control register. - */ -#define MCHP_DMA_I2C0_SLV_REQ_ID 0 -#define MCHP_DMA_I2C0_MTR_REQ_ID 1 -#define MCHP_DMA_I2C1_SLV_REQ_ID 2 -#define MCHP_DMA_I2C1_MTR_REQ_ID 3 -#define MCHP_DMA_I2C2_SLV_REQ_ID 4 -#define MCHP_DMA_I2C2_MTR_REQ_ID 5 -#define MCHP_DMA_I2C3_SLV_REQ_ID 6 -#define MCHP_DMA_I2C3_MTR_REQ_ID 7 -#define MCHP_DMA_GPSPI0_TX_REQ_ID 8 -#define MCHP_DMA_GPSPI0_RX_REQ_ID 9 -#define MCHP_DMA_GPSPI1_TX_REQ_ID 10 -#define MCHP_DMA_GPSPI1_RX_REQ_ID 11 -#define MCHP_DMA_QMSPI0_TX_REQ_ID 12 -#define MCHP_DMA_QMSPI0_RX_REQ_ID 13 - -/* - * Required structure typedef for common/dma.h interface - * !!! checkpatch.pl will not like this !!! - */ - -/* Registers for a single channel of the DMA controller */ -struct MCHP_dma_chan { - uint32_t act; /* Activate */ - uint32_t mem_start; /* Memory start address */ - uint32_t mem_end; /* Memory end address */ - uint32_t dev; /* Device address */ - uint32_t ctrl; /* Control */ - uint32_t int_status; /* Interrupt status */ - uint32_t int_enabled; /* Interrupt enabled */ - uint32_t chfsm; /* channel fsm read-only */ - uint32_t alu_en; /* channels 0 & 1 only */ - uint32_t alu_data; /* channels 0 & 1 only */ - uint32_t alu_sts; /* channel 0 only */ - uint32_t alu_ro; /* channel 0 only */ - uint32_t rsvd[4]; /* 0x30 - 0x3F */ -}; - -/* Common code and header file must use this */ -typedef struct MCHP_dma_chan dma_chan_t; - -/* - * Hardware delay register. - * Write of 0 <= n <= 31 will stall the Cortex-M4 - * for n+1 microseconds. Interrupts will not be - * serviced during the delay period. Reads have - * no effect. - */ -#define MCHP_USEC_DELAY_REG_ADDR (0x10000000) -#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x)) - -/* IRQ Numbers */ -#ifdef CHIP_FAMILY - -#ifdef CHIP_FAMILY_MEC17XX - -#define MCHP_IRQ_GIRQ8 0 -#define MCHP_IRQ_GIRQ9 1 -#define MCHP_IRQ_GIRQ10 2 -#define MCHP_IRQ_GIRQ11 3 -#define MCHP_IRQ_GIRQ12 4 -#define MCHP_IRQ_GIRQ13 5 -#define MCHP_IRQ_GIRQ14 6 -#define MCHP_IRQ_GIRQ15 7 -#define MCHP_IRQ_GIRQ16 8 -#define MCHP_IRQ_GIRQ17 9 -#define MCHP_IRQ_GIRQ18 10 -#define MCHP_IRQ_GIRQ19 11 -#define MCHP_IRQ_GIRQ20 12 -#define MCHP_IRQ_GIRQ21 13 -/* - * GIRQ22 is not connected to NVIC, it wakes peripheral - * subsystem but not ARM core. - */ -#define MCHP_IRQ_GIRQ23 14 -#define MCHP_IRQ_GIRQ24 15 -#define MCHP_IRQ_GIRQ25 16 -#define MCHP_IRQ_GIRQ26 17 -/* 18 - 19 Not connected */ -#define MCHP_IRQ_I2C_0 20 -#define MCHP_IRQ_I2C_1 21 -#define MCHP_IRQ_I2C_2 22 -#define MCHP_IRQ_I2C_3 23 -#define MCHP_IRQ_DMA_0 24 -#define MCHP_IRQ_DMA_1 25 -#define MCHP_IRQ_DMA_2 26 -#define MCHP_IRQ_DMA_3 27 -#define MCHP_IRQ_DMA_4 28 -#define MCHP_IRQ_DMA_5 29 -#define MCHP_IRQ_DMA_6 30 -#define MCHP_IRQ_DMA_7 31 -#define MCHP_IRQ_DMA_8 32 -#define MCHP_IRQ_DMA_9 33 -#define MCHP_IRQ_DMA_10 34 -#define MCHP_IRQ_DMA_11 35 -#define MCHP_IRQ_DMA_12 36 -#define MCHP_IRQ_DMA_13 37 -/* 38 - 39 Not connected */ -#define MCHP_IRQ_UART0 40 -#define MCHP_IRQ_UART1 41 -#define MCHP_IRQ_EMI0 42 -#define MCHP_IRQ_EMI1 43 -#define MCHP_IRQ_EMI2 44 -#define MCHP_IRQ_ACPIEC0_IBF 45 -#define MCHP_IRQ_ACPIEC0_OBE 46 -#define MCHP_IRQ_ACPIEC1_IBF 47 -#define MCHP_IRQ_ACPIEC1_OBE 48 -#define MCHP_IRQ_ACPIEC2_IBF 49 -#define MCHP_IRQ_ACPIEC2_OBE 50 -#define MCHP_IRQ_ACPIEC3_IBF 51 -#define MCHP_IRQ_ACPIEC3_OBE 52 -#define MCHP_IRQ_ACPIEC4_IBF 53 -#define MCHP_IRQ_ACPIEC4_OBE 54 -#define MCHP_IRQ_ACPIPM1_CTL 55 -#define MCHP_IRQ_ACPIPM1_EN 56 -#define MCHP_IRQ_ACPIPM1_STS 57 -#define MCHP_IRQ_8042EM_OBE 58 -#define MCHP_IRQ_8042EM_IBF 59 -#define MCHP_IRQ_MAILBOX_DATA 60 -/* 61 Not connected */ -#define MCHP_IRQ_PORT80DBG0 62 -#define MCHP_IRQ_PORT80DBG1 63 -/* 64 Not connected */ -#define MCHP_IRQ_PKE_ERR 65 -#define MCHP_IRQ_PKE_END 66 -#define MCHP_IRQ_NDRNG 67 -#define MCHP_IRQ_AES 68 -#define MCHP_IRQ_HASH 69 -#define MCHP_IRQ_PECI_HOST 70 -#define MCHP_IRQ_TACH_0 71 -#define MCHP_IRQ_TACH_1 72 -#define MCHP_IRQ_TACH_2 73 -#define MCHP_IRQ_FAN0_FAIL 74 -#define MCHP_IRQ_FAN0_STALL 75 -#define MCHP_IRQ_FAN1_FAIL 76 -#define MCHP_IRQ_FAN1_STALL 77 -#define MCHP_IRQ_ADC_SNGL 78 -#define MCHP_IRQ_ADC_RPT 79 -#define MCHP_IRQ_RCID0 80 -#define MCHP_IRQ_RCID1 81 -#define MCHP_IRQ_RCID2 82 -#define MCHP_IRQ_LED0_WDT 83 -#define MCHP_IRQ_LED1_WDT 84 -#define MCHP_IRQ_LED2_WDT 85 -#define MCHP_IRQ_LED3_WDT 86 -#define MCHP_IRQ_PHOT 87 -#define MCHP_IRQ_PWRGRD0 88 -#define MCHP_IRQ_PWRGRD1 89 -#define MCHP_IRQ_LPC 90 -#define MCHP_IRQ_QMSPI0 91 -#define MCHP_IRQ_SPI0_TX 92 -#define MCHP_IRQ_SPI0_RX 93 -#define MCHP_IRQ_SPI1_TX 94 -#define MCHP_IRQ_SPI1_RX 95 -#define MCHP_IRQ_BCM0_ERR 96 -#define MCHP_IRQ_BCM0_BUSY 97 -#define MCHP_IRQ_BCM1_ERR 98 -#define MCHP_IRQ_BCM1_BUSY 99 -#define MCHP_IRQ_PS2_0 100 -#define MCHP_IRQ_PS2_1 101 -#define MCHP_IRQ_PS2_2 102 -#define MCHP_IRQ_ESPI_PC 103 -#define MCHP_IRQ_ESPI_BM1 104 -#define MCHP_IRQ_ESPI_BM2 105 -#define MCHP_IRQ_ESPI_LTR 106 -#define MCHP_IRQ_ESPI_OOB_UP 107 -#define MCHP_IRQ_ESPI_OOB_DN 108 -#define MCHP_IRQ_ESPI_FC 109 -#define MCHP_IRQ_ESPI_RESET 110 -#define MCHP_IRQ_RTOS_TIMER 111 -#define MCHP_IRQ_HTIMER0 112 -#define MCHP_IRQ_HTIMER1 113 -#define MCHP_IRQ_WEEK_ALARM 114 -#define MCHP_IRQ_SUBWEEK 115 -#define MCHP_IRQ_WEEK_SEC 116 -#define MCHP_IRQ_WEEK_SUBSEC 117 -#define MCHP_IRQ_WEEK_SYSPWR 118 -#define MCHP_IRQ_RTC 119 -#define MCHP_IRQ_RTC_ALARM 120 -#define MCHP_IRQ_VCI_OVRD_IN 121 -#define MCHP_IRQ_VCI_IN0 122 -#define MCHP_IRQ_VCI_IN1 123 -#define MCHP_IRQ_VCI_IN2 124 -#define MCHP_IRQ_VCI_IN3 125 -#define MCHP_IRQ_VCI_IN4 126 -#define MCHP_IRQ_VCI_IN5 127 -#define MCHP_IRQ_VCI_IN6 128 -#define MCHP_IRQ_PS20A_WAKE 129 -#define MCHP_IRQ_PS20B_WAKE 130 -#define MCHP_IRQ_PS21A_WAKE 131 -#define MCHP_IRQ_PS21B_WAKE 132 -#define MCHP_IRQ_PS2_2_WAKE 133 -#define MCHP_IRQ_ENVMON 134 -#define MCHP_IRQ_KSC_INT 135 -#define MCHP_IRQ_TIMER16_0 136 -#define MCHP_IRQ_TIMER16_1 137 -#define MCHP_IRQ_TIMER16_2 138 -#define MCHP_IRQ_TIMER16_3 139 -#define MCHP_IRQ_TIMER32_0 140 -#define MCHP_IRQ_TIMER32_1 141 -#define MCHP_IRQ_CNTR_TM0 142 -#define MCHP_IRQ_CNTR_TM1 143 -#define MCHP_IRQ_CNTR_TM2 144 -#define MCHP_IRQ_CNTR_TM3 145 -#define MCHP_IRQ_CCT_TMR 146 -#define MCHP_IRQ_CCT_CAP0 147 -#define MCHP_IRQ_CCT_CAP1 148 -#define MCHP_IRQ_CCT_CAP2 149 -#define MCHP_IRQ_CCT_CAP3 150 -#define MCHP_IRQ_CCT_CAP4 151 -#define MCHP_IRQ_CCT_CAP5 152 -#define MCHP_IRQ_CCT_CMP0 153 -#define MCHP_IRQ_CCT_CMP1 154 -#define MCHP_IRQ_EEPROM 155 -#define MCHP_IRQ_ESPI_VW_EN 156 - -#define MCHP_IRQ_MAX 157 - -#else -#error "BUILD ERROR: CHIP_FAMILY_MEC17XX not defined!" -#endif /* #ifdef CHIP_FAMILY_MEC17XX */ - -#else -#error "BUILD ERROR: CHIP_FAMILY not defined!" -#endif /* #ifdef CHIP_FAMILY */ - -/* Wake pin definitions, defined at board-level */ -extern const enum gpio_signal hibernate_wake_pins[]; -extern const int hibernate_wake_pins_used; - - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c deleted file mode 100644 index 2d5a7e9a3f..0000000000 --- a/chip/mchp/spi.c +++ /dev/null @@ -1,297 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* QMSPI master module for MCHP MEC family */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "timer.h" -#include "util.h" -#include "hooks.h" -#include "task.h" -#include "spi_chip.h" -#include "qmspi_chip.h" -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) -#include "gpspi_chip.h" -#endif -#include "tfdp_chip.h" - -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) -#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 - - - -static const struct dma_option spi_rx_option[] = { - { - MCHP_DMAC_QMSPI0_RX, - (void *)(MCHP_QMSPI0_RX_FIFO_ADDR), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) -#if CONFIG_MCHP_GPSPI & 0x01 - { - MCHP_DMAC_SPI0_RX, - (void *)&MCHP_SPI_RD(0), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#endif -#if CONFIG_MCHP_GPSPI & 0x02 - { - MCHP_DMAC_SPI1_RX, - (void *)&MCHP_SPI_RD(1), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#endif -#endif -}; - -static const struct dma_option spi_tx_option[] = { - { - MCHP_DMAC_QMSPI0_TX, - (void *)(MCHP_QMSPI0_TX_FIFO_ADDR), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) -#if CONFIG_MCHP_GPSPI & 0x01 - { - MCHP_DMAC_SPI0_TX, - (void *)&MCHP_SPI_TD(0), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#endif -#if CONFIG_MCHP_GPSPI & 0x02 - { - MCHP_DMAC_SPI1_TX, - (void *)&MCHP_SPI_TD(1), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, -#endif -#endif -}; - -/* only regular image needs mutex, LFW does not have scheduling */ -#ifndef LFW -static struct mutex spi_mutex[ARRAY_SIZE(spi_rx_option)]; - -/* - * Acquire mutex for specified SPI controller/port. - * Note if mutex is owned by another task this routine - * will block until mutex is released. - */ -static void spi_mutex_lock(uint8_t hw_port) -{ - uint32_t n; - - n = 0; -#ifdef CONFIG_MCHP_GPSPI - if (hw_port & 0xF0) { -#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03 - n = (hw_port & 0x0F) + 1; -#else - n = 1; -#endif - } -#endif - mutex_lock(&spi_mutex[n]); -} - -/* - * Release mutex for specified SPI controller/port. - */ -static void spi_mutex_unlock(uint8_t hw_port) -{ - uint32_t n; - - n = 0; -#ifdef CONFIG_MCHP_GPSPI - if (hw_port & 0xF0) { -#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03 - n = (hw_port & 0x0F) + 1; -#else - n = 1; -#endif - } -#endif - mutex_unlock(&spi_mutex[n]); -} -#endif /* #ifndef LFW */ - -/* - * Public SPI interface - */ - -const void *spi_dma_option(const struct spi_device_t *spi_device, - int is_tx) -{ - uint32_t n; - - if (spi_device == NULL) - return NULL; - - n = 0; -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) - if (spi_device->port & 0xF0) { -#if (CONFIG_MCHP_GPSPI & 0x03) == 0x03 - n = (spi_device->port & 0x0F) + 1; -#else - n = 1; -#endif - } -#endif - - if (is_tx) - return &spi_tx_option[n]; - else - return &spi_rx_option[n]; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rc; - - if (spi_device == NULL) - return EC_ERROR_INVAL; - - switch (spi_device->port) { -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) - case GPSPI0_PORT: - case GPSPI1_PORT: - rc = gpspi_transaction_async(spi_device, txdata, - txlen, rxdata, rxlen); - break; -#endif - case QMSPI0_PORT: - rc = qmspi_transaction_async(spi_device, txdata, - txlen, rxdata, rxlen); - break; - default: - rc = EC_ERROR_INVAL; - } - - return rc; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int rc; - - if (spi_device == NULL) - return EC_ERROR_INVAL; - - switch (spi_device->port) { -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) - case GPSPI0_PORT: - case GPSPI1_PORT: - rc = gpspi_transaction_flush(spi_device); - break; -#endif - case QMSPI0_PORT: - rc = qmspi_transaction_flush(spi_device); - break; - default: - rc = EC_ERROR_INVAL; - } - - return rc; -} - -/* Wait for async response received but do not de-assert chip select */ -int spi_transaction_wait(const struct spi_device_t *spi_device) -{ - int rc; - - if (spi_device == NULL) - return EC_ERROR_INVAL; - - switch (spi_device->port) { -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) -#ifndef LFW - case GPSPI0_PORT: - case GPSPI1_PORT: - rc = gpspi_transaction_wait(spi_device); - break; -#endif -#endif - case QMSPI0_PORT: - rc = qmspi_transaction_wait(spi_device); - break; - default: - rc = EC_ERROR_INVAL; - } - - return rc; -} - -/* - * called from common/spi_flash.c - * For tranfers reading less than the size of QMSPI RX FIFO call - * a routine where reads use FIFO only no DMA. - * GP-SPI only has a one byte RX FIFO but small data transfers will be OK - * without the overhead of DMA setup. - */ -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rc; - - if (spi_device == NULL) - return EC_ERROR_PARAM1; - -#ifndef LFW - spi_mutex_lock(spi_device->port); -#endif - - rc = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - if (rc == EC_SUCCESS) - rc = spi_transaction_flush(spi_device); - -#ifndef LFW - spi_mutex_unlock(spi_device->port); -#endif - - return rc; -} - -/** - * Enable SPI port and associated controller - * - * @param port Zero based index into spi_device an array of - * struct spi_device_t - * @param enable - * @return EC_SUCCESS or EC_ERROR_INVAL if port is unrecognized - * @note called from common/spi_flash.c - * - * spi_devices[].port is defined as - * bits[3:0] = controller instance - * bits[7:4] = controller family 0 = QMSPI, 1 = GPSPI - */ -int spi_enable(int port, int enable) -{ - int rc; - uint8_t hw_port; - - rc = EC_ERROR_INVAL; - if (port < spi_devices_used) { - hw_port = spi_devices[port].port; - if ((hw_port & 0xF0) == QMSPI_CLASS) - rc = qmspi_enable(hw_port, enable); -#if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) - if ((hw_port & 0xF0) == GPSPI_CLASS) - rc = gpspi_enable(hw_port, enable); -#endif - } - - return rc; -} diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h deleted file mode 100644 index 75973e4a78..0000000000 --- a/chip/mchp/spi_chip.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MCHP MEC processor - */ -/** @file qmpis_chip.h - *MCHP MEC Quad SPI Master - */ -/** @defgroup MCHP MEC qmspi - */ - -#ifndef _SPI_CHIP_H -#define _SPI_CHIP_H - -#include <stdint.h> -#include <stddef.h> - -/* struct spi_device_t */ -#include "spi.h" - -#define SPI_DMA_OPTION_RD 0 -#define SPI_DMA_OPTION_WR 1 - -/* - * bits[3:0] = controller instance - * bits[7:4] = controller family - * 0 = QMSPI, 1 = GPSPI - */ -#define QMSPI0_PORT 0x00 -#define GPSPI0_PORT 0x10 -#define GPSPI1_PORT 0x11 - - -#define QMSPI_CLASS0 0 -#define GPSPI_CLASS0 1 - -#define QMSPI_CLASS (0 << 4) -#define GPSPI_CLASS BIT(4) - -#define QMSPI_CTRL0 0 -#define GPSPI_CTRL0 0 -#define GPSPI_CTRL1 1 - -/* - * Encode zero based controller class and instance values - * in port value of spi_device_t. - */ -#define SPI_CTRL_ID(c, i) (((c & 0xf) << 4) + (i & 0xf)) - -/* - * helper to return pointer to QMSPI or GPSPI struct dma_option - */ -const void *spi_dma_option(const struct spi_device_t *spi_device, - int is_tx); - -#endif /* #ifndef _QMSPI_CHIP_H */ -/** @} - */ - diff --git a/chip/mchp/system.c b/chip/mchp/system.c deleted file mode 100644 index c19db25759..0000000000 --- a/chip/mchp/system.c +++ /dev/null @@ -1,475 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : MCHP hardware specific implementation */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "gpio.h" -#include "host_command.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "hooks.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "spi.h" -#include "clock_chip.h" -#include "lpc_chip.h" -#include "tfdp_chip.h" - - -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - - -/* Indices for hibernate data registers (RAM backed by VBAT) */ -enum hibdata_index { - HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ - HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ - HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ - HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ -}; - -static void check_reset_cause(void) -{ - uint32_t status = MCHP_VBAT_STS; - uint32_t flags = 0; - uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & - (MCHP_PWR_RST_STS_VTR | - MCHP_PWR_RST_STS_VBAT); - - trace12(0, MEC, 0, - "check_reset_cause: VBAT_PFR = 0x%08X PCR PWRST = 0x%08X", - status, rst_sts); - - /* Clear the reset causes now that we've read them */ - MCHP_VBAT_STS |= status; - MCHP_PCR_PWR_RST_STS |= rst_sts; - - trace0(0, MEC, 0, "check_reset_cause: after clear"); - trace11(0, MEC, 0, " VBAT_PFR = 0x%08X", MCHP_VBAT_STS); - trace11(0, MEC, 0, " PCR PWRST = 0x%08X", MCHP_PCR_PWR_RST_STS); - - /* - * BIT[6] determine VTR reset - */ - if (rst_sts & MCHP_PWR_RST_STS_VTR) - flags |= EC_RESET_FLAG_RESET_PIN; - - - flags |= MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); - MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; - - if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) - flags |= EC_RESET_FLAG_WATCHDOG; - - trace11(0, MEC, 0, "check_reset_cause: EC reset flags = 0x%08x", flags); - - system_set_reset_flags(flags); -} - -int system_is_reboot_warm(void) -{ - uint32_t reset_flags; - /* - * Check reset cause here, - * gpio_pre_init is executed faster than system_pre_init - */ - check_reset_cause(); - reset_flags = system_get_reset_flags(); - - if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT)) - return 0; - else - return 1; -} - -/* - * Sleep unused blocks to reduce power. - * Drivers/modules will unsleep their blocks. - * Keep sleep enables cleared for required blocks: - * ECIA, PMC, CPU, ECS and optionally JTAG. - * SLEEP_ALL feature will set these upon sleep entry. - * Based on CONFIG_CHIPSET_DEBUG enable or disable JTAG. - * JTAG mode (4-pin or 2-pin SWD + 1-pin SWV) was set - * by Boot-ROM. We can override Boot-ROM JTAG mode - * using - * CONFIG_MCHP_JTAG_MODE - */ -static void chip_periph_sleep_control(void) -{ - uint32_t d; - - d = MCHP_PCR_SLP_EN0_SLEEP; -#ifdef CONFIG_CHIPSET_DEBUG - d &= ~(MCHP_PCR_SLP_EN0_JTAG); -#ifdef CONFIG_MCHP_JTAG_MODE - MCHP_EC_JTAG_EN = CONFIG_MCHP_JTAG_MODE; -#else - MCHP_EC_JTAG_EN |= 0x01; -#endif -#else - MCHP_EC_JTAG_EN &= ~0x01; -#endif - MCHP_PCR_SLP_EN0 = d; - MCHP_PCR_SLP_EN1 = MCHP_PCR_SLP_EN1_UNUSED_BLOCKS; - MCHP_PCR_SLP_EN2 = MCHP_PCR_SLP_EN2_SLEEP; - MCHP_PCR_SLP_EN3 = MCHP_PCR_SLP_EN3_SLEEP; - MCHP_PCR_SLP_EN4 = MCHP_PCR_SLP_EN4_SLEEP; -} - -#ifdef CONFIG_CHIP_PRE_INIT -void chip_pre_init(void) -{ -#ifdef CONFIG_MCHP_TFDP - uint8_t imgtype; -#endif - chip_periph_sleep_control(); - -#ifdef CONFIG_MCHP_TFDP - /* - * MCHP Enable TFDP for fast debug messages - * If not defined then traceN() and TRACEN() macros are empty - */ - tfdp_power(1); - tfdp_enable(1, 1); - imgtype = MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX); - CPRINTS("chip_pre_init: Image type = 0x%02x", imgtype); - trace1(0, MEC, 0, - "chip_pre_init: Image type = 0x%02x", imgtype); - - trace11(0, MEC, 0, - "chip_pre_init: MCHP_VBAT_STS = 0x%0x", - MCHP_VBAT_STS); - trace11(0, MEC, 0, - "chip_pre_init: MCHP_PCR_PWR_RST_STS = 0x%0x", - MCHP_VBAT_STS); -#endif -} -#endif - -void system_pre_init(void) -{ - /* - * Make sure AHB Error capture is enabled. - * Signals bus fault to Cortex-M4 core if an address presented - * to AHB is not claimed by any HW block. - */ - MCHP_EC_AHB_ERR = 0; /* write any value to clear */ - MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */ - -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18; -#endif - -#ifndef CONFIG_CHIP_PRE_INIT - chip_periph_sleep_control(); -#endif - - /* Enable direct NVIC */ - MCHP_EC_INT_CTRL |= 1; - - /* Disable ARM TRACE debug port */ - MCHP_EC_TRACE_EN &= ~1; - - /* - * Enable aggregated only interrupt GIRQ's - * Make sure direct mode interrupt sources aggregated outputs - * are not enabled. - * Aggregated only GIRQ's 8,9,10,11,12,22,24,25,26 - * Direct GIRQ's = 13,14,15,16,17,18,19,21,23 - * These bits only need to be touched again on RESET_SYS. - * NOTE: GIRQ22 wake for AHB peripherals not processor. - */ - MCHP_INT_BLK_DIS = 0xfffffffful; - MCHP_INT_BLK_EN = (0x1Ful << 8) + (0x07ul << 24); - - spi_enable(CONFIG_SPI_FLASH_PORT, 1); -} - -void chip_save_reset_flags(uint32_t flags) -{ - MCHP_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags; -} - -void __attribute__((noreturn)) _system_reset(int flags, - int wake_from_hibernate) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - trace12(0, MEC, 0, - "_system_reset: flags=0x%08X wake_from_hibernate=%d", - flags, wake_from_hibernate); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - if (wake_from_hibernate) - save_flags |= EC_RESET_FLAG_HIBERNATE; - else if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - else - save_flags |= EC_RESET_FLAG_SOFT; - - chip_save_reset_flags(save_flags); - - trace11(0, MEC, 0, "_system_reset: save_flags=0x%08X", save_flags); - - /* - * Trigger chip reset - */ -#if defined(CONFIG_CHIPSET_DEBUG) -#else - MCHP_PCR_SYS_RST |= MCHP_PCR_SYS_SOFT_RESET; -#endif - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -void system_reset(int flags) -{ - _system_reset(flags, 0); -} - -const char *system_get_chip_vendor(void) -{ - return "mchp"; -} - -/* - * MEC1701H Chip ID = 0x2D - * Rev = 0x82 - */ -const char *system_get_chip_name(void) -{ - switch (MCHP_CHIP_DEV_ID) { - case 0x2D: - return "mec1701"; - default: - return "unknown"; - } -} - -static char to_hex(int x) -{ - if (x >= 0 && x <= 9) - return '0' + x; - return 'a' + x - 10; -} - -const char *system_get_chip_revision(void) -{ - static char buf[3]; - uint8_t rev = MCHP_CHIP_DEV_REV; - - buf[0] = to_hex(rev / 16); - buf[1] = to_hex(rev & 0xf); - buf[2] = '\0'; - return buf; -} - -static int bbram_idx_lookup(enum system_bbram_idx idx) -{ - switch (idx) { - case SYSTEM_BBRAM_IDX_PD0: - return HIBDATA_INDEX_PD0; - case SYSTEM_BBRAM_IDX_PD1: - return HIBDATA_INDEX_PD1; - case SYSTEM_BBRAM_IDX_PD2: - return HIBDATA_INDEX_PD2; - default: - return 1; - } -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - *value = MCHP_VBAT_RAM(hibdata); - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - MCHP_VBAT_RAM(hibdata) = value; - return EC_SUCCESS; -} - -int system_set_scratchpad(uint32_t value) -{ - MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value; - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - return MCHP_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD); -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* Disable interrupts */ - interrupt_disable(); - for (i = 0; i < MCHP_IRQ_MAX; ++i) { - task_disable_irq(i); - task_clear_pending_irq(i); - } - - for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) { - MCHP_INT_DISABLE(i) = 0xffffffff; - MCHP_INT_SOURCE(i) = 0xffffffff; - } - - /* Disable UART */ - MCHP_UART_ACT(0) &= ~0x1; -#ifdef CONFIG_HOSTCMD_ESPI - MCHP_ESPI_ACTIVATE &= ~0x01; -#else - MCHP_LPC_ACT &= ~0x1; -#endif - /* Disable JTAG */ - MCHP_EC_JTAG_EN &= ~1; - - /* Stop watchdog */ - MCHP_WDG_CTL &= ~1; - - /* Stop timers */ - MCHP_TMR32_CTL(0) &= ~1; - MCHP_TMR32_CTL(1) &= ~1; - for (i = 0; i < MCHP_TMR16_MAX; i++) - MCHP_TMR16_CTL(i) &= ~1; - - /* Power down ADC */ - /* - * If ADC is in middle of acquisition it will continue until finished - */ - MCHP_ADC_CTRL &= ~1; - - /* Disable blocks */ - MCHP_PCR_SLOW_CLK_CTL &= ~(MCHP_PCR_SLOW_CLK_CTL_MASK); - - /* Setup GPIOs for hibernate */ - if (board_hibernate_late) - board_hibernate_late(); - - if (hibernate_wake_pins_used > 0) { - for (i = 0; i < hibernate_wake_pins_used; ++i) { - const enum gpio_signal pin = hibernate_wake_pins[i]; - - gpio_reset(pin); - gpio_enable_interrupt(pin); - } - - interrupt_enable(); - task_enable_irq(MCHP_IRQ_GIRQ8); - task_enable_irq(MCHP_IRQ_GIRQ9); - task_enable_irq(MCHP_IRQ_GIRQ10); - task_enable_irq(MCHP_IRQ_GIRQ11); - task_enable_irq(MCHP_IRQ_GIRQ12); - task_enable_irq(MCHP_IRQ_GIRQ26); - } - - if (seconds || microseconds) { - htimer_init(); - system_set_htimer_alarm(seconds, microseconds); - interrupt_enable(); - } else { - /* Not using hibernation timer. Disable 32KHz clock */ - MCHP_VBAT_CE &= ~0x2; - } - - /* - * Set sleep state - * arm sleep state to trigger on next WFI - */ - CPU_SCB_SYSCTRL |= 0x4; - MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_HEAVY; - MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL; - - asm("dsb"); - asm("wfi"); - asm("isb"); - asm("nop"); - - /* Use 48MHz clock to speed through wake-up */ - MCHP_PCR_PROC_CLK_CTL = 1; - - trace0(0, SYS, 0, "Wake from hibernate: _system_reset[0,1]"); - - /* Reboot */ - _system_reset(0, 1); - - /* We should never get here. */ - while (1) - ; -} - -void htimer_interrupt(void) -{ - /* Time to wake up */ -} -DECLARE_IRQ(MCHP_IRQ_HTIMER0, htimer_interrupt, 1); - -enum system_image_copy_t system_get_shrspi_image_copy(void) -{ - return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX); -} - -uint32_t system_get_lfw_address(void) -{ - uint32_t * const lfw_vector = - (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE; - - return *(lfw_vector + 1); -} - -void system_set_image_copy(enum system_image_copy_t copy) -{ - MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == SYSTEM_IMAGE_RW) ? - SYSTEM_IMAGE_RW : SYSTEM_IMAGE_RO; -} - diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c deleted file mode 100644 index b4368b46a8..0000000000 --- a/chip/mchp/tfdp.c +++ /dev/null @@ -1,499 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** @file tfdp.c - *MCHP Trace FIFO Data Port hardware access - */ -/** @defgroup MCHP Peripherals TFDP - * @{ - */ - -#include "common.h" -#include "gpio.h" -#include "registers.h" -#include "tfdp_chip.h" - -#ifdef CONFIG_MCHP_TFDP - - -static uint32_t get_disable_intr(void) -{ - uint32_t m; - - __asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m)); - - return m; -} - -static void restore_intr(uint32_t m) -{ - if (!m) - __asm__ __volatile__ ("cpsie i" : : : "memory"); -} - - -/** - * tfdp_power - Gate clocks On/Off to TFDP block when idle - * - * @param pwr_on (0=Gate clocks when idle), (1=Do not gate - * clocks when idle) - */ -void tfdp_power(uint8_t pwr_on) -{ - if (pwr_on) - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_TFDP); - else - MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP); -} - - -/** - * tfdp_enable - Init Trace FIFO Data Port - * @param uint8_t non-zero=enable TFDP, false=disable TFDP - * @param uint8_t non-zero=change TFDP pin configuration. - * If TFDP is enabled then GPIO170/171 set to Alt. Func. 1 - * Else GPIO170/171 set to GPIO input, internal pull-up enabled. - * @note - - */ -#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) -#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) - -void tfdp_enable(uint8_t en, uint8_t pin_cfg) -{ - if (en) { - MCHP_TFDP_CTRL = 0x01u; - if (pin_cfg) - gpio_config_module(MODULE_TFDP, 1); - } else { - MCHP_TFDP_CTRL = 0x00u; - if (pin_cfg) - gpio_config_module(MODULE_TFDP, 0); - } -} /* end tfdp_enable() */ - - -/** - * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first - * over TFDP. - * - * @param nbr 16-bit trace number - * @param b unused - * - * @return uint8_t always TRUE - * @note Function implements critical section. - * Uses tool kit __disable_irq()/__enable_irq() pair which may use - * priviledged Cortex-Mx instructions. - */ -void TFDPTrace0(uint16_t nbr) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first - * and 16-bit data lsb first over TFDP. - * - * @param nbr 16-bit trace number - * @param b unused - * @param uint32_t p1 16-bit data1 in b[15:0] - * - * @return uint8_t always TRUE - * @note Function implements critical section. - * Uses tool kit __disable_irq()/__enable_irq() pair which may use - * priviledged Cortex-Mx instructions. - */ -void TFDPTrace1(uint16_t nbr, uint32_t p1) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first - * and two 16-bit data parameters lsb first over TFDP. - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 16-bit data1 in b[15:0] - * @param uint32_t p2 16-bit data2 in b[15:0] - * - * @return uint8_t always TRUE - * @note Uses tool kit functions to save/disable/restore - * interrupts for critical section. These may use - * priviledged instructions. - */ -void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first - * and three 16-bit data parameters lsb first over TFDP. - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 16-bit data1 in b[15:0] - * @param uint32_t p2 16-bit data2 in b[15:0] - * @param uint32_t p3 16-bit data3 in b[15:0] - * - * @return uint8_t always TRUE - * @note Uses tool kit functions to save/disable/restore - * interrupts for critical section. These may use - * priviledged instructions. - */ -void TFDPTrace3(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p3; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 8); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first - * and four 16-bit data parameters lsb first over TFDP. - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 16-bit data1 in b[15:0] - * @param uint32_t p2 16-bit data2 in b[15:0] - * @param uint32_t p3 16-bit data3 in b[15:0] - * @param uint32_t p4 16-bit data4 in b[15:0] - * - * @return uint8_t always TRUE - * @note Uses tool kit functions to save/disable/restore - * interrupts for critical section. These may use - * priviledged instructions. - */ -void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p3; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p4; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p4 >> 8); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TFDPTrace11 - Transmit one 32-bit data item over TFDP - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 32-bit data to be transmitted - * - */ -void TFDPTrace11(uint16_t nbr, uint32_t p1) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 24); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - - -/** - * TFDPTrace12 - Transmit two 32-bit data items over TFDP - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 32-bit data1 to be transmitted - * @param uint32_t p2 32-bit data2 to be transmitted - * - */ -void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 24); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - -/** - * TFDPTrace13 - Transmit three 32-bit data items over TFDP - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 32-bit data1 to be transmitted - * @param uint32_t p2 32-bit data2 to be transmitted - * @param uint32_t p3 32-bit data3 to be transmitted - * - */ -void TFDPTrace13(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p3; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 24); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - -/** - * TFDPTrace14 - Transmit four 32-bit data items over TFDP - * - * @param nbr trace number - * @param b unused - * @param uint32_t p1 32-bit data1 to be transmitted - * @param uint32_t p2 32-bit data2 to be transmitted - * @param uint32_t p3 32-bit data3 to be transmitted - * @param uint32_t p4 32-bit data4 to be transmitted - */ -void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4) -{ -#ifdef MCHP_TRACE_MASK_IRQ - uint32_t prim; - - prim = get_disable_intr(); -#endif - - MCHP_TFDP_DATA = (TFDP_FRAME_START); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)nbr; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(nbr >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p1; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p1 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p2; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p2 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p3; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p3 >> 24); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)p4; - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p4 >> 8); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p4 >> 16); - TFDP_DELAY(); - MCHP_TFDP_DATA = (uint8_t)(p4 >> 24); - TFDP_DELAY(); - -#ifdef MCHP_TRACE_MASK_IRQ - restore_intr(prim); -#endif -} - -#endif /* #ifdef CONFIG_MCHP_TFDP */ - - -/* end tfdp.c */ -/** @} - */ diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h deleted file mode 100644 index 64d4d0b77e..0000000000 --- a/chip/mchp/tfdp_chip.h +++ /dev/null @@ -1,131 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/** @file tfdp_chip.h - *MCHP MEC TFDP Peripheral Library API - */ -/** @defgroup MCHP MEC Peripherals Trace - */ - -#ifndef _TFDP_CHIP_H -#define _TFDP_CHIP_H - -#include <stdint.h> - - -#ifdef CONFIG_MCHP_TFDP - -#undef TRACE0 -#undef TRACE1 -#undef TRACE2 -#undef TRACE3 -#undef TRACE4 -#undef TRACE11 -#undef TRACE12 -#undef TRACE13 -#undef TRACE14 -#undef trace0 -#undef trace1 -#undef trace2 -#undef trace3 -#undef trace4 -#undef trace11 -#undef trace12 -#undef trace13 -#undef trace14 - -#define MCHP_TFDP_BASE_ADDR (0x40008c00ul) - -#define TFDP_FRAME_START (0xFD) - -#define TFDP_POWER_ON (1u) -#define TFDP_POWER_OFF (0u) - -#define TFDP_ENABLE (1u) -#define TFDP_DISABLE (0u) -#define TFDP_CFG_PINS (1u) -#define TFDP_NO_CFG_PINS (0u) - -#define MCHP_TRACE_MASK_IRQ - -#define TFDP_DELAY() - -#ifdef __cplusplus -extern "C" { -#endif - -void tfdp_power(uint8_t pwr_on); -void tfdp_enable(uint8_t en, uint8_t pin_cfg); -void TFDPTrace0(uint16_t nbr); -void TFDPTrace1(uint16_t nbr, uint32_t p1); -void TFDPTrace2(uint16_t nbr, uint32_t p1, - uint32_t p2); -void TFDPTrace3(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3); -void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4); -void TFDPTrace11(uint16_t nbr, uint32_t p1); -void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2); -void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3); -void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4); - -#ifdef __cplusplus -} -#endif - -#define TRACE0(nbr, cat, b, str) TFDPTrace0(nbr) -#define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1) -#define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2) -#define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3) -#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \ - p3, p4) -#define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1) -#define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2) -#define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3) -#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \ - TFDPTrace14(nbr, p1, p2, p3, p4) - - -#else /* #ifdef MCHP_TRACE */ - -/* !!! To prevent compiler warnings of unused parameters, - * when trace is disabled by TRGEN source processing, - * you can either: - * 1. Disable compiler's unused parameter warning - * 2. Change these macros to write parameters to a read-only - * register. - */ -#define tfdp_power(pwr_on) -#define tfdp_enable(en, pin_cfg) -#define TRACE0(nbr, cat, b, str) -#define TRACE1(nbr, cat, b, str, p1) -#define TRACE2(nbr, cat, b, str, p1, p2) -#define TRACE3(nbr, cat, b, str, p1, p2, p3) -#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) -#define TRACE11(nbr, cat, b, str, p1) -#define TRACE12(nbr, cat, b, str, p1, p2) -#define TRACE13(nbr, cat, b, str, p1, p2, p3) -#define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) - -#endif /* #ifdef CONFIG_MCHP_TFDP */ - -/* - * Always define lower case traceN(...) as blank (fully removed) - */ -#define trace0(nbr, cat, b, str) -#define trace1(nbr, cat, b, str, p1) -#define trace2(nbr, cat, b, str, p1, p2) -#define trace3(nbr, cat, b, str, p1, p2, p3) -#define trace4(nbr, cat, b, str, p1, p2, p3, p4) -#define trace11(nbr, cat, b, str, p1) -#define trace12(nbr, cat, b, str, p1, p2) -#define trace13(nbr, cat, b, str, p1, p2, p3) -#define trace14(nbr, cat, b, str, p1, p2, p3, p4) - -#endif /* #ifndef _TFDP_CHIP_H */ -/* end tfdp_chip.h */ -/** @} - */ diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c deleted file mode 100644 index 0f8bd62db8..0000000000 --- a/chip/mchp/uart.c +++ /dev/null @@ -1,238 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for MCHP MEC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "lpc.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" -#include "tfdp_chip.h" - -#define TX_FIFO_SIZE 16 - -static int init_done; -static int tx_fifo_used; - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (MCHP_UART_IER(0) & BIT(1)) - return; - - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - - /* - * Re-enable the transmit interrupt, then forcibly trigger the - * interrupt. This works around a hardware problem with the - * UART where the FIFO only triggers the interrupt when its - * threshold is _crossed_, not just met. - */ - MCHP_UART_IER(0) |= BIT(1); - task_trigger_irq(MCHP_IRQ_UART0); -} - -void uart_tx_stop(void) -{ - MCHP_UART_IER(0) &= ~BIT(1); - - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - /* Wait for transmit FIFO empty */ - while (!(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY)) - ; -} - -int uart_tx_ready(void) -{ - /* - * We have no indication of free space in transmit FIFO. To work around - * this, we check transmit FIFO empty bit every 16 characters written. - */ - return tx_fifo_used != 0 || - (MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY); -} - -int uart_tx_in_progress(void) -{ - /* return 0: FIFO is empty, 1: FIFO NOT Empty */ - return !(MCHP_UART_LSR(0) & MCHP_LSR_TX_EMPTY); -} - -int uart_rx_available(void) -{ - return MCHP_UART_LSR(0) & BIT(0); -} - -void uart_write_char(char c) -{ - /* Wait for space in transmit FIFO. */ - while (!uart_tx_ready()) - ; - - tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE; - MCHP_UART_TB(0) = c; -} - -int uart_read_char(void) -{ - return MCHP_UART_RB(0); -} - -static void uart_clear_rx_fifo(int channel) -{ - MCHP_UART_FCR(0) = BIT(0) | BIT(1); -} - -void uart_disable_interrupt(void) -{ - task_disable_irq(MCHP_IRQ_UART0); -} - -void uart_enable_interrupt(void) -{ - task_enable_irq(MCHP_IRQ_UART0); -} - -/** - * Interrupt handler for UART. - * Lower priority below other critical ISR's. - */ -void uart_ec_interrupt(void) -{ - /* Read input FIFO until empty, then fill output FIFO */ - uart_process_input(); - /* Trace statement to provide time marker for UART output? */ - uart_process_output(); -} -DECLARE_IRQ(MCHP_IRQ_UART0, uart_ec_interrupt, 2); - -void uart_init(void) -{ - /* Clear UART PCR sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0); - - /* Set UART to reset on VCC1_RESET instead of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~BIT(0); - - /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= BIT(7); - - /* PBRG0/PBRG1 */ - MCHP_UART_PBRG0(0) = 1; - MCHP_UART_PBRG1(0) = 0; - - /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~BIT(7); - - /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MCHP_UART_FCR(0) = BIT(0); - - /* Activate UART */ - MCHP_UART_ACT(0) |= BIT(0); - - gpio_config_module(MODULE_UART, 1); - - /* - * Enable interrupts for UART0. - */ - uart_clear_rx_fifo(0); - MCHP_UART_IER(0) |= BIT(0); - MCHP_UART_MCR(0) |= BIT(3); - MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); - - task_enable_irq(MCHP_IRQ_UART0); - - init_done = 1; -} - -#ifdef CONFIG_LOW_POWER_IDLE -void uart_enter_dsleep(void) -{ - /* Disable the UART interrupt. */ - task_disable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART=13 */ - - /* - * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt - * with the flags defined in the gpio.inc file. - */ - gpio_reset(GPIO_UART0_RX); - - /* power-down/de-activate UART0 */ - MCHP_UART_ACT(0) &= ~BIT(0); - - /* clear interrupt enable for UART0 */ - MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); - - /* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */ - MCHP_INT_SOURCE(9) = BIT(5); - - /* Enable GPIO interrupts on the UART0 RX pin. */ - gpio_enable_interrupt(GPIO_UART0_RX); -} - - -void uart_exit_dsleep(void) -{ - /* - * If the UART0 RX GPIO interrupt has not fired, then no edge has been - * detected. Disable the GPIO interrupt so that switching the pin over - * to a UART pin doesn't inadvertently cause a GPIO edge interrupt. - * Note: we can't disable this interrupt if it has already fired - * because then the IRQ will not run at all. - */ - if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */ - gpio_disable_interrupt(GPIO_UART0_RX); - - /* Configure UART0 pins for use in UART peripheral. */ - gpio_config_module(MODULE_UART, 1); - - /* Clear pending interrupts on UART peripheral and enable interrupts. */ - uart_clear_rx_fifo(0); - MCHP_INT_SOURCE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); - MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); - task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */ - - /* power-up/activate UART0 */ - MCHP_UART_ACT(0) |= BIT(0); -} - -void uart_deepsleep_interrupt(enum gpio_signal signal) -{ - /* - * Activity seen on UART RX pin while UART was disabled for deep sleep. - * The console won't see that character because the UART is disabled, - * so we need to inform the clock module of UART activity ourselves. - */ - clock_refresh_console_in_use(); - - /* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */ - gpio_disable_interrupt(GPIO_UART0_RX); -} -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py deleted file mode 100755 index c7fe74d028..0000000000 --- a/chip/mchp/util/pack_ec.py +++ /dev/null @@ -1,539 +0,0 @@ -#!/usr/bin/env python2 - -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# A script to pack EC binary into SPI flash image for MEC17xx -# Based on MEC170x_ROM_Description.pdf DS00002225C (07-28-17). -from __future__ import print_function - -import argparse -import hashlib -import os -import struct -import subprocess -import tempfile -import zlib # CRC32 - -# from six import int2byte - - -# MEC1701 has 256KB SRAM from 0xE0000 - 0x120000 -# SRAM is divided into contiguous CODE & DATA -# CODE at [0xE0000, 0x117FFF] DATA at [0x118000, 0x11FFFF] -# SPI flash size for board is 512KB -# Boot-ROM TAG is located at SPI offset 0 (two 4-byte tags) -# - -LFW_SIZE = 0x1000 -LOAD_ADDR = 0x0E0000 -LOAD_ADDR_RW = 0xE1000 -HEADER_SIZE = 0x40 -SPI_CLOCK_LIST = [48, 24, 16, 12] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] - -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] - -def dummy_print(*args, **kwargs): - pass - -debug_print = dummy_print - -def Crc8(crc, data): - """Update CRC8 value.""" - data_bytes = map(lambda b: ord(b) if isinstance(b, str) else b, data) - for v in data_bytes: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 - -def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return struct.unpack('<I', s)[0] - -def GetPayloadFromOffset(payload_file, offset): - """Read payload and pad it to 64-byte aligned.""" - with open(payload_file, 'rb') as f: - f.seek(offset) - payload = bytearray(f.read()) - rem_len = len(payload) % 64 - if rem_len: - payload += '\0' * (64 - rem_len) - return payload - -def GetPayload(payload_file): - """Read payload and pad it to 64-byte aligned.""" - return GetPayloadFromOffset(payload_file, 0) - -def GetPublicKey(pem_file): - """Extract public exponent and modulus from PEM file.""" - s = subprocess.check_output(['openssl', 'rsa', '-in', pem_file, - '-text', '-noout']) - modulus_raw = [] - in_modulus = False - for line in s.split('\n'): - if line.startswith('modulus'): - in_modulus = True - elif not line.startswith(' '): - in_modulus = False - elif in_modulus: - modulus_raw.extend(line.strip().strip(':').split(':')) - if line.startswith('publicExponent'): - exp = int(line.split(' ')[1], 10) - modulus_raw.reverse() - modulus = bytearray(''.join(map(lambda x: chr(int(x, 16)), - modulus_raw[0:256]))) - return struct.pack('<Q', exp), modulus - -def GetSpiClockParameter(args): - assert args.spi_clock in SPI_CLOCK_LIST, \ - "Unsupported SPI clock speed %d MHz" % args.spi_clock - return SPI_CLOCK_LIST.index(args.spi_clock) - -def GetSpiReadCmdParameter(args): - assert args.spi_read_cmd in SPI_READ_CMD_LIST, \ - "Unsupported SPI read command 0x%x" % args.spi_read_cmd - return SPI_READ_CMD_LIST.index(args.spi_read_cmd) - -def PadZeroTo(data, size): - data.extend('\0' * (size - len(data))) - -def BuildHeader(args, payload_len, load_addr, rorofile): - # Identifier and header version - header = bytearray(['P', 'H', 'C', 'M', '\0']) - - # byte[5] - b = GetSpiClockParameter(args) - b |= (1 << 2) - header.append(b) - - # byte[6] - b = 0 - header.append(b) - - # byte[7] - header.append(GetSpiReadCmdParameter(args)) - - # bytes 0x08 - 0x0b - header.extend(struct.pack('<I', load_addr)) - # bytes 0x0c - 0x0f - header.extend(struct.pack('<I', GetEntryPoint(rorofile))) - # bytes 0x10 - 0x13 - header.append((payload_len >> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - # bytes 0x14 - 0x17 - header.extend(struct.pack('<I', args.payload_offset)) - - # bytes 0x14 - 0x3F all 0 - PadZeroTo(header, 0x40) - - # header signature is appended by the caller - - return header - - -def BuildHeader2(args, payload_len, load_addr, payload_entry): - # Identifier and header version - header = bytearray(['P', 'H', 'C', 'M', '\0']) - - # byte[5] - b = GetSpiClockParameter(args) - b |= (1 << 2) - header.append(b) - - # byte[6] - b = 0 - header.append(b) - - # byte[7] - header.append(GetSpiReadCmdParameter(args)) - - # bytes 0x08 - 0x0b - header.extend(struct.pack('<I', load_addr)) - # bytes 0x0c - 0x0f - header.extend(struct.pack('<I', payload_entry)) - # bytes 0x10 - 0x13 - header.append((payload_len >> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - # bytes 0x14 - 0x17 - header.extend(struct.pack('<I', args.payload_offset)) - - # bytes 0x14 - 0x3F all 0 - PadZeroTo(header, 0x40) - - # header signature is appended by the caller - - return header - -# -# Compute SHA-256 of data and return digest -# as a bytearray -# -def HashByteArray(data): - hasher = hashlib.sha256() - hasher.update(data) - h = hasher.digest() - bah = bytearray(h) - return bah - -# -# Return 64-byte signature of byte array data. -# Signature is SHA256 of data with 32 0 bytes appended -# -def SignByteArray(data): - debug_print("Signature is SHA-256 of data") - sigb = HashByteArray(data) - sigb.extend("\0" * 32) - return sigb - - -# MEC1701H supports two 32-bit Tags located at offsets 0x0 and 0x4 -# in the SPI flash. -# Tag format: -# bits[23:0] correspond to bits[31:8] of the Header SPI address -# Header is always on a 256-byte boundary. -# bits[31:24] = CRC8-ITU of bits[23:0]. -# Notice there is no chip-select field in the Tag both Tag's point -# to the same flash part. -# -def BuildTag(args): - tag = bytearray([(args.header_loc >> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - tag.append(Crc8(0, tag)) - return tag - -def BuildTagFromHdrAddr(header_loc): - tag = bytearray([(header_loc >> 8) & 0xff, - (header_loc >> 16) & 0xff, - (header_loc >> 24) & 0xff]) - tag.append(Crc8(0, tag)) - return tag - - -# -# Creates temporary file for read/write -# Reads binary file containing LFW image_size (loader_file) -# Writes LFW image to temporary file -# Reads RO image at beginning of rorw_file up to image_size -# (assumes RO/RW images have been padded with 0xFF -# Returns temporary file name -# -def PacklfwRoImage(rorw_file, loader_file, image_size): - """Create a temp file with the - first image_size bytes from the loader file and append bytes - from the rorw file. - return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: # read 4KB loader file - pro = fin1.read() - fo.write(pro) # write 4KB loader data to temp file - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - - fo.write(ro) - fo.close() - return fo.name - -# -# Generate a test EC_RW image of same size -# as original. -# Preserve image_data structure and fill all -# other bytes with 0xA5. -# useful for testing SPI read and EC build -# process hash generation. -# -def gen_test_ecrw(pldrw): - debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) - debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) - cookie1_pos = pldrw.find(b'\x99\x88\x77\xce') - cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4) - t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28]) - size = t[0] - debug_print("EC_RW size =", size, " = ", hex(size)) - - debug_print("Found cookie1 at ", hex(cookie1_pos)) - debug_print("Found cookie2 at ", hex(cookie2_pos)) - - if cookie1_pos > 0 and cookie2_pos > cookie1_pos: - for i in range(0, cookie1_pos): - pldrw[i] = 0xA5 - for i in range(cookie2_pos+4, len(pldrw)): - pldrw[i] = 0xA5 - - with open("ec_RW_test.bin", "wb") as fecrw: - fecrw.write(pldrw[:size]) - -def parseargs(): - rpath = os.path.dirname(os.path.relpath(__file__)) - - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in KB", - default=512) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash", - default=0x1000) - parser.add_argument("-p", "--payload_offset", type=int, - help="The offset of payload from the start of header", - default=0x80) - parser.add_argument("-r", "--rw_loc", type=int, - help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", - default=-1) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image. Default 220KB", - default=(220 * 1024)) - parser.add_argument("--test_spi", action='store_true', - help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", - default=False) - parser.add_argument("--test_ecrw", action='store_true', - help="Use fixed pattern for EC_RW but preserve image_data", - default=False) - parser.add_argument("--verbose", action='store_true', - help="Enable verbose output", - default=False) - - return parser.parse_args() - -# Debug helper routine -def dumpsects(spi_list): - debug_print("spi_list has {0} entries".format(len(spi_list))) - for s in spi_list: - debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2])) - -def printByteArrayAsHex(ba, title): - debug_print(title,"= ") - count = 0 - for b in ba: - count = count + 1 - debug_print("0x{0:02x}, ".format(b),end="") - if (count % 8) == 0: - debug_print("") - debug_print("\n") - -def print_args(args): - debug_print("parsed arguments:") - debug_print(".input = ", args.input) - debug_print(".output = ", args.output) - debug_print(".loader_file = ", args.loader_file) - debug_print(".spi_size (KB) = ", hex(args.spi_size)) - debug_print(".image_size = ", hex(args.image_size)) - debug_print(".header_loc = ", hex(args.header_loc)) - debug_print(".payload_offset = ", hex(args.payload_offset)) - if args.rw_loc < 0: - debug_print(".rw_loc = ", args.rw_loc) - else: - debug_print(".rw_loc = ", hex(args.rw_loc)) - debug_print(".spi_clock = ", args.spi_clock) - debug_print(".spi_read_cmd = ", args.spi_read_cmd) - debug_print(".test_spi = ", args.test_spi) - debug_print(".verbose = ", args.verbose) - -# -# Handle quiet mode build from Makefile -# Quiet mode when V is unset or V=0 -# Verbose mode when V=1 -# -def main(): - global debug_print - - args = parseargs() - - if args.verbose: - debug_print = print - - debug_print("Begin MEC17xx pack_ec.py script") - - - # MEC17xx maximum 192KB each for RO & RW - # mec1701 chip Makefile sets args.spi_size = 512 - # Tags at offset 0 - # - print_args(args) - - spi_size = args.spi_size * 1024 - debug_print("SPI Flash image size in bytes =", hex(spi_size)) - - # !!! IMPORTANT !!! - # These values MUST match chip/mec1701/config_flash_layout.h - # defines. - # MEC17xx Boot-ROM TAGs are at offset 0 and 4. - # lfw + EC_RO starts at beginning of second 4KB sector - # EC_RW starts at offset 0x40000 (256KB) - - spi_list = [] - - debug_print("args.input = ",args.input) - debug_print("args.loader_file = ",args.loader_file) - debug_print("args.image_size = ",hex(args.image_size)) - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - - payload = GetPayload(rorofile) - payload_len = len(payload) - # debug - debug_print("EC_LFW + EC_RO length = ",hex(payload_len)) - - # SPI image integrity test - # compute CRC32 of EC_RO except for last 4 bytes - # skip over 4KB LFW - # Store CRC32 in last 4 bytes - if args.test_spi == True: - crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)])) - crc_ofs = payload_len - 4 - debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs)) - for i in range(4): - payload[crc_ofs + i] = crc & 0xff - crc = crc >> 8 - - # Chromebooks are not using MEC BootROM ECDSA. - # We implemented the ECDSA disabled case where - # the 64-byte signature contains a SHA-256 of the binary plus - # 32 zeros bytes. - payload_signature = SignByteArray(payload) - # debug - printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature") - - # MEC17xx Header is 0x80 bytes with an 64 byte signature - # (32 byte SHA256 + 32 zero bytes) - header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile) - # debug - printByteArrayAsHex(header, "Header LFW + EC_RO") - - # MEC17xx payload ECDSA not used, 64 byte signature is - # SHA256 + 32 zero bytes - header_signature = SignByteArray(header) - # debug - printByteArrayAsHex(header_signature, "header_signature") - - tag = BuildTag(args) - # MEC17xx truncate RW length to args.image_size to not overwrite LFW - # offset may be different due to Header size and other changes - # MCHP we want to append a SHA-256 to the end of the actual payload - # to test SPI read routines. - debug_print("Call to GetPayloadFromOffset") - debug_print("args.input = ", args.input) - debug_print("args.image_size = ", hex(args.image_size)) - - payload_rw = GetPayloadFromOffset(args.input, args.image_size) - debug_print("type(payload_rw) is ", type(payload_rw)) - debug_print("len(payload_rw) is ", hex(len(payload_rw))) - - # truncate to args.image_size - rw_len = args.image_size - payload_rw = payload_rw[:rw_len] - payload_rw_len = len(payload_rw) - debug_print("Truncated size of EC_RW = ", hex(payload_rw_len)) - - payload_entry_tuple = struct.unpack_from('<I', payload_rw, 4) - debug_print("payload_entry_tuple = ", payload_entry_tuple) - - payload_entry = payload_entry_tuple[0] - debug_print("payload_entry = ", hex(payload_entry)) - - # Note: payload_rw is a bytearray therefore is mutable - if args.test_ecrw: - gen_test_ecrw(payload_rw) - - # SPI image integrity test - # compute CRC32 of EC_RW except for last 4 bytes - # Store CRC32 in last 4 bytes - if args.test_spi == True: - crc = zlib.crc32(bytes(payload_rw[:(payload_rw_len - 32)])) - crc_ofs = payload_rw_len - 4 - debug_print("EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs)) - for i in range(4): - payload_rw[crc_ofs + i] = crc & 0xff - crc = crc >> 8 - - payload_rw_sig = SignByteArray(payload_rw) - # debug - printByteArrayAsHex(payload_rw_sig, "payload_rw_sig") - - os.remove(rorofile) # clean up the temp file - - # MEC170x Boot-ROM Tags are located at SPI offset 0 - spi_list.append((0, tag, "tag")) - - spi_list.append((args.header_loc, header, "header(lwf + ro)")) - spi_list.append((args.header_loc + HEADER_SIZE, header_signature, - "header(lwf + ro) signature")) - spi_list.append((args.header_loc + args.payload_offset, payload, - "payload(lfw + ro)")) - - offset = args.header_loc + args.payload_offset + payload_len - - # No SPI Header for EC_RW as its not loaded by BootROM - spi_list.append((offset, payload_signature, - "payload(lfw_ro) signature")) - - # EC_RW location - rw_offset = int(spi_size // 2) - if args.rw_loc >= 0: - rw_offset = args.rw_loc - - debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) - - if rw_offset < offset + len(payload_signature): - print("ERROR: EC_RW overlaps EC_RO") - - spi_list.append((rw_offset, payload_rw, "payload(rw)")) - - # don't add to EC_RW. We don't know if Google will process - # EC SPI flash binary with other tools during build of - # coreboot and OS. - #offset = rw_offset + payload_rw_len - #spi_list.append((offset, payload_rw_sig, "payload(rw) signature")) - - spi_list = sorted(spi_list) - - dumpsects(spi_list) - - # - # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI. - # - with open(args.output, 'wb') as f: - debug_print("Write spi list to file", args.output) - addr = 0 - for s in spi_list: - if addr < s[0]: - debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr), - "fill with 0xff") - f.write('\xff' * (s[0] - addr)) - addr = s[0] - debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data") - - f.write(s[1]) - addr += len(s[1]) - - if addr < spi_size: - debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr), - "fill with 0xff") - f.write('\xff' * (spi_size - addr)) - - f.flush() - -if __name__ == '__main__': - main() diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c deleted file mode 100644 index 0533155e08..0000000000 --- a/chip/mchp/watchdog.c +++ /dev/null @@ -1,123 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "watchdog.h" -#include "tfdp_chip.h" - -void watchdog_reload(void) -{ - MCHP_WDG_KICK = 1; - -#ifdef CONFIG_WATCHDOG_HELP - /* Reload the auxiliary timer */ - MCHP_TMR16_CTL(0) &= ~BIT(5); - MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CTL(0) |= BIT(5); -#endif -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ -#ifdef CONFIG_WATCHDOG_HELP - uint32_t val; - - /* - * Watchdog does not warn us before expiring. Let's use a 16-bit - * timer as an auxiliary timer. - */ - - /* Clear 16-bit basic timer 0 PCR sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0); - - /* Stop the auxiliary timer if it's running */ - MCHP_TMR16_CTL(0) &= ~BIT(5); - - /* Enable auxiliary timer */ - MCHP_TMR16_CTL(0) |= BIT(0); - - val = MCHP_TMR16_CTL(0); - - /* Pre-scale = 48000 -> 1kHz -> Period = 1ms */ - val = (val & 0xffff) | (47999 << 16); - - /* No auto restart */ - val &= ~BIT(3); - - /* Count down */ - val &= ~BIT(2); - - MCHP_TMR16_CTL(0) = val; - - /* Enable interrupt from auxiliary timer */ - MCHP_TMR16_IEN(0) |= 1; - task_enable_irq(MCHP_IRQ_TIMER16_0); - MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0); - - /* Load and start the auxiliary timer */ - MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CNT(0) |= BIT(5); -#endif - - /* Clear WDT PCR sleep enable */ - MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_WDT); - - /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ - MCHP_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007; - - /* Start watchdog */ -#ifdef CONFIG_CHIPSET_DEBUG - /* WDT will not count if JTAG TRST# is pulled high by JTAG cable */ - MCHP_WDG_CTL = BIT(4) | BIT(0); -#else - MCHP_WDG_CTL |= 1; -#endif - - return EC_SUCCESS; -} - -#ifdef CONFIG_WATCHDOG_HELP -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - trace0(0, WDT, 0, "Watchdog check from 16-bit basic timer0 ISR"); - - /* Clear status */ - MCHP_TMR16_STS(0) |= 1; - /* clear aggregator status */ - MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0); - - watchdog_trace(excep_lr, excep_sp); -} - -void -IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked)); -void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* - * Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveninently saves - * R0=LR so we can pass it to task_resched_if_needed. - */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); -} - -/* - * Put the watchdog at the highest interrupt priority. - */ -const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0) - __attribute__((section(".rodata.irqprio"))) - = {MCHP_IRQ_TIMER16_0, 0}; -#endif diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c deleted file mode 100644 index fd797a7f15..0000000000 --- a/chip/mec1322/adc.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "adc_chip.h" -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* - * Conversion on a single channel takes less than 12 ms. Set timeout to - * 15 ms so that we have a 3-ms margin. - */ -#define ADC_SINGLE_READ_TIME 15000 - -struct mutex adc_lock; - -static volatile task_id_t task_waiting; - -static int start_single_and_wait(int timeout) -{ - int event; - - task_waiting = task_get_current(); - - /* Start conversion */ - MEC1322_ADC_CTRL |= BIT(1); - - /* Wait for interrupt */ - event = task_wait_event(timeout); - task_waiting = TASK_ID_INVALID; - return event != TASK_EVENT_TIMER; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - - mutex_lock(&adc_lock); - - MEC1322_ADC_SINGLE = 1 << adc->channel; - - if (start_single_and_wait(ADC_SINGLE_READ_TIME)) - value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul / - adc->factor_div + adc->shift; - else - value = ADC_READ_ERROR; - - mutex_unlock(&adc_lock); - return value; -} - -static void adc_init(void) -{ - /* Activate ADC module */ - MEC1322_ADC_CTRL |= BIT(0); - - /* Enable interrupt */ - task_waiting = TASK_ID_INVALID; - MEC1322_INT_ENABLE(17) |= BIT(10); - MEC1322_INT_BLK_EN |= BIT(17); - task_enable_irq(MEC1322_IRQ_ADC_SNGL); -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); - -void adc_interrupt(void) -{ - /* Clear interrupt status bit */ - MEC1322_ADC_CTRL |= BIT(7); - - if (task_waiting != TASK_ID_INVALID) - task_wake(task_waiting); -} -DECLARE_IRQ(MEC1322_IRQ_ADC_SNGL, adc_interrupt, 2); diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h deleted file mode 100644 index bc25344b11..0000000000 --- a/chip/mec1322/adc_chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322-specific ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - int channel; -}; - -/* - * Boards must provide this list of ADC channel definitions. This must match - * the enum adc_channel list provided by the board. - */ -extern const struct adc_t adc_channels[]; - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 1023 - -/* Just plain id mapping for code readability */ -#define MEC1322_ADC_CH(x) (x) - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk deleted file mode 100644 index 2b0c9cc229..0000000000 --- a/chip/mec1322/build.mk +++ /dev/null @@ -1,79 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# MEC1322 chip specific files build -# - -# MEC1322 SoC has a Cortex-M4 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 - -ifeq ($(CONFIG_LTO),y) -# Re-include the core's build.mk file so we can remove the lto flag. -include core/$(CORE)/build.mk -endif - -# Required chip modules -chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o -chip-$(CONFIG_ADC)+=adc.o -chip-$(CONFIG_FANS)+=fan.o -chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o -chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif -chip-$(CONFIG_DMA)+=dma.o -chip-$(CONFIG_SPI)+=spi.o - -# location of the scripts and keys used to pack the SPI flash image -SCRIPTDIR:=./chip/${CHIP}/util - -# Allow SPI size to be overridden by board specific size, default to 256KB. -CHIP_SPI_SIZE_KB?=256 - -# Commands to convert $^ to $@.tmp -cmd_obj_to_bin = $(OBJCOPY) --gap-fill=0xff -O binary $< $@.tmp1 ; \ - ${SCRIPTDIR}/pack_ec.py -o $@.tmp -i $@.tmp1 \ - --loader_file $(mec1322-lfw-flat) \ - --payload_key ${SCRIPTDIR}/rsakey_sign_payload.pem \ - --header_key ${SCRIPTDIR}/rsakey_sign_header.pem \ - --spi_size ${CHIP_SPI_SIZE_KB} \ - --image_size $(_rw_size); rm -f $@.tmp1 - -mec1322-lfw = chip/mec1322/lfw/ec_lfw -mec1322-lfw-flat = $(out)/RW/$(mec1322-lfw)-lfw.flat - -# build these specifically for lfw with -lfw suffix -objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \ - $(addprefix common/, util gpio) \ - $(addprefix chip/$(CHIP)/, spi dma gpio clock hwtimer) \ - core/$(CORE)/cpu $(mec1322-lfw)) - -# reuse version.o (and its dependencies) from main board -objs_lfw += $(out)/RW/common/version.o - -dirs-y+=chip/$(CHIP)/lfw - -# objs with -lfw suffix are to include lfw's gpio -$(out)/RW/%-lfw.o: private CC+=-I$(BDIR)/lfw -DLFW=$(EMPTY) -# Remove the lto flag for the loader. It actually causes it to bloat in size. -ifeq ($(CONFIG_LTO),y) -$(out)/RW/%-lfw.o: private CFLAGS_CPU := $(filter-out -flto, $(CFLAGS_CPU)) -endif -$(out)/RW/%-lfw.o: %.c - $(call quiet,c_to_o,CC ) - -# let lfw's elf link only with selected objects -$(out)/RW/%-lfw.elf: private objs = $(objs_lfw) -$(out)/RW/%-lfw.elf: override shlib := -$(out)/RW/%-lfw.elf: %.ld $(objs_lfw) - $(call quiet,elf,LD ) - -# final image needs lfw loader -$(out)/$(PROJECT).bin: $(mec1322-lfw-flat) diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c deleted file mode 100644 index ce07284891..0000000000 --- a/chip/mec1322/clock.c +++ /dev/null @@ -1,484 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" -#include "vboot_hash.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -#ifdef CONFIG_LOW_POWER_IDLE -/* Recovery time for HvySlp2 is 0 usec */ -#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 - -#define SET_HTIMER_DELAY_USEC 200 - -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t total_idle_dsleep_time_us; - -/* - * Fixed amount of time to keep the console in use flag true after boot in - * order to give a permanent window in which the heavy sleep mode is not used. - */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) -static int console_in_use_timeout_sec = 60; -static timestamp_t console_expire_time; -#endif /*CONFIG_LOW_POWER_IDLE */ - -static int freq = 48000000; - -void clock_wait_cycles(uint32_t cycles) -{ - asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); -} - -int clock_get_freq(void) -{ - return freq; -} - -void clock_init(void) -{ -#ifdef CONFIG_CLOCK_CRYSTAL - /* XOSEL: 0 = Parallel resonant crystal */ - MEC1322_VBAT_CE &= ~0x1; -#else - /* XOSEL: 1 = Single ended clock source */ - MEC1322_VBAT_CE |= 0x1; -#endif - - /* 32K clock enable */ - MEC1322_VBAT_CE |= 0x2; - -#ifdef CONFIG_CLOCK_CRYSTAL - /* Wait for crystal to stabilize (OSC_LOCK == 1) */ - while (!(MEC1322_PCR_CHIP_OSC_ID & 0x100)) - ; -#endif -} - -/** - * Speed through boot + vboot hash calculation, dropping our processor clock - * only after vboot hashing is completed. - */ -static void clock_turbo_disable(void); -DECLARE_DEFERRED(clock_turbo_disable); - -static void clock_turbo_disable(void) -{ -#ifdef CONFIG_VBOOT_HASH - if (vboot_hash_in_progress()) - hook_call_deferred(&clock_turbo_disable_data, 100 * MSEC); - else -#endif - /* Use 12 MHz processor clock for power savings */ - MEC1322_PCR_PROC_CLK_CTL = 4; -} -DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); - -#ifdef CONFIG_LOW_POWER_IDLE -/** - * initialization of Hibernation timer - */ -static void htimer_init(void) -{ - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ - MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ - - task_enable_irq(MEC1322_IRQ_HTIMER); -} - -/** - * Use hibernate module to set up an htimer interrupt at a given - * time from now - * - * @param seconds Number of seconds before htimer interrupt - * @param microseconds Number of microseconds before htimer interrupt - */ -static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds) -{ - if (seconds || microseconds) { - - if (seconds > 2) { - /* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */ - ASSERT(seconds <= 0xffff / 8); - MEC1322_HTIMER_CONTROL = 1; /* 0.125(=1/8) per clock */ - /* (number of counts to be loaded) - * = seconds * ( 8 clocks per second ) - * + microseconds / 125000 - * ---> (0 if (microseconds < 125000) - */ - MEC1322_HTIMER_PRELOAD = - (seconds * 8 + microseconds / 125000); - - } else { /* count up to 2 sec. */ - - MEC1322_HTIMER_CONTROL = 0; /* 30.5(= 2/61) usec */ - - /* (number of counts to be loaded) - * = (total microseconds) / 30.5; - */ - MEC1322_HTIMER_PRELOAD = - (seconds * 1000000 + microseconds) * 2 / 61; - } - } -} - -/** - * return time slept in micro-seconds - */ -static timestamp_t system_get_htimer(void) -{ - uint16_t count; - timestamp_t time; - - count = MEC1322_HTIMER_COUNT; - - - if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */ - /* 0.125 sec per count */ - time.le.lo = (uint32_t)(count * 125000); - else /* if < 2 sec */ - /* 30.5(=61/2)usec per count */ - time.le.lo = (uint32_t)(count * 61 / 2); - - time.le.hi = 0; - - return time; /* in uSec */ -} - -/** - * Disable and clear hibernation timer interrupt - */ -static void system_reset_htimer_alarm(void) -{ - MEC1322_HTIMER_PRELOAD = 0; -} - -/** - * This is mec1322 specific and equivalent to ARM Cortex's - * 'DeepSleep' via system control block register, CPU_SCB_SYSCTRL - */ -static void prepare_for_deep_sleep(void) -{ - uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN | - MEC1322_PCR_EC_SLP_EN_SLEEP; - - /* sysTick timer */ - CPU_NVIC_ST_CTRL &= ~ST_ENABLE; - CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG; - - /* Disable JTAG */ - MEC1322_EC_JTAG_EN &= ~1; - /* Power down ADC VREF, ADC_VREF overrides ADC_CTRL. */ - MEC1322_EC_ADC_VREF_PD |= 1; - - /* Stop watchdog */ - MEC1322_WDG_CTL &= ~1; - - /* Stop timers */ - MEC1322_TMR32_CTL(0) &= ~1; - MEC1322_TMR32_CTL(1) &= ~1; - MEC1322_TMR16_CTL(0) &= ~1; - - MEC1322_PCR_CHIP_SLP_EN |= 0x3; -#ifdef CONFIG_PWM - if (pwm_get_keep_awake_mask()) - ec_slp_en &= ~pwm_get_keep_awake_mask(); - else -#endif - /* Disable 100 Khz clock */ - MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; - - MEC1322_PCR_EC_SLP_EN = ec_slp_en; - MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; - MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; - -#ifndef CONFIG_POWER_S0IX - MEC1322_LPC_ACT = 0x0; -#endif - - MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ - - CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */ -} - -static void resume_from_deep_sleep(void) -{ - CPU_NVIC_ST_CTRL |= ST_TICKINT; /* SYS_TICK_INT_ENABLE */ - CPU_NVIC_ST_CTRL |= ST_ENABLE; - - MEC1322_EC_JTAG_EN = 1; - MEC1322_EC_ADC_VREF_PD &= ~1; - /* ADC_VREF_PD overrides ADC_CTRL ! */ - - /* Enable timer */ - MEC1322_TMR32_CTL(0) |= 1; - MEC1322_TMR32_CTL(1) |= 1; - MEC1322_TMR16_CTL(0) |= 1; - - /* Enable watchdog */ - MEC1322_WDG_CTL |= 1; - - MEC1322_PCR_SLOW_CLK_CTL |= 0x1e0; - MEC1322_PCR_CHIP_SLP_EN &= ~0x3; - MEC1322_PCR_EC_SLP_EN &= MEC1322_PCR_EC_SLP_EN_WAKE; - MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE; - MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE; - - MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ - -#ifndef CONFIG_POWER_S0IX - /* Enable LPC */ - MEC1322_LPC_ACT |= 1; -#endif -} - - -void clock_refresh_console_in_use(void) -{ - disable_sleep(SLEEP_MASK_CONSOLE); - - /* Set console in use expire time. */ - console_expire_time = get_time(); - console_expire_time.val += console_in_use_timeout_sec * SECOND; -} - -/** - * Low power idle task. Executed when no tasks are ready to be scheduled. - */ -void __idle(void) -{ - timestamp_t t0; - timestamp_t t1; - timestamp_t ht_t1; - uint32_t next_delay; - uint32_t max_sleep_time; - int time_for_dsleep; - int uart_ready_for_deepsleep; - - htimer_init(); /* hibernation timer initialize */ - - disable_sleep(SLEEP_MASK_CONSOLE); - console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; - - - /* - * Print when the idle task starts. This is the lowest priority task, - * so this only starts once all other tasks have gotten a chance to do - * their task inits and have gone to sleep. - */ - CPRINTS("low power idle task started"); - - while (1) { - /* Disable interrupts */ - interrupt_disable(); - - t0 = get_time(); /* uSec */ - - /* __hw_clock_event_get() is next programmed timer event */ - next_delay = __hw_clock_event_get() - t0.le.lo; - - time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC + - SET_HTIMER_DELAY_USEC); - - max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC; - - /* check if there enough time for deep sleep */ - if (DEEP_SLEEP_ALLOWED && time_for_dsleep) { - - - /* - * Check if the console use has expired and console - * sleep is masked by GPIO(UART-RX) interrupt. - */ - if ((sleep_mask & SLEEP_MASK_CONSOLE) && - t0.val > console_expire_time.val) { - /* allow console to sleep. */ - enable_sleep(SLEEP_MASK_CONSOLE); - - /* - * Wait one clock before checking if heavy sleep - * is allowed to give time for sleep mask - * to be updated. - */ - clock_wait_cycles(1); - - if (LOW_SPEED_DEEP_SLEEP_ALLOWED) - CPRINTS("Disable console in deepsleep"); - } - - - /* UART is not being used */ - uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED - && !uart_tx_in_progress() - && uart_buffer_empty(); - - /* - * Since MEC1322's heavysleep modes requires all block - * to be sleepable, UART/console's readiness is final - * decision factor of heavysleep of EC. - */ - if (uart_ready_for_deepsleep) { - - idle_dsleep_cnt++; - - /* - * config UART Rx as GPIO wakeup interrupt - * source - */ - uart_enter_dsleep(); - - /* MEC1322 specific deep-sleep mode */ - prepare_for_deep_sleep(); - - /* - * 'max_sleep_time' value should be big - * enough so that hibernation timer's interrupt - * triggers only after 'wfi' completes its - * excution. - */ - max_sleep_time -= (get_time().le.lo - t0.le.lo); - - /* setup/enable htimer wakeup interrupt */ - system_set_htimer_alarm(0, max_sleep_time); - } else { - idle_sleep_cnt++; - } - - /* Wait for interrupt: goes into deep sleep. */ - asm("wfi"); - - if (uart_ready_for_deepsleep) { - - resume_from_deep_sleep(); - - /* - * Fast forward timer according to htimer - * counter: - * Since all blocks including timers will be in - * sleep mode, timers stops except hibernate - * timer. - * And system schedule timer should be corrected - * after wakeup by either hibernate timer or - * GPIO_UART_RX interrupt. - */ - ht_t1 = system_get_htimer(); - - /* disable/clear htimer wakeup interrupt */ - system_reset_htimer_alarm(); - - t1.val = t0.val + - (uint64_t)(max_sleep_time - ht_t1.le.lo); - - force_time(t1); - - /* re-eanble UART */ - uart_exit_dsleep(); - - /* Record time spent in deep sleep. */ - total_idle_dsleep_time_us += - (uint64_t)(max_sleep_time - ht_t1.le.lo); - } - - } else { /* CPU 'Sleep' mode */ - - idle_sleep_cnt++; - - asm("wfi"); - - } - - interrupt_enable(); - } /* while(1) */ -} - -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - - ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n", - total_idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n\n", ts.val); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* defined(CONFIG_CMD_IDLE_STATS) */ - -/** - * Configure deep sleep clock settings. - */ -static int command_dsleep(int argc, char **argv) -{ - int v; - - if (argc > 1) { - if (parse_bool(argv[1], &v)) { - /* - * Force deep sleep not to use heavy sleep mode or - * allow it to use the heavy sleep mode. - */ - if (v) /* 'on' */ - disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); - else /* 'off' */ - enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); - } else { - /* Set console in use timeout. */ - char *e; - v = strtoi(argv[1], &e, 10); - if (*e) - return EC_ERROR_PARAM1; - - console_in_use_timeout_sec = v; - - /* Refresh console in use to use new timeout. */ - clock_refresh_console_in_use(); - } - } - - ccprintf("Sleep mask: %08x\n", sleep_mask); - ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | <timeout> sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep NOT to enter heavysleep mode.\nUse 'off' to " - "allow deep sleep to use heavysleep whenever conditions" - "allow.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleepmask'."); -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h deleted file mode 100644 index 414fb492bf..0000000000 --- a/chip/mec1322/config_chip.h +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 93 - -/* Use a bigger console output buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* - * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one - * additional port. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER - -#define I2C_CONTROLLER_COUNT 4 -#define I2C_PORT_COUNT 5 - -/****************************************************************************/ -/* Memory mapping */ - -/* - * The memory region for RAM is actually 0x00100000-0x00120000. - * RAM for RO/RW = 20k - * CODE size of the Loader is 3k - * As per the above configuartion the upper 20k - * is used to store data.The rest is for code. - * the lower 107K is flash[ 3k Loader and 104k RO/RW], - * and the higher 20K is RAM shared by loader and RO/RW. - */ - -/****************************************************************************/ -/* Define our RAM layout. */ - -#define CONFIG_MEC_SRAM_BASE_START 0x00100000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 -#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_MEC_SRAM_BASE_START) - -/* 20k RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00005000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_RAM_SIZE) - -/* System stack size */ -#define CONFIG_STACK_SIZE 1024 - -/* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 640 - -#define CHARGER_TASK_STACK_SIZE 640 -#define HOOKS_TASK_STACK_SIZE 640 -#define CONSOLE_TASK_STACK_SIZE 640 -#define HOST_CMD_TASK_STACK_SIZE 640 - -/* - * TODO: Large stack consumption - * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 - */ -#define PD_TASK_STACK_SIZE 800 - -/* Default task stack size */ -#define TASK_STACK_SIZE 512 - -/****************************************************************************/ -/* Define our flash layout. */ - -/* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 -/* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 -/* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 - -/* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 - -/* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 - -#include "config_flash_layout.h" - -/****************************************************************************/ -/* Customize the build */ -/* Optional features present on this chip */ -#if 0 -#define CONFIG_ADC -#define CONFIG_PECI -#define CONFIG_MPU -#endif -#define CONFIG_DMA -#define CONFIG_HOSTCMD_LPC -#define CONFIG_SPI -#define CONFIG_SWITCH - -#define GPIO_PIN(index) (index / 10), (1 << (index % 10)) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h deleted file mode 100644 index 3ab249668d..0000000000 --- a/chip/mec1322/config_flash_layout.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H -#define __CROS_EC_CONFIG_FLASH_LAYOUT_H - -/* - * mec1322 flash layout: - * - Non memory-mapped, external SPI. - * - RW image at the beginning of writable region. - * - Bootloader at the beginning of protected region, followed by RO image. - * - Loader + (RO | RW) loaded into program memory. - */ - -/* Non-memmapped, external SPI */ -#define CONFIG_EXTERNAL_STORAGE -#undef CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE -#define CONFIG_SPI_FLASH - -/* EC region of SPI resides at end of ROM, protected region follows writable */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x20000) -#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 - -/* Loader resides at the beginning of program memory */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 - -/* Write protect Loader and RO Image */ -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -/* - * Write protect 128k section of 256k physical flash which contains loader - * and RO Images. - */ -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* - * RO / RW images follow the loader in program memory. Either RO or RW - * image will be loaded -- both cannot be loaded at the same time. - */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE - -/* WP region consists of second half of SPI, and begins with the boot header */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 - -/* Loader / lfw image immediately follows the boot header on SPI */ -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) - -/* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) - -/* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 - -#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c deleted file mode 100644 index a6c6fed5ad..0000000000 --- a/chip/mec1322/dma.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) - -mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel) -{ - mec1322_dma_regs_t *dma = MEC1322_DMA_REGS; - - return &dma->chan[channel]; -} - -void dma_disable(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - - if (chan->ctrl & BIT(0)) - chan->ctrl &= ~BIT(0); - - if (chan->act == 1) - chan->act = 0; -} - -void dma_disable_all(void) -{ - int ch; - mec1322_dma_regs_t *dma; - - for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) { - mec1322_dma_chan_t *chan = dma_get_channel(ch); - /* Abort any current transfer. */ - chan->ctrl |= BIT(25); - /* Disable the channel. */ - chan->ctrl &= ~BIT(0); - chan->act = 0; - } - - /* Soft-reset the block. */ - dma = MEC1322_DMA_REGS; - dma->ctrl |= 0x2; -} - -/** - * Prepare a channel for use and start it - * - * @param chan Channel to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register, normally: - * MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV for tx - * MEC1322_DMA_INC_MEM for rx - */ -static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, - void *periph, void *memory, unsigned flags) -{ - int xfer_size = (flags >> 20) & 0x7; - - if (chan->ctrl & BIT(0)) - chan->ctrl &= ~BIT(0); - - chan->act |= 0x1; - chan->dev = (uint32_t)periph; - chan->mem_start = MEC1322_RAM_ALIAS((uint32_t)memory); - chan->mem_end = MEC1322_RAM_ALIAS((uint32_t)memory) + xfer_size * count; - chan->ctrl = flags; -} - -void dma_go(mec1322_dma_chan_t *chan) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - chan->ctrl |= MEC1322_DMA_RUN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - mec1322_dma_chan_t *chan = dma_get_channel(option->channel); - - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the channel for transmit. - */ - prepare_channel(chan, count, option->periph, (void *)memory, - MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV | - MEC1322_DMA_DEV(option->channel) | option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) -{ - mec1322_dma_chan_t *chan; - - chan = dma_get_channel(option->channel); - - prepare_channel(chan, count, option->periph, memory, - MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) | - option->flags); - dma_go(chan); -} - -int dma_bytes_done(mec1322_dma_chan_t *chan, int orig_count) -{ - int xfer_size = (chan->ctrl >> 20) & 0x7; - - return orig_count - (chan->mem_end - chan->mem_start) / xfer_size; -} - -bool dma_is_enabled(mec1322_dma_chan_t *chan) -{ - return (chan->ctrl & MEC1322_DMA_RUN); -} - -void dma_init(void) -{ - mec1322_dma_regs_t *dma = MEC1322_DMA_REGS; - dma->ctrl |= 0x1; -} - -int dma_wait(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - timestamp_t deadline; - - if (chan->act == 0) - return EC_SUCCESS; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while (!(chan->int_status & 0x4)) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -void dma_clear_isr(enum dma_channel channel) -{ - mec1322_dma_chan_t *chan = dma_get_channel(channel); - - chan->int_status |= 0x4; -} diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c deleted file mode 100644 index 1f54389fc7..0000000000 --- a/chip/mec1322/fan.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322 fan control module. */ - -/* This assumes 2-pole fan. For each rotation, 5 edges are measured. */ - -#include "fan.h" -#include "registers.h" -#include "util.h" - -/* Maximum tach reading/target value */ -#define MAX_TACH 0x1fff - -/* Tach target value for disable fan */ -#define FAN_OFF_TACH 0xfff8 - -/* - * RPM = (n - 1) * m * f * 60 / poles / TACH - * n = number of edges = 5 - * m = multiplier defined by RANGE = 2 in our case - * f = 32.768K - * poles = 2 - */ -#define RPM_TO_TACH(rpm) MIN((7864320 / MAX((rpm), 1)), MAX_TACH) -#define TACH_TO_RPM(tach) (7864320 / MAX((tach), 1)) - -static int rpm_setting; -static int duty_setting; -static int in_rpm_mode = 1; - - -static void clear_status(void) -{ - /* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */ - MEC1322_FAN_STATUS = 0x23; -} - -void fan_set_enabled(int ch, int enabled) -{ - if (in_rpm_mode) { - if (enabled) - fan_set_rpm_target(ch, rpm_setting); - else - MEC1322_FAN_TARGET = FAN_OFF_TACH; - } else { - if (enabled) - fan_set_duty(ch, duty_setting); - else - MEC1322_FAN_SETTING = 0; - } - clear_status(); -} - -int fan_get_enabled(int ch) -{ - if (in_rpm_mode) - return (MEC1322_FAN_TARGET & 0xff00) != 0xff00; - else - return !!MEC1322_FAN_SETTING; -} - -void fan_set_duty(int ch, int percent) -{ - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - duty_setting = percent; - MEC1322_FAN_SETTING = percent * 255 / 100; - clear_status(); -} - -int fan_get_duty(int ch) -{ - return duty_setting; -} - -int fan_get_rpm_mode(int ch) -{ - return !!(MEC1322_FAN_CFG1 & BIT(7)); -} - -void fan_set_rpm_mode(int ch, int rpm_mode) -{ - if (rpm_mode) - MEC1322_FAN_CFG1 |= BIT(7); - else - MEC1322_FAN_CFG1 &= ~BIT(7); - clear_status(); -} - -int fan_get_rpm_actual(int ch) -{ - if ((MEC1322_FAN_READING >> 8) == 0xff) - return 0; - else - return TACH_TO_RPM(MEC1322_FAN_READING >> 3); -} - -int fan_get_rpm_target(int ch) -{ - return rpm_setting; -} - -void fan_set_rpm_target(int ch, int rpm) -{ - rpm_setting = rpm; - MEC1322_FAN_TARGET = RPM_TO_TACH(rpm) << 3; - clear_status(); -} - -enum fan_status fan_get_status(int ch) -{ - uint8_t sts = MEC1322_FAN_STATUS; - - if (sts & (BIT(5) | BIT(1))) - return FAN_STATUS_FRUSTRATED; - if (fan_get_rpm_actual(ch) == 0) - return FAN_STATUS_STOPPED; - return FAN_STATUS_LOCKED; -} - -int fan_is_stalled(int ch) -{ - uint8_t sts = MEC1322_FAN_STATUS; - if (fan_get_rpm_actual(ch)) { - MEC1322_FAN_STATUS = 0x1; - return 0; - } - return sts & 0x1; -} - -void fan_channel_setup(int ch, unsigned int flags) -{ - /* - * Fan configuration 1 register: - * 0x80 = bit 7 = RPM mode (0x00 if FAN_USE_RPM_MODE not set) - * 0x20 = bits 6:5 = min 1000 RPM, multiplier = 2 - * 0x08 = bits 4:3 = 5 edges, 2 poles - * 0x03 = bits 2:0 = 400 ms update time - * - * Fan configuration 2 register: - * 0x00 = bit 6 = Ramp control disabled - * 0x00 = bit 5 = Glitch filter enabled - * 0x18 = bits 4:3 = Using both derivative options - * 0x02 = bits 2:1 = error range is 50 RPM - * 0x00 = bits 0 = normal polarity - */ - if (flags & FAN_USE_RPM_MODE) - MEC1322_FAN_CFG1 = 0xab; - else - MEC1322_FAN_CFG1 = 0x2b; - MEC1322_FAN_CFG2 = 0x1a; - clear_status(); -} diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c deleted file mode 100644 index b6ab76113b..0000000000 --- a/chip/mec1322/flash.c +++ /dev/null @@ -1,268 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "host_command.h" -#include "shared_mem.h" -#include "spi.h" -#include "spi_flash.h" -#include "system.h" -#include "util.h" -#include "hooks.h" - -#define PAGE_SIZE 256 - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -static int entire_flash_locked; - -/* The previous write protect state before sys jump */ - -struct flash_wp_state { - int entire_flash_locked; -}; - -/** - * Read from physical flash. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Destination buffer for data. - */ -int flash_physical_read(int offset, int size, char *data) -{ - return spi_flash_read(data, offset, size); -} - -/** - * Write to physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE. - * - * @param offset Flash offset to write. - * @param size Number of bytes to write. - * @param data Data to write to flash. Must be 32-bit aligned. - */ -int flash_physical_write(int offset, int size, const char *data) -{ - int ret = EC_SUCCESS; - int i, write_size; - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size | (uint32_t)(uintptr_t)data) & 3) - return EC_ERROR_INVAL; - - for (i = 0; i < size; i += write_size) { - write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE); - ret = spi_flash_write(offset + i, - write_size, - (uint8_t *)data + i); - if (ret != EC_SUCCESS) - break; - } - return ret; -} - -/** - * Erase physical flash. - * - * Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE. - * - * @param offset Flash offset to erase. - * @param size Number of bytes to erase. - */ -int flash_physical_erase(int offset, int size) -{ - int ret; - - if (entire_flash_locked) - return EC_ERROR_ACCESS_DENIED; - - ret = spi_flash_erase(offset, size); - return ret; -} - -/** - * Read physical write protect setting for a flash bank. - * - * @param bank Bank index to check. - * @return non-zero if bank is protected until reboot. - */ -int flash_physical_get_protect(int bank) -{ - return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE, - CONFIG_FLASH_BANK_SIZE); -} - -/** - * Protect flash now. - * - * This is always successful, and only emulates "now" protection - * - * @param all Protect all (=1) or just read-only - * @return non-zero if error. - */ -int flash_physical_protect_now(int all) -{ - if (all) - entire_flash_locked = 1; - - /* - * RO "now" protection is not currently implemented. If needed, it - * can be added by splitting the entire_flash_locked variable into - * and RO and RW vars, and setting + checking the appropriate var - * as required. - */ - return EC_SUCCESS; -} - -/** - * Return flash protect state flags from the physical layer. - * - * This should only be called by flash_get_protect(). - * - * Uses the EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - if (spi_flash_check_protect(CONFIG_WP_STORAGE_OFF, - CONFIG_WP_STORAGE_SIZE)) { - flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - } - - if (entire_flash_locked) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - return flags; -} - -/** - * Return the valid flash protect flags. - * - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -/** - * Return the writable flash protect flags. - * - * @param cur_flags The current flash protect flags. - * @return A combination of EC_FLASH_PROTECT_* flags from ec_commands.h - */ -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - enum spi_flash_wp wp_status = SPI_WP_NONE; - - wp_status = spi_flash_check_wp(); - - if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE && - !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) - ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - - if (!entire_flash_locked) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -/** - * Enable write protect for the specified range. - * - * Once write protect is enabled, it will stay enabled until HW PIN is - * de-asserted and SRP register is unset. - * - * However, this implementation treats EC_FLASH_PROTECT_ALL_AT_BOOT as - * EC_FLASH_PROTECT_RO_AT_BOOT but tries to remember if "all" region - * is protected. - * - * @param new_flags to protect (only EC_FLASH_PROTECT_*_AT_BOOT are - * taken care of) - * @return EC_SUCCESS, or nonzero if error. - */ -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - int offset, size, ret; - enum spi_flash_wp flashwp = SPI_WP_NONE; - - if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) { - /* Clear protection */ - offset = size = 0; - flashwp = SPI_WP_NONE; - } else { - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - entire_flash_locked = 1; - - offset = CONFIG_WP_STORAGE_OFF; - size = CONFIG_WP_STORAGE_SIZE; - flashwp = SPI_WP_HARDWARE; - } - - ret = spi_flash_set_protect(offset, size); - if (ret == EC_SUCCESS) - ret = spi_flash_set_wp(flashwp); - return ret; -} - -/** - * Initialize the module. - * - * Applies at-boot protection settings if necessary. - */ -int flash_pre_init(void) -{ - flash_physical_restore_state(); - return EC_SUCCESS; -} - -int flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) - entire_flash_locked = prev->entire_flash_locked; - return 1; - } - - return 0; -} - -/*****************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - struct flash_wp_state state; - - state.entire_flash_locked = entire_flash_locked; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c deleted file mode 100644 index 331022c87c..0000000000 --- a/chip/mec1322/gpio.c +++ /dev/null @@ -1,291 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for MEC1322 */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -struct gpio_int_mapping { - int8_t girq_id; - int8_t port_offset; -}; - -/* Mapping from GPIO port to GIRQ info */ -static const struct gpio_int_mapping int_map[22] = { - {11, 0}, {11, 0}, {11, 0}, {11, 0}, - {10, 4}, {10, 4}, {10, 4}, {-1, -1}, - {-1, -1}, {-1, -1}, {9, 10}, {9, 10}, - {9, 10}, {9, 10}, {8, 14}, {8, 14}, - {8, 14}, {-1, -1}, {-1, -1}, {-1, -1}, - {20, 20}, {20, 20} -}; - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - int i; - uint32_t val; - - while (mask) { - i = __builtin_ffs(mask) - 1; - val = MEC1322_GPIO_CTL(port, i); - val &= ~(BIT(12) | BIT(13)); - /* mux_control = DEFAULT, indicates GPIO */ - if (func > GPIO_ALT_FUNC_DEFAULT) - val |= (func & 0x3) << 12; - MEC1322_GPIO_CTL(port, i) = val; - mask &= ~BIT(i); - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - uint32_t val; - - if (mask == 0) - return 0; - i = GPIO_MASK_TO_NUM(mask); - val = MEC1322_GPIO_CTL(gpio_list[signal].port, i); - - return (val & BIT(24)) ? 1 : 0; -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - uint32_t mask = gpio_list[signal].mask; - int i; - - if (mask == 0) - return; - i = GPIO_MASK_TO_NUM(mask); - - if (value) - MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); - else - MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - int i; - uint32_t val; - while (mask) { - i = GPIO_MASK_TO_NUM(mask); - mask &= ~BIT(i); - val = MEC1322_GPIO_CTL(port, i); - - /* - * Select open drain first, so that we don't glitch the signal - * when changing the line to an output. - */ - if (flags & GPIO_OPEN_DRAIN) - val |= BIT(8); - else - val &= ~BIT(8); - - if (flags & GPIO_OUTPUT) { - val |= BIT(9); - val &= ~BIT(10); - } else { - val &= ~BIT(9); - val |= BIT(10); - } - - /* Handle pullup / pulldown */ - if (flags & GPIO_PULL_UP) - val = (val & ~0x3) | 0x1; - else if (flags & GPIO_PULL_DOWN) - val = (val & ~0x3) | 0x2; - else - val &= ~0x3; - - /* Set up interrupt */ - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - val |= BIT(7); - else - val &= ~BIT(7); - - val &= ~(0x7 << 4); - - if ((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) - val |= 0x7 << 4; - else if (flags & GPIO_INT_F_RISING) - val |= 0x5 << 4; - else if (flags & GPIO_INT_F_FALLING) - val |= 0x6 << 4; - else if (flags & GPIO_INT_F_HIGH) - val |= 0x1 << 4; - else if (!(flags & GPIO_INT_F_LOW)) /* No interrupt flag set */ - val |= 0x4 << 4; - - /* Set up level */ - if (flags & GPIO_HIGH) - val |= BIT(16); - else if (flags & GPIO_LOW) - val &= ~BIT(16); - - MEC1322_GPIO_CTL(port, i) = val; - } -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id); - MEC1322_INT_BLK_EN |= BIT(girq_id); - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - MEC1322_INT_DISABLE(girq_id) = BIT(bit_id); - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - int i, port, girq_id, bit_id; - - if (gpio_list[signal].mask == 0) - return EC_SUCCESS; - - i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); - port = gpio_list[signal].port; - girq_id = int_map[port].girq_id; - bit_id = (port - int_map[port].port_offset) * 8 + i; - - /* Clear interrupt source sticky status bit even if not enabled */ - MEC1322_INT_SOURCE(girq_id) |= 1 << bit_id; - - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - int i; - int flags; - int is_warm = system_is_reboot_warm(); - const struct gpio_info *g = gpio_list; - - - for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - - /* Use as GPIO, not alternate function */ - gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); - } -} - -/* Clear any interrupt flags before enabling GPIO interrupt */ -#define ENABLE_GPIO_GIRQ(x) \ - do { \ - MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \ - task_enable_irq(MEC1322_IRQ_GIRQ ## x); \ - } while (0) - -static void gpio_init(void) -{ - ENABLE_GPIO_GIRQ(8); - ENABLE_GPIO_GIRQ(9); - ENABLE_GPIO_GIRQ(10); - ENABLE_GPIO_GIRQ(11); - ENABLE_GPIO_GIRQ(20); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/*****************************************************************************/ -/* Interrupt handlers */ - - -/** - * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for - * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt - * handlers. - * - * @param girq GIRQ index - * @param port_offset GPIO port offset for the given GIRQ - */ -static void gpio_interrupt(int girq, int port_offset) -{ - int i, bit; - const struct gpio_info *g = gpio_list; - uint32_t sts = MEC1322_INT_RESULT(girq); - - MEC1322_INT_SOURCE(girq) |= sts; - - for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) { - bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1; - if (sts & BIT(bit)) - gpio_irq_handlers[i](i); - sts &= ~BIT(bit); - } -} - -#define GPIO_IRQ_FUNC(irqfunc, girq, port_offset) \ - void irqfunc(void) \ - { \ - gpio_interrupt(girq, port_offset); \ - } - -GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 14); -GPIO_IRQ_FUNC(__girq_9_interrupt, 9, 10); -GPIO_IRQ_FUNC(__girq_10_interrupt, 10, 4); -GPIO_IRQ_FUNC(__girq_11_interrupt, 11, 0); -GPIO_IRQ_FUNC(__girq_20_interrupt, 20, 20); - -#undef GPIO_IRQ_FUNC - -/* - * Declare IRQs. Nesting this macro inside the GPIO_IRQ_FUNC macro works - * poorly because DECLARE_IRQ() stringizes its inputs. - */ -DECLARE_IRQ(MEC1322_IRQ_GIRQ8, __girq_8_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ9, __girq_9_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ10, __girq_10_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ11, __girq_11_interrupt, 1); -DECLARE_IRQ(MEC1322_IRQ_GIRQ20, __girq_20_interrupt, 1); diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c deleted file mode 100644 index a5c5858620..0000000000 --- a/chip/mec1322/hwtimer.c +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "clock.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" - -void __hw_clock_event_set(uint32_t deadline) -{ - MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - - (0xffffffff - deadline); - MEC1322_TMR32_CTL(1) |= BIT(5); -} - -uint32_t __hw_clock_event_get(void) -{ - return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff; -} - -void __hw_clock_event_clear(void) -{ - MEC1322_TMR32_CTL(1) &= ~BIT(5); -} - -uint32_t __hw_clock_source_read(void) -{ - return 0xffffffff - MEC1322_TMR32_CNT(0); -} - -void __hw_clock_source_set(uint32_t ts) -{ - MEC1322_TMR32_CTL(0) &= ~BIT(5); - MEC1322_TMR32_CNT(0) = 0xffffffff - ts; - MEC1322_TMR32_CTL(0) |= BIT(5); -} - -static void __hw_clock_source_irq(int timer_id) -{ - if (timer_id == 1) - MEC1322_TMR32_STS(1) |= 1; - /* If IRQ is from timer 0, 32-bit timer overflowed */ - process_timers(timer_id == 0); -} - -void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); } -DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1); -void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); } -DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1); - -static void configure_timer(int timer_id) -{ - uint32_t val; - - /* Ensure timer is not running */ - MEC1322_TMR32_CTL(timer_id) &= ~BIT(5); - - /* Enable timer */ - MEC1322_TMR32_CTL(timer_id) |= BIT(0); - - val = MEC1322_TMR32_CTL(timer_id); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MEC1322_TMR32_CTL(timer_id) = val; - - /* Set preload to use the full 32 bits of the timer */ - MEC1322_TMR32_PRE(timer_id) = 0xffffffff; - - /* Enable interrupt */ - MEC1322_TMR32_IEN(timer_id) |= 1; -} - -int __hw_clock_source_init(uint32_t start_t) -{ - /* - * The timer can only fire interrupt when its value reaches zero. - * Therefore we need two timers: - * - Timer 0 as free running timer - * - Timer 1 as event timer - */ - configure_timer(0); - configure_timer(1); - - /* Override the count */ - MEC1322_TMR32_CNT(0) = 0xffffffff - start_t; - - /* Auto restart */ - MEC1322_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= BIT(5); - - /* Enable interrupt */ - task_enable_irq(MEC1322_IRQ_TIMER32_0); - task_enable_irq(MEC1322_IRQ_TIMER32_1); - MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5); - MEC1322_INT_BLK_EN |= BIT(23); - - return MEC1322_IRQ_TIMER32_1; -} diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c deleted file mode 100644 index fe72b870ef..0000000000 --- a/chip/mec1322/i2c.c +++ /dev/null @@ -1,531 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* I2C port module for MEC1322 */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_CLOCK 16000000 /* 16 MHz */ - -/* Status */ -#define STS_NBB BIT(0) /* Bus busy */ -#define STS_LAB BIT(1) /* Arbitration lost */ -#define STS_LRB BIT(3) /* Last received bit */ -#define STS_BER BIT(4) /* Bus error */ -#define STS_PIN BIT(7) /* Pending interrupt */ - -/* Control */ -#define CTRL_ACK BIT(0) /* Acknowledge */ -#define CTRL_STO BIT(1) /* STOP */ -#define CTRL_STA BIT(2) /* START */ -#define CTRL_ENI BIT(3) /* Enable interrupt */ -#define CTRL_ESO BIT(6) /* Enable serial output */ -#define CTRL_PIN BIT(7) /* Pending interrupt not */ - -/* Completion */ -#define COMP_IDLE BIT(29) /* i2c bus is idle */ -#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ - -/* Maximum transfer of a SMBUS block transfer */ -#define SMBUS_MAX_BLOCK_SIZE 32 - -/* - * Amount of time to blocking wait for i2c bus to finish. After this blocking - * timeout, if the bus is still not finished, then allow other tasks to run. - * Note: this is just long enough for a 400kHz bus to finish transmitting one - * byte assuming the bus isn't being held. - */ -#define I2C_WAIT_BLOCKING_TIMEOUT_US 25 - -enum i2c_transaction_state { - /* Stop condition was sent in previous transaction */ - I2C_TRANSACTION_STOPPED, - /* Stop condition was not sent in previous transaction */ - I2C_TRANSACTION_OPEN, -}; - -/* I2C controller state data */ -static struct { - /* Transaction timeout, or 0 to use default. */ - uint32_t timeout_us; - /* Task waiting on port, or TASK_ID_INVALID if none. */ - volatile task_id_t task_waiting; - enum i2c_transaction_state transaction_state; -} cdata[I2C_CONTROLLER_COUNT]; - -/* Map port number to port name in datasheet, for debug prints. */ -static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = { - [MEC1322_I2C0_0] = "0_0", - [MEC1322_I2C0_1] = "0_1", - [MEC1322_I2C1] = "1", - [MEC1322_I2C2] = "2", - [MEC1322_I2C3] = "3", -}; - -static void configure_controller_speed(int controller, int kbps) -{ - int t_low, t_high; - const int period = I2C_CLOCK / 1000 / kbps; - - /* - * Refer to NXP UM10204 for minimum timing requirement of T_Low and - * T_High. - * http://www.nxp.com/documents/user_manual/UM10204.pdf - */ - if (kbps > 400) { - /* Fast mode plus */ - t_low = t_high = period / 2 - 1; - MEC1322_I2C_DATA_TIM(controller) = 0x06060601; - MEC1322_I2C_DATA_TIM_2(controller) = 0x06; - } else if (kbps > 100) { - /* Fast mode */ - /* By spec, clk low period is 1.3us min */ - t_low = MAX((int)(I2C_CLOCK * 1.3 / 1000000), period / 2 - 1); - t_high = period - t_low - 2; - MEC1322_I2C_DATA_TIM(controller) = 0x040a0a01; - MEC1322_I2C_DATA_TIM_2(controller) = 0x0a; - } else { - /* Standard mode */ - t_low = t_high = period / 2 - 1; - MEC1322_I2C_DATA_TIM(controller) = 0x0c4d5006; - MEC1322_I2C_DATA_TIM_2(controller) = 0x4d; - } - - /* Clock periods is one greater than the contents of these fields */ - MEC1322_I2C_BUS_CLK(controller) = ((t_high & 0xff) << 8) | - (t_low & 0xff); -} - -static void configure_controller(int controller, int kbps) -{ - MEC1322_I2C_CTRL(controller) = CTRL_PIN; - MEC1322_I2C_OWN_ADDR(controller) = 0x0; - configure_controller_speed(controller, kbps); - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_ACK | CTRL_ENI; - MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ - - /* Enable interrupt */ - MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ - MEC1322_INT_ENABLE(12) |= BIT(controller); - MEC1322_INT_BLK_EN |= BIT(12); -} - -static void reset_controller(int controller) -{ - int i; - - MEC1322_I2C_CONFIG(controller) |= BIT(9); - udelay(100); - MEC1322_I2C_CONFIG(controller) &= ~BIT(9); - - for (i = 0; i < i2c_ports_used; ++i) - if (controller == i2c_port_to_controller(i2c_ports[i].port)) { - configure_controller(controller, i2c_ports[i].kbps); - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - break; - } -} - -static int wait_for_interrupt(int controller, int timeout) -{ - int event; - - if (timeout <= 0) - return EC_ERROR_TIMEOUT; - - cdata[controller].task_waiting = task_get_current(); - task_enable_irq(MEC1322_IRQ_I2C_0 + controller); - - /* Wait until I2C interrupt or timeout. */ - event = task_wait_event_mask(TASK_EVENT_I2C_IDLE, timeout); - - task_disable_irq(MEC1322_IRQ_I2C_0 + controller); - cdata[controller].task_waiting = TASK_ID_INVALID; - - return (event & TASK_EVENT_TIMER) ? EC_ERROR_TIMEOUT : EC_SUCCESS; -} - -static int wait_idle(int controller) -{ - uint8_t sts = MEC1322_I2C_STATUS(controller); - uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - uint64_t task_timeout = block_timeout + cdata[controller].timeout_us; - int rv = 0; - - while (!(sts & STS_NBB)) { - if (rv) - return rv; - if (get_time().val > block_timeout) - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - sts = MEC1322_I2C_STATUS(controller); - } - - if (sts & (STS_BER | STS_LAB)) - return EC_ERROR_UNKNOWN; - return EC_SUCCESS; -} - -static int wait_byte_done(int controller) -{ - uint8_t sts = MEC1322_I2C_STATUS(controller); - uint64_t block_timeout = get_time().val + I2C_WAIT_BLOCKING_TIMEOUT_US; - uint64_t task_timeout = block_timeout + cdata[controller].timeout_us; - int rv = 0; - - while (sts & STS_PIN) { - if (rv) - return rv; - if (get_time().val > block_timeout) - rv = wait_for_interrupt(controller, - task_timeout - get_time().val); - sts = MEC1322_I2C_STATUS(controller); - } - - return sts & STS_LRB; -} - -static void select_port(int port) -{ - /* - * I2C0_1 uses port 1 of controller 0. All other I2C pin sets - * use port 0. - */ - uint8_t port_sel = (port == MEC1322_I2C0_1) ? 1 : 0; - int controller = i2c_port_to_controller(port); - - MEC1322_I2C_CONFIG(controller) &= ~0xf; - MEC1322_I2C_CONFIG(controller) |= port_sel; - -} - -static inline int get_line_level(int controller) -{ - int ret, ctrl; - /* - * We need to enable BB (Bit Bang) mode in order to read line level - * properly, othervise line levels return always idle (0x60). - */ - ctrl = MEC1322_I2C_BB_CTRL(controller); - MEC1322_I2C_BB_CTRL(controller) |= 1; - ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3; - MEC1322_I2C_BB_CTRL(controller) = ctrl; - return ret; -} - -static inline void push_in_buf(uint8_t **in, uint8_t val, int skip) -{ - if (!skip) { - **in = val; - (*in)++; - } -} - -int chip_i2c_xfer(const int port, - const uint16_t slave_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) -{ - int i; - int controller; - int send_start = flags & I2C_XFER_START; - int send_stop = flags & I2C_XFER_STOP; - int skip = 0; - int bytes_to_read; - uint8_t reg; - int ret_done; - - if (out_size == 0 && in_size == 0) - return EC_SUCCESS; - - select_port(port); - controller = i2c_port_to_controller(port); - if (send_start && - cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED) - wait_idle(controller); - - reg = MEC1322_I2C_STATUS(controller); - if (send_start && - cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED && - (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) || - (get_line_level(controller) - != I2C_LINE_IDLE))) { - CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d", - i2c_port_names[port], reg, - get_line_level(controller) & I2C_LINE_SCL_HIGH, - get_line_level(controller) & I2C_LINE_SDA_HIGH); - - /* Attempt to unwedge the port. */ - i2c_unwedge(port); - - /* Bus error, bus busy, or arbitration lost. Try reset. */ - reset_controller(controller); - select_port(port); - - /* - * We don't know what edges the slave saw, so sleep long enough - * that the slave will see the new start condition below. - */ - usleep(1000); - } - - if (out_size) { - if (send_start) { - MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_GET_ADDR(slave_addr_flags) - << 1); - - /* Clock out the slave address, sending START bit */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_ENI | CTRL_ACK | - CTRL_STA; - cdata[controller].transaction_state = - I2C_TRANSACTION_OPEN; - } - - for (i = 0; i < out_size; ++i) { - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - MEC1322_I2C_DATA(controller) = out[i]; - } - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - /* - * Send STOP bit if the stop flag is on, and caller - * doesn't expect to receive data. - */ - if (send_stop && in_size == 0) { - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - } - } - - if (in_size) { - /* Resend start bit when changing direction */ - if (out_size || send_start) { - /* Repeated start case */ - if (cdata[controller].transaction_state == - I2C_TRANSACTION_OPEN) - MEC1322_I2C_CTRL(controller) = CTRL_ESO | - CTRL_STA | - CTRL_ACK | - CTRL_ENI; - - MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_GET_ADDR(slave_addr_flags) - << 1) - | 0x01; - - /* New transaction case, clock out slave address. */ - if (cdata[controller].transaction_state == - I2C_TRANSACTION_STOPPED) - MEC1322_I2C_CTRL(controller) = CTRL_ESO | - CTRL_STA | - CTRL_ACK | - CTRL_ENI | - CTRL_PIN; - - cdata[controller].transaction_state = - I2C_TRANSACTION_OPEN; - - /* Skip over the dummy byte */ - skip = 1; - in_size++; - } - - /* Special flags need to be set for last two bytes */ - bytes_to_read = send_stop ? in_size - 2 : in_size; - - for (i = 0; i < bytes_to_read; ++i) { - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - push_in_buf(&in, MEC1322_I2C_DATA(controller), skip); - skip = 0; - } - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - if (send_stop) { - /* - * De-assert ACK bit before reading the next to last - * byte, so that the last byte is NACK'ed. - */ - MEC1322_I2C_CTRL(controller) = CTRL_ESO | CTRL_ENI; - push_in_buf(&in, MEC1322_I2C_DATA(controller), skip); - ret_done = wait_byte_done(controller); - if (ret_done) - goto err_chip_i2c_xfer; - - /* Send STOP */ - MEC1322_I2C_CTRL(controller) = - CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO; - - cdata[controller].transaction_state = - I2C_TRANSACTION_STOPPED; - - /* - * We need to know our stop point two bytes in - * advance. If we don't know soon enough, we need - * to do an extra dummy read (to last_addr + 1) to - * issue the stop. - */ - push_in_buf(&in, MEC1322_I2C_DATA(controller), - in_size == 1); - } - } - - /* Check for error conditions */ - if (MEC1322_I2C_STATUS(controller) & (STS_LAB | STS_BER)) - return EC_ERROR_UNKNOWN; - - return EC_SUCCESS; -err_chip_i2c_xfer: - /* Send STOP and return error */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; - cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; - if (ret_done == STS_LRB) - return EC_ERROR_BUSY; - else if (ret_done == EC_ERROR_TIMEOUT) { - /* - * If our transaction timed out then our i2c controller - * may be wedged without showing any other outward signs - * of failure. Reset the controller so that future - * transactions have a chance of success. - */ - reset_controller(controller); - return EC_ERROR_TIMEOUT; - } - else - return EC_ERROR_UNKNOWN; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - - return gpio_get_level(g); -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS) - return 1; - - return gpio_get_level(g); -} - -int i2c_get_line_levels(int port) -{ - int rv; - - i2c_lock(port, 1); - select_port(port); - rv = get_line_level(i2c_port_to_controller(port)); - i2c_lock(port, 0); - return rv; -} - -int i2c_port_to_controller(int port) -{ - if (port < 0 || port >= MEC1322_I2C_PORT_COUNT) - return -1; - return (port == MEC1322_I2C0_0) ? 0 : port - 1; -} - -void i2c_set_timeout(int port, uint32_t timeout) -{ - /* Param is port, but timeout is stored by-controller. */ - cdata[i2c_port_to_controller(port)].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; -} - -void i2c_init(void) -{ - int i; - int controller; - int controller0_kbps = -1; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - for (i = 0; i < i2c_ports_used; ++i) { - /* - * If this controller has multiple ports, check if we already - * configured it. If so, ensure previously configured bitrate - * matches. - */ - controller = i2c_port_to_controller(i2c_ports[i].port); - if (controller == 0) { - if (controller0_kbps != -1) { - ASSERT(controller0_kbps == i2c_ports[i].kbps); - continue; - } - controller0_kbps = i2c_ports[i].kbps; - } - configure_controller(controller, i2c_ports[i].kbps); - cdata[controller].task_waiting = TASK_ID_INVALID; - cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; - - /* Use default timeout. */ - i2c_set_timeout(i2c_ports[i].port, 0); - } -} - -static void handle_interrupt(int controller) -{ - int id = cdata[controller].task_waiting; - - /* Clear the interrupt status */ - MEC1322_I2C_COMPLETE(controller) &= (COMP_RW_BITS_MASK | COMP_IDLE); - - /* - * Write to control register interferes with I2C transaction. - * Instead, let's disable IRQ from the core until the next time - * we want to wait for STS_PIN/STS_NBB. - */ - task_disable_irq(MEC1322_IRQ_I2C_0 + controller); - - /* Wake up the task which was waiting on the I2C interrupt, if any. */ - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_I2C_IDLE, 0); -} - -void i2c0_interrupt(void) { handle_interrupt(0); } -void i2c1_interrupt(void) { handle_interrupt(1); } -void i2c2_interrupt(void) { handle_interrupt(2); } -void i2c3_interrupt(void) { handle_interrupt(3); } - -DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_2, i2c2_interrupt, 2); -DECLARE_IRQ(MEC1322_IRQ_I2C_3, i2c3_interrupt, 2); diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c deleted file mode 100644 index 2c62ada9ac..0000000000 --- a/chip/mec1322/keyboard_raw.c +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for MEC1322 - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void keyboard_raw_init(void) -{ - keyboard_raw_enable_interrupt(0); - gpio_config_module(MODULE_KEYBOARD_SCAN, 1); - - /* Enable keyboard scan interrupt */ - MEC1322_INT_ENABLE(17) |= BIT(21); - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_KS_KSI_INT_EN = 0xff; -} - -void keyboard_raw_task_start(void) -{ - task_enable_irq(MEC1322_IRQ_KSC_INT); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - if (out == KEYBOARD_COLUMN_ALL) { - MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 1); -#endif - } else if (out == KEYBOARD_COLUMN_NONE) { - MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - gpio_set_level(GPIO_KBD_KSO2, 0); -#endif - } else { -#ifdef CONFIG_KEYBOARD_COL2_INVERTED - if (out == 2) { - MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ - gpio_set_level(GPIO_KBD_KSO2, 1); - } else { - MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; - gpio_set_level(GPIO_KBD_KSO2, 0); - } -#else - MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; -#endif - } -} - -test_mockable int keyboard_raw_read_rows(void) -{ - /* Invert it so 0=not pressed, 1=pressed */ - return (MEC1322_KS_KSI_INPUT & 0xff) ^ 0xff; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - task_clear_pending_irq(MEC1322_IRQ_KSC_INT); - task_enable_irq(MEC1322_IRQ_KSC_INT); - } else { - task_disable_irq(MEC1322_IRQ_KSC_INT); - } -} - -void keyboard_raw_interrupt(void) -{ - /* Clear interrupt status bits */ - MEC1322_KS_KSI_STATUS = 0xff; - - /* Wake keyboard scan task to handle interrupt */ - task_wake(TASK_ID_KEYSCAN); -} -DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1); - -int keyboard_raw_is_input_low(int port, int id) -{ - return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0; -} diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c deleted file mode 100644 index 7dacfc3077..0000000000 --- a/chip/mec1322/lfw/ec_lfw.c +++ /dev/null @@ -1,285 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -#include <stdint.h> - -#include "config.h" -#include "gpio.h" -#include "spi.h" -#include "spi_flash.h" -#include "util.h" -#include "timer.h" -#include "dma.h" -#include "registers.h" -#include "cpu.h" -#include "clock.h" -#include "system.h" -#include "version.h" -#include "hwtimer.h" -#include "gpio_list.h" - -#include "ec_lfw.h" - -__attribute__ ((section(".intvector"))) -const struct int_vector_t hdr_int_vect = { - (void *)0x11FA00, /* init sp, unused, - set by MEC ROM loader*/ - &lfw_main, /* reset vector */ - &fault_handler, /* NMI handler */ - &fault_handler, /* HardFault handler */ - &fault_handler, /* MPU fault handler */ - &fault_handler /* Bus fault handler */ -}; - -/* SPI devices - from glados/board.c*/ -const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0}, -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - - -void timer_init() -{ - uint32_t val = 0; - - /* Ensure timer is not running */ - MEC1322_TMR32_CTL(0) &= ~BIT(5); - - /* Enable timer */ - MEC1322_TMR32_CTL(0) |= BIT(0); - - val = MEC1322_TMR32_CTL(0); - - /* Pre-scale = 48 -> 1MHz -> Period = 1us */ - val = (val & 0xffff) | (47 << 16); - - MEC1322_TMR32_CTL(0) = val; - - /* Set preload to use the full 32 bits of the timer */ - MEC1322_TMR32_PRE(0) = 0xffffffff; - - /* Override the count */ - MEC1322_TMR32_CNT(0) = 0xffffffff; - - /* Auto restart */ - MEC1322_TMR32_CTL(0) |= BIT(3); - - /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= BIT(5); - -} - -static int spi_flash_readloc(uint8_t *buf_usr, - unsigned int offset, - unsigned int bytes) -{ - uint8_t cmd[4] = {SPI_FLASH_READ, - (offset >> 16) & 0xFF, - (offset >> 8) & 0xFF, - offset & 0xFF}; - - if (offset + bytes > CONFIG_FLASH_SIZE) - return EC_ERROR_INVAL; - - return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes); -} - -int spi_image_load(uint32_t offset) -{ - uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + - CONFIG_PROGRAM_MEMORY_BASE); - uint32_t i; - - BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE); - memset((void *)buf, 0xFF, (CONFIG_RO_SIZE - 4)); - - for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE) - spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); - - return 0; - -} - -void udelay(unsigned us) -{ - uint32_t t0 = __hw_clock_source_read(); - while (__hw_clock_source_read() - t0 < us) - ; -} - -void usleep(unsigned us) -{ - udelay(us); -} - -int timestamp_expired(timestamp_t deadline, const timestamp_t *now) -{ - timestamp_t now_val; - - if (!now) { - now_val = get_time(); - now = &now_val; - } - - return now->le.lo >= deadline.le.lo; -} - - -timestamp_t get_time(void) -{ - timestamp_t ts; - - ts.le.hi = 0; - ts.le.lo = __hw_clock_source_read(); - return ts; -} - -void uart_write_c(char c) -{ - /* Put in carriage return prior to newline to mimic uart_vprintf() */ - if (c == '\n') - uart_write_c('\r'); - - /* Wait for space in transmit FIFO. */ - while (!(MEC1322_UART_LSR & BIT(5))) - ; - MEC1322_UART_TB = c; -} - -void uart_puts(const char *str) -{ - if (!str || !*str) - return; - - do { - uart_write_c(*str++); - } while (*str); -} - -void fault_handler(void) -{ - uart_puts("EXCEPTION!\nTriggering watchdog reset\n"); - /* trigger reset in 1 ms */ - MEC1322_WDG_LOAD = 1; - MEC1322_WDG_CTL |= 1; - while (1) - ; - -} - -void jump_to_image(uintptr_t init_addr) -{ - void (*resetvec)(void) = (void(*)(void))init_addr; - resetvec(); -} - -void uart_init(void) -{ - /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~BIT(0); - - /* Set DLAB = 1 */ - MEC1322_UART_LCR |= BIT(7); - - /* PBRG0/PBRG1 */ - MEC1322_UART_PBRG0 = 1; - MEC1322_UART_PBRG1 = 0; - - /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~BIT(7); - - /* Set word length to 8-bit */ - MEC1322_UART_LCR |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MEC1322_UART_FCR = BIT(0); - - /* Activate UART */ - MEC1322_UART_ACT |= BIT(0); - - gpio_config_module(MODULE_UART, 1); -} - -void system_init(void) -{ - - uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT; - uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & - MEC1322_PWR_RST_STS_VCC1; - - if (rst_sts || wdt_sts) - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) - = SYSTEM_IMAGE_RO; -} - -enum system_image_copy_t system_get_image_copy(void) -{ - return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX); -} - -void lfw_main() -{ - - uintptr_t init_addr; - - /* install vector table */ - *((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect; - - /* Use 48 MHz processor clock to power through boot */ - MEC1322_PCR_PROC_CLK_CTL = 1; - -#ifdef CONFIG_WATCHDOG - /* Reload watchdog which may be running in case of sysjump */ - MEC1322_WDG_KICK = 1; -#ifdef CONFIG_WATCHDOG_HELP - /* Stop aux timer */ - MEC1322_TMR16_CTL(0) &= ~1; -#endif -#endif - - timer_init(); - clock_init(); - cpu_init(); - dma_init(); - uart_init(); - system_init(); - spi_enable(CONFIG_SPI_FLASH_PORT, 1); - - uart_puts("littlefw "); - uart_puts(current_image_data.version); - uart_puts("\n"); - - switch (system_get_image_copy()) { - case SYSTEM_IMAGE_RW: - uart_puts("lfw-RW load\n"); - init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - spi_image_load(CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF); - break; - case SYSTEM_IMAGE_RO: - uart_puts("lfw-RO load\n"); - spi_image_load(CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF); - /* fall through */ - default: - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = - SYSTEM_IMAGE_RO; - init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE; - } - - jump_to_image(*(uintptr_t *)(init_addr + 4)); - - /* should never get here */ - while (1) - ; -} diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h deleted file mode 100644 index b7f9f6359f..0000000000 --- a/chip/mec1322/lfw/ec_lfw.h +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -void lfw_main(void) __attribute__ ((noreturn, naked)); -void fault_handler(void) __attribute__((naked)); - -struct int_vector_t { - void *stack_ptr; - void *reset_vector; - void *nmi; - void *hard_fault; - void *bus_fault; - void *usage_fault; -}; - -#define SPI_CHUNK_SIZE 1024 diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld deleted file mode 100644 index 65e17e4941..0000000000 --- a/chip/mec1322/lfw/ec_lfw.ld +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * MEC1322 SoC little FW - * - */ - -/* Memory Spaces Definitions */ -MEMORY -{ - VECTOR(r ) : ORIGIN = 0x100000, LENGTH = 0x18 - SRAM (xrw) : ORIGIN = 0x100018, LENGTH = 0xBE8 -} - -/* - * ld does not allow mathematical expressions in ORIGIN/LENGTH, so check the - * values here. - */ -ASSERT(ORIGIN(VECTOR) + LENGTH(VECTOR) == ORIGIN(SRAM), "Invalid SRAM origin.") -ASSERT(LENGTH(VECTOR) + LENGTH(SRAM) == 0xC00, "Invalid VECTOR+SRAM length.") - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ -ENTRY(lfw_main) - -/* Sections Definitions */ - -SECTIONS -{ - - /* - * The vector table goes first - */ - .intvector : - { - . = ALIGN(4); - KEEP(*(.intvector)) - } > VECTOR - - /* - * The program code is stored in the .text section, - * which goes to FLASH. - */ - - .text : - { - *(.text .text.*) /* all remaining code */ - *(.rodata .rodata.*) /* read-only data (constants) */ - } >SRAM - - . = ALIGN(4); - - /* Padding */ - - .fill : { - FILL(0xFF); - . = ORIGIN(SRAM) + LENGTH(SRAM) - 1; - BYTE(0xFF); /* emit at least a byte to make linker happy */ - } - - __image_size = LOADADDR(.text) + SIZEOF(.text) - ORIGIN(VECTOR); -} diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c deleted file mode 100644 index 69fe3b856c..0000000000 --- a/chip/mec1322/lpc.c +++ /dev/null @@ -1,520 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* LPC module for MEC1322 */ - -#include "acpi.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "keyboard_protocol.h" -#include "lpc.h" -#include "port80.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "chipset.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - -static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align"))); - -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ - -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); -static int init_done; - -static struct ec_lpc_host_args * const lpc_host_args = - (struct ec_lpc_host_args *)mem_mapped; - -static void keyboard_irq_assert(void) -{ -#ifdef CONFIG_KEYBOARD_IRQ_GPIO - /* - * Enforce signal-high for long enough for the signal to be pulled high - * by the external pullup resistor. This ensures the host will see the - * following falling edge, regardless of the line state before this - * function call. - */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); - udelay(4); - /* Generate a falling edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 0); - udelay(4); - - /* Set signal high, now that we've generated the edge */ - gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1); -#else - /* - * SERIRQ is automatically sent by KBC - */ -#endif -} - -/** - * Generate SMI pulse to the host chipset via GPIO. - * - * If the x86 is in S0, SMI# is sampled at 33MHz, so minimum pulse length is - * 60ns. If the x86 is in S3, SMI# is sampled at 32.768KHz, so we need pulse - * length >61us. Both are short enough and events are infrequent, so just - * delay for 65us. - */ -static void lpc_generate_smi(void) -{ - gpio_set_level(GPIO_PCH_SMI_L, 0); - udelay(65); - gpio_set_level(GPIO_PCH_SMI_L, 1); -} - -static void lpc_generate_sci(void) -{ -#ifdef CONFIG_SCI_GPIO - gpio_set_level(CONFIG_SCI_GPIO, 0); - udelay(65); - gpio_set_level(CONFIG_SCI_GPIO, 1); -#else - MEC1322_ACPI_PM_STS |= 1; - udelay(65); - MEC1322_ACPI_PM_STS &= ~1; -#endif -} - -/** - * Update the level-sensitive wake signal to the AP. - * - * @param wake_events Currently asserted wake events - */ -static void lpc_update_wake(host_event_t wake_events) -{ - /* - * Mask off power button event, since the AP gets that through a - * separate dedicated GPIO. - */ - wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); - - /* Signal is asserted low when wake events is non-zero */ - gpio_set_level(GPIO_PCH_WAKE_L, !wake_events); -} - -uint8_t *lpc_get_memmap_range(void) -{ - return mem_mapped + 0x100; -} - -static uint8_t *lpc_get_hostcmd_data_range(void) -{ - return mem_mapped; -} - -/** - * Update the host event status. - * - * Sends a pulse if masked event status becomes non-zero: - * - SMI pulse via PCH_SMI_L GPIO - * - SCI pulse via PCH_SCI_L GPIO - */ -void lpc_update_host_event_status(void) -{ - int need_sci = 0; - int need_smi = 0; - - if (!init_done) - return; - - /* Disable LPC interrupt while updating status register */ - task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) { - /* Only generate SMI for first event */ - if (!(MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_SMI_PENDING)) - need_smi = 1; - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SMI_PENDING; - } else { - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SMI_PENDING; - } - - if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) { - /* Generate SCI for every event */ - need_sci = 1; - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_SCI_PENDING; - } else { - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_SCI_PENDING; - } - - /* Copy host events to mapped memory */ - *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); - - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - /* Process the wake events. */ - lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE)); - - /* Send pulse on SMI signal if needed */ - if (need_smi) - lpc_generate_smi(); - - /* ACPI 5.0-12.6.1: Generate SCI for SCI_EVT=1. */ - if (need_sci) - lpc_generate_sci(); -} - -static void lpc_send_response_packet(struct host_packet *pkt) -{ - /* Ignore in-progress on LPC since interface is synchronous anyway */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result to the data byte. */ - MEC1322_ACPI_EC_EC2OS(1, 0) = pkt->driver_result; - - /* Clear the busy bit, so the host knows the EC is done. */ - MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; -} - -/* - * Most registers in LPC module are reset when the host is off. We need to - * set up LPC again when the host is starting up. - */ -static void setup_lpc(void) -{ - gpio_config_module(MODULE_LPC, 1); - - /* Set up interrupt on LRESET# deassert */ - MEC1322_INT_SOURCE(19) = BIT(1); - MEC1322_INT_ENABLE(19) |= BIT(1); - MEC1322_INT_BLK_EN |= BIT(19); - task_enable_irq(MEC1322_IRQ_GIRQ19); - - /* Set up ACPI0 for 0x62/0x66 */ - MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; - MEC1322_INT_ENABLE(15) |= BIT(6); - MEC1322_INT_BLK_EN |= BIT(15); - /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); - - /* Set up ACPI1 for 0x200/0x204 */ - MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; - MEC1322_INT_ENABLE(15) |= BIT(8); - MEC1322_INT_BLK_EN |= BIT(15); - MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); - - /* Set up 8042 interface at 0x60/0x64 */ - MEC1322_LPC_8042_BAR = 0x00608104; - - /* Set up indication of Auxiliary sts */ - MEC1322_8042_KB_CTRL |= BIT(7); - - MEC1322_8042_ACT |= 1; - MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14)); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_8042EM_IBF); - task_enable_irq(MEC1322_IRQ_8042EM_OBF); - -#ifndef CONFIG_KEYBOARD_IRQ_GPIO - /* Set up SERIRQ for keyboard */ - MEC1322_8042_KB_CTRL |= BIT(5); - MEC1322_LPC_SIRQ(1) = 0x01; -#endif - - /* Set up EMI module for memory mapped region, base address 0x800 */ - MEC1322_LPC_EMI_BAR = 0x0800800f; - MEC1322_INT_ENABLE(15) |= BIT(2); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_EMI); - - /* Access data RAM through alias address */ - MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000; - - /* - * Limit EMI read / write range. First 256 bytes are RW for host - * commands. Second 256 bytes are RO for mem-mapped data. - */ - MEC1322_EMI_MRL0 = 0x200; - MEC1322_EMI_MWL0 = 0x100; - - /* Set up Mailbox for Port80 trapping */ - MEC1322_MBX_INDEX = 0xff; - MEC1322_LPC_MAILBOX_BAR = 0x00808901; - - /* We support LPC args and version 3 protocol */ - *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; - - /* Sufficiently initialized */ - init_done = 1; - - /* Update host events now that we can copy them to memmap */ - lpc_update_host_event_status(); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST); - -static void lpc_init(void) -{ - /* Activate LPC interface */ - MEC1322_LPC_ACT |= 1; - - /* - * Ring Oscillator not permitted to shut down - * until LPC activate bit is cleared - */ - MEC1322_LPC_CLK_CTRL |= 3; - - /* Initialize host args and memory map to all zero */ - memset(lpc_host_args, 0, sizeof(*lpc_host_args)); - memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE); - - setup_lpc(); -} -/* - * Set prio to higher than default; this way LPC memory mapped data is ready - * before other inits try to initialize their memmap data. - */ -DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC); - -#ifdef CONFIG_CHIPSET_RESET_HOOK -static void lpc_chipset_reset(void) -{ - hook_notify(HOOK_CHIPSET_RESET); -} -DECLARE_DEFERRED(lpc_chipset_reset); -#endif - -void girq19_interrupt(void) -{ - /* Check interrupt result for LRESET# trigger */ - if (MEC1322_INT_RESULT(19) & BIT(1)) { - /* Initialize LPC module when LRESET# is deasserted */ - if (!lpc_get_pltrst_asserted()) { - setup_lpc(); - } else { - /* Store port 80 reset event */ - port_80_write(PORT_80_EVENT_RESET); - -#ifdef CONFIG_CHIPSET_RESET_HOOK - /* Notify HOOK_CHIPSET_RESET */ - hook_call_deferred(&lpc_chipset_reset_data, MSEC); -#endif - } - - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); - - /* Clear interrupt source */ - MEC1322_INT_SOURCE(19) = BIT(1); - } -} -DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1); - -void emi_interrupt(void) -{ - port_80_write(MEC1322_EMI_H2E_MBX); -} -DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1); - -/* - * Port80 POST code polling limitation: - * - POST code 0xFF is ignored. - */ -int port_80_read(void) -{ - int data; - - /* read MBX_INDEX for POST code */ - data = MEC1322_MBX_INDEX; - - /* clear MBX_INDEX for next POST code*/ - MEC1322_MBX_INDEX = 0xff; - - /* mark POST code 0xff as invalid */ - if (data == 0xff) - data = PORT_80_IGNORE; - - return data; -} - -void acpi_0_interrupt(void) -{ - uint8_t value, result, is_cmd; - - is_cmd = MEC1322_ACPI_EC_STATUS(0) & EC_LPC_STATUS_LAST_CMD; - - /* Set the bust bi */ - MEC1322_ACPI_EC_STATUS(0) |= EC_LPC_STATUS_PROCESSING; - - /* Read command/data; this clears the FRMH bit. */ - value = MEC1322_ACPI_EC_OS2EC(0, 0); - - /* Handle whatever this was. */ - if (acpi_ap_to_ec(is_cmd, value, &result)) - MEC1322_ACPI_EC_EC2OS(0, 0) = result; - - /* Clear the busy bit */ - MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; - - /* - * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer - * Full condition on the kernel channel. - */ - lpc_generate_sci(); -} -DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1); - -void acpi_1_interrupt(void) -{ - uint8_t st = MEC1322_ACPI_EC_STATUS(1); - if (!(st & EC_LPC_STATUS_FROM_HOST) || - !(st & EC_LPC_STATUS_LAST_CMD)) - return; - - /* Set the busy bit */ - MEC1322_ACPI_EC_STATUS(1) |= EC_LPC_STATUS_PROCESSING; - - /* - * Read the command byte. This clears the FRMH bit in - * the status byte. - */ - host_cmd_args.command = MEC1322_ACPI_EC_OS2EC(1, 0); - - host_cmd_args.result = EC_RES_SUCCESS; - host_cmd_flags = lpc_host_args->flags; - - /* We only support new style command (v3) now */ - if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) { - lpc_packet.send_response = lpc_send_response_packet; - - lpc_packet.request = (const void *)lpc_get_hostcmd_data_range(); - lpc_packet.request_temp = params_copy; - lpc_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE; - - lpc_packet.response = (void *)lpc_get_hostcmd_data_range(); - lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE; - lpc_packet.response_size = 0; - - lpc_packet.driver_result = EC_RES_SUCCESS; - host_packet_receive(&lpc_packet); - return; - } else { - /* Old style command unsupported */ - host_cmd_args.result = EC_RES_INVALID_COMMAND; - } - - /* Hand off to host command handler */ - host_command_received(&host_cmd_args); -} -DECLARE_IRQ(MEC1322_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1); - -#ifdef HAS_TASK_KEYPROTO -void kb_ibf_interrupt(void) -{ - if (lpc_keyboard_input_pending()) - keyboard_host_write(MEC1322_8042_H2E, - MEC1322_8042_STS & BIT(3)); - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); - -void kb_obf_interrupt(void) -{ - task_wake(TASK_ID_KEYPROTO); -} -DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1); -#endif - -int lpc_keyboard_has_char(void) -{ - return (MEC1322_8042_STS & BIT(0)) ? 1 : 0; -} - -int lpc_keyboard_input_pending(void) -{ - return (MEC1322_8042_STS & BIT(1)) ? 1 : 0; -} - -void lpc_keyboard_put_char(uint8_t chr, int send_irq) -{ - MEC1322_8042_E2H = chr; - if (send_irq) - keyboard_irq_assert(); -} - -void lpc_keyboard_clear_buffer(void) -{ - volatile char dummy __attribute__((unused)); - - dummy = MEC1322_8042_OBF_CLR; -} - -void lpc_keyboard_resume_irq(void) -{ - if (lpc_keyboard_has_char()) - keyboard_irq_assert(); -} - -void lpc_set_acpi_status_mask(uint8_t mask) -{ - MEC1322_ACPI_EC_STATUS(0) |= mask; -} - -void lpc_clear_acpi_status_mask(uint8_t mask) -{ - MEC1322_ACPI_EC_STATUS(0) &= ~mask; -} - -int lpc_get_pltrst_asserted(void) -{ - return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0; -} - -/* Enable LPC ACPI-EC0 interrupts */ -void lpc_enable_acpi_interrupts(void) -{ - task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); -} - -/* Disable LPC ACPI-EC0 interrupts */ -void lpc_disable_acpi_interrupts(void) -{ - task_disable_irq(MEC1322_IRQ_ACPIEC0_IBF); -} - -/* On boards without a host, this command is used to set up LPC */ -static int lpc_command_init(int argc, char **argv) -{ - lpc_init(); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(lpcinit, lpc_command_init, NULL, NULL); - -/* Get protocol information */ -static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions = BIT(3); - r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; - r->flags = 0; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c deleted file mode 100644 index df4583ed8b..0000000000 --- a/chip/mec1322/port80.c +++ /dev/null @@ -1,104 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Port 80 Timer Interrupt for MEC1322 */ - -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "lpc.h" -#include "port80.h" -#include "registers.h" -#include "task.h" - -/* Fire timer interrupt every 1000 usec to check for port80 data. */ -#define POLL_PERIOD_USEC 1000 -/* After 30 seconds of no port 80 data, disable the timer interrupt. */ -#define INTERRUPT_DISABLE_TIMEOUT_SEC 30 -#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \ - * 1000000 \ - / POLL_PERIOD_USEC) - -/* Count the number of consecutive interrupts with no port 80 data. */ -static int idle_count; - -static void port_80_interrupt_enable(void) -{ - idle_count = 0; - - /* Enable the interrupt. */ - task_enable_irq(MEC1322_IRQ_TIMER16_1); - /* Enable and start the timer. */ - MEC1322_TMR16_CTL(1) |= 1 | BIT(5); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); - -static void port_80_interrupt_disable(void) -{ - /* Disable the timer block. */ - MEC1322_TMR16_CTL(1) &= ~1; - /* Disable the interrupt. */ - task_disable_irq(MEC1322_IRQ_TIMER16_1); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable, - HOOK_PRIO_DEFAULT); - -/* - * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown - * timer. This timer is on GIRQ23, bit 1. - */ -static void port_80_interrupt_init(void) -{ - uint32_t val = 0; - - /* - * The timers are driven by a 48MHz oscillator. Prescale down to - * 1MHz. 48MHz/48 -> 1MHz - */ - val = MEC1322_TMR16_CTL(1); - val = (val & 0xFFFF) | (47 << 16); - /* Automatically restart the timer. */ - val |= BIT(3); - /* The counter should decrement. */ - val &= ~BIT(2); - MEC1322_TMR16_CTL(1) = val; - - /* Set the reload value(us). */ - MEC1322_TMR16_PRE(1) = POLL_PERIOD_USEC; - - /* Clear the status if any. */ - MEC1322_TMR16_STS(1) |= 1; - - /* Clear any pending interrupt. */ - MEC1322_INT_SOURCE(23) = BIT(1); - /* Enable IRQ vector 23. */ - MEC1322_INT_BLK_EN |= BIT(23); - /* Enable the interrupt. */ - MEC1322_TMR16_IEN(1) |= 1; - MEC1322_INT_ENABLE(23) = BIT(1); - - port_80_interrupt_enable(); -} -DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT); - -void port_80_interrupt(void) -{ - int data; - - MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */ - if (BIT(1) & MEC1322_INT_RESULT(23)) { - data = port_80_read(); - - if (data != PORT_80_IGNORE) { - idle_count = 0; - port_80_write(data); - } - } - - if (++idle_count >= INTERRUPT_DISABLE_IDLE_COUNT) - port_80_interrupt_disable(); -} -DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2); diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c deleted file mode 100644 index ce94e50e7e..0000000000 --- a/chip/mec1322/pwm.c +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for MEC1322 */ - -#include "hooks.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "util.h" - -/* - * PWMs that must remain active in low-power idle - MEC1322_PCR_EC_SLP_EN - * bit mask. - */ -static uint32_t pwm_keep_awake_mask; - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - int id = pwm_channels[ch].channel; - - if (enabled) { - MEC1322_PWM_CFG(id) |= 0x1; - if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) - pwm_keep_awake_mask |= - MEC1322_PCR_EC_SLP_EN_PWM(id); - } else { - MEC1322_PWM_CFG(id) &= ~0x1; - pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id); - } -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - return MEC1322_PWM_CFG(pwm_channels[ch].channel) & 0x1; -} - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - int id = pwm_channels[ch].channel; - - if (percent < 0) - percent = 0; - else if (percent > 100) - percent = 100; - - MEC1322_PWM_ON(id) = percent; - MEC1322_PWM_OFF(id) = 100 - percent; -} - -int pwm_get_duty(enum pwm_channel ch) -{ - return MEC1322_PWM_ON(pwm_channels[ch].channel); -} - -uint32_t pwm_get_keep_awake_mask(void) -{ - return pwm_keep_awake_mask; -} - -static void pwm_configure(int ch, int active_low, int clock_low) -{ - /* - * clock_low=0 selects the 48MHz Ring Oscillator source - * clock_low=1 selects the 100kHz_Clk source - */ - MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? BIT(2) : 0) | - (clock_low ? BIT(1) : 0); -} - -static void pwm_init(void) -{ - int i; - - for (i = 0; i < PWM_CH_COUNT; ++i) { - pwm_configure(pwm_channels[i].channel, - pwm_channels[i].flags & PWM_CONFIG_ACTIVE_LOW, - pwm_channels[i].flags & PWM_CONFIG_ALT_CLOCK); - pwm_set_duty(i, 0); - } -} -DECLARE_HOOK(HOOK_INIT, pwm_init, HOOK_PRIO_INIT_PWM); diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h deleted file mode 100644 index 9c441aaecd..0000000000 --- a/chip/mec1322/pwm_chip.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* MEC1322-specific PWM module for Chrome EC */ -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* PWM Channel ID */ - int channel; - - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; -}; - -extern const struct pwm_t pwm_channels[]; - -/* - * Returns PWMs that must remain active in low-power idle - - * MEC1322_PCR_EC_SLP_EN bit mask. - */ -uint32_t pwm_get_keep_awake_mask(void); -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h deleted file mode 100644 index 7e5bbc7cea..0000000000 --- a/chip/mec1322/registers.h +++ /dev/null @@ -1,505 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for MEC1322 processor - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" - -/* Helper function for RAM address aliasing */ -#define MEC1322_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) - -/* EC Chip Configuration */ -#define MEC1322_CHIP_BASE 0x400fff00 -#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20) -#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21) - - -/* Power/Clocks/Resets */ -#define MEC1322_PCR_BASE 0x40080100 -#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0) -#define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4) -#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8) -/* Command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 -#define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) -#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) -#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10) -/* Command all blocks to sleep */ -#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003 -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003) -#define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14) -#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18) -#define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20) -#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24) -/* Mask to command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8 -/* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8) -#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28) -#define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c) -#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30) -#define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34) -#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38) -#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c) -#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40) -#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) -#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) - -/* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ -#define MEC1322_PWR_RST_STS_VCC1 BIT(6) -#define MEC1322_PWR_RST_STS_VBAT BIT(5) - -/* EC Subsystem */ -#define MEC1322_EC_BASE 0x4000fc00 -#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18) -#define MEC1322_EC_TRACE_EN REG32(MEC1322_EC_BASE + 0x1c) -#define MEC1322_EC_JTAG_EN REG32(MEC1322_EC_BASE + 0x20) -#define MEC1322_EC_WDT_CNT REG32(MEC1322_EC_BASE + 0x28) -#define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38) - -/* Interrupt aggregator */ -#define MEC1322_INT_BASE 0x4000c000 -#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x) - 8) * 0x14) -#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0) -#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4) -#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8) -#define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc) -#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200) -#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204) -#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208) - - -/* UART */ -#define MEC1322_UART_CONFIG_BASE 0x400f1f00 -#define MEC1322_UART_RUNTIME_BASE 0x400f1c00 - -#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30) -#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0) - -/* DLAB=0 */ -#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1) -/* DLAB=1 */ -#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1) - -#define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) -#define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) -#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3) -#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4) -#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5) -#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6) -#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) - -/* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY BIT(5) - -/* GPIO */ -#define MEC1322_GPIO_BASE 0x40081000 - -static inline uintptr_t gpio_port_base(int port_id) -{ - int oct = (port_id / 10) * 8 + port_id % 10; - return MEC1322_GPIO_BASE + oct * 0x20; -} -#define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2)) - -#define DUMMY_GPIO_BANK 0 - - -/* Timer */ -#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x) * 0x20) -#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x) * 0x20) - -#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0) -#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4) -#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8) -#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc) -#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10) -#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0) -#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4) -#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8) -#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc) -#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10) - - -/* Watchdog */ -#define MEC1322_WDG_BASE 0x40000400 -#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0) -#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4) -#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8) -#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc) - - -/* VBAT */ -#define MEC1322_VBAT_BASE 0x4000a400 -#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0) -#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8) -#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) - -/* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT BIT(5) - -/* Miscellaneous firmware control fields - * scratch pad index cannot be more than 16 as - * mec has 64 bytes = 16 indexes of scratchpad RAM - */ -#define MEC1322_IMAGETYPE_IDX 15 - -/* LPC */ -#define MEC1322_LPC_CFG_BASE 0x400f3300 -#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30) -#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x)) -#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60) -#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64) -#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68) -#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78) -#define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88) -#define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c) -#define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90) -#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94) -#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98) -#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c) -#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0) -#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4) - -#define MEC1322_LPC_RT_BASE 0x400f3100 -#define MEC1322_LPC_BUS_MONITOR REG32(MEC1322_LPC_RT_BASE + 0x4) -#define MEC1322_LPC_CLK_CTRL REG32(MEC1322_LPC_RT_BASE + 0x10) -#define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc) - - -/* EMI */ -#define MEC1322_EMI_BASE 0x400f0100 -#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0) -#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1) -#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4) -#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8) -#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa) -#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc) -#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10) -#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12) -#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14) -#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16) - -#define MEC1322_EMI_RT_BASE 0x400f0000 -#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8) -#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9) -#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa) -#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb) - - -/* Mailbox */ -#define MEC1322_MBX_RT_BASE 0x400f2400 -#define MEC1322_MBX_INDEX REG8(MEC1322_MBX_RT_BASE + 0x0) -#define MEC1322_MBX_DATA REG8(MEC1322_MBX_RT_BASE + 0x1) - -#define MEC1322_MBX_BASE 0x400f2500 -#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0) -#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4) -#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8) -#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) -#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) - - -/* PWM */ -#define MEC1322_PWM_BASE(x) (0x40005800 + (x) * 0x10) -#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00) -#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04) -#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08) - - -/* ACPI */ -#define MEC1322_ACPI_EC_BASE(x) (0x400f0c00 + (x) * 0x400) -#define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y)) -#define MEC1322_ACPI_EC_STATUS(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x104) -#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105) -#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y)) - -#define MEC1322_ACPI_PM_RT_BASE 0x400f1400 -#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0) -#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1) -#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2) -#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3) -#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4) -#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5) -#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6) -#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7) -#define MEC1322_ACPI_PM_EC_BASE 0x400f1500 -#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10) - - -/* 8042 */ -#define MEC1322_8042_BASE 0x400f0400 -#define MEC1322_8042_OBF_CLR REG8(MEC1322_8042_BASE + 0x0) -#define MEC1322_8042_H2E REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_E2H REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_STS REG8(MEC1322_8042_BASE + 0x104) -#define MEC1322_8042_KB_CTRL REG8(MEC1322_8042_BASE + 0x108) -#define MEC1322_8042_PCOBF REG8(MEC1322_8042_BASE + 0x114) -#define MEC1322_8042_ACT REG8(MEC1322_8042_BASE + 0x330) - - -/* FAN */ -#define MEC1322_FAN_BASE 0x4000a000 -#define MEC1322_FAN_SETTING REG8(MEC1322_FAN_BASE + 0x0) -#define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1) -#define MEC1322_FAN_CFG1 REG8(MEC1322_FAN_BASE + 0x2) -#define MEC1322_FAN_CFG2 REG8(MEC1322_FAN_BASE + 0x3) -#define MEC1322_FAN_GAIN REG8(MEC1322_FAN_BASE + 0x5) -#define MEC1322_FAN_SPIN_UP REG8(MEC1322_FAN_BASE + 0x6) -#define MEC1322_FAN_STEP REG8(MEC1322_FAN_BASE + 0x7) -#define MEC1322_FAN_MIN_DRV REG8(MEC1322_FAN_BASE + 0x8) -#define MEC1322_FAN_VALID_CNT REG8(MEC1322_FAN_BASE + 0x9) -#define MEC1322_FAN_DRV_FAIL REG16(MEC1322_FAN_BASE + 0xa) -#define MEC1322_FAN_TARGET REG16(MEC1322_FAN_BASE + 0xc) -#define MEC1322_FAN_READING REG16(MEC1322_FAN_BASE + 0xe) -#define MEC1322_FAN_BASE_FREQ REG8(MEC1322_FAN_BASE + 0x10) -#define MEC1322_FAN_STATUS REG8(MEC1322_FAN_BASE + 0x11) - - -/* I2C */ -#define MEC1322_I2C0_BASE 0x40001800 -#define MEC1322_I2C1_BASE 0x4000ac00 -#define MEC1322_I2C2_BASE 0x4000b000 -#define MEC1322_I2C3_BASE 0x4000b400 -#define MEC1322_I2C_BASESEP 0x00000400 -#define MEC1322_I2C_ADDR(controller, offset) \ - (offset + (controller == 0 ? MEC1322_I2C0_BASE : \ - MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1))) - -/* - * MEC1322 has five ports distributed among four controllers. Locking must - * occur by-controller (not by-port). - */ -enum mec1322_i2c_port { - MEC1322_I2C0_0 = 0, /* Controller 0, port 0 */ - MEC1322_I2C0_1 = 1, /* Controller 0, port 1 */ - MEC1322_I2C1 = 2, /* Controller 1 */ - MEC1322_I2C2 = 3, /* Controller 2 */ - MEC1322_I2C3 = 4, /* Controller 3 */ - MEC1322_I2C_PORT_COUNT, -}; - -#define MEC1322_I2C_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_STATUS(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_OWN_ADDR(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x4)) -#define MEC1322_I2C_DATA(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x8)) -#define MEC1322_I2C_MASTER_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0xc)) -#define MEC1322_I2C_SLAVE_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x10)) -#define MEC1322_I2C_PEC(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x14)) -#define MEC1322_I2C_DATA_TIM_2(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x18)) -#define MEC1322_I2C_COMPLETE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x20)) -#define MEC1322_I2C_IDLE_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x24)) -#define MEC1322_I2C_CONFIG(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x28)) -#define MEC1322_I2C_BUS_CLK(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x2c)) -#define MEC1322_I2C_BLK_ID(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x30)) -#define MEC1322_I2C_REV(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x34)) -#define MEC1322_I2C_BB_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x38)) -#define MEC1322_I2C_DATA_TIM(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x40)) -#define MEC1322_I2C_TOUT_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x44)) -#define MEC1322_I2C_SLAVE_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x48)) -#define MEC1322_I2C_SLAVE_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x4c)) -#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50)) -#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54)) - - -/* Keyboard scan matrix */ -#define MEC1322_KS_BASE 0x40009c00 -#define MEC1322_KS_KSO_SEL REG32(MEC1322_KS_BASE + 0x4) -#define MEC1322_KS_KSI_INPUT REG32(MEC1322_KS_BASE + 0x8) -#define MEC1322_KS_KSI_STATUS REG32(MEC1322_KS_BASE + 0xc) -#define MEC1322_KS_KSI_INT_EN REG32(MEC1322_KS_BASE + 0x10) -#define MEC1322_KS_EXT_CTRL REG32(MEC1322_KS_BASE + 0x14) - - -/* ADC */ -#define MEC1322_ADC_BASE 0x40007c00 -#define MEC1322_ADC_CTRL REG32(MEC1322_ADC_BASE + 0x0) -#define MEC1322_ADC_DELAY REG32(MEC1322_ADC_BASE + 0x4) -#define MEC1322_ADC_STS REG32(MEC1322_ADC_BASE + 0x8) -#define MEC1322_ADC_SINGLE REG32(MEC1322_ADC_BASE + 0xc) -#define MEC1322_ADC_REPEAT REG32(MEC1322_ADC_BASE + 0x10) -#define MEC1322_ADC_READ(x) REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4) - - -/* Hibernation timer */ -#define MEC1322_HTIMER_BASE 0x40009800 -#define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0) -#define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4) -#define MEC1322_HTIMER_COUNT REG16(MEC1322_HTIMER_BASE + 0x8) - - -/* SPI */ -#define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port)) -#define MEC1322_SPI_AR(port) REG8(MEC1322_SPI_BASE(port) + 0x00) -#define MEC1322_SPI_CR(port) REG8(MEC1322_SPI_BASE(port) + 0x04) -#define MEC1322_SPI_SR(port) REG8(MEC1322_SPI_BASE(port) + 0x08) -#define MEC1322_SPI_TD(port) REG8(MEC1322_SPI_BASE(port) + 0x0c) -#define MEC1322_SPI_RD(port) REG8(MEC1322_SPI_BASE(port) + 0x10) -#define MEC1322_SPI_CC(port) REG8(MEC1322_SPI_BASE(port) + 0x14) -#define MEC1322_SPI_CG(port) REG8(MEC1322_SPI_BASE(port) + 0x18) - - -/* DMA */ -#define MEC1322_DMA_BASE 0x40002400 - -/* - * Available DMA channels. - * - * On MEC1322, any DMA channel may serve any device. Since we have - * 12 channels and 12 devices, we make each channel dedicated to the - * device of the same number. - */ -enum dma_channel { - /* Channel numbers */ - MEC1322_DMAC_I2C0_SLAVE = 0, - MEC1322_DMAC_I2C0_MASTER = 1, - MEC1322_DMAC_I2C1_SLAVE = 2, - MEC1322_DMAC_I2C1_MASTER = 3, - MEC1322_DMAC_I2C2_SLAVE = 4, - MEC1322_DMAC_I2C2_MASTER = 5, - MEC1322_DMAC_I2C3_SLAVE = 6, - MEC1322_DMAC_I2C3_MASTER = 7, - MEC1322_DMAC_SPI0_TX = 8, - MEC1322_DMAC_SPI0_RX = 9, - MEC1322_DMAC_SPI1_TX = 10, - MEC1322_DMAC_SPI1_RX = 11, - - /* Channel count */ - MEC1322_DMAC_COUNT = 12, -}; - -/* Registers for a single channel of the DMA controller */ -struct mec1322_dma_chan { - uint32_t act; /* Activate */ - uint32_t mem_start; /* Memory start address */ - uint32_t mem_end; /* Memory end address */ - uint32_t dev; /* Device address */ - uint32_t ctrl; /* Control */ - uint32_t int_status; /* Interrupt status */ - uint32_t int_enabled; /* Interrupt enabled */ - uint32_t pad; -}; - -/* Always use mec1322_dma_chan_t so volatile keyword is included! */ -typedef volatile struct mec1322_dma_chan mec1322_dma_chan_t; - -/* Common code and header file must use this */ -typedef mec1322_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct mec1322_dma_regs { - uint32_t ctrl; - uint32_t data; - uint32_t pad[2]; - mec1322_dma_chan_t chan[MEC1322_DMAC_COUNT]; -}; - -/* Always use mec1322_dma_regs_t so volatile keyword is included! */ -typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; - -#define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) - -/* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN BIT(0) -#define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV BIT(17) -#define MEC1322_DMA_INC_MEM BIT(16) -#define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV BIT(8) -#define MEC1322_DMA_DONE BIT(2) -#define MEC1322_DMA_RUN BIT(0) - - -/* IRQ Numbers */ -#define MEC1322_IRQ_I2C_0 0 -#define MEC1322_IRQ_I2C_1 1 -#define MEC1322_IRQ_I2C_2 2 -#define MEC1322_IRQ_I2C_3 3 -#define MEC1322_IRQ_DMA_0 4 -#define MEC1322_IRQ_DMA_1 5 -#define MEC1322_IRQ_DMA_2 6 -#define MEC1322_IRQ_DMA_3 7 -#define MEC1322_IRQ_DMA_4 8 -#define MEC1322_IRQ_DMA_5 9 -#define MEC1322_IRQ_DMA_6 10 -#define MEC1322_IRQ_DMA_7 11 -#define MEC1322_IRQ_LPC 12 -#define MEC1322_IRQ_UART 13 -#define MEC1322_IRQ_EMI 14 -#define MEC1322_IRQ_ACPIEC0_IBF 15 -#define MEC1322_IRQ_ACPIEC0_OBF 16 -#define MEC1322_IRQ_ACPIEC1_IBF 17 -#define MEC1322_IRQ_ACPIEC1_OBF 18 -#define MEC1322_IRQ_ACPIPM1_CTL 19 -#define MEC1322_IRQ_ACPIPM1_EN 20 -#define MEC1322_IRQ_ACPIPM1_STS 21 -#define MEC1322_IRQ_8042EM_OBF 22 -#define MEC1322_IRQ_8042EM_IBF 23 -#define MEC1322_IRQ_MAILBOX 24 -#define MEC1322_IRQ_PECI_HOST 25 -#define MEC1322_IRQ_TACH_0 26 -#define MEC1322_IRQ_TACH_1 27 -#define MEC1322_IRQ_ADC_SNGL 28 -#define MEC1322_IRQ_ADC_RPT 29 -#define MEC1322_IRQ_PS2_0 32 -#define MEC1322_IRQ_PS2_1 33 -#define MEC1322_IRQ_PS2_2 34 -#define MEC1322_IRQ_PS2_3 35 -#define MEC1322_IRQ_SPI0_TX 36 -#define MEC1322_IRQ_SPI0_RX 37 -#define MEC1322_IRQ_HTIMER 38 -#define MEC1322_IRQ_KSC_INT 39 -#define MEC1322_IRQ_MAILBOX_DATA 40 -#define MEC1322_IRQ_TIMER16_0 49 -#define MEC1322_IRQ_TIMER16_1 50 -#define MEC1322_IRQ_TIMER16_2 51 -#define MEC1322_IRQ_TIMER16_3 52 -#define MEC1322_IRQ_TIMER32_0 53 -#define MEC1322_IRQ_TIMER32_1 54 -#define MEC1322_IRQ_SPI1_TX 55 -#define MEC1322_IRQ_SPI1_RX 56 -#define MEC1322_IRQ_GIRQ8 57 -#define MEC1322_IRQ_GIRQ9 58 -#define MEC1322_IRQ_GIRQ10 59 -#define MEC1322_IRQ_GIRQ11 60 -#define MEC1322_IRQ_GIRQ12 61 -#define MEC1322_IRQ_GIRQ13 62 -#define MEC1322_IRQ_GIRQ14 63 -#define MEC1322_IRQ_GIRQ15 64 -#define MEC1322_IRQ_GIRQ16 65 -#define MEC1322_IRQ_GIRQ17 66 -#define MEC1322_IRQ_GIRQ18 67 -#define MEC1322_IRQ_GIRQ19 68 -#define MEC1322_IRQ_GIRQ20 69 -#define MEC1322_IRQ_GIRQ21 70 -#define MEC1322_IRQ_GIRQ22 71 -#define MEC1322_IRQ_GIRQ23 72 -#define MEC1322_IRQ_DMA_8 81 -#define MEC1322_IRQ_DMA_9 82 -#define MEC1322_IRQ_DMA_10 83 -#define MEC1322_IRQ_DMA_11 84 -#define MEC1322_IRQ_PWM_WDT3 85 -#define MEC1322_IRQ_RTC 91 -#define MEC1322_IRQ_RTC_ALARM 92 - -/* Wake pin definitions, defined at board-level */ -extern const enum gpio_signal hibernate_wake_pins[]; -extern const int hibernate_wake_pins_used; - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c deleted file mode 100644 index 834fbd10b1..0000000000 --- a/chip/mec1322/spi.c +++ /dev/null @@ -1,176 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SPI master module for MEC1322 */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "registers.h" -#include "spi.h" -#include "timer.h" -#include "util.h" -#include "hooks.h" -#include "task.h" - -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -#define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) -#define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 - -#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2) - -/* only regular image needs mutex, LFW does not have scheduling */ -/* TODO: Move SPI locking to common code */ -#ifndef LFW -static struct mutex spi_mutex; -#endif - -static const struct dma_option spi_rx_option[] = { - { - SPI_DMA_CHANNEL(0), - (void *)&MEC1322_SPI_RD(0), - MEC1322_DMA_XFER_SIZE(1) - }, - { - SPI_DMA_CHANNEL(1), - (void *)&MEC1322_SPI_RD(1), - MEC1322_DMA_XFER_SIZE(1) - }, -}; - -static int wait_byte(const int port) -{ - timestamp_t deadline; - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - while ((MEC1322_SPI_SR(port) & 0x3) != 0x3) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - return EC_SUCCESS; -} - -static int spi_tx(const int port, const uint8_t *txdata, int txlen) -{ - int i; - int ret = EC_SUCCESS; - uint8_t dummy __attribute__((unused)) = 0; - - for (i = 0; i < txlen; ++i) { - MEC1322_SPI_TD(port) = txdata[i]; - ret = wait_byte(port); - if (ret != EC_SUCCESS) - return ret; - dummy = MEC1322_SPI_RD(port); - } - - return ret; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int port = spi_device->port; - int ret = EC_SUCCESS; - - gpio_set_level(spi_device->gpio_cs, 0); - - /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~BIT(5); - - ret = spi_tx(port, txdata, txlen); - if (ret != EC_SUCCESS) - return ret; - - /* Enable auto read */ - MEC1322_SPI_CR(port) |= BIT(5); - - if (rxlen != 0) { - dma_start_rx(&spi_rx_option[port], rxlen, rxdata); - MEC1322_SPI_TD(port) = 0; - } - return ret; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int port = spi_device->port; - int ret = dma_wait(SPI_DMA_CHANNEL(port)); - uint8_t dummy __attribute__((unused)) = 0; - - timestamp_t deadline; - - /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~BIT(5); - - deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; - /* Wait for FIFO empty SPISR_TXBE */ - while ((MEC1322_SPI_SR(port) & 0x01) != 0x1) { - if (timestamp_expired(deadline, NULL)) - return EC_ERROR_TIMEOUT; - usleep(SPI_BYTE_TRANSFER_POLL_INTERVAL_US); - } - - dma_disable(SPI_DMA_CHANNEL(port)); - dma_clear_isr(SPI_DMA_CHANNEL(port)); - if (MEC1322_SPI_SR(port) & 0x2) - dummy = MEC1322_SPI_RD(port); - - gpio_set_level(spi_device->gpio_cs, 1); - - return ret; -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int ret; - -#ifndef LFW - mutex_lock(&spi_mutex); -#endif - ret = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - if (ret) - return ret; - ret = spi_transaction_flush(spi_device); - -#ifndef LFW - mutex_unlock(&spi_mutex); -#endif - return ret; -} - -int spi_enable(int port, int enable) -{ - if (enable) { - gpio_config_module(MODULE_SPI, 1); - - /* Set enable bit in SPI_AR */ - MEC1322_SPI_AR(port) |= 0x1; - - /* Set SPDIN to 0 -> Full duplex */ - MEC1322_SPI_CR(port) &= ~(0x3 << 2); - - /* Set CLKPOL, TCLKPH, RCLKPH to 0 */ - MEC1322_SPI_CC(port) &= ~0x7; - - /* Set LSBF to 0 -> MSB first */ - MEC1322_SPI_CR(port) &= ~0x1; - } else { - /* Clear enable bit in SPI_AR */ - MEC1322_SPI_AR(port) &= ~0x1; - - gpio_config_module(MODULE_SPI, 0); - } - - return EC_SUCCESS; -} - diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c deleted file mode 100644 index 6dac6abfc6..0000000000 --- a/chip/mec1322/system.c +++ /dev/null @@ -1,393 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : MEC1322 hardware specific implementation */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "gpio.h" -#include "host_command.h" -#include "registers.h" -#include "shared_mem.h" -#include "system.h" -#include "hooks.h" -#include "task.h" -#include "timer.h" -#include "usb_pd.h" -#include "util.h" -#include "spi.h" - -/* Indices for hibernate data registers (RAM backed by VBAT) */ -enum hibdata_index { - HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ - HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ - HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ - HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ -}; - -static void check_reset_cause(void) -{ - uint32_t status = MEC1322_VBAT_STS; - uint32_t flags = 0; - uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & - (MEC1322_PWR_RST_STS_VCC1 | - MEC1322_PWR_RST_STS_VBAT); - - /* Clear the reset causes now that we've read them */ - MEC1322_VBAT_STS |= status; - MEC1322_PCR_CHIP_PWR_RST |= rst_sts; - - /* - * BIT[6] determine VCC1 reset - */ - if (rst_sts & MEC1322_PWR_RST_STS_VCC1) - flags |= EC_RESET_FLAG_RESET_PIN; - - - flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); - MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; - - if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) - flags |= EC_RESET_FLAG_WATCHDOG; - - system_set_reset_flags(flags); -} - -int system_is_reboot_warm(void) -{ - uint32_t reset_flags; - /* - * Check reset cause here, - * gpio_pre_init is executed faster than system_pre_init - */ - check_reset_cause(); - reset_flags = system_get_reset_flags(); - - if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT) || - (reset_flags & EC_RESET_FLAG_HIBERNATE)) - return 0; - else - return 1; -} - -void system_pre_init(void) -{ - /* Enable direct NVIC */ - MEC1322_EC_INT_CTRL |= 1; - - /* Disable ARM TRACE debug port */ - MEC1322_EC_TRACE_EN &= ~1; - - /* Deassert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL &= ~BIT(0); - - spi_enable(CONFIG_SPI_FLASH_PORT, 1); -} - -void chip_save_reset_flags(uint32_t flags) -{ - MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = flags; -} - -uint32_t chip_read_reset_flags(void) -{ - return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); -} - -__attribute__((noreturn)) -void _system_reset(int flags, int wake_from_hibernate) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - if (wake_from_hibernate) - save_flags |= EC_RESET_FLAG_HIBERNATE; - else if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - else - save_flags |= EC_RESET_FLAG_SOFT; - - chip_save_reset_flags(save_flags); - - /* Trigger watchdog in 1ms */ - MEC1322_WDG_LOAD = 1; - MEC1322_WDG_CTL |= 1; - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -void system_reset(int flags) -{ - _system_reset(flags, 0); -} - -const char *system_get_chip_vendor(void) -{ - return "smsc"; -} - -const char *system_get_chip_name(void) -{ - switch (MEC1322_CHIP_DEV_ID) { - case 0x15: - return "mec1322"; - default: - return "unknown"; - } -} - -static char to_hex(int x) -{ - if (x >= 0 && x <= 9) - return '0' + x; - return 'a' + x - 10; -} - -const char *system_get_chip_revision(void) -{ - static char buf[3]; - uint8_t rev = MEC1322_CHIP_DEV_REV; - - buf[0] = to_hex(rev / 16); - buf[1] = to_hex(rev & 0xf); - buf[2] = '\0'; - return buf; -} - -static int bbram_idx_lookup(enum system_bbram_idx idx) -{ - switch (idx) { - case SYSTEM_BBRAM_IDX_PD0: - return HIBDATA_INDEX_PD0; - case SYSTEM_BBRAM_IDX_PD1: - return HIBDATA_INDEX_PD1; - case SYSTEM_BBRAM_IDX_PD2: - return HIBDATA_INDEX_PD2; - default: - return -1; - } -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - *value = MEC1322_VBAT_RAM(hibdata); - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - int hibdata = bbram_idx_lookup(idx); - - if (hibdata < 0) - return EC_ERROR_UNIMPLEMENTED; - - MEC1322_VBAT_RAM(hibdata) = value; - return EC_SUCCESS; -} - -int system_set_scratchpad(uint32_t value) -{ - MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD) = value; - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - return MEC1322_VBAT_RAM(HIBDATA_INDEX_SCRATCHPAD); -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* Disable interrupts */ - interrupt_disable(); - for (i = 0; i <= 92; ++i) { - task_disable_irq(i); - task_clear_pending_irq(i); - } - - for (i = 8; i <= 23; ++i) - MEC1322_INT_DISABLE(i) = 0xffffffff; - - MEC1322_INT_BLK_DIS |= 0xffff00; - - /* Power down ADC VREF */ - MEC1322_EC_ADC_VREF_PD |= 1; - - /* Assert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL |= 1; - - /* Disable UART */ - MEC1322_UART_ACT &= ~0x1; - MEC1322_LPC_ACT &= ~0x1; - - /* Disable JTAG */ - MEC1322_EC_JTAG_EN &= ~1; - - /* Disable 32KHz clock */ - MEC1322_VBAT_CE &= ~0x2; - - /* Stop watchdog */ - MEC1322_WDG_CTL &= ~1; - - /* Stop timers */ - MEC1322_TMR32_CTL(0) &= ~1; - MEC1322_TMR32_CTL(1) &= ~1; - MEC1322_TMR16_CTL(0) &= ~1; - - /* Power down ADC */ - MEC1322_ADC_CTRL &= ~1; - - /* Disable blocks */ - MEC1322_PCR_CHIP_SLP_EN |= 0x3; - MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP; - MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; - MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; - MEC1322_PCR_SLOW_CLK_CTL &= 0xfffffc00; - - /* Set sleep state */ - MEC1322_PCR_SYS_SLP_CTL = (MEC1322_PCR_SYS_SLP_CTL & ~0x7) | 0x2; - CPU_SCB_SYSCTRL |= 0x4; - - /* Setup GPIOs for hibernate */ - if (board_hibernate_late) - board_hibernate_late(); - -#ifdef CONFIG_USB_PD_PORT_MAX_COUNT - /* - * Leave USB-C charging enabled in hibernate, in order to - * allow wake-on-plug. 5V enable must be pulled low. - */ - switch (board_get_usb_pd_port_count()) { -#if CONFIG_USB_PD_PORT_MAX_COUNT >= 2 - case 2: - gpio_set_flags(GPIO_USB_C1_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT); - gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 0); - /* Fall through */ -#endif -#if CONFIG_USB_PD_PORT_MAX_COUNT >= 1 - case 1: - gpio_set_flags(GPIO_USB_C0_5V_EN, GPIO_PULL_DOWN | GPIO_INPUT); - gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0); - /* Fall through */ -#endif - case 0: - /* Nothing to do but break */ - break; - default: - /* More ports needs to be defined */ - ASSERT(false); - break; - } -#endif /* CONFIG_USB_PD_PORT_MAX_COUNT */ - - if (hibernate_wake_pins_used > 0) { - for (i = 0; i < hibernate_wake_pins_used; ++i) { - const enum gpio_signal pin = hibernate_wake_pins[i]; - - gpio_reset(pin); - gpio_enable_interrupt(pin); - } - - interrupt_enable(); - task_enable_irq(MEC1322_IRQ_GIRQ8); - task_enable_irq(MEC1322_IRQ_GIRQ9); - task_enable_irq(MEC1322_IRQ_GIRQ10); - task_enable_irq(MEC1322_IRQ_GIRQ11); - task_enable_irq(MEC1322_IRQ_GIRQ20); - } - - if (seconds || microseconds) { - MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_INT_ENABLE(17) |= BIT(20); - interrupt_enable(); - task_enable_irq(MEC1322_IRQ_HTIMER); - if (seconds > 2) { - ASSERT(seconds <= 0xffff / 8); - MEC1322_HTIMER_CONTROL = 1; - MEC1322_HTIMER_PRELOAD = - (seconds * 8 + microseconds / 125000); - } else { - MEC1322_HTIMER_CONTROL = 0; - MEC1322_HTIMER_PRELOAD = - (seconds * 1000000 + microseconds) * 2 / 71; - } - } - - asm("wfi"); - - /* Use 48MHz clock to speed through wake-up */ - MEC1322_PCR_PROC_CLK_CTL = 1; - - /* Reboot */ - _system_reset(0, 1); - - /* We should never get here. */ - while (1) - ; -} - -void htimer_interrupt(void) -{ - /* Time to wake up */ -} -DECLARE_IRQ(MEC1322_IRQ_HTIMER, htimer_interrupt, 1); - -enum system_image_copy_t system_get_shrspi_image_copy(void) -{ - return MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX); -} - -uint32_t system_get_lfw_address(void) -{ - uint32_t * const lfw_vector = - (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE; - - return *(lfw_vector + 1); -} - -void system_set_image_copy(enum system_image_copy_t copy) -{ - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == SYSTEM_IMAGE_RW) ? - SYSTEM_IMAGE_RW : SYSTEM_IMAGE_RO; -} diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c deleted file mode 100644 index 2c607d0b72..0000000000 --- a/chip/mec1322/uart.c +++ /dev/null @@ -1,220 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* UART module for MEC1322 */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "lpc.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -#define TX_FIFO_SIZE 16 - -static int init_done; -static int tx_fifo_used; - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (MEC1322_UART_IER & BIT(1)) - return; - - /* Do not allow deep sleep while transmit in progress */ - disable_sleep(SLEEP_MASK_UART); - - /* - * Re-enable the transmit interrupt, then forcibly trigger the - * interrupt. This works around a hardware problem with the - * UART where the FIFO only triggers the interrupt when its - * threshold is _crossed_, not just met. - */ - MEC1322_UART_IER |= BIT(1); - task_trigger_irq(MEC1322_IRQ_UART); -} - -void uart_tx_stop(void) -{ - MEC1322_UART_IER &= ~BIT(1); - - /* Re-allow deep sleep */ - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - /* Wait for transmit FIFO empty */ - while (!(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY)) - ; -} - -int uart_tx_ready(void) -{ - /* - * We have no indication of free space in transmit FIFO. To work around - * this, we check transmit FIFO empty bit every 16 characters written. - */ - return tx_fifo_used != 0 || (MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY); -} - -int uart_tx_in_progress(void) -{ - /* return 0: FIFO is empty, 1: FIFO NOT Empty */ - return !(MEC1322_UART_LSR & MEC1322_LSR_TX_EMPTY); -} - -int uart_rx_available(void) -{ - return MEC1322_UART_LSR & BIT(0); -} - -void uart_write_char(char c) -{ - /* Wait for space in transmit FIFO. */ - while (!uart_tx_ready()) - ; - - tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE; - MEC1322_UART_TB = c; -} - -int uart_read_char(void) -{ - return MEC1322_UART_RB; -} - -static void uart_clear_rx_fifo(int channel) -{ - MEC1322_UART_FCR = BIT(0) | BIT(1); -} - -/** - * Interrupt handler for UART - */ -void uart_ec_interrupt(void) -{ - /* Read input FIFO until empty, then fill output FIFO */ - uart_process_input(); - uart_process_output(); -} -DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1); - -void uart_init(void) -{ - /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~BIT(1); - - /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ - - /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~BIT(0); - - /* Set DLAB = 1 */ - MEC1322_UART_LCR |= BIT(7); - - /* PBRG0/PBRG1 */ - MEC1322_UART_PBRG0 = 1; - MEC1322_UART_PBRG1 = 0; - - /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~BIT(7); - - /* Set word length to 8-bit */ - MEC1322_UART_LCR |= BIT(0) | BIT(1); - - /* Enable FIFO */ - MEC1322_UART_FCR = BIT(0); - - /* Activate UART */ - MEC1322_UART_ACT |= BIT(0); - - /* - clock_enable_peripheral(CGC_OFFSET_UART, mask, - CGC_MODE_RUN | CGC_MODE_SLEEP);*/ - - gpio_config_module(MODULE_UART, 1); - - /* - * Enable interrupts for UART0. - */ - uart_clear_rx_fifo(0); - MEC1322_UART_IER |= BIT(0); - MEC1322_UART_MCR |= BIT(3); - MEC1322_INT_ENABLE(15) |= BIT(0); - MEC1322_INT_BLK_EN |= BIT(15); - task_enable_irq(MEC1322_IRQ_UART); - - init_done = 1; -} - -#ifdef CONFIG_LOW_POWER_IDLE -void uart_enter_dsleep(void) -{ - /* Disable the UART interrupt. */ - task_disable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART=13 */ - - /* - * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt - * with the flags defined in the gpio.inc file. - */ - gpio_reset(GPIO_UART0_RX); - - /* power-down/de-activate UART0 */ - MEC1322_UART_ACT &= ~BIT(0); - - /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ - MEC1322_INT_SOURCE(8) = (1<<18); - - /* Enable GPIO interrupts on the UART0 RX pin. */ - gpio_enable_interrupt(GPIO_UART0_RX); -} - - -void uart_exit_dsleep(void) -{ - /* - * If the UART0 RX GPIO interrupt has not fired, then no edge has been - * detected. Disable the GPIO interrupt so that switching the pin over - * to a UART pin doesn't inadvertently cause a GPIO edge interrupt. - * Note: we can't disable this interrupt if it has already fired - * because then the IRQ will not run at all. - */ - if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ - gpio_disable_interrupt(GPIO_UART0_RX); - - /* Configure UART0 pins for use in UART peripheral. */ - gpio_config_module(MODULE_UART, 1); - - /* Clear pending interrupts on UART peripheral and enable interrupts. */ - uart_clear_rx_fifo(0); - task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */ - - /* power-up/activate UART0 */ - MEC1322_UART_ACT |= BIT(0); -} - -void uart_deepsleep_interrupt(enum gpio_signal signal) -{ - /* - * Activity seen on UART RX pin while UART was disabled for deep sleep. - * The console won't see that character because the UART is disabled, - * so we need to inform the clock module of UART activity ourselves. - */ - clock_refresh_console_in_use(); - - /* Disable interrupts on UART0 RX pin to avoid repeated interrupts. */ - gpio_disable_interrupt(GPIO_UART0_RX); -} -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py deleted file mode 100755 index 8cbeb57c1b..0000000000 --- a/chip/mec1322/util/pack_ec.py +++ /dev/null @@ -1,254 +0,0 @@ -#!/usr/bin/env python2 - -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# A script to pack EC binary into SPI flash image for MEC1322 -# Based on MEC1322_ROM_Doc_Rev0.5.pdf. - -import argparse -import hashlib -import os -import struct -import subprocess -import tempfile - -LOAD_ADDR = 0x100000 -HEADER_SIZE = 0x140 -SPI_CLOCK_LIST = [48, 24, 12, 8] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b] - -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] - -def Crc8(crc, data): - """Update CRC8 value.""" - data_bytes = map(lambda b: ord(b) if isinstance(b, str) else b, data) - for v in data_bytes: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 - -def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return struct.unpack('<I', s)[0] - -def GetPayloadFromOffset(payload_file,offset): - """Read payload and pad it to 64-byte aligned.""" - with open(payload_file, 'rb') as f: - f.seek(offset) - payload = bytearray(f.read()) - rem_len = len(payload) % 64 - if rem_len: - payload += '\0' * (64 - rem_len) - return payload - -def GetPayload(payload_file): - """Read payload and pad it to 64-byte aligned.""" - return GetPayloadFromOffset(payload_file, 0) - -def GetPublicKey(pem_file): - """Extract public exponent and modulus from PEM file.""" - s = subprocess.check_output(['openssl', 'rsa', '-in', pem_file, - '-text', '-noout']) - modulus_raw = [] - in_modulus = False - for line in s.split('\n'): - if line.startswith('modulus'): - in_modulus = True - elif not line.startswith(' '): - in_modulus = False - elif in_modulus: - modulus_raw.extend(line.strip().strip(':').split(':')) - if line.startswith('publicExponent'): - exp = int(line.split(' ')[1], 10) - modulus_raw.reverse() - modulus = bytearray(''.join(map(lambda x: chr(int(x, 16)), - modulus_raw[0:256]))) - return struct.pack('<Q', exp), modulus - -def GetSpiClockParameter(args): - assert args.spi_clock in SPI_CLOCK_LIST, \ - "Unsupported SPI clock speed %d MHz" % args.spi_clock - return SPI_CLOCK_LIST.index(args.spi_clock) - -def GetSpiReadCmdParameter(args): - assert args.spi_read_cmd in SPI_READ_CMD_LIST, \ - "Unsupported SPI read command 0x%x" % args.spi_read_cmd - return SPI_READ_CMD_LIST.index(args.spi_read_cmd) - -def PadZeroTo(data, size): - data.extend('\0' * (size - len(data))) - -def BuildHeader(args, payload_len, rorofile): - # Identifier and header version - header = bytearray(['C', 'S', 'M', 'S', '\0']) - - PadZeroTo(header, 0x6) - header.append(GetSpiClockParameter(args)) - header.append(GetSpiReadCmdParameter(args)) - - header.extend(struct.pack('<I', LOAD_ADDR)) - header.extend(struct.pack('<I', GetEntryPoint(rorofile))) - header.append((payload_len >> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - header.extend(struct.pack('<I', args.payload_offset)) - - exp, modulus = GetPublicKey(args.payload_key) - PadZeroTo(header, 0x20) - header.extend(exp) - PadZeroTo(header, 0x30) - header.extend(modulus) - PadZeroTo(header, HEADER_SIZE) - - return header - -def SignByteArray(data, pem_file): - hash_file = tempfile.mkstemp(prefix='pack_ec.')[1] - sign_file = tempfile.mkstemp(prefix='pack_ec.')[1] - try: - with open(hash_file, 'wb') as f: - hasher = hashlib.sha256() - hasher.update(data) - f.write(hasher.digest()) - subprocess.check_call(['openssl', 'rsautl', '-sign', '-inkey', pem_file, - '-keyform', 'PEM', '-in', hash_file, - '-out', sign_file]) - with open(sign_file, 'rb') as f: - signed = list(f.read()) - signed.reverse() - return bytearray(''.join(signed)) - finally: - os.remove(hash_file) - os.remove(sign_file) - -def BuildTag(args): - tag = bytearray([(args.header_loc >> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - if args.chip_select != 0: - tag[2] |= 0x80 - tag.append(Crc8(0, tag)) - return tag - -def PacklfwRoImage(rorw_file, loader_file, image_size): - """TODO:Clean up to get rid of Temp file and just use memory - to save data""" - """Create a temp file with the - first image_size bytes from the rorw file and the - bytes from the loader_file appended - return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: - pro = fin1.read() - fo.write(pro) - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - fo.write(ro) - fo.close() - return fo.name - -def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--header_key", - help="PEM key file for signing header", - default="rsakey_sign_header.pem") - parser.add_argument("--payload_key", - help="PEM key file for signing payload", - default="rsakey_sign_payload.pem") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in MB", - default=4) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash", - default=0x170000) - parser.add_argument("-p", "--payload_offset", type=int, - help="The offset of payload from the header", - default=0x240) - parser.add_argument("-r", "--rwpayload_loc", type=int, - help="The offset of payload from the header", - default=0x190000) - parser.add_argument("-z", "--romstart", type=int, - help="The first location to output of the rom", - default=0) - parser.add_argument("-c", "--chip_select", type=int, - help="Chip select signal to use, either 0 or 1.", - default=0) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image.", - default=(96 * 1024)) - return parser.parse_args() - -# Debug helper routine -def dumpsects(spi_list): - for s in spi_list: - print "%x %d %s\n"%(s[0],len(s[1]),s[2]) - -def main(): - args = parseargs() - - spi_size = args.spi_size * 1024 - args.header_loc = spi_size - (128 * 1024) - args.rwpayload_loc = spi_size - (256 * 1024) - args.romstart = spi_size - (256 * 1024) - - spi_list = [] - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - payload = GetPayload(rorofile) - payload_len = len(payload) - #print payload_len - payload_signature = SignByteArray(payload, args.payload_key) - header = BuildHeader(args, payload_len, rorofile) - header_signature = SignByteArray(header, args.header_key) - tag = BuildTag(args) - # truncate the RW to 128k - payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024] - os.remove(rorofile) # clean up the temp file - - spi_list.append((args.header_loc, header, "header")) - spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature")) - spi_list.append((args.header_loc + args.payload_offset, payload, "payload")) - spi_list.append((args.header_loc + args.payload_offset + payload_len, - payload_signature, "payload_signature")) - spi_list.append((spi_size - 256, tag, "tag")) - spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw")) - - - spi_list = sorted(spi_list) - #dumpsects(spi_list) - - with open(args.output, 'wb') as f: - addr = args.romstart - for s in spi_list: - assert addr <= s[0] - if addr < s[0]: - f.write('\xff' * (s[0] - addr)) - addr = s[0] - f.write(s[1]) - addr += len(s[1]) - if addr < spi_size: - f.write('\xff' * (spi_size - addr)) - -if __name__ == '__main__': - main() diff --git a/chip/mec1322/util/rsakey_sign_header.pem b/chip/mec1322/util/rsakey_sign_header.pem deleted file mode 100644 index 37799ebbec..0000000000 --- a/chip/mec1322/util/rsakey_sign_header.pem +++ /dev/null @@ -1,28 +0,0 @@ ------BEGIN PRIVATE KEY----- -MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQCd0knJ+sVzkO40 -g7VguqpqrmwqgYPfgq3m7GHGitWgxjM/JDpKaOvq4G9O+yYUD/75V5GZJkRY0iE8 -MJCCvSkyoFHcCP0jvma9G/c13wXfLPGUunrJnV+Wzwy5+S1MXdax532gK9qeUmOB -HpIttkFRl3qhVHu9to2dbsx1S/AIA0GIPAINkcZxfRCAcheIoqK/oMqse+EDS9Zm -6frha9oS1+iRlqMPYKrOgWTKnkY3H/4M/HFj90hVzxun3qQj0mo3EdYoSrbCnyjG -JNjnuCdSEODmG5+FCTVWCfl/AolYmOWjMfCnfX7/HlfhOY+fOR91FKrgOjWHHf3a -0FhdUZDNAgMBAAECggEBAJKea6j2jXu42GP3PIk5wdrMYnb2zeHXEOJpFskR8Dem -CrQNXw4D/bC+gwo4Lv8SgUl6PiyurW5rAS9e2tJrFBwRbxthSnNrjxz/HyJwKI9W -vLT0reAikUyU3Hjl8lxxDWVH76DfPQI6/nBVS26mVHaNqQK6bx8nutbYuZ/7RWra -zatdjrl29D0E/xTva0S4AUPI7DmflwS6YbfVlTsyhnwphaEwD7eCDhD9h4nGQG8z -0WKDN2X1F7CmjrK9fy7SCHO9SKc3WNSjp2Dc0ImF2k72Mfw5jtOs81lczktztPy0 -gv4x6Tg0ws4Et9eI6Ub80tAZ+wQ5Vj+wzExMOp4K5KECgYEA0jz5IsRmie6y/WRG -6dI98nnyLoISIQue8xOA5J/OUyYfHn9CgJvGslRVg2mmSQ9GPkaMIN0dADvB6Tsh -XelAZZjnAo8pSyahz3OdcdgP6xksMjtKReXiLqu0ntfQS42nQDYNvRd2/clrYYRN -SlijT53QMqI4DSMz+0rLqUwvRskCgYEAwCyEEJ1Z/CI2ONN1tIEnJSuzZRYxlwNL -mVXx03ZSVi+L2MOMJjiCoeUZ/MVSacW+Elg6aU3U1GdOhNfQaPZJNqISACtm314Y -Xi9bMXegyQp3uBRnEah82ejm8hloOAOKZNgbqgt9o6FDrsccw3udIgzsgPY4koUK -1fNrDPJ5x+UCgYBwlEH8whr+hZnHYqkukGynqXFsQi6fD3AATlNZGdIMaH+FfzQH -VmNiHxLjmfF3cfx1YKWs+3qKI3XFBOrrNPpM7UHW9v5vxbIkOo725XIwvHwUMfel -0mH6B+ximsJpkuMa2VcmCKipYfBkecpBo5FgEuvoEUHelxlA2V6Ru8AdMQKBgQC/ -uanoiZQFIHzIJPABrfjH9Nl9uK6w4vDBgiVJu3pZ0gXLtQxV9Xse2dsbfCHEtSv0 -UWG1PZlgb9C+aDHdBhn1D6y1zpdLsizNiqGIsLkQ2gim9nP+AgLNxLbkQsTfXWjt -Q04WUHCAl5tW+/+OZ/1Uw2ARKZU3WNR+r+PVfvRQoQKBgQCjksWLe3Zx2yxnUenz -vaY09UTt42rawbUkm+xpNzOt7K1TudRODe444XG9fFgkNa5HPiAENoZ91Jv223x8 -Fi2SjfGA6/r/J1ash4cDcJLogTEP27YyJyhwXZFKtjfFeD3e2hvcMFMDG4EBHHXd -Bv/r6+6E+f30Y4bN3ZgK/rN6Tg== ------END PRIVATE KEY----- diff --git a/chip/mec1322/util/rsakey_sign_payload.pem b/chip/mec1322/util/rsakey_sign_payload.pem deleted file mode 100644 index 6845097749..0000000000 --- a/chip/mec1322/util/rsakey_sign_payload.pem +++ /dev/null @@ -1,28 +0,0 @@ ------BEGIN PRIVATE KEY----- -MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDQaeNJ6+a/KXhs -/0Xa2coG+4d+pc+4qs4O/6caxAtzr1YP155C4QxqfZw0DETreK7K/kgSgOJ6Q1gW -Yo88Fb4foxVYJbV2Bb+mdNlaHP/o6TrvBmqdsIjP5u1FwtmjquaewL2E3T4rHCXl -QgM7AQXAFzKt2HeaMeHvC2t+x/AganhfztOpqhGTL6lHiLC55SPNkWCb3GokotbL -Ul7q+wLSTpKS0vNuigjGVBVuV7YrwWhehOoLuV5FDMXHlMTemYH6+V5j78ZtSrXm -0RmKAKXoO+HbKbgALICUw5kzxXLSAoHx2rXLlou9I00olxsWir1lokxaWa1La3wA -pr214pxXAgMBAAECggEAdsXxrz4OeaEDrXJpeAioNwR/unB6ie5lkmyl6f4R3LLu -5AZofgrNTZ8aNxtK57sWOj9iCZGEAFOCzvcKVB68BEGnt11+Ja2vBAkRmWZvfWf1 -myTX+9gQkBM144zhBYIu/ggvuZlwhZb8DcRqHOU/RrKxwhtcRfbpoJasg0skkQO0 -bU2hwSu4kM+T2diyXp4V1PR4vrxZPNQ+B8sWxWKJs58+3NdWswwe9NcFQla0QTFz -7MIlMJNlJgTXjSYC8TjDlBlevwE5HoikpfSSvFr4uouyfpfWBxNFd8Tm/yFSTUqY -XO3oyU/NLK+BN7Sxj6Cs1Fx65yhMCmsqGQqCNOz2OQKBgQD4gIF6vVduyKfPV3EE -4lhFktlFRXeR+z9LXpGth3vwNN0XpPql1jr8hYPQqpSKefZRF5r8hLjt2ZaLDbnb -iVYwHxbXRuF5P6qsaSy1uVYG4og5LV5ddSBzf+/MhDInQk/O5tdvOrgQfcJzRJRg -MSx5uzs66r8/AFKCVTB/ptNgzQKBgQDWs7qqaHNHGRRfegRhwkkDvhRAMQKWsgL7 -kTWw/qW+b8mRYhCC4JvbU+OeFkf5kejGpFgDuvB4eH+rsPRVU8jSWZXrMKjGdZN1 -T6fFa5vz1VsRNhiVU3F2jfXTY5t7qQ18jEoMQxGxdGJy52Py+3N34ZWNS4cifLNS -rYjZnQmhswKBgD3rd1foGgMmyHmnpie7ZpdfcfgKyTJ80larZ80/dyhxY63ik/oC -mYwWkLPL7Vtb7H5kTWAiihnqH9LiRq9nVyyCcqSNqt0VeiefxV46oi7w/1SP83WC -G+XruQrS3dRed5hseL3kebzSOUOTkQ0u85AZkTarC6BdKjIDnCQSo5T5AoGAKNep -087o1waTVJJOkRY3c4nOKmPoXShh3t9BunjGqNJ1Ir3n7C20GGX9783HRVeXU2ph -/9uo8RHjH5Ma97xngHRgS4xHHvGw6mkLvkd5NEpK95w10vo7pFTfBaZ2JnEDSsUZ -NPnxPLOqIreX0No6nfyAyY8rlsjoB/tRBCyWb3cCgYEAgzJCllzahDvgCbmjI9Km -h7mUVc5U2fQR5B/WRa5iTSlQd+O4TXna7ZCxKDyYlesSBAiKanX0669Iri6cu4S6 -gMc7MJmm3VrnZGXoukSv3Zyot+hkaFrZTrXAIQiuYDK6YC5OK7kqM+DqtJOWUsfg -itdiqPKeYtViDQkxqJ1nkSw= ------END PRIVATE KEY----- diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c deleted file mode 100644 index ad93fb1240..0000000000 --- a/chip/mec1322/watchdog.c +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "watchdog.h" - -void watchdog_reload(void) -{ - MEC1322_WDG_KICK = 1; - -#ifdef CONFIG_WATCHDOG_HELP - /* Reload the auxiliary timer */ - MEC1322_TMR16_CTL(0) &= ~BIT(5); - MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CTL(0) |= BIT(5); -#endif -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ -#ifdef CONFIG_WATCHDOG_HELP - uint32_t val; - - /* - * Watchdog does not warn us before expiring. Let's use a 16-bit - * timer as an auxiliary timer. - */ - - /* Stop the auxiliary timer if it's running */ - MEC1322_TMR16_CTL(0) &= ~BIT(5); - - /* Enable auxiliary timer */ - MEC1322_TMR16_CTL(0) |= BIT(0); - - val = MEC1322_TMR16_CTL(0); - - /* Pre-scale = 48000 -> 1kHz -> Period = 1ms */ - val = (val & 0xffff) | (47999 << 16); - - /* No auto restart */ - val &= ~BIT(3); - - /* Count down */ - val &= ~BIT(2); - - MEC1322_TMR16_CTL(0) = val; - - /* Enable interrupt from auxiliary timer */ - MEC1322_TMR16_IEN(0) |= 1; - task_enable_irq(MEC1322_IRQ_TIMER16_0); - MEC1322_INT_ENABLE(23) |= BIT(0); - MEC1322_INT_BLK_EN |= BIT(23); - - /* Load and start the auxiliary timer */ - MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CNT(0) |= BIT(5); -#endif - - /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ - MEC1322_WDG_LOAD = CONFIG_WATCHDOG_PERIOD_MS * 1000 / 1007; - - /* Start watchdog */ - MEC1322_WDG_CTL |= 1; - - return EC_SUCCESS; -} - -#ifdef CONFIG_WATCHDOG_HELP -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - /* Clear status */ - MEC1322_TMR16_STS(0) |= 1; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) __attribute__((naked)); -void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveninently saves - * R0=LR so we can pass it to task_resched_if_needed. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0) - __attribute__((section(".rodata.irqprio"))) - = {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the - highest priority */ -#endif diff --git a/chip/mt_scp/audio_codec_wov.c b/chip/mt_scp/audio_codec_wov.c deleted file mode 100644 index 0a4684f909..0000000000 --- a/chip/mt_scp/audio_codec_wov.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "audio_codec.h" -#include "hooks.h" -#include "memmap.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* VIF FIFO irq is triggered above this level */ -#define WOV_TRIGGER_LEVEL 160 - -int audio_codec_wov_enable_notifier(void) -{ - SCP_VIF_FIFO_DATA_THRE = WOV_TRIGGER_LEVEL + 1; - SCP_VIF_FIFO_EN |= VIF_FIFO_IRQ_EN; - - task_enable_irq(SCP_IRQ_MAD_FIFO); - - return EC_SUCCESS; -} - -int audio_codec_wov_disable_notifier(void) -{ - SCP_VIF_FIFO_EN &= ~VIF_FIFO_IRQ_EN; - - task_disable_irq(SCP_IRQ_MAD_FIFO); - - return EC_SUCCESS; -} - -int audio_codec_wov_enable(void) -{ - SCP_VIF_FIFO_EN = 0; - - SCP_RXIF_CFG0 = (RXIF_CFG0_RESET_VAL & ~RXIF_RGDL2_MASK) | - RXIF_RGDL2_DMIC_16K; - SCP_RXIF_CFG1 = RXIF_CFG1_RESET_VAL; - - SCP_VIF_FIFO_EN |= VIF_FIFO_RSTN; - - return EC_SUCCESS; -} - -int audio_codec_wov_disable(void) -{ - SCP_VIF_FIFO_EN = 0; - - return EC_SUCCESS; -} - -static size_t wov_fifo_level(void) -{ - uint32_t fifo_status = SCP_VIF_FIFO_STATUS; - - if (!(fifo_status & VIF_FIFO_VALID)) - return 0; - - if (fifo_status & VIF_FIFO_FULL) - return VIF_FIFO_MAX; - - return VIF_FIFO_LEVEL(fifo_status); -} - -int32_t audio_codec_wov_read(void *buf, uint32_t count) -{ - int16_t *out = buf; - uint8_t gain = 1; - - if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN)) - audio_codec_dmic_get_gain_idx(0, &gain); - - count >>= 1; - - while (count-- && wov_fifo_level()) { - if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN)) - *out++ = audio_codec_s16_scale_and_clip( - SCP_VIF_FIFO_DATA, gain); - else - *out++ = SCP_VIF_FIFO_DATA; - } - - return (void *)out - buf; -} - -static void wov_fifo_interrupt_handler(void) -{ -#ifdef HAS_TASK_WOV - task_wake(TASK_ID_WOV); -#endif - - audio_codec_wov_disable_notifier(); - - /* Read to clear */ - SCP_VIF_FIFO_IRQ_STATUS; -} -DECLARE_IRQ(SCP_IRQ_MAD_FIFO, wov_fifo_interrupt_handler, 2); - -int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr) -{ - return memmap_ap_to_scp(ap_addr, ec_addr); -} diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk deleted file mode 100644 index fa6164056e..0000000000 --- a/chip/mt_scp/build.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -*- makefile -*- -# Copyright 2018 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# SCP specific files build -# - -CORE:=cortex-m -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 - -# Required chip modules -chip-y=clock.o gpio.o memmap.o system.o uart.o - -ifeq ($(CONFIG_IPI),y) -$(out)/RO/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc -$(out)/RW/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc -endif - -ifeq ($(CONFIG_AUDIO_CODEC_WOV),y) -HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a -ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),) -LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB) -HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y -endif -endif - -# Optional chip modules -chip-$(CONFIG_AUDIO_CODEC_WOV)+=audio_codec_wov.o -chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o -chip-$(CONFIG_I2C)+=i2c.o -chip-$(CONFIG_IPI)+=ipi.o ipi_table.o -chip-$(CONFIG_SPI)+=spi.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o diff --git a/chip/mt_scp/clock.c b/chip/mt_scp/clock.c deleted file mode 100644 index e28106bcc3..0000000000 --- a/chip/mt_scp/clock.c +++ /dev/null @@ -1,359 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#include "clock.h" -#include "clock_chip.h" -#include "common.h" -#include "console.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) - -#define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS) -#define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS) - -void clock_init(void) -{ - /* Set VREQ to HW mode */ - SCP_CPU_VREQ = CPU_VREQ_HW_MODE; - SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ; - - /* Set DDREN auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* Initialize 26MHz system clock counter reset value to 1. */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1); - /* Initialize high frequency ULPOSC counter reset value to 1. */ - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1); - /* Initialize sleep mode control VREQ counter. */ - SCP_CLK_SLEEP_CTRL = - (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1); - - /* Set normal wake clock */ - SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK; - - /* Enable fast wakeup support */ - SCP_CLK_SLEEP = 0; - SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) | - HIGH_FINAL_VAL_DEFAULT; - SCP_FAST_WAKE_CNT_END = - (SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) | - FAST_WAKE_CNT_END_DEFAULT; - - /* Set slow wake clock */ - SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) | - WAKE_CKSW_SEL_SLOW_DEFAULT; - - /* Select CLK_HIGH as wakeup clock */ - SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL & - ~(CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) | - CKSW_SEL_SLOW_ULPOSC2_CLK; - - /* - * Set legacy wakeup - * - disable SPM sleep control - * - disable SCP sleep mode - */ - SCP_CLK_SLEEP_CTRL &= ~(EN_SLEEP_CTRL | SPM_SLEEP_MODE); - - task_enable_irq(SCP_IRQ_CLOCK); - task_enable_irq(SCP_IRQ_CLOCK2); -} - -static void scp_ulposc_config(int osc, uint32_t osc_div, uint32_t osc_cali) -{ - uint32_t val; - - /* Clear all bits */ - val = 0; - /* Enable CP */ - val |= OSC_CP_EN; - /* Set div */ - val |= osc_div << 17; - /* F-band = 0, I-band = 4 */ - val |= 4 << 6; - /* Set calibration */ - val |= osc_cali; - /* Set control register 1 */ - AP_ULPOSC_CON02(osc) = val; - /* Set control register 2, enable div2 */ - AP_ULPOSC_CON13(osc) |= OSC_DIV2_EN; -} - -static inline void busy_udelay(int usec) -{ - /* - * Delaying by busy-looping, for place that can't use udelay because of - * the clock not configured yet. The value 28 is chosen approximately - * from experiment. - */ - volatile int i = usec * 28; - - while (i--) - ; -} - -static unsigned int scp_measure_ulposc_freq(int osc) -{ - unsigned int result = 0; - int cnt; - - /* Before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; - - /* Select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); - - /* Set meter divisor to 1, bit[31:24] = b00000000 */ - AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | - MISC_METER_DIV_1; - - /* Enable frequency meter, without start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_ENABLE; - - /* Trigger frequency meter start */ - AP_SCP_CFG_0 |= CFG_FREQ_METER_RUN; - - /* - * Frequency meter counts cycles in 1 / (26 * 1024) second period. - * freq_in_hz = freq_counter * 26 * 1024 - * - * The hardware takes 38us to count cycles. Delay up to 100us, - * as busy_udelay may not be accurate when sysclk is not 26Mhz - * (e.g. when recalibrating/measuring after boot). - */ - for (cnt = 100; cnt; cnt--) { - busy_udelay(1); - if (!(AP_SCP_CFG_0 & CFG_FREQ_METER_RUN)) { - result = CFG_FREQ_COUNTER(AP_SCP_CFG_1); - break; - } - } - - /* Disable freq meter */ - AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE; - return result; -} - -static inline int signum(int v) -{ - return (v > 0) - (v < 0); -} - -static inline int abs(int v) -{ - return (v >= 0) ? v : -v; -} - -static int scp_ulposc_config_measure(int osc, int div, int cali) -{ - int freq; - - scp_ulposc_config(osc, div, cali); - freq = scp_measure_ulposc_freq(osc); - CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", - osc + 1, div, cali, freq, - freq * 26 * 1000 / 1024); - - return freq; -} - -/** - * Calibrate ULPOSC to target frequency. - * - * @param osc 0:ULPOSC1, 1:ULPOSC2 - * @param target_mhz Target frequency to set - * @return Frequency counter output - * - */ -static int scp_calibrate_ulposc(int osc, int target_mhz) -{ - int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26); - struct ulposc { - int div; /* frequency divisor/multiplier */ - int cali; /* variable resistor calibrator */ - int freq; /* frequency counter measure result */ - } curr, prev = {0}; - enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV; - int param, param_max; - - curr.div = ULPOSC_DIV_MAX / 2; - curr.cali = ULPOSC_CALI_MAX / 2; - - param = curr.div; - param_max = ULPOSC_DIV_MAX; - - /* - * In the loop below, linear search closest div value to get desired - * frequency counter value. Then adjust cali to get a better result. - * Note that this doesn't give optimal output frequency, but it's - * usually close enough. - * TODO(b:120176040): See if we can efficiently calibrate the clock with - * more precision by exploring more of the cali/div space. - * - * The frequency function follows. Note that f is positively correlated - * with both div and cali: - * f(div, cali) = k1 * (div + k2) / R(cali) * C - * Where: - * R(cali) = k3 / (1 + k4 * (cali - k4)) - */ - while (1) { - curr.freq = scp_ulposc_config_measure(osc, curr.div, curr.cali); - - if (!curr.freq) - return 0; - - /* - * If previous and current are on either side of the desired - * frequency, pick the closest one. - */ - if (prev.freq && signum(target_freq - curr.freq) != - signum(target_freq - prev.freq)) { - if (abs(target_freq - prev.freq) < - abs(target_freq - curr.freq)) - curr = prev; - - if (stage == STAGE_CALI) - break; - - /* Switch to optimizing cali */ - stage = STAGE_CALI; - param = curr.cali; - param_max = ULPOSC_CALI_MAX; - } - - prev = curr; - param += signum(target_freq - curr.freq); - - if (param < 0 || param >= param_max) - return 0; - - if (stage == STAGE_DIV) - curr.div = param; - else - curr.cali = param; - } - - /* - * It's possible we end up using prev, so reset the configuration and - * measure again. - */ - return scp_ulposc_config_measure(osc, curr.div, curr.cali); -} - -static void scp_clock_high_enable(int osc) -{ - /* Enable high speed clock */ - SCP_CLK_EN |= EN_CLK_HIGH; - - switch (osc) { - case 0: - /* After 25ms, enable ULPOSC */ - busy_udelay(25 * MSEC); - SCP_CLK_EN |= CG_CLK_HIGH; - break; - case 1: - /* Turn off ULPOSC2 high-core-disable switch */ - SCP_CLK_ON_CTRL &= ~HIGH_CORE_DIS_SUB; - /* After 25ms, turn on ULPOSC2 high core clock gate */ - busy_udelay(25 * MSEC); - SCP_CLK_HIGH_CORE |= CLK_HIGH_CORE_CG; - break; - default: - break; - } -} - -void scp_enable_clock(void) -{ - /* Select default CPU clock */ - SCP_CLK_SEL = CLK_SEL_SYS_26M; - - /* VREQ */ - SCP_CPU_VREQ = 0x10001; - SCP_SECURE_CTRL &= ~ENABLE_SPM_MASK_VREQ; - - /* DDREN auto mode */ - SCP_SYS_CTRL |= AUTO_DDREN; - - /* Set settle time */ - SCP_CLK_SYS_VAL = 1; /* System clock */ - SCP_CLK_HIGH_VAL = 1; /* ULPOSC */ - SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2; - - /* Disable slow wake */ - SCP_CLK_SLEEP = SLOW_WAKE_DISABLE; - /* Disable SPM sleep control, disable sleep mode */ - SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL); - - /* Turn off ULPOSC2 */ - SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; - scp_ulposc_config(0, 12, 32); - scp_clock_high_enable(0); /* Turn on ULPOSC1 */ - scp_ulposc_config(1, 16, 32); - scp_clock_high_enable(1); /* Turn on ULPOSC2 */ - - /* Calibrate ULPOSC */ - scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ); - scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ); - - /* Select ULPOSC2 high speed CPU clock */ - SCP_CLK_SEL = CLK_SEL_ULPOSC_2; - - /* Enable default clock gate */ - SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_M | CG_MAD_M | CG_AP2P_M; - - /* Select pwrap_ulposc */ - AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16; - - /* Enable pwrap_ulposc clock gate */ - AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG; -} - -void clock_control_irq(void) -{ - /* Read ack CLK_IRQ */ - (SCP_CLK_IRQ_ACK); - task_clear_pending_irq(SCP_IRQ_CLOCK); -} -DECLARE_IRQ(SCP_IRQ_CLOCK, clock_control_irq, 3); - -void clock_fast_wakeup_irq(void) -{ - /* Ack fast wakeup */ - SCP_SLEEP_IRQ2 = 1; - task_clear_pending_irq(SCP_IRQ_CLOCK2); -} -DECLARE_IRQ(SCP_IRQ_CLOCK2, clock_fast_wakeup_irq, 3); - -/* Console command */ -int command_ulposc(int argc, char *argv[]) -{ - if (argc > 1 && !strncmp(argv[1], "cal", 3)) { - scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ); - scp_calibrate_ulposc(1, ULPOSC2_CLOCK_MHZ); - } - - /* SCP clock meter counts every (26MHz / 1024) tick */ - ccprintf("ULPOSC1 frequency: %u kHz\n", - scp_measure_ulposc_freq(0) * 26 * 1000 / 1024); - ccprintf("ULPOSC2 frequency: %u kHz\n", - scp_measure_ulposc_freq(1) * 26 * 1000 / 1024); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(ulposc, command_ulposc, "[calibrate]", - "Calibrate ULPOSC frequency"); diff --git a/chip/mt_scp/clock_chip.h b/chip/mt_scp/clock_chip.h deleted file mode 100644 index ab03d5c2f6..0000000000 --- a/chip/mt_scp/clock_chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks, PLL and power settings */ - -#ifndef __CROS_EC_CLOCK_CHIP_H -#define __CROS_EC_CLOCK_CHIP_H - -#include "common.h" -#include "registers.h" - -/* Default ULPOSC clock speed in MHz */ -#ifndef ULPOSC1_CLOCK_MHZ -#define ULPOSC1_CLOCK_MHZ 240 -#endif -#ifndef ULPOSC2_CLOCK_MHZ -#define ULPOSC2_CLOCK_MHZ 330 -#endif - -void scp_enable_clock(void); - -#endif /* __CROS_EC_CLOCK_CHIP_H */ diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h deleted file mode 100644 index 245c9f1bc6..0000000000 --- a/chip/mt_scp/config_chip.h +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#include "core/cortex-m/config_core.h" - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Default to UART 2 (AP UART) for EC console */ -#define CONFIG_UART_CONSOLE 2 - -/* Number of IRQ vectors */ -#define CONFIG_IRQ_COUNT 56 - -/* - * Number of EINT can be 0 ~ 160. Change this to conditional macro - * on adding other variants. - */ -#define MAX_NUM_EINT 8 -#define MAX_EINT_PORT (MAX_NUM_EINT / 32) - -/* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE 0 -#define CONFIG_RW_MEM_OFF 0 -#define CONFIG_RW_SIZE 0x40000 /* 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_PROGRAM_MEMORY_BASE 0 -#define CONFIG_MAPPED_STORAGE_BASE 0 -/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/ -#define CONFIG_MPU - -/* Unsupported features/commands */ -#undef CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_POWER_AP -#undef CONFIG_FLASH -#undef CONFIG_FLASH_PHYSICAL -#undef CONFIG_FMAP -#undef CONFIG_HIBERNATE - -/* Task stack size */ -#define CONFIG_STACK_SIZE 1024 -#define IDLE_TASK_STACK_SIZE 256 -#define SMALLER_TASK_STACK_SIZE 384 -#define TASK_STACK_SIZE 488 -#define LARGER_TASK_STACK_SIZE 640 -#define VENTI_TASK_STACK_SIZE 768 - -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_PIN(num) ((num) / 32), ((num) % 32) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mt_scp/gpio.c b/chip/mt_scp/gpio.c deleted file mode 100644 index a4896aae72..0000000000 --- a/chip/mt_scp/gpio.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module */ - -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - int bit, mode_reg_index, shift; - uint32_t mode_bits, mode_mask; - - /* Up to 8 alt functions per port */ - if (func > GPIO_ALT_FUNC_7) - return; - - if (func == GPIO_ALT_FUNC_NONE) - func = GPIO_ALT_FUNC_DEFAULT; - - while (mask) { - /* 32 gpio per port */ - bit = get_next_bit(&mask); - /* 8 gpio per mode reg */ - mode_reg_index = (port << 2) | (bit >> 3); - /* - * b[3] - write enable(?) - * b[2:0] - mode - */ - shift = (bit & 7) << 2; - mode_bits = func << shift; - mode_mask = ~(0xf << shift); - AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) & - mode_mask) | mode_bits; - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return !!(AP_GPIO_DIN(gpio_list[signal].port) & - gpio_list[signal].mask); -} - - -void gpio_set_level(enum gpio_signal signal, int value) -{ - if (value) - AP_GPIO_DOUT(gpio_list[signal].port) |= gpio_list[signal].mask; - else - AP_GPIO_DOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask; -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - /* Set input/output mode */ - if (flags & GPIO_OUTPUT) { - /* Set level before changing to output mode */ - if (flags & GPIO_HIGH) - AP_GPIO_DOUT(port) |= mask; - if (flags & GPIO_LOW) - AP_GPIO_DOUT(port) &= ~mask; - AP_GPIO_DIR(port) |= mask; - } else { - AP_GPIO_DIR(port) &= ~mask; - } - - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_HIGH)) - SCP_EINT_POLARITY_SET[port] = mask; - - if (flags & (GPIO_INT_F_FALLING | GPIO_INT_F_LOW)) - SCP_EINT_POLARITY_CLR[port] = mask; - else - SCP_EINT_POLARITY_SET[port] = mask; - - /* Set sensitivity register on edge trigger */ - if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - SCP_EINT_SENS_SET[port] = mask; - else - SCP_EINT_SENS_CLR[port] = mask; -} - -int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) -{ - /* TODO(b/120167145): implement get flags */ - return 0; -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_MASK_CLR[g->port] = g->mask; - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_MASK_SET[g->port] = g->mask; - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (signal >= GPIO_IH_COUNT || !g->mask) - return EC_ERROR_INVAL; - - SCP_EINT_ACK[g->port] = g->mask; - - return EC_SUCCESS; -} - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - int i; - int is_warm = system_is_reboot_warm(); - - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - gpio_set_flags_by_mask(g->port, g->mask, flags); - } -} - -void gpio_init(void) -{ - /* Enable EINT IRQ */ - task_enable_irq(SCP_IRQ_EINT); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -/* Interrupt handler */ -void __keep gpio_interrupt(void) -{ - int bit, port; - uint32_t pending; - enum gpio_signal signal; - - for (port = 0; port <= MAX_EINT_PORT; port++) { - pending = SCP_EINT_STATUS[port]; - - while (pending) { - bit = get_next_bit(&pending); - SCP_EINT_ACK[port] = BIT(bit); - /* Skip masked gpio */ - if (SCP_EINT_MASK_GET[port] & BIT(bit)) - continue; - /* Call handler */ - signal = port * 32 + bit; - if (signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } - } -} -DECLARE_IRQ(SCP_IRQ_EINT, gpio_interrupt, 1); diff --git a/chip/mt_scp/hrtimer.c b/chip/mt_scp/hrtimer.c deleted file mode 100644 index f970af6eb5..0000000000 --- a/chip/mt_scp/hrtimer.c +++ /dev/null @@ -1,253 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * High-res hardware timer - * - * SCP hardware 32bit count down timer can be configured to source clock from - * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a - * source, countdown mode and converts to micro second value matching common - * timer. - */ - -#include "clock.h" -#include "clock_chip.h" -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -#define IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) - -#define TIMER_SYSTEM 5 -#define TIMER_EVENT 3 - -/* ULPOSC1 should be a multiple of 8. */ -BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0); -#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8) - -/* Common timer overflows at 0x100000000 micro seconds */ -#define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1) - -static uint8_t sys_high; -static uint8_t event_high; - -/* Convert hardware countdown timer to 64bit countup ticks */ -static inline uint64_t timer_read_raw_system(void) -{ - uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(TIMER_SYSTEM); - uint32_t sys_high_adj = sys_high; - - /* - * If an IRQ is pending, but has not been serviced yet, adjust the - * sys_high value. - */ - if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1); - - return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | - SCP_TIMER_VAL(TIMER_SYSTEM)); -} - -static inline uint64_t timer_read_raw_event(void) -{ - return OVERFLOW_TICKS - (((uint64_t)event_high << 32) | - SCP_TIMER_VAL(TIMER_EVENT)); -} - -static inline void timer_set_clock(int n, uint32_t clock_source) -{ - SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | - clock_source; -} - -static inline void timer_ack_irq(int n) -{ - SCP_TIMER_IRQ_CTRL(n) |= TIMER_IRQ_CLEAR; -} - -/* Set hardware countdown value */ -static inline void timer_set_reset_value(int n, uint32_t reset_value) -{ - SCP_TIMER_RESET_VAL(n) = reset_value; -} - -static void timer_reset(int n) -{ - __hw_timer_enable_clock(n, 0); - timer_ack_irq(n); - timer_set_reset_value(n, 0xffffffff); - timer_set_clock(n, TIMER_CLK_32K); -} - -/* Reload a new 32bit countdown value */ -static void timer_reload(int n, uint32_t value) -{ - __hw_timer_enable_clock(n, 0); - timer_set_reset_value(n, value); - __hw_timer_enable_clock(n, 1); -} - -static int timer_reload_event_high(void) -{ - if (event_high) { - if (SCP_TIMER_RESET_VAL(TIMER_EVENT) == 0xffffffff) - __hw_timer_enable_clock(TIMER_EVENT, 1); - else - timer_reload(TIMER_EVENT, 0xffffffff); - event_high--; - return 1; - } - - /* Disable event timer clock when done. */ - __hw_timer_enable_clock(TIMER_EVENT, 0); - return 0; -} - -void __hw_clock_event_clear(void) -{ - __hw_timer_enable_clock(TIMER_EVENT, 0); - timer_set_reset_value(TIMER_EVENT, 0x0000c1ea4); - event_high = 0; -} - -void __hw_clock_event_set(uint32_t deadline) -{ - uint64_t deadline_raw = (uint64_t)deadline * TIMER_CLOCK_MHZ; - uint64_t now_raw = timer_read_raw_system(); - uint32_t event_deadline; - - if (deadline_raw > now_raw) { - deadline_raw -= now_raw; - event_deadline = (uint32_t)deadline_raw; - event_high = deadline_raw >> 32; - } else { - event_deadline = 1; - event_high = 0; - } - - if (event_deadline) - timer_reload(TIMER_EVENT, event_deadline); - else - timer_reload_event_high(); -} - -void __hw_timer_enable_clock(int n, int enable) -{ - if (enable) { - SCP_TIMER_IRQ_CTRL(n) |= 1; - SCP_TIMER_EN(n) |= 1; - } else { - SCP_TIMER_EN(n) &= ~1; - SCP_TIMER_IRQ_CTRL(n) &= ~1; - } -} - -int __hw_clock_source_init(uint32_t start_t) -{ - int t; - - /* - * TODO(b/120169529): check clock tree to see if we need to turn on - * MCLK and BCLK gate. - */ - SCP_CLK_GATE |= (CG_TIMER_M | CG_TIMER_B); - - /* Reset all timer, select 32768Hz clock source */ - for (t = 0; t < NUM_TIMERS; t++) - timer_reset(t); - - /* Enable timer IRQ wake source */ - SCP_INTC_IRQ_WAKEUP |= (1 << IRQ_TIMER(0)) | (1 << IRQ_TIMER(1)) | - (1 << IRQ_TIMER(2)) | (1 << IRQ_TIMER(3)) | - (1 << IRQ_TIMER(4)) | (1 << IRQ_TIMER(5)); - /* - * Timer configuration: - * OS TIMER - count up @ 13MHz, 64bit value with latch. - * SYS TICK - count down @ 26MHz - * EVENT TICK - count down @ 26MHz - */ - - /* Turn on OS TIMER, tick at 13MHz */ - SCP_OSTIMER_CON |= 1; - - /* System timestamp timer from BCLK (sourced from ULPOSC) */ - SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8; - - timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK); - sys_high = TIMER_CLOCK_MHZ-1; - timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); - __hw_timer_enable_clock(TIMER_SYSTEM, 1); - task_enable_irq(IRQ_TIMER(TIMER_SYSTEM)); - /* Event tick timer */ - timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK); - task_enable_irq(IRQ_TIMER(TIMER_EVENT)); - - return IRQ_TIMER(TIMER_SYSTEM); -} - -uint32_t __hw_clock_source_read(void) -{ - return timer_read_raw_system() / TIMER_CLOCK_MHZ; -} - -uint32_t __hw_clock_event_get(void) -{ - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; -} - -static void __hw_clock_source_irq(int n) -{ - uint32_t timer_ctrl = SCP_TIMER_IRQ_CTRL(n); - - /* Ack if we're hardware interrupt */ - if (timer_ctrl & TIMER_IRQ_STATUS) - timer_ack_irq(n); - - switch (n) { - case TIMER_EVENT: - if (timer_ctrl & TIMER_IRQ_STATUS) { - if (timer_reload_event_high()) - return; - } - process_timers(0); - break; - case TIMER_SYSTEM: - /* If this is a hardware irq, check overflow */ - if (timer_ctrl & TIMER_IRQ_STATUS) { - if (sys_high) { - sys_high--; - process_timers(0); - } else { - /* Overflow, reload system timer */ - sys_high = TIMER_CLOCK_MHZ-1; - process_timers(1); - } - } else { - process_timers(0); - } - break; - default: - return; - } - -} - -#define DECLARE_TIMER_IRQ(n) \ - void __hw_clock_source_irq_##n(void) { __hw_clock_source_irq(n); } \ - DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2) - -DECLARE_TIMER_IRQ(0); -DECLARE_TIMER_IRQ(1); -DECLARE_TIMER_IRQ(2); -DECLARE_TIMER_IRQ(3); -DECLARE_TIMER_IRQ(4); -DECLARE_TIMER_IRQ(5); diff --git a/chip/mt_scp/ipi.c b/chip/mt_scp/ipi.c deleted file mode 100644 index 222e117a79..0000000000 --- a/chip/mt_scp/ipi.c +++ /dev/null @@ -1,352 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Inter-Processor Communication (IPC) and Inter-Processor Interrupt (IPI) - * - * IPC is a communication bridge between AP and SCP. AP/SCP sends an IPC - * interrupt to SCP/AP to inform to collect the commmunication mesesages in the - * shared buffer. - * - * There are 4 IPCs in the current architecture, from IPC0 to IPC3. The - * priority of IPC is proportional to its IPC index. IPC3 has the highest - * priority and IPC0 has the lowest one. - * - * IPC0 may contain zero or more IPIs. Each IPI represents a task or a service, - * e.g. host command, or video encoding. IPIs are recognized by IPI ID, which - * should sync across AP and SCP. Shared buffer should designated which IPI - * ID it talks to. - * - * Currently, we don't have IPC handlers for IPC1, IPC2, and IPC3. - */ - -#include "console.h" -#include "hooks.h" -#include "host_command.h" -#include "ipi_chip.h" -#include "mkbp_event.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "hwtimer.h" - -#define CPRINTF(format, args...) cprintf(CC_IPI, format, ##args) -#define CPRINTS(format, args...) cprints(CC_IPI, format, ##args) - -#define IPI_MAX_REQUEST_SIZE CONFIG_IPC_SHARED_OBJ_BUF_SIZE -/* Reserve 1 extra byte for HOSTCMD_TYPE and 3 bytes for padding. */ -#define IPI_MAX_RESPONSE_SIZE (CONFIG_IPC_SHARED_OBJ_BUF_SIZE - 4) -#define HOSTCMD_TYPE_HOSTCMD 1 -#define HOSTCMD_TYPE_HOSTEVENT 2 - -static volatile int16_t ipc0_enabled_count; -static struct mutex ipc0_lock; -static struct mutex ipi_lock; -/* IPC0 shared objects, including send object and receive object. */ -static struct ipc_shared_obj *const scp_send_obj = - (struct ipc_shared_obj *)CONFIG_IPC_SHARED_OBJ_ADDR; -static struct ipc_shared_obj *const scp_recv_obj = - (struct ipc_shared_obj *)(CONFIG_IPC_SHARED_OBJ_ADDR + - sizeof(struct ipc_shared_obj)); -static char ipi_ready; - -#ifdef HAS_TASK_HOSTCMD -/* - * hostcmd and hostevent share the same IPI ID, and use first byte type to - * indicate its type. - */ -static struct hostcmd_data { - const uint8_t type; - /* To be compatible with CONFIG_HOSTCMD_ALIGNED */ - uint8_t response[IPI_MAX_RESPONSE_SIZE] __aligned(4); -} hc_cmd_obj = { .type = HOSTCMD_TYPE_HOSTCMD }; -BUILD_ASSERT(sizeof(struct hostcmd_data) == CONFIG_IPC_SHARED_OBJ_BUF_SIZE); - -static struct host_packet ipi_packet; -#endif - -/* Check if SCP to AP IPI is in use. */ -static inline int is_ipi_busy(void) -{ - return SCP_HOST_INT & IPC_SCP2HOST_BIT; -} - -/* If IPI is declared as a wake-up source, wake AP up. */ -static inline void try_to_wakeup_ap(int32_t id) -{ -#ifdef CONFIG_RPMSG_NAME_SERVICE - if (id == IPI_NS_SERVICE) - return; -#endif - - if (*ipi_wakeup_table[id]) - SCP_SPM_INT = SPM_INT_A2SPM; -} - -void ipi_disable_irq(int irq) -{ - /* Only support SCP_IRQ_IPC0 for now. */ - if (irq != SCP_IRQ_IPC0) - return; - - mutex_lock(&ipc0_lock); - - if ((--ipc0_enabled_count) == 0) - task_disable_irq(irq); - - mutex_unlock(&ipc0_lock); -} - -void ipi_enable_irq(int irq) -{ - /* Only support SCP_IRQ_IPC0 for now. */ - if (irq != SCP_IRQ_IPC0) - return; - - mutex_lock(&ipc0_lock); - - if ((++ipc0_enabled_count) == 1) { - int pending_ipc = SCP_GIPC_IN & SCP_GPIC_IN_CLEAR_ALL; - - task_enable_irq(irq); - - if (ipi_ready && pending_ipc) - /* - * IPC may be triggered while SCP_IRQ_IPC0 was disabled. - * AP will still updates SCP_GIPC_IN. - * Trigger the IRQ handler if it has a - * pending IPC. - */ - task_trigger_irq(irq); - } - - mutex_unlock(&ipc0_lock); -} - -/* Send data from SCP to AP. */ -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait) -{ - if (!ipi_ready) - return EC_ERROR_BUSY; - - /* TODO(b:117917141): Remove this check completely. */ - if (in_interrupt_context()) { - CPRINTS("Err: invoke %s() in ISR CTX", __func__); - return EC_ERROR_BUSY; - } - - if (len > sizeof(scp_send_obj->buffer)) - return EC_ERROR_INVAL; - - ipi_disable_irq(SCP_IRQ_IPC0); - mutex_lock(&ipi_lock); - - /* Check if there is already an IPI pending in AP. */ - if (is_ipi_busy()) { - /* - * If the following conditions meet, - * 1) There is an IPI pending in AP. - * 2) The incoming IPI is a wakeup IPI. - * then it assumes that AP is in suspend state. - * Send a AP wakeup request to SPM. - * - * The incoming IPI will be checked if it's a wakeup source. - */ - try_to_wakeup_ap(id); - - mutex_unlock(&ipi_lock); - ipi_enable_irq(SCP_IRQ_IPC0); - CPRINTS("Err: IPI Busy, %d", id); - - return EC_ERROR_BUSY; - } - - - scp_send_obj->id = id; - scp_send_obj->len = len; - memcpy(scp_send_obj->buffer, buf, len); - - /* Send IPI to AP: interrutp AP to receive IPI messages. */ - try_to_wakeup_ap(id); - SCP_HOST_INT = IPC_SCP2HOST_BIT; - - while (wait && is_ipi_busy()) - ; - - mutex_unlock(&ipi_lock); - ipi_enable_irq(SCP_IRQ_IPC0); - - return EC_SUCCESS; -} - -static void ipi_handler(void) -{ - if (scp_recv_obj->id >= IPI_COUNT) { - CPRINTS("#ERR IPI %d", scp_recv_obj->id); - return; - } - - /* - * Pass the buffer to handler. Each handler should be in charge of - * the buffer copying/reading before returning from handler. - */ - ipi_handler_table[scp_recv_obj->id]( - scp_recv_obj->id, scp_recv_obj->buffer, scp_recv_obj->len); -} - -void ipi_inform_ap(void) -{ - struct scp_run_t scp_run; - int ret; -#ifdef CONFIG_RPMSG_NAME_SERVICE - struct rpmsg_ns_msg ns_msg; -#endif - - scp_run.signaled = 1; - strncpy(scp_run.fw_ver, system_get_version(SYSTEM_IMAGE_RW), - SCP_FW_VERSION_LEN); - scp_run.dec_capability = VCODEC_CAPABILITY_4K_DISABLED; - scp_run.enc_capability = 0; - - ret = ipi_send(IPI_SCP_INIT, (void *)&scp_run, sizeof(scp_run), 1); - - if (ret) - ccprintf("Failed to send initialization IPC messages.\n"); - -#ifdef CONFIG_RPMSG_NAME_SERVICE - ns_msg.id = IPI_HOST_COMMAND; - strncpy(ns_msg.name, "cros-ec-rpmsg", RPMSG_NAME_SIZE); - ret = ipi_send(IPI_NS_SERVICE, &ns_msg, sizeof(ns_msg), 1); - if (ret) - ccprintf("Failed to announce host command channel.\n"); -#endif -} - -#ifdef HAS_TASK_HOSTCMD -#if defined(CONFIG_MKBP_USE_CUSTOM) -int mkbp_set_host_active_via_custom(int active, uint32_t *timestamp) -{ - static const uint8_t hc_evt_obj = HOSTCMD_TYPE_HOSTEVENT; - - /* This should be moved into ipi_send for more accuracy */ - if (timestamp) - *timestamp = __hw_clock_source_read(); - - if (active) - return ipi_send(IPI_HOST_COMMAND, &hc_evt_obj, - sizeof(hc_evt_obj), 1); - return EC_SUCCESS; -} -#endif - -static void ipi_send_response_packet(struct host_packet *pkt) -{ - int ret; - - ret = ipi_send(IPI_HOST_COMMAND, &hc_cmd_obj, - pkt->response_size + - offsetof(struct hostcmd_data, response), - 1); - if (ret) - CPRINTS("#ERR IPI HOSTCMD %d", ret); -} - -static void ipi_hostcmd_handler(int32_t id, void *buf, uint32_t len) -{ - uint8_t *in_msg = buf; - struct ec_host_request *r = (struct ec_host_request *)in_msg; - int i; - - if (in_msg[0] != EC_HOST_REQUEST_VERSION) { - CPRINTS("ERROR: Protocol V2 is not supported!"); - CPRINTF("in_msg=["); - for (i = 0; i < len; i++) - CPRINTF("%02x ", in_msg[i]); - CPRINTF("]\n"); - return; - } - - /* Protocol version 3 */ - - ipi_packet.send_response = ipi_send_response_packet; - - /* - * Just assign the buffer to request, host_packet_receive - * handles the buffer copy. - */ - ipi_packet.request = (void *)r; - ipi_packet.request_temp = NULL; - ipi_packet.request_max = IPI_MAX_REQUEST_SIZE; - ipi_packet.request_size = host_request_expected_size(r); - - ipi_packet.response = hc_cmd_obj.response; - /* Reserve space for the preamble and trailing byte */ - ipi_packet.response_max = IPI_MAX_RESPONSE_SIZE; - ipi_packet.response_size = 0; - - ipi_packet.driver_result = EC_RES_SUCCESS; - - host_packet_receive(&ipi_packet); -} -DECLARE_IPI(IPI_HOST_COMMAND, ipi_hostcmd_handler, 0); - -/* - * Get protocol information - */ -static enum ec_status ipi_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions |= BIT(3); - r->max_request_packet_size = IPI_MAX_REQUEST_SIZE; - r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE; - - args->response_size = sizeof(*r); - - return EC_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, ipi_get_protocol_info, - EC_VER_MASK(0)); -#endif - -static void ipi_enable_ipc0_deferred(void) -{ - /* Clear IPC0 IRQs. */ - SCP_GIPC_IN = SCP_GPIC_IN_CLEAR_ALL; - - /* All tasks are up, we can safely enable IPC0 IRQ now. */ - SCP_INTC_IRQ_ENABLE |= IPC0_IRQ_EN; - ipi_enable_irq(SCP_IRQ_IPC0); - - ipi_ready = 1; - - /* Inform AP that SCP is inited. */ - ipi_inform_ap(); - - CPRINTS("ipi init"); -} -DECLARE_DEFERRED(ipi_enable_ipc0_deferred); - -/* Initialize IPI. */ -static void ipi_init(void) -{ - /* Clear send share buffer. */ - memset(scp_send_obj, 0, sizeof(struct ipc_shared_obj)); - - /* Enable IRQ after all tasks are up. */ - hook_call_deferred(&ipi_enable_ipc0_deferred_data, 0); -} -DECLARE_HOOK(HOOK_INIT, ipi_init, HOOK_PRIO_DEFAULT); - -void ipc_handler(void) -{ - /* TODO(b/117917141): We only support IPC_ID(0) for now. */ - if (SCP_GIPC_IN & SCP_GIPC_IN_CLEAR_IPCN(0)) { - ipi_handler(); - SCP_GIPC_IN &= SCP_GIPC_IN_CLEAR_IPCN(0); - } - - SCP_GIPC_IN &= (SCP_GPIC_IN_CLEAR_ALL & ~SCP_GIPC_IN_CLEAR_IPCN(0)); -} -DECLARE_IRQ(SCP_IRQ_IPC0, ipc_handler, 4); diff --git a/chip/mt_scp/ipi_chip.h b/chip/mt_scp/ipi_chip.h deleted file mode 100644 index 6b9580e112..0000000000 --- a/chip/mt_scp/ipi_chip.h +++ /dev/null @@ -1,116 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_IPI_CHIP_H -#define __CROS_EC_IPI_CHIP_H - -#include "chip/mt_scp/registers.h" -#include "common.h" - -#define IPC_MAX 1 -#define IPC_ID(n) (n) - -/* - * Length of EC version string is at most 32 byte (NULL included), which - * also aligns SCP fw_version length. - */ -#define SCP_FW_VERSION_LEN 32 - -/* - * Video decoder supported capability: - * BIT(4): 0 enable 4K - * 1 disable 4K - */ -#define VCODEC_CAPABILITY_4K_DISABLED BIT(4) - -#ifndef IPI_SCP_INIT -#error If CONFIG_IPI is enabled, IPI_SCP_INIT must be defined. -#endif - -/* - * Share buffer layout for IPI_SCP_INIT response. This structure should sync - * across kernel and EC. - */ -struct scp_run_t { - uint32_t signaled; - int8_t fw_ver[SCP_FW_VERSION_LEN]; - uint32_t dec_capability; - uint32_t enc_capability; -}; - -/* - * The layout of the IPC0 AP/SCP shared buffer. - * This should sync across kernel and EC. - */ -struct ipc_shared_obj { - /* IPI ID */ - int32_t id; - /* Length of the contents in buffer. */ - uint32_t len; - /* Shared buffer contents. */ - uint8_t buffer[CONFIG_IPC_SHARED_OBJ_BUF_SIZE]; -}; - -/* Send a IPI contents to AP. This shouldn't be used in ISR context. */ -int ipi_send(int32_t id, const void *buf, uint32_t len, int wait); - -/* Size of the rpmsg device name, should sync across kernel and EC. */ -#define RPMSG_NAME_SIZE 32 - -/* - * The layout of name service message. - * This should sync across kernel and EC. - */ -struct rpmsg_ns_msg { - /* Name of the corresponding rpmsg_driver. */ - char name[RPMSG_NAME_SIZE]; - /* IPC ID */ - uint32_t id; -}; - -/* - * IPC Handler. - */ -void ipc_handler(void); - -/* - * An IPC IRQ could be shared across many IPI handlers. - * Those handlers would usually operate on disabling or enabling the IPC IRQ. - * This may disorder the actual timing to on/off the IRQ when there are many - * tasks try to operate on it. As a result, any access to the SCP_IRQ_* - * should go through ipi_{en,dis}able_irq(), which support a counter to - * enable/disable the IRQ at correct timeing. - */ -/* Disable IPI IRQ. */ -void ipi_disable_irq(int irq); -/* Enable IPI IRQ. */ -void ipi_enable_irq(int irq); - -/* IPI tables */ -extern void (*ipi_handler_table[])(int32_t, void *, uint32_t); -extern int *ipi_wakeup_table[]; - -/* Helper macros to build the IPI handler and wakeup functions. */ -#define IPI_HANDLER(id) CONCAT3(ipi_, id, _handler) -#define IPI_WAKEUP(id) CONCAT3(ipi_, id, _wakeup) - -/* - * Macro to declare an IPI handler. - * _id: The ID of the IPI - * handler: The IPI handler function - * is_wakeup_src: Declare IPI ID as a wake-up source or not - */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int dummy1[_id < IPI_COUNT ? 1 : -1]; \ - int dummy2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ - const int __keep IPI_WAKEUP(_id) = is_wakeup_src - -#endif /* __CROS_EC_IPI_CHIP_H */ diff --git a/chip/mt_scp/ipi_table.c b/chip/mt_scp/ipi_table.c deleted file mode 100644 index 8569ab24a7..0000000000 --- a/chip/mt_scp/ipi_table.c +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * IPI handlers declaration - */ - -#include "common.h" -#include "ipi_chip.h" - -typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); - -#ifndef PASS -#define PASS 1 -#endif - -#define ipi_arguments int32_t id, void *data, uint32_t len - -#if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } - -const int ipi_wakeup_undefined; - -#define table(type, name, x) x - -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix(args); - -#define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; - -#endif /* PASS == 1 */ - -#if PASS == 2 - -#undef table -#undef ipi_x_func -#undef ipi_x_var - -#define table(type, name, x) \ - type name[] __aligned(4) \ - __attribute__((section(".rodata.ipi, \"a\" @"))) = {x} - -#define ipi_x_var(suffix, number) \ - [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, - -#define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) - -#endif /* PASS == 2 */ - -/* - * Include generated IPI table (by util/gen_ipi_table). The contents originate - * from IPI_COUNT definition in board.h - */ -#include "ipi_table_gen.inc" - -#if PASS == 1 -#undef PASS -#define PASS 2 -#include "ipi_table.c" -BUILD_ASSERT(ARRAY_SIZE(ipi_handler_table) == IPI_COUNT); -BUILD_ASSERT(ARRAY_SIZE(ipi_wakeup_table) == IPI_COUNT); -#endif diff --git a/chip/mt_scp/memmap.c b/chip/mt_scp/memmap.c deleted file mode 100644 index 5926ae791e..0000000000 --- a/chip/mt_scp/memmap.c +++ /dev/null @@ -1,322 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SCP memory map - */ - -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "hooks.h" -#include "memmap.h" -#include "registers.h" -#include "util.h" - -/* - * Map SCP address (bits 31~28) to AP address - * - * SCP addr : AP addr - * 0x20000000 0x40000000 - * 0x30000000 0x50000000 - * 0x60000000 0x60000000 - * 0x70000000 0x70000000 - * 0x80000000 0x80000000 - * 0x90000000 0x00000000 - * 0xA0000000 0x10000000 - * 0xB0000000 0x20000000 - * 0xC0000000 0x30000000 - * 0xD0000000 0x10000000 - * 0xE0000000 0xA0000000 - * 0xF0000000 0x90000000 - */ - -#define MAP_INVALID 0xff - -static const uint8_t addr_map[16] = { - MAP_INVALID, /* 0x0: SRAM */ - MAP_INVALID, /* 0x1: Cached access (see below) */ - 0x4, 0x5, /* 0x2-0x3 */ - MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */ - 0x6, 0x7, 0x8, /* 0x6-0x8 */ - 0x0, 0x1, 0x2, 0x3, /* 0x9-0xc */ - 0x1, 0xa, 0x9 /* 0xd-0xf */ -}; - -/* - * AP addr : SCP cache addr - * 0x50000000 0x10000000 - */ -#define CACHE_TRANS_AP_ADDR 0x50000000 -#define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000 -/* FIXME: This should be configurable */ -#define CACHE_TRANS_AP_SIZE 0x00400000 - -#ifdef CONFIG_DRAM_BASE -BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR); -BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR); -#endif - -static void cpu_invalidate_icache(void) -{ - SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_ICACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - asm volatile("dsb; isb"); -} - -void cpu_invalidate_dcache(void) -{ - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Dummy read is necessary to confirm the invalidation finish. */ - REG32(CACHE_TRANS_SCP_CACHE_ADDR); - asm volatile("dsb;"); -} - -void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) -{ - size_t pos; - uintptr_t addr; - - for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { - addr = base + pos; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ - REG32(addr); - } - asm volatile("dsb;"); -} - -void cpu_clean_invalidate_dcache(void) -{ - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN; - SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ - REG32(CACHE_TRANS_SCP_CACHE_ADDR); - asm volatile("dsb;"); -} - -void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length) -{ - size_t pos; - uintptr_t addr; - - for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { - addr = base + pos; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN; - /* Dummy read necessary to confirm the invalidation finish. */ - REG32(addr); - } - asm volatile("dsb;"); -} - -static void scp_cache_init(void) -{ - int c; - const int region = 0; - - /* First make sure all caches are disabled, and reset stats. */ - for (c = 0; c < CACHE_COUNT; c++) { - /* - * Changing cache-size config may change the SRAM logical - * address in the mean time. This may break the loaded - * memory layout, and thus break the system. Cache-size - * should only be be configured in kernel driver before - * laoding the firmware. b/137920815#comment18 - */ - SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK | - SCP_CACHE_CON_WAYEN); - SCP_CACHE_REGION_EN(c) = 0; - SCP_CACHE_ENTRY(c, region) = 0; - SCP_CACHE_END_ENTRY(c, region) = 0; - - /* Reset statistics. */ - SCP_CACHE_HCNT0U(c) = 0; - SCP_CACHE_HCNT0L(c) = 0; - SCP_CACHE_CCNT0U(c) = 0; - SCP_CACHE_CCNT0L(c) = 0; - } - - /* No "normal" remap. */ - SCP_L1_REMAP_CFG0 = 0; - SCP_L1_REMAP_CFG1 = 0; - SCP_L1_REMAP_CFG2 = 0; - SCP_L1_REMAP_CFG3 = 0; - /* - * Setup OTHER1: Remap register for addr msb 31 to 28 equal to 0x1 and - * not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7. - */ - SCP_L1_REMAP_OTHER = - (CACHE_TRANS_AP_ADDR >> SCP_L1_EXT_ADDR_OTHER_SHIFT) << 8; - - /* Disable sleep protect */ - SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG & - ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN); - - /* Enable region 0 for both I-cache and D-cache. */ - for (c = 0; c < CACHE_COUNT; c++) { - SCP_CACHE_ENTRY(c, region) = CACHE_TRANS_SCP_CACHE_ADDR; - SCP_CACHE_END_ENTRY(c, region) = - CACHE_TRANS_SCP_CACHE_ADDR + CACHE_TRANS_AP_SIZE; - SCP_CACHE_ENTRY(c, region) |= SCP_CACHE_ENTRY_C; - - SCP_CACHE_REGION_EN(c) |= 1 << region; - - /* - * Enable cache. Note that cache size setting should have been - * done in kernel driver. b/137920815#comment18 - */ - SCP_CACHE_CON(c) |= SCP_CACHE_CON_MCEN | SCP_CACHE_CON_CNTEN0; - } - - cpu_invalidate_icache(); - cpu_invalidate_dcache(); -} - -static int command_cacheinfo(int argc, char **argv) -{ - const char cache_name[] = {'I', 'D'}; - int c; - - for (c = 0; c < 2; c++) { - uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) | - SCP_CACHE_HCNT0L(c); - uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) | - SCP_CACHE_CCNT0L(c); - - ccprintf("%ccache hit count: %llu\n", cache_name[c], hit); - ccprintf("%ccache access count: %llu\n", cache_name[c], access); - } - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, - NULL, - "Dump cache info"); - -void scp_memmap_init(void) -{ - /* - * Default config, LARGE DRAM not active: - * REG32(0xA0001F00) & 0x2000 != 0 - */ - - /* - * SCP_REMAP_CFG1 - * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7 - * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6 - * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 - * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 - */ - SCP_REMAP_CFG1 = - (uint32_t)addr_map[0x7] << 24 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x3] << 8 | - (uint32_t)addr_map[0x2]; - - /* - * SCP_REMAP_CFG2 - * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb - * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa - * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 - * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 - */ - SCP_REMAP_CFG2 = - (uint32_t)addr_map[0xb] << 24 | - (uint32_t)addr_map[0xa] << 16 | - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0x8]; - /* - * SCP_REMAP_CFG3 - * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd - * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf - * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe - * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc - */ - SCP_REMAP_CFG3 = - (uint32_t)addr_map[0xd] << 28 | - (uint32_t)addr_map[0xf] << 16 | - (uint32_t)addr_map[0xe] << 8 | - (uint32_t)addr_map[0xc]; - - /* Initialize cache remapping. */ - scp_cache_init(); -} - -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) -{ - int i; - uint8_t msb = ap_addr >> SCP_REMAP_ADDR_SHIFT; - - for (i = 0; i < ARRAY_SIZE(addr_map); i++) { - if (addr_map[i] != msb) - continue; - - *scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) | - (i << SCP_REMAP_ADDR_SHIFT); - return EC_SUCCESS; - } - - return EC_ERROR_INVAL; -} - -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) -{ - int i = scp_addr >> SCP_REMAP_ADDR_SHIFT; - - if (addr_map[i] == MAP_INVALID) - return EC_ERROR_INVAL; - - *ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) | - (addr_map[i] << SCP_REMAP_ADDR_SHIFT); - return EC_SUCCESS; -} - -#ifdef CONFIG_DRAM_BASE -BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR); -BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR); -#endif - -int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr) -{ - uintptr_t lsb; - - if ((ap_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != CACHE_TRANS_AP_ADDR) - return EC_ERROR_INVAL; - - lsb = ap_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK; - if (lsb > CACHE_TRANS_AP_SIZE) - return EC_ERROR_INVAL; - - *scp_addr = CACHE_TRANS_SCP_CACHE_ADDR | lsb; - return EC_SUCCESS; -} - -int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) -{ - uintptr_t lsb; - - if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != - CACHE_TRANS_SCP_CACHE_ADDR) - return EC_ERROR_INVAL; - - lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK; - if (lsb >= CACHE_TRANS_AP_SIZE) - return EC_ERROR_INVAL; - - *ap_addr = CACHE_TRANS_AP_ADDR | lsb; - return EC_SUCCESS; -} diff --git a/chip/mt_scp/memmap.h b/chip/mt_scp/memmap.h deleted file mode 100644 index fbecb5e8cf..0000000000 --- a/chip/mt_scp/memmap.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SCP memory map - */ - -#ifndef __CROS_EC_MEMMAP_H -#define __CROS_EC_MEMMAP_H - -void scp_memmap_init(void); - -/** - * Translate AP addr to SCP addr. - * - * @param ap_addr AP address to translate - * @param scp_addr Tranlated AP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr); - -/** - * Translate SCP addr to AP addr. - * - * @param scp_addr SCP address to tranlate - * @param ap_addr Translated SCP address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr); - -/** - * Translate AP addr to SCP cache addr. - * - * @param ap_addr AP address to translate - * @param scp_addr Tranlated AP cache address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_ap_to_scp_cache(uintptr_t ap_addr, uintptr_t *scp_addr); - -/** - * Translate SCP addr to AP addr. - * - * @param scp_addr SCP cache address to tranlate - * @param ap_addr Translated SCP cache address - * @return EC_SUCCESS or EC_ERROR_INVAL - */ -int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr); - -#endif /* #ifndef __CROS_EC_MEMMAP_H */ diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h deleted file mode 100644 index 6196a936e2..0000000000 --- a/chip/mt_scp/registers.h +++ /dev/null @@ -1,641 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for SCP - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" - -/* IRQ numbers */ -#define SCP_IRQ_IPC0 0 -#define SCP_IRQ_IPC1 1 -#define SCP_IRQ_IPC2 2 -#define SCP_IRQ_IPC3 3 -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 -#define SCP_IRQ_UART0 8 -#define SCP_IRQ_UART1 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1 11 -#define SCP_IRQ_I2C2 12 -#define SCP_IRQ_CLOCK 13 -#define SCP_IRQ_MAD_FIFO 14 -#define SCP_IRQ_TIMER0 15 -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_TIMER_STATUS 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 -#define SCP_IRQ_DMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD1_F216 26 -#define SCP_IRQ_MD1 27 -#define SCP_IRQ_C2K 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 -#define SCP_IRQ_AP_EINT 32 -#define SCP_IRQ_DEBUG 33 -#define SCP_CCIF0 34 -#define SCP_CCIF1 35 -#define SCP_CCIF2 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_USB0 38 -#define SCP_IRQ_USB1 39 -#define SCP_IRQ_TWAM 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_HWDVFS_HIGH 42 -#define SCP_IRQ_HWDVFS_LOW 43 -#define SCP_IRQ_CLOCK2 44 -/* RESERVED 45-52 */ -#define SCP_IRQ_AP_EINT2 53 -#define SCP_IRQ_AP_EINT_EVT 54 -#define SCP_IRQ_MAD_DATA 55 - -#define SCP_CFG_BASE 0x405C0000 - -#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04) -#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08) - -/* SCP to host interrupt */ -#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C) -#define IPC_SCP2HOST_SSHUB 0xff0000 -#define WDT_INT 0x100 -#define IPC_SCP2HOST 0xff -#define IPC_SCP2HOST_BIT 0x1 - -/* SCP to SPM interrupt */ -#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) -#define SPM_INT_A2SPM BIT(0) -#define SPM_INT_B2SPM BIT(1) -#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) - -/* - * AP side to SCP IPC - * APMCU writes 1 bit to trigger ith IPC to SCP. - * SCP writes 1 bit to ith bit to clear ith IPC. - */ -#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28) - #define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n)) - #define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF -#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C) - -/* 8 general purpose registers, 0 ~ 7 */ -#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50) -/* - * SCP_GPR[0] - * b15-b0 : scratchpad - * b31-b16 : saved flags - * SCP_GPR[1] - * b15-b0 : power on state - */ -#define SCP_PWRON_STATE SCP_GPR[1] -#define PWRON_DEFAULT 0xdee80000 -#define PWRON_WATCHDOG BIT(0) -#define PWRON_RESET BIT(1) -/* AP defined features */ -#define SCP_EXPECTED_FREQ SCP_GPR[3] -#define SCP_CURRENT_FREQ SCP_GPR[4] -#define SCP_REBOOT SCP_GPR[5] -#define READY_TO_REBOOT 0x34 -#define REBOOT_OK 1 - -/* Miscellaneous */ -#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90) -#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0) -#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4) -#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8) -#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC) -#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) -#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) -#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) -#define P_CACHE_SLP_PROT_EN BIT(3) -#define D_CACHE_SLP_PROT_EN BIT(4) -#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) -#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) -#define ENABLE_SPM_MASK_VREQ BIT(28) -#define DISABLE_REMAP BIT(22) -#define DISABLE_JTAG BIT(21) -#define DISABLE_AP_TCM BIT(20) -#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) -#define DDREN_FIX_VALUE BIT(28) -#define AUTO_DDREN BIT(18) - -/* Memory remap control */ -/* - * EXT_ADDR3[29:24] remap register for addr msb 31~28 equal to 0x7 - * EXT_ADDR2[21:16] remap register for addr msb 31~28 equal to 0x6 - * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 - * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 - */ -#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120) -/* - * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb - * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa - * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 - * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 - */ -#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124) -/* - * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd - * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf - * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe - * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc - */ -#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128) - -#define SCP_REMAP_ADDR_SHIFT 28 -#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) - -/* Cached memory remap control */ -#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C) -/* - * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401 - * L1C_EXT_ADDR0[13:0] remap register for addr msb 31~20 equal to 0x400 - */ -#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130) -/* - * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403 - * L1C_EXT_ADDR2[13:0] remap register for addr msb 31~20 equal to 0x402 - */ -#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134) -/* - * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405 - * L1C_EXT_ADDR4[13:0] remap register for addr msb 31~20 equal to 0x404 - */ -#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138) -/* - * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1 - * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0 - * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7 - */ -#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C) - -#define SCP_L1_EXT_ADDR_SHIFT 20 -#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28 -#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) - -/* Audio/voice FIFO */ -#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000) -#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE) -#define VIF_FIFO_RSTN (1 << 0) -#define VIF_FIFO_IRQ_EN (1 << 1) -#define VIF_FIFO_SRAM_PWR (1 << 2) -#define VIF_FIFO_RSTN_STATUS (1 << 4) -#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04) -#define VIF_FIFO_VALID (1 << 0) -#define VIF_FIFO_FULL (1 << 4) -#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff) -#define VIF_FIFO_MAX 256 -#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08) -#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C) -/* VIF IRQ status clears on read! */ -#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10) -/* Audio/voice serial interface */ -#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14) -#define RXIF_CFG0_RESET_VAL 0x2A130001 -#define RXIF_AFE_ON (1 << 0) -#define RXIF_SCKINV (1 << 1) -#define RXIF_RG_DL_2_IN_MODE(mode) (((mode) & 0xf) << 8) -#define RXIF_RGDL2_AMIC_16K (0x1 << 8) -#define RXIF_RGDL2_DMIC_16K (0x2 << 8) -#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8) -#define RXIF_RGDL2_AMIC_32K (0x5 << 8) -#define RXIF_RGDL2_MASK (0xf << 8) -#define RXIF_UP8X_RSP(p) (((p) & 0x7) << 16) -#define RXIF_RG_RX_READEN (1 << 19) -#define RXIF_MONO (1 << 20) -#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt) & 0xff) << 24) -#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18) -#define RXIF_CFG1_RESET_VAL 0x33180014 -#define RXIF_RG_SYNC_CNT_TBL(t) ((t) & 0x1ff) -#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t) & 0x1f) << 16) -#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r) & 0xf) << 24) -#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r) & 0xf) << 28) -#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C) -#define RXIF_SYNC_WORD(w) ((w) & 0xffff) -#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20) -#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24) -#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28) - -/* INTC control */ -#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) -#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) -#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) -#define IPC0_IRQ_EN BIT(0) -#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) -#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) -#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) -#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14) -#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18) -#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C) -#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80) -#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84) -#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88) -#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C) - -/* Timer */ -#define NUM_TIMERS 6 -#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n))) -#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n)) -#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) -#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) -#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) -#define TIMER_IRQ_ENABLE BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLEAR BIT(5) -#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) -#define TIMER_CLK_32K (0 << 4) -#define TIMER_CLK_26M BIT(4) -#define TIMER_CLK_BCLK (2 << 4) -#define TIMER_CLK_PCLK (3 << 4) -#define TIMER_CLK_MASK (3 << 4) -/* OS timer */ -#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080) -#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE) -#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04) -#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08) -#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C) -#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) -#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) -#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) -#define OSTIMER_LATCH0_EN BIT(5) -#define OSTIMER_LATCH1_EN BIT(13) -#define OSTIMER_LATCH2_EN BIT(21) -#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) -#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) -#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) -#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C) -#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30) -#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34) -#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38) - -/* Clock, PMIC wrapper, etc. */ -#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000) -#define SCP_CLK_SEL REG32(SCP_CLK_BASE) -#define CLK_SEL_SYS_26M 0 -#define CLK_SEL_32K 1 -#define CLK_SEL_ULPOSC_2 2 -#define CLK_SEL_ULPOSC_1 3 - -#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) -#define EN_CLK_SYS BIT(0) /* System clock */ -#define EN_CLK_HIGH BIT(1) /* ULPOSC */ -#define CG_CLK_HIGH BIT(2) -#define EN_SYS_IRQ BIT(16) -#define EN_HIGH_IRQ BIT(17) -#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) -#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) -#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) -/* - * System clock counter value. - * CLK_SYS_VAL[9:0] System clock counter initial/reset value. - */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14) -#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_SYS_VAL(n) ((n) & CLK_SYS_VAL_MASK) -/* - * ULPOSC clock counter value. - * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value. - */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18) -#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_HIGH_VAL(n) ((n) & CLK_HIGH_VAL_MASK) -#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C) -#define CKSW_SEL_SLOW_MASK 0x3 -#define CKSW_SEL_SLOW_DIV_MASK 0x30 -#define CKSW_SEL_SLOW_SYS_CLK 0 -#define CKSW_SEL_SLOW_32K_CLK 1 -#define CKSW_SEL_SLOW_ULPOSC2_CLK 2 -#define CKSW_SEL_SLOW_ULPOSC1_CLK 3 -/* - * Sleep mode control. - * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the - * voltage after returning from sleep mode. - */ -#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) -#define EN_SLEEP_CTRL BIT(0) -#define VREQ_COUNTER_MASK 0xfe -#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) -#define SPM_SLEEP_MODE BIT(8) -#define SPM_SLEEP_MODE_CLK_AO BIT(9) -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) -#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) -#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) -#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) -#define CG_TIMER_M BIT(0) -#define CG_TIMER_B BIT(1) -#define CG_MAD_M BIT(2) -#define CG_I2C_M BIT(3) -#define CG_I2C_B BIT(4) -#define CG_GPIO_M BIT(5) -#define CG_AP2P_M BIT(6) -#define CG_UART_M BIT(7) -#define CG_UART_B BIT(8) -#define CG_UART_RSTN BIT(9) -#define CG_UART1_M BIT(10) -#define CG_UART1_B BIT(11) -#define CG_UART1_RSTN BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_TWAM BIT(20) -#define CG_CACHE_I_CTRL BIT(21) -#define CG_CACHE_D_CTRL BIT(22) -#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) -#define PMICW_SLEEP_REQ BIT(0) -#define PMICW_SLEEP_ACK BIT(4) -#define PMICW_CLK_MUX BIT(8) -#define PMICW_DCM BIT(9) -#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) -#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) -#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) -#define WAKE_CKSW_SEL_NORMAL_MASK 0x3 -#define WAKE_CKSW_SEL_SLOW_MASK 0x30 -#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10 -#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44) -#define CLK_UART_SEL_MASK 0x3 -#define CLK_UART_SEL_26M 0x0 -#define CLK_UART_SEL_32K 0x1 -/* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART_SEL_ULPOSC1_DIV10 0x2 -#define CLK_UART1_SEL_MASK (0x3 << 16) -#define CLK_UART1_SEL_26M (0x0 << 16) -#define CLK_UART1_SEL_32K (0x1 << 16) -/* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16) -#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48) -#define CLK_BCLK_SEL_MASK 0x3 -#define CLK_BCLK_SEL_SYS_DIV8 0x0 -#define CLK_BCLK_SEL_32K 0x1 -#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2 -#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C) -#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50) -#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54) -#define CPU_VREQ_HW_MODE 0x10001 -#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58) -#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C) -#define CLK_HIGH_CORE_CG (1 << 1) -#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) -#define HIGH_AO BIT(0) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) -#define HIGH_FINAL_VAL_MASK 0x1f00 -#define HIGH_FINAL_VAL_DEFAULT 0x300 -#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) -#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94) -#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0) -#define SLOW_WAKE_DISABLE 1 -#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4) -#define FAST_WAKE_CNT_END_MASK 0xfff -#define FAST_WAKE_CNT_END_DEFAULT 0x18 -#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000 - -/* Peripherals */ -#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000) -#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000) -#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000) - -#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000) -#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000) -#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000) -#define SCP_UART_COUNT 2 - -/* External GPIO interrupt */ -#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000) -#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE) -#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040) -#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080) -#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0) -#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100) -#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140) -#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180) -#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0) -#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200) -#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240) -#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280) -#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300) -#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340) -#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380) -#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400) -#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420) -#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500) -#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600) -#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700) - -#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000) -#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200) -#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204) -#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208) -#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000) -#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000) -#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20) -#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000) -#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000) -#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000) - -#define CACHE_ICACHE 0 -#define CACHE_DCACHE 1 -#define CACHE_COUNT 2 -#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) -#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) -#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) -#define SCP_CACHE_CON_MCEN BIT(0) -#define SCP_CACHE_CON_CNTEN0 BIT(2) -#define SCP_CACHE_CON_CNTEN1 BIT(3) -#define SCP_CACHE_CON_CACHESIZE_SHIFT 8 -#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_WAYEN BIT(10) - -#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) -#define SCP_CACHE_OP_EN BIT(0) -#define SCP_CACHE_OP_OP_SHIFT 1 -#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) - -#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT) - -#define SCP_CACHE_OP_TADDR_SHIFT 5 -#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT) -#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT) - -/* Cache statistics */ -#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08) -#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c) -#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10) -#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14) -#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18) -#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c) -#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20) -#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24) - -#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c) - -#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000) -#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4) -#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) -#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + \ - (reg)*4) -#define SCP_CACHE_ENTRY_C BIT(8) -#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) - -/* ARMV7 regs */ -#define ARM_SCB_SCR REG32(0xE000ED10) -#define SCR_DEEPSLEEP BIT(2) - -/* AP regs */ -#define AP_BASE 0xA0000000 -#define TOPCK_BASE AP_BASE /* Top clock */ -#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */ - -/* CLK_CFG_5 regs */ -#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090) -#define PWRAP_ULPOSC_MASK (0x3000000) -#define CLK26M (0 << 24) -#define OSC_D16 (1 << 24) -#define OSC_D4 (2 << 24) -#define OSC_D8 (3 << 24) -#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098) -#define PWRAP_ULPOSC_CG BIT(31) - -/* OSC meter */ -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) -#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16) -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN (1 << 4) -#define CFG_FREQ_METER_ENABLE (1 << 12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) - -/* GPIO */ -#define AP_GPIO_BASE (AP_BASE + 0x00005000) -/* - * AP_GPIO_DIR - * GPIO input/out direction, 1 bit per pin. - * 0:input 1:output - */ -#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4)) -/* - * AP_GPIO_DOUT, n in [0..5] - * GPIO output level, 1 bit per pin - * 0:low 1:high - */ -#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4)) -/* - * AP_GPIO_DIN, n in [0..5] - * GPIO input level, 1 bit per pin - * 0:low 1:high - */ -#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4)) -/* - * AP_GPIO_MODE, n in [0..22] - * Pin mode selection, 4 bit per pin - * bit3 - write enable, set to 1 for hw to fetch bit2,1,0. - * bit2-0 - mode 0 ~ 7 - */ -#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4)) -#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0) -#define AP_GPIO_DUMMY REG32(AP_GPIO_BASE + 0x6C0) -#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0) -#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0) -/* AP_GPIO_SEC, n in [0..5] */ -#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4)) - -/* - * PLL ULPOSC - * ULPOSC1: AP_ULPOSC_CON[0] AP_ULPOSC_CON[1] - * ULPOSC2: AP_ULPOSC_CON[2] AP_ULPOSC_CON[3] - * osc: 0 for ULPOSC1, 1 for ULPSOC2. - */ -#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700) -#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704) -#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc) * 0x8) -#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc) * 0x8) -/* - * AP_ULPOSC_CON[0,2] - * bit0-5: calibration - * bit6-12: I-band - * bit13-16: F-band - * bit17-22: div - * bit23: CP_EN - * bit24-31: reserved - */ -#define OSC_CALI_MSK (0x3f << 0) -#define OSC_CALI_BITS 6 -#define OSC_IBAND_MASK (0x7f << 6) -#define OSC_FBAND_MASK (0x0f << 13) -#define OSC_DIV_MASK (0x1f << 17) -#define OSC_DIV_BITS 5 -#define OSC_CP_EN BIT(23) -#define OSC_RESERVED_MASK (0xff << 24) -/* AP_ULPOSC_CON[1,3] */ -#define OSC_MOD_MASK (0x03 << 0) -#define OSC_DIV2_EN BIT(2) - -#define DUMMY_GPIO_BANK 0 - -#ifndef __ASSEMBLER__ - -/* - * Cortex-M4 mod - * Available power saving features: - * 1. FPU freeze - freeze FPU operand when FPU is not used - * 2. LSU gating - gate LSU clock when not LSU operation - * 3. Trace clk disable - gate trace clock - * 4. DCM for CPU stall - gate CPU clock when CPU stall - */ -#define CM4_MODIFICATION REG32(0xE00FE000) -#define CM4_DCM_FEATURE REG32(0xE00FE004) -/* UART, 16550 compatible */ -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] -#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) - -/* Watchdog */ -#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84) -#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset) -#define SCP_WDT_CFG SCP_WDT_REG(0) -#define SCP_WDT_FREQ 33825 -#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) -#define SCP_WDT_ENABLE BIT(31) -#define SCP_WDT_RELOAD SCP_WDT_REG(4) -#define SCP_WDT_RELOAD_VALUE 1 - -#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/serial_reg.h deleted file mode 100644 index 5344566272..0000000000 --- a/chip/mt_scp/serial_reg.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * UART register map - */ - -#ifndef __CROS_EC_SERIAL_REG_H -#define __CROS_EC_SERIAL_REG_H - -#include "registers.h" - -/* Number of hardware ports */ -#define HW_UART_PORTS 2 - -/* DLAB (Divisor Latch Access Bit) == 0 */ - -/* Data register - * (Read) Rcvr buffer register - * (Write) Xmit holding register - */ -#define UART_DATA(n) UART_REG(n, 0) -/* (Write) Interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* Recv data int */ -#define UART_IER_THRI BIT(1) /* Xmit holding register int */ -#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ -#define UART_IER_MSI BIT(3) /* Modem status int */ -/* (Read) Interrupt ID register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT BIT(0) /* No int pending */ -#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ -#define UART_IIR_MSI 0x00 -#define UART_IIR_THRI 0x02 -#define UART_IIR_RDI 0x04 -#define UART_IIR_RLSI 0x06 -#define UART_IIR_BUSY 0x07 /* DW APB busy */ -/* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) -/* FIFO trigger levels */ -#define UART_FCR_T_TRIG_00 0x00 -#define UART_FCR_T_TRIG_01 0x10 -#define UART_FCR_T_TRIG_10 0x20 -#define UART_FCR_T_TRIG_11 0x30 -#define UART_FCR_R_TRIG_00 0x00 -#define UART_FCR_R_TRIG_01 0x40 -#define UART_FCR_R_TRIG_10 0x80 -#define UART_FCR_R_TRIG_11 0x80 -/* (Write) Line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* Word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* Parity enable */ -#define UART_LCR_EPAR BIT(4) /* Even parity */ -#define UART_LCR_SPAR BIT(5) /* Stick parity */ -#define UART_LCR_SBC BIT(6) /* Set break control */ -#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ -/* (Write) Modem control register */ -#define UART_MCR(n) UART_REG(n, 4) -/* (Read) Line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* Data ready */ -#define UART_LSR_OE BIT(1) /* Overrun error */ -#define UART_LSR_PE BIT(2) /* Parity error */ -#define UART_LSR_FE BIT(3) /* Frame error */ -#define UART_LSR_BI BIT(4) /* Break interrupt */ -#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT BIT(6) /* Xmit empty */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ - -/* DLAB == 1 */ - -/* (Write) Divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) /* Low */ -#define UART_DLH(n) UART_REG(n, 1) /* High */ - -/* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) -#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) -#define UART_SAMPLE_POINT(n) UART_REG(n, 11) -#define UART_RATE_FIX(n) UART_REG(n, 13) - -#endif /* __CROS_EC_SERIAL_REG_H */ diff --git a/chip/mt_scp/system.c b/chip/mt_scp/system.c deleted file mode 100644 index 6bd2e76644..0000000000 --- a/chip/mt_scp/system.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System : hardware specific implementation */ - -#include "clock_chip.h" -#include "console.h" -#include "cpu.h" -#include "flash.h" -#include "hooks.h" -#include "host_command.h" -#include "memmap.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "version.h" -#include "watchdog.h" - -/* - * SCP_GPR[0] b15-b0 - scratchpad - * SCP_GPR[0] b31-b16 - saved_flags - */ - -int system_set_scratchpad(uint32_t value) -{ - /* Check if value fits in 16 bits */ - if (value & 0xffff0000) - return EC_ERROR_INVAL; - - SCP_GPR[0] = (SCP_GPR[0] & 0xffff0000) | value; - - return EC_SUCCESS; -} - -uint32_t system_get_scratchpad(void) -{ - return SCP_GPR[0] & 0xffff; -} - -const char *system_get_chip_vendor(void) -{ - return "mtk"; -} - -const char *system_get_chip_name(void) -{ - /* Support only SCP_A for now */ - return "scp_a"; -} - -const char *system_get_chip_revision(void) -{ - return ""; -} - -void chip_pre_init(void) -{ -} - -static void scp_cm4_mod(void) -{ - CM4_MODIFICATION = 3; - CM4_DCM_FEATURE = 3; -} - -static void scp_enable_pirq(void) -{ - /* Enable all peripheral to SCP IRQ, except IPC0. */ - SCP_INTC_IRQ_ENABLE = 0xFFFFFFFE; - SCP_INTC_IRQ_ENABLE_MSB = 0xFFFFFFFF; -} - -void system_pre_init(void) -{ - /* CM4 Modification */ - scp_cm4_mod(); - /* Clock */ - scp_enable_clock(); - /* Peripheral IRQ */ - scp_enable_pirq(); - /* Init dram mapping (and cache) */ - scp_memmap_init(); - /* Disable jump (mt_scp has only RW) and enable MPU. */ - system_disable_jump(); -} - -void system_reset(int flags) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - /* Remember that the software asked us to hard reboot */ - if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - - /* Reset flags are 32-bits, but save only 16 bits. */ - ASSERT(!(save_flags >> 16)); - SCP_GPR[0] = (save_flags << 16) | (SCP_GPR[0] & 0xffff); - - /* SCP can not hard reset itself */ - ASSERT(!(flags & SYSTEM_RESET_HARD)); - - if (flags & SYSTEM_RESET_WAIT_EXT) { - int i; - - /* Wait 10 seconds for external reset */ - for (i = 0; i < 1000; i++) { - watchdog_reload(); - udelay(10000); - } - } - - /* Set watchdog timer to small value, and spin wait for watchdog reset */ - SCP_WDT_CFG = 0; - SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1); - watchdog_reload(); - while (1) - ; -} - -static void check_reset_cause(void) -{ - uint32_t flags = 0; - uint32_t raw_reset_cause = SCP_GPR[1]; - - /* Set state to power-on */ - SCP_PWRON_STATE = PWRON_DEFAULT; - - if ((raw_reset_cause & 0xffff0000) == PWRON_DEFAULT) { - /* Reboot */ - if (raw_reset_cause & PWRON_WATCHDOG) - flags |= EC_RESET_FLAG_WATCHDOG; - else if (raw_reset_cause & PWRON_RESET) - flags |= EC_RESET_FLAG_POWER_ON; - else - flags |= EC_RESET_FLAG_OTHER; - } else { - /* Power lost restart */ - flags |= EC_RESET_FLAG_POWER_ON; - } - system_set_reset_flags(SCP_GPR[0] >> 16); - SCP_GPR[0] &= 0xffff; -} - -int system_is_reboot_warm(void) -{ - const uint32_t cold_flags = - EC_RESET_FLAG_RESET_PIN | - EC_RESET_FLAG_POWER_ON | - EC_RESET_FLAG_WATCHDOG | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HIBERNATE; - - check_reset_cause(); - - return !(system_get_reset_flags() & cold_flags); -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - return EC_ERROR_INVAL; -} diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/uart.c deleted file mode 100644 index 78ea594c6b..0000000000 --- a/chip/mt_scp/uart.c +++ /dev/null @@ -1,179 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SCP UART module */ - -#include "clock_chip.h" -#include "console.h" -#include "registers.h" -#include "serial_reg.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Console UART index */ -#define UARTN CONFIG_UART_CONSOLE -#define UART_IDLE_WAIT_US 500 - -static uint8_t uart_done, tx_started; - -int uart_init_done(void) -{ - /* - * TODO: AP UART support - * When access AP UART port, wait for AP peripheral clock - */ - return uart_done; -} - -void uart_tx_start(void) -{ - tx_started = 1; - - /* AP UART mode doesn't support interrupt */ - if (UARTN >= SCP_UART_COUNT) - return; - - if (UART_IER(UARTN) & UART_IER_THRI) - return; - disable_sleep(SLEEP_MASK_UART); - UART_IER(UARTN) |= UART_IER_THRI; -} - -void uart_tx_stop(void) -{ - tx_started = 0; - - /* AP UART mode doesn't support interrupt */ - if (UARTN >= SCP_UART_COUNT) - return; - - UART_IER(UARTN) &= ~UART_IER_THRI; - enable_sleep(SLEEP_MASK_UART); -} - -void uart_tx_flush(void) -{ - while (!(UART_LSR(UARTN) & UART_LSR_TEMT)) - ; -} - -int uart_tx_ready(void) -{ - /* Check xmit FIFO empty */ - return UART_LSR(UARTN) & UART_LSR_THRE; -} - -int uart_rx_available(void) -{ - /* Check rcvr data ready */ - return UART_LSR(UARTN) & UART_LSR_DR; -} - -void uart_write_char(char c) -{ - while (!uart_tx_ready()) - ; - - UART_DATA(UARTN) = c; -} - -int uart_read_char(void) -{ - return UART_DATA(UARTN); -} - -void uart_process(void) -{ - uart_process_input(); - uart_process_output(); -} - -#if (UARTN < SCP_UART_COUNT) -void uart_interrupt(void) -{ - uint8_t ier; - - task_clear_pending_irq(UART_IRQ(UARTN)); - uart_process(); - ier = UART_IER(UARTN); - UART_IER(UARTN) = 0; - UART_IER(UARTN) = ier; -} -DECLARE_IRQ(UART_IRQ(UARTN), uart_interrupt, 2); - -void uart_rx_interrupt(void) -{ - uint8_t ier; - - task_clear_pending_irq(UART_RX_IRQ(UARTN)); - SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN); - uart_process(); - ier = UART_IER(UARTN); - UART_IER(UARTN) = 0; - UART_IER(UARTN) = ier; - SCP_INTC_UART_RX_IRQ |= 1 << UARTN; -} -DECLARE_IRQ(UART_RX_IRQ(UARTN), uart_rx_interrupt, 2); -#endif - -void uart_task(void) -{ -#if (UARTN >= SCP_UART_COUNT) - while (1) { - if (uart_rx_available() || tx_started) - uart_process(); - else - task_wait_event(UART_IDLE_WAIT_US); - } -#endif -} - -void uart_init(void) -{ - const uint32_t baud_rate = CONFIG_UART_BAUD_RATE; - /* - * UART clock source is set to ULPOSC1 / 10 below. - * - * TODO(b:134035444): We could get slightly more precise frequency by - * using the _measured_ ULPOSC1 frequency (instead of the target). - */ - const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000; - const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16); - - /* Init clock */ -#if UARTN == 0 - SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10; - SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN; -#elif UARTN == 1 - SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10; - SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN; -#endif - - /* Init and clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; - /* Line control: parity none, 8 bit, 1 stop bit */ - UART_LCR(UARTN) = UART_LCR_WLEN8; - /* For baud rate <= 115200 */ - UART_HIGHSPEED(UARTN) = 0; - /* DLAB = 1 and update DLL DLH */ - UART_LCR(UARTN) |= UART_LCR_DLAB; - UART_DLL(UARTN) = div & 0xff; - UART_DLH(UARTN) = (div >> 8) & 0xff; - UART_LCR(UARTN) &= ~UART_LCR_DLAB; - UART_IER(UARTN) |= UART_IER_RDI; - -#if (UARTN < SCP_UART_COUNT) - task_enable_irq(UART_IRQ(UARTN)); - task_enable_irq(UART_RX_IRQ(UARTN)); - /* UART RX IRQ needs an extra enable */ - SCP_INTC_UART_RX_IRQ |= 1 << UARTN; -#endif - gpio_config_module(MODULE_UART, 1); - uart_done = 1; -} diff --git a/chip/mt_scp/watchdog.c b/chip/mt_scp/watchdog.c deleted file mode 100644 index 74e2cad8e5..0000000000 --- a/chip/mt_scp/watchdog.c +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "hooks.h" -#include "panic.h" -#include "registers.h" -#include "watchdog.h" - -void watchdog_reload(void) -{ - SCP_WDT_RELOAD = SCP_WDT_RELOAD_VALUE; -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - const uint32_t watchdog_timeout = - SCP_WDT_PERIOD(CONFIG_WATCHDOG_PERIOD_MS); - - /* Disable watchdog */ - SCP_WDT_CFG = 0; - /* Enable watchdog */ - SCP_WDT_CFG = SCP_WDT_ENABLE | watchdog_timeout; - /* Reload watchdog */ - watchdog_reload(); - - return EC_SUCCESS; -} diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c deleted file mode 100644 index 6fe123ac4e..0000000000 --- a/chip/nrf51/bluetooth_le.c +++ /dev/null @@ -1,537 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "bluetooth_le.h" -#include "include/bluetooth_le.h" -#include "console.h" -#include "ppi.h" -#include "radio.h" -#include "registers.h" -#include "timer.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_BLUETOOTH_LE, outstr) -#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args) - -static void ble2nrf_packet(struct ble_pdu *ble_p, - struct nrf51_ble_packet_t *radio_p) -{ - if (ble_p->header_type_adv) { - radio_p->s0 = ble_p->header.adv.type & 0xf; - radio_p->s0 |= (ble_p->header.adv.txaddr ? - 1 << BLE_ADV_HEADER_TXADD_SHIFT : 0); - radio_p->s0 |= (ble_p->header.adv.rxaddr ? - 1 << BLE_ADV_HEADER_RXADD_SHIFT : 0); - radio_p->length = ble_p->header.adv.length & 0x3f; /* 6 bits */ - } else { - radio_p->s0 = ble_p->header.data.llid & 0x3; - radio_p->s0 |= (ble_p->header.data.nesn ? - 1 << BLE_DATA_HEADER_NESN_SHIFT : 0); - radio_p->s0 |= (ble_p->header.data.sn ? - 1 << BLE_DATA_HEADER_SN_SHIFT : 0); - radio_p->s0 |= (ble_p->header.data.md ? - 1 << BLE_DATA_HEADER_MD_SHIFT : 0); - radio_p->length = ble_p->header.data.length & 0x1f; /* 5 bits */ - } - - if (radio_p->length > 0) - memcpy(radio_p->payload, ble_p->payload, radio_p->length); -} - -static void nrf2ble_packet(struct ble_pdu *ble_p, - struct nrf51_ble_packet_t *radio_p, int type_adv) -{ - if (type_adv) { - ble_p->header_type_adv = 1; - ble_p->header.adv.type = radio_p->s0 & 0xf; - ble_p->header.adv.txaddr = (radio_p->s0 & - BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0; - ble_p->header.adv.rxaddr = (radio_p->s0 & - BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0; - /* Length check? 6-37 Bytes */ - ble_p->header.adv.length = radio_p->length; - } else { - ble_p->header_type_adv = 0; - ble_p->header.data.llid = radio_p->s0 & 0x3; - ble_p->header.data.nesn = (radio_p->s0 & - BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0; - ble_p->header.data.sn = (radio_p->s0 & - BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0; - ble_p->header.data.md = (radio_p->s0 & - BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0; - /* Length check? 0-31 Bytes */ - ble_p->header.data.length = radio_p->length; - } - - if (radio_p->length > 0) - memcpy(ble_p->payload, radio_p->payload, radio_p->length); -} - -struct ble_pdu adv_packet; -struct nrf51_ble_packet_t on_air_packet; - -struct ble_pdu rcv_packet; - -int ble_radio_init(uint32_t access_address, uint32_t crc_init_val) -{ - int rv = radio_init(BLE_1MBIT); - - if (rv) - return rv; - NRF51_RADIO_CRCCNF = 3 | NRF51_RADIO_CRCCNF_SKIP_ADDR; /* 3-byte CRC */ - /* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */ - /* 0x1_0000_0000_0000_0110_0101_1011 */ - NRF51_RADIO_CRCPOLY = 0x100065B; - - NRF51_RADIO_CRCINIT = crc_init_val; - - NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM; - - NRF51_RADIO_BASE0 = access_address << 8; - NRF51_RADIO_PREFIX0 = access_address >> 24; - - if (access_address != BLE_ADV_ACCESS_ADDRESS) - CPRINTF("Initializing radio for data packet.\n"); - - NRF51_RADIO_TXADDRESS = 0; - NRF51_RADIO_RXADDRESSES = 1; - NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_ADV_DATA; - NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_ADV_DATA; - - return rv; - -} - -static struct nrf51_ble_packet_t tx_packet; - -static uint32_t tx_end, rsp_end; - -void ble_tx(struct ble_pdu *pdu) -{ - uint32_t timeout_time; - - ble2nrf_packet(pdu, &tx_packet); - - NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet; - NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0; - NRF51_RADIO_RXEN = 0; - NRF51_RADIO_TXEN = 1; - - timeout_time = get_time().val + RADIO_SETUP_TIMEOUT; - while (!NRF51_RADIO_READY) { - if (get_time().val > timeout_time) { - CPRINTF("ERROR DURING RADIO TX SETUP. TRY AGAIN.\n"); - return; - } - } - - timeout_time = get_time().val + RADIO_SETUP_TIMEOUT; - while (!NRF51_RADIO_END) { - if (get_time().val > timeout_time) { - CPRINTF("RADIO DID NOT SHUT DOWN AFTER TX. " - "RECOMMEND REBOOT.\n"); - return; - } - } - NRF51_RADIO_DISABLE = 1; -} - -static struct nrf51_ble_packet_t rx_packet; -int ble_rx(struct ble_pdu *pdu, int timeout, int adv) -{ - uint32_t done; - uint32_t timeout_time; - int ppi_channel_requested; - - /* Prevent illegal wait times */ - if (timeout <= 0) { - NRF51_RADIO_DISABLE = 1; - return EC_ERROR_TIMEOUT; - } - - NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet; - NRF51_RADIO_END = NRF51_RADIO_PAYLOAD = NRF51_RADIO_ADDRESS = 0; - /* - * These shortcuts cause packet transmission 150 microseconds after - * packet receive, as is the BTLE standard. See NRF51 manual: - * section 17.1.12 - */ - NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START | - NRF51_RADIO_SHORTS_DISABLED_TXEN | - NRF51_RADIO_SHORTS_END_DISABLE; - - /* - * This creates a shortcut that marks the time - * that the payload was received by the radio - * in NRF51_TIMER_CC(0,1) - */ - ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1; - if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) { - NRF51_PPI_CHEN |= BIT(ppi_channel_requested); - NRF51_PPI_CHENSET |= BIT(ppi_channel_requested); - } - - - NRF51_RADIO_RXEN = 1; - - timeout_time = get_time().val + RADIO_SETUP_TIMEOUT; - while (!NRF51_RADIO_READY) { - if (get_time().val > timeout_time) { - CPRINTF("RADIO NOT SET UP IN TIME. TIMING OUT.\n"); - return EC_ERROR_TIMEOUT; - } - } - - timeout_time = get_time().val + timeout; - do { - if (get_time().val >= timeout_time) { - NRF51_RADIO_DISABLE = 1; - return EC_ERROR_TIMEOUT; - } - done = NRF51_RADIO_END; - } while (!done); - - rsp_end = get_time().le.lo; - - if (NRF51_RADIO_CRCSTATUS == 0) { - CPRINTF("INVALID CRC\n"); - return EC_ERROR_CRC; - } - - nrf2ble_packet(pdu, &rx_packet, adv); - - /* - * Throw error if radio not yet disabled. Something has - * gone wrong. May be in an unexpected state. - */ - if (NRF51_RADIO_DISABLED != 1) - return EC_ERROR_UNKNOWN; - - return EC_SUCCESS; -} - -/* White list handling */ -int ble_radio_clear_white_list(void) -{ - NRF51_RADIO_DACNF = 0; - return EC_SUCCESS; -} - -int ble_radio_read_white_list_size(uint8_t *ret_size) -{ - int i, size = 0; - uint32_t dacnf = NRF51_RADIO_DACNF; - - /* Count the bits that are set */ - for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) - if (dacnf & NRF51_RADIO_DACNF_ENA(i)) - size++; - - *ret_size = size; - - return EC_SUCCESS; -} - -int ble_radio_add_device_to_white_list(const uint8_t *addr_ptr, uint8_t rand) -{ - uint32_t dacnf = NRF51_RADIO_DACNF; - int i; - uint32_t aligned; - - /* Check for duplicates using ble_radio_remove_device? */ - - /* Find a free entry */ - for (i = 0; i < NRF51_RADIO_DACNF_MAX && - (dacnf & NRF51_RADIO_DACNF_ENA(i)); i++) - ; - - if (i == NRF51_RADIO_DACNF_MAX) - return EC_ERROR_OVERFLOW; - - memcpy(&aligned, addr_ptr, 4); - NRF51_RADIO_DAB(i) = aligned; - memcpy(&aligned, addr_ptr + 4, 2); - NRF51_RADIO_DAP(i) = aligned; - - NRF51_RADIO_DACNF = dacnf | NRF51_RADIO_DACNF_ENA(i) | - (rand ? NRF51_RADIO_DACNF_TXADD(i) : 0); - - return EC_SUCCESS; -} - -int ble_radio_remove_device_from_white_list(const uint8_t *addr_ptr, - uint8_t rand) -{ - int i, dacnf = NRF51_RADIO_DACNF; - - /* Find a matching entry */ - for (i = 0; i < NRF51_RADIO_DACNF_MAX; i++) { - uint32_t dab = NRF51_RADIO_DAB(i), dap = NRF51_RADIO_DAP(i); - - if ((dacnf & NRF51_RADIO_DACNF_ENA(i)) && /* Enabled */ - /* Rand flag matches */ - (rand == ((dacnf & NRF51_RADIO_DACNF_TXADD(i)) != 0)) && - /* Address matches */ - (!memcmp(addr_ptr, &dab, 4)) && - (!memcmp(addr_ptr + 4, &dap, 2))) - break; - } - - if (i == NRF51_RADIO_DACNF_MAX) /* Not found is successfully removed */ - return EC_SUCCESS; - - NRF51_RADIO_DACNF = dacnf & ~((NRF51_RADIO_DACNF_ENA(i)) | - (rand ? NRF51_RADIO_DACNF_TXADD(i) : 0)); - - return EC_SUCCESS; -} - - -int ble_adv_packet(struct ble_pdu *adv_packet, int chan) -{ - int done; - int rv; - - /* Change channel */ - NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan)); - NRF51_RADIO_DATAWHITEIV = chan; - - ble_tx(adv_packet); - - do { - done = NRF51_RADIO_END; - } while (!done); - - tx_end = get_time().le.lo; - - if (adv_packet->header.adv.type == - BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND) - return EC_SUCCESS; - - rv = ble_rx(&rcv_packet, 16000, 1); - - if (rv != EC_SUCCESS) - return rv; - - /* Check for valid responses */ - switch (rcv_packet.header.adv.type) { - case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ: - /* Scan requests are only allowed for ADV_IND and SCAN_IND */ - if (adv_packet->header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_IND && - adv_packet->header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) - return rv; - /* The advertising address needs to match */ - if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS], - &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS)) - return rv; - break; - case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ: - /* Connections are only allowed for two types of advertising */ - if (adv_packet->header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_IND && - adv_packet->header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND) - return rv; - /* The advertising address needs to match */ - if (memcmp(&rcv_packet.payload[BLUETOOTH_ADDR_OCTETS], - &adv_packet->payload[0], BLUETOOTH_ADDR_OCTETS)) - return rv; - /* The InitAddr needs to match for Directed advertising */ - if (adv_packet->header.adv.type == - BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && - memcmp(&adv_packet->payload[BLUETOOTH_ADDR_OCTETS], - &rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS)) - return rv; - break; - default: /* Unhandled response packet */ - return rv; - break; - } - - dump_ble_packet(&rcv_packet); - CPRINTF("tx_end %u Response %u\n", tx_end, rsp_end); - - return rv; -} - -int ble_adv_event(struct ble_pdu *adv_packet) -{ - int chan; - int rv; - - for (chan = 37; chan < 40; chan++) { - rv = ble_adv_packet(adv_packet, chan); - if (rv != EC_SUCCESS) - return rv; - } - - return rv; -} - -static void fill_header(struct ble_pdu *adv, int type, int txaddr, int rxaddr) -{ - adv->header_type_adv = 1; - adv->header.adv.type = type; - adv->header.adv.txaddr = txaddr ? - BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR; - adv->header.adv.rxaddr = rxaddr ? - BLE_ADV_HEADER_RANDOM_ADDR : BLE_ADV_HEADER_PUBLIC_ADDR; - adv->header.adv.length = 0; -} - -static int fill_payload(uint8_t *payload, uint64_t addr, int name_length) -{ - uint8_t *curr; - - curr = pack_adv_addr(payload, addr); - curr = pack_adv(curr, name_length, GAP_COMPLETE_NAME, - "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrs"); - curr = pack_adv_int(curr, 2, GAP_APPEARANCE, - GAP_APPEARANCE_HID_KEYBOARD); - curr = pack_adv_int(curr, 1, GAP_FLAGS, - GAP_FLAGS_LE_LIM_DISC | GAP_FLAGS_LE_NO_BR_EDR); - curr = pack_adv_int(curr, 2, GAP_COMP_16_BIT_UUID, - GATT_SERVICE_HID_UUID); - - return curr - payload; -} - -static void fill_packet(struct ble_pdu *adv, uint64_t addr, int type, - int name_length) -{ - fill_header(adv, type, BLE_ADV_HEADER_RANDOM_ADDR, - BLE_ADV_HEADER_PUBLIC_ADDR); - - adv->header.adv.length = fill_payload(adv->payload, addr, name_length); -} - -static int command_ble_adv(int argc, char **argv) -{ - int type, length, reps, interval; - uint64_t addr; - char *e; - int i; - int rv; - - if (argc < 3 || argc > 5) - return EC_ERROR_PARAM_COUNT; - - type = strtoi(argv[1], &e, 0); - if (*e || type < 0 || (type > 2 && type != 6)) - return EC_ERROR_PARAM1; - - length = strtoi(argv[2], &e, 0); - if (*e || length > 32) - return EC_ERROR_PARAM2; - - if (argc >= 4) { - reps = strtoi(argv[3], &e, 0); - if (*e || reps < 0) - return EC_ERROR_PARAM3; - } else { - reps = 1; - } - - if (argc >= 5) { - interval = strtoi(argv[4], &e, 0); - if (*e || interval < 0) - return EC_ERROR_PARAM4; - } else { - interval = 100000; - } - - if (type == BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && length != 12) { - length = 12; - CPRINTS("type DIRECT needs to have a length of 12"); - } - - rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT); - - - CPRINTS("ADV @%pP", &adv_packet); - - ((uint32_t *)&addr)[0] = 0xA3A2A1A0 | type; - ((uint32_t *)&addr)[1] = BLE_RANDOM_ADDR_MSBS_STATIC << 8 | 0x5A4; - - fill_packet(&adv_packet, addr, type, length); - - for (i = 0; i < reps; i++) { - ble_adv_event(&adv_packet); - usleep(interval); - } - - return rv; -} -DECLARE_CONSOLE_COMMAND(ble_adv, command_ble_adv, - "type len [reps] [interval = 100000 (100ms)]", - "Send a BLE packet of type type of length len"); - -static int command_ble_adv_scan(int argc, char **argv) -{ - int chan, packets, i; - int addr_lsbyte; - char *e; - int rv; - - if (argc < 2) - return EC_ERROR_PARAM_COUNT; - - chan = strtoi(argv[1], &e, 0); - if (*e || chan < 37 || chan > 39) - return EC_ERROR_PARAM1; - - chan = strtoi(argv[1], &e, 0); - if (*e || chan < 37 || chan > 39) - return EC_ERROR_PARAM1; - - if (argc >= 3) { - packets = strtoi(argv[2], &e, 0); - if (*e || packets < 0) - return EC_ERROR_PARAM2; - } else { - packets = 1; - } - - if (argc >= 4) { - addr_lsbyte = strtoi(argv[3], &e, 0); - if (*e || addr_lsbyte > 255) - return EC_ERROR_PARAM3; - } else { - addr_lsbyte = -1; - } - - rv = ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT); - - /* Change channel */ - NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(chan)); - NRF51_RADIO_DATAWHITEIV = chan; - - CPRINTS("ADV Listen"); - if (addr_lsbyte != -1) - CPRINTS("filtered (%x)", addr_lsbyte); - - for (i = 0; i < packets; i++) { - rv = ble_rx(&rcv_packet, 1000000, 1); - - if (rv == EC_ERROR_TIMEOUT) - continue; - - if (addr_lsbyte == -1 || rcv_packet.payload[0] == addr_lsbyte) - dump_ble_packet(&rcv_packet); - } - - rv = radio_disable(); - - CPRINTS("on_air payload rcvd %pP", &rx_packet); - - return rv; -} -DECLARE_CONSOLE_COMMAND(ble_scan, command_ble_adv_scan, - "chan [num] [addr0]", - "Scan for [num] BLE packets on channel chan"); - diff --git a/chip/nrf51/bluetooth_le.h b/chip/nrf51/bluetooth_le.h deleted file mode 100644 index a2b3807a7e..0000000000 --- a/chip/nrf51/bluetooth_le.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __NRF51_BLUETOOTH_LE_H -#define __NRF51_BLUETOOTH_LE_H - -#include "common.h" -#include "include/bluetooth_le.h" - -#define NRF51_BLE_LENGTH_BITS 8 -#define NRF51_BLE_S0_BYTES 1 -#define NRF51_BLE_S1_BITS 0 /* no s1 field */ - -#define BLE_ACCESS_ADDRESS_BYTES 4 -#define EXTRA_RECEIVE_BYTES 0 -#define BLE_ADV_WHITEN 1 - -#define RADIO_SETUP_TIMEOUT 1000 - -/* Data and Advertisements have the same PCNF values */ -#define NRF51_RADIO_PCNF0_ADV_DATA \ - NRF51_RADIO_PCNF0_VAL(NRF51_BLE_LENGTH_BITS, \ - NRF51_BLE_S0_BYTES, \ - NRF51_BLE_S1_BITS) - -#define NRF51_RADIO_PCNF1_ADV_DATA \ - NRF51_RADIO_PCNF1_VAL(BLE_MAX_ADV_PAYLOAD_OCTETS, \ - EXTRA_RECEIVE_BYTES, \ - BLE_ACCESS_ADDRESS_BYTES - 1, \ - BLE_ADV_WHITEN) - -struct nrf51_ble_packet_t { - uint8_t s0; /* First byte */ - uint8_t length; /* Length field */ - uint8_t payload[BLE_MAX_DATA_PAYLOAD_OCTETS]; -} __packed; - -struct nrf51_ble_config_t { - uint8_t channel; - uint8_t address; - uint32_t crc_init; -}; - -/* Initialize the nRF51 radio for BLE */ -int ble_radio_init(uint32_t access_address, uint32_t crc_init_val); - -/* Transmit pdu on the radio */ -void ble_tx(struct ble_pdu *pdu); - -/* Receive a packet into pdu if one comes before the timeout */ -int ble_rx(struct ble_pdu *pdu, int timeout, int adv); - -/* White list handling */ - -/* Clear the white list */ -int ble_radio_clear_white_list(void); - -/* Read the size of the white list and assign it to ret_size */ -int ble_radio_read_white_list_size(uint8_t *ret_size); - -/* Add the device with the address specified by addr_ptr and type */ -int ble_radio_add_device_to_white_list(const uint8_t *addr_ptr, uint8_t type); - -/* Remove the device with the address specified by addr_ptr and type */ -int ble_radio_remove_device_from_white_list(const uint8_t *addr_ptr, - uint8_t type); - -#endif /* __NRF51_BLUETOOTH_LE_H */ diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk deleted file mode 100644 index 7a7a33d402..0000000000 --- a/chip/nrf51/build.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -*- makefile -*- -# Copyright 2014 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# nRF51822 chip specific files build -# - -CORE:=cortex-m0 -# Force ARMv6-M ISA used by the Cortex-M0 -# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M -# without "svc" instruction, but that was short-lived. ARMv6S-M was the option -# with "svc". GCC kept that naming scheme even though the distinction is long -# gone. -CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 - -chip-y+=gpio.o system.o uart.o -chip-y+=watchdog.o ppi.o - -chip-$(CONFIG_BLUETOOTH_LE)+=radio.o bluetooth_le.o -chip-$(CONFIG_BLUETOOTH_LE_RADIO_TEST)+=radio_test.o -chip-$(CONFIG_COMMON_TIMER)+=hwtimer.o clock.o -chip-$(CONFIG_I2C)+=i2c.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif diff --git a/chip/nrf51/clock.c b/chip/nrf51/clock.c deleted file mode 100644 index fe56140175..0000000000 --- a/chip/nrf51/clock.c +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -void clock_init(void) -{ -} - -int clock_get_freq(void) -{ - /* constant 16 MHz clock */ - return 16000000; -} diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h deleted file mode 100644 index 401ac4779f..0000000000 --- a/chip/nrf51/config_chip.h +++ /dev/null @@ -1,64 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#include "core/cortex-m0/config_core.h" - -/* System stack size */ -#define CONFIG_STACK_SIZE 1024 - -/* Idle task stack size */ -#define IDLE_TASK_STACK_SIZE 256 - -/* Default task stack size */ -#define TASK_STACK_SIZE 488 - -/* Larger task stack size, for hook task */ -#define LARGER_TASK_STACK_SIZE 640 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* Number of I2C ports */ -#define I2C_PORT_COUNT 2 - -/* - * --- chip variant settings --- - */ - -/* RAM mapping */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 - -/* Flash mapping */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 -#define CONFIG_FLASH_SIZE 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 - -/* Memory-mapped internal flash */ -#define CONFIG_INTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE - -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE - -/* Compute the rest of the flash params from these */ -#include "config_std_internal_flash.h" - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Not that much RAM, set to smaller */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 1024 - -#define GPIO_PIN(port, index) GPIO_##port, BIT(index) -#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) - -#endif /* __CROS_EC_CONFIG_CHIP_H */ - diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c deleted file mode 100644 index 53694b5a74..0000000000 --- a/chip/nrf51/gpio.c +++ /dev/null @@ -1,311 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * For each interrupt (INT0-INT3, PORT), record which GPIO entry uses it. - */ - -static const struct gpio_info *gpio_ints[NRF51_GPIOTE_IN_COUNT]; -static const struct gpio_info *gpio_int_port; - -volatile uint32_t * const nrf51_alt_funcs[] = { - /* UART */ - &NRF51_UART_PSELRTS, - &NRF51_UART_PSELTXD, - &NRF51_UART_PSELCTS, - &NRF51_UART_PSELRXD, - /* SPI1 (SPI Master) */ - &NRF51_SPI0_PSELSCK, - &NRF51_SPI0_PSELMOSI, - &NRF51_SPI0_PSELMISO, - /* TWI0 (I2C) */ - &NRF51_TWI0_PSELSCL, - &NRF51_TWI0_PSELSDA, - /* SPI1 (SPI Master) */ - &NRF51_SPI1_PSELSCK, - &NRF51_SPI1_PSELMOSI, - &NRF51_SPI1_PSELMISO, - /* TWI1 (I2C) */ - &NRF51_TWI1_PSELSCL, - &NRF51_TWI1_PSELSDA, - /* SPIS1 (SPI SLAVE) */ - &NRF51_SPIS1_PSELSCK, - &NRF51_SPIS1_PSELMISO, - &NRF51_SPIS1_PSELMOSI, - &NRF51_SPIS1_PSELCSN, - /* QDEC (ROTARY DECODER) */ - &NRF51_QDEC_PSELLED, - &NRF51_QDEC_PSELA, - &NRF51_QDEC_PSELB, - /* LPCOMP (Low Power Comparator) */ - &NRF51_LPCOMP_PSEL, -}; - -const unsigned int nrf51_alt_func_count = ARRAY_SIZE(nrf51_alt_funcs); - -/* Make sure the function table and defines stay in sync */ -BUILD_ASSERT(ARRAY_SIZE(nrf51_alt_funcs) == NRF51_MAX_ALT_FUNCS && - NRF51_MAX_ALT_FUNCS <= GPIO_ALT_FUNC_MAX); - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - uint32_t val = 0; - uint32_t bit = GPIO_MASK_TO_NUM(mask); - - if (flags & GPIO_OUTPUT) - val |= NRF51_PIN_CNF_DIR_OUTPUT; - else if (flags & GPIO_INPUT) - val |= NRF51_PIN_CNF_DIR_INPUT; - - if (flags & GPIO_PULL_DOWN) - val |= NRF51_PIN_CNF_PULLDOWN; - else if (flags & GPIO_PULL_UP) - val |= NRF51_PIN_CNF_PULLUP; - - /* TODO: Drive strength? H0D1? */ - if (flags & GPIO_OPEN_DRAIN) - val |= NRF51_PIN_CNF_DRIVE_S0D1; - - if (flags & GPIO_OUTPUT) { - if (flags & GPIO_HIGH) - NRF51_GPIO0_OUTSET = mask; - else if (flags & GPIO_LOW) - NRF51_GPIO0_OUTCLR = mask; - } - - /* Interrupt levels */ - if (flags & GPIO_INT_SHARED) { - /* - * There are no shared edge-triggered interrupts; - * they're either high or low. - */ - ASSERT((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) == 0); - ASSERT((flags & GPIO_INT_LEVEL) != GPIO_INT_LEVEL); - if (flags & GPIO_INT_F_LOW) - val |= NRF51_PIN_CNF_SENSE_LOW; - else if (flags & GPIO_INT_F_HIGH) - val |= NRF51_PIN_CNF_SENSE_HIGH; - } - - NRF51_PIN_CNF(bit) = val; -} - - -static void gpio_init(void) -{ - task_enable_irq(NRF51_PERID_GPIOTE); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return !!(NRF51_GPIO0_IN & gpio_list[signal].mask); -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - if (value) - NRF51_GPIO0_OUTSET = gpio_list[signal].mask; - else - NRF51_GPIO0_OUTCLR = gpio_list[signal].mask; -} - - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - int is_warm = 0; - int i; - - if (NRF51_POWER_RESETREAS & - (NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */ - NRF51_POWER_RESETREAS_LPCOMP)) { - /* This is a warm reboot */ - is_warm = 1; - } - - /* Initialize Interrupt configuration */ - for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) - gpio_ints[i] = NULL; - gpio_int_port = NULL; - - /* Set all GPIOs to defaults */ - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels again. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - /* Set up GPIO based on flags */ - gpio_set_flags_by_mask(g->port, g->mask, flags); - } -} - -/* - * NRF51 doesn't have an alternate function table. - * Use the pin select registers in place of the function number. - */ -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - uint32_t bit = GPIO_MASK_TO_NUM(mask); - - ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */ - ASSERT(port == GPIO_0); - ASSERT((func >= GPIO_ALT_FUNC_DEFAULT && func < nrf51_alt_func_count) || - func == GPIO_ALT_FUNC_NONE); - - /* Remove the previous setting(s) */ - if (func == GPIO_ALT_FUNC_NONE) { - int i; - for (i = 0; i < nrf51_alt_func_count; i++) { - if (*(nrf51_alt_funcs[i]) == bit) - *(nrf51_alt_funcs[i]) = 0xffffffff; - } - } else { - *(nrf51_alt_funcs[func]) = bit; - } -} - - -/* - * Enable the interrupt associated with the "signal" - * The architecture has one general (PORT) - * and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts. - * - */ -int gpio_enable_interrupt(enum gpio_signal signal) -{ - int pin; - const struct gpio_info *g = gpio_list + signal; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - /* If it's not shared, use INT0-INT3, otherwise use PORT. */ - if (!(g->flags & GPIO_INT_SHARED)) { - int int_num, free_slot = -1; - uint32_t event_config = 0; - - for (int_num = 0; int_num < NRF51_GPIOTE_IN_COUNT; int_num++) { - if (gpio_ints[int_num] == g) - return EC_SUCCESS; /* This is already set up. */ - - if (gpio_ints[int_num] == NULL && free_slot == -1) - free_slot = int_num; - } - - ASSERT(free_slot != -1); - - gpio_ints[free_slot] = g; - pin = GPIO_MASK_TO_NUM(g->mask); - event_config = (pin << NRF51_GPIOTE_PSEL_POS) | - NRF51_GPIOTE_MODE_EVENT; - - ASSERT(g->flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)); - - /* RISING | FALLING = TOGGLE */ - if (g->flags & GPIO_INT_F_RISING) - event_config |= NRF51_GPIOTE_POLARITY_LOTOHI; - if (g->flags & GPIO_INT_F_FALLING) - event_config |= NRF51_GPIOTE_POLARITY_HITOLO; - - NRF51_GPIOTE_CONFIG(free_slot) = event_config; - - /* Enable the IN[] interrupt. */ - NRF51_GPIOTE_INTENSET = 1 << free_slot; - - } else { - /* The first handler for the shared interrupt wins. */ - if (gpio_int_port == NULL) { - gpio_int_port = g; - - /* Enable the PORT interrupt. */ - NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT; - } - } - - return EC_SUCCESS; -} - -/* - * Disable the interrupt associated with the "signal" - * The architecture has one general (PORT) - * and NRF51_GPIOTE_IN_COUNT single-pin (IN0, IN1, ...) interrupts. - */ -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - int i; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - /* If it's not shared, use INT0-INT3, otherwise use PORT. */ - if (!(g->flags & GPIO_INT_SHARED)) { - for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) { - /* Remove matching handler. */ - if (gpio_ints[i] == g) { - /* Disable the interrupt */ - NRF51_GPIOTE_INTENCLR = - 1 << NRF51_GPIOTE_IN_BIT(i); - /* Zero the handler */ - gpio_ints[i] = NULL; - } - } - } else { - /* Disable the interrupt */ - NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT; - /* Zero the shared handler */ - gpio_int_port = NULL; - } - - return EC_SUCCESS; -} - -/* - * Clear interrupt and run handler. - */ -void gpio_interrupt(void) -{ - const struct gpio_info *g; - int i; - int signal; - - for (i = 0; i < NRF51_GPIOTE_IN_COUNT; i++) { - if (NRF51_GPIOTE_IN(i)) { - NRF51_GPIOTE_IN(i) = 0; - g = gpio_ints[i]; - signal = g - gpio_list; - if (g && signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } - } - - if (NRF51_GPIOTE_PORT) { - NRF51_GPIOTE_PORT = 0; - g = gpio_int_port; - signal = g - gpio_list; - if (g && signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } -} -DECLARE_IRQ(NRF51_PERID_GPIOTE, gpio_interrupt, 1); diff --git a/chip/nrf51/hwtimer.c b/chip/nrf51/hwtimer.c deleted file mode 100644 index 980a889657..0000000000 --- a/chip/nrf51/hwtimer.c +++ /dev/null @@ -1,179 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Hardware timers driver. - * - * nRF51x has one fully functional hardware counter, but 4 stand-alone - * capture/compare (CC) registers. - */ - -#include "common.h" -#include "console.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* - * capture/compare (CC) registers: - * CC_INTERRUPT -- used to interrupt next clock event. - * CC_CURRENT -- used to capture the current value. - * CC_OVERFLOW -- used to detect overflow on virtual timer (not hardware). - */ - -#define CC_INTERRUPT 0 -#define CC_CURRENT 1 -#define CC_OVERFLOW 2 - -/* The nRF51 has 3 timers, use HWTIMER to specify which one is used here. */ -#define HWTIMER 0 - -static uint32_t last_deadline; /* cache of event set */ - -/* - * The nRF51x timer cannot be set to a specified value (reset to zero only). - * Thus, we have to use a variable "shift" to maintain the offset between the - * hardware value and virtual clock value. - * - * Once __hw_clock_source_set(ts) is called, the shift will be like: - * - * virtual time ------------------------------------------------ - * <----------> ^ - * shift | ts - * 0 | | - * hardware v - * counter time ------------------------------------------------ - * - * - * Below diagram shows what it is when overflow happens. - * - * | now | prev_read - * v v - * virtual time ------------------------------------------------ - * ----> <------ - * shift shift - * | - * hardware v - * counter time ------------------------------------------------ - * - */ -static uint32_t shift; - -void __hw_clock_event_set(uint32_t deadline) -{ - last_deadline = deadline; - NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = deadline - shift; - - /* enable interrupt */ - NRF51_TIMER_INTENSET(HWTIMER) = - 1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT); -} - -uint32_t __hw_clock_event_get(void) -{ - return last_deadline; -} - -void __hw_clock_event_clear(void) -{ - /* disable interrupt */ - NRF51_TIMER_INTENCLR(HWTIMER) = - 1 << NRF51_TIMER_COMPARE_BIT(CC_INTERRUPT); -} - -uint32_t __hw_clock_source_read(void) -{ - /* to capture the current value */ - NRF51_TIMER_CAPTURE(HWTIMER, CC_CURRENT) = 1; - return NRF51_TIMER_CC(HWTIMER, CC_CURRENT) + shift; -} - -void __hw_clock_source_set(uint32_t ts) -{ - shift = ts; - - /* reset counter to zero */ - NRF51_TIMER_STOP(HWTIMER) = 1; - NRF51_TIMER_CLEAR(HWTIMER) = 1; - - /* So that no interrupt until next __hw_clock_event_set() */ - NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = ts - 1; - - /* Update the overflow point */ - NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0 - shift; - - /* Start the timer again */ - NRF51_TIMER_START(HWTIMER) = 1; -} - - -/* Interrupt handler for timer */ -void timer_irq(void) -{ - int overflow = 0; - - /* clear status */ - NRF51_TIMER_COMPARE(HWTIMER, CC_INTERRUPT) = 0; - - if (NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW)) { - NRF51_TIMER_COMPARE(HWTIMER, CC_OVERFLOW) = 0; - overflow = 1; - } - - process_timers(overflow); -} - -/* DECLARE_IRQ doesn't like the NRF51_PERID_TIMER(n) macro */ -BUILD_ASSERT(NRF51_PERID_TIMER(HWTIMER) == NRF51_PERID_TIMER0); -DECLARE_IRQ(NRF51_PERID_TIMER0, timer_irq, 1); - -int __hw_clock_source_init(uint32_t start_t) -{ - - /* Start the high freq crystal oscillator */ - NRF51_CLOCK_HFCLKSTART = 1; - /* TODO: check if the crystal oscillator is running (HFCLKSTAT) */ - - /* 32-bit timer mode */ - NRF51_TIMER_MODE(HWTIMER) = NRF51_TIMER_MODE_TIMER; - NRF51_TIMER_BITMODE(HWTIMER) = NRF51_TIMER_BITMODE_32; - - /* - * The external crystal oscillator is 16MHz (HFCLK). - * Set the prescaler to 16 so that the timer counter is increasing - * every micro-second (us). - */ - NRF51_TIMER_PRESCALER(HWTIMER) = 4; /* actual value is 2**4 = 16 */ - - /* Not to trigger interrupt until __hw_clock_event_set() is called. */ - NRF51_TIMER_CC(HWTIMER, CC_INTERRUPT) = 0xffffffff; - - /* Set to 0 so that the next overflow can trigger timer_irq(). */ - NRF51_TIMER_CC(HWTIMER, CC_OVERFLOW) = 0; - NRF51_TIMER_INTENSET(HWTIMER) = - 1 << NRF51_TIMER_COMPARE_BIT(CC_OVERFLOW); - - /* Clear the timer counter */ - NRF51_TIMER_CLEAR(HWTIMER) = 1; - - /* Override the count with the start value now that counting has - * started. */ - __hw_clock_source_set(start_t); - - /* Enable interrupt */ - task_enable_irq(NRF51_PERID_TIMER(HWTIMER)); - - /* Start the timer */ - NRF51_TIMER_START(HWTIMER) = 1; - - return NRF51_PERID_TIMER(HWTIMER); -} - diff --git a/chip/nrf51/i2c.c b/chip/nrf51/i2c.c deleted file mode 100644 index 09a4a210e6..0000000000 --- a/chip/nrf51/i2c.c +++ /dev/null @@ -1,304 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "ppi.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_TIMEOUT 20000 - -/* Keep track of the PPI channel used for each port */ -static int i2c_ppi_chan[] = {-1, -1}; - -static void i2c_init_port(unsigned int port); - -/* board-specific setup for post-I2C module init */ -void __board_i2c_post_init(int port) -{ -} - -void board_i2c_post_init(int port) - __attribute__((weak, alias("__board_i2c_post_init"))); - -static void i2c_init_port(unsigned int port) -{ - NRF51_TWI_RXDRDY(port) = 0; - NRF51_TWI_TXDSENT(port) = 0; - - NRF51_TWI_PSELSCL(port) = NRF51_TWI_SCL_PIN(port); - NRF51_TWI_PSELSDA(port) = NRF51_TWI_SDA_PIN(port); - NRF51_TWI_FREQUENCY(port) = NRF51_TWI_FREQ(port); - - NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port]; - - NRF51_PPI_EEP(i2c_ppi_chan[port]) = (uint32_t)&NRF51_TWI_BB(port); - NRF51_PPI_TEP(i2c_ppi_chan[port]) = - (uint32_t)&NRF51_TWI_SUSPEND(port); - - /* Master enable */ - NRF51_TWI_ENABLE(port) = NRF51_TWI_ENABLE_VAL; - - if (!(i2c_raw_get_scl(port) && (i2c_raw_get_sda(port)))) - CPRINTF("port %d could be wedged\n", port); -} - -void i2c_init(void) -{ - int i, rv; - - gpio_config_module(MODULE_I2C, 1); - - for (i = 0; i < i2c_ports_used; i++) { - if (i2c_ppi_chan[i] == -1) { - rv = ppi_request_channel(&i2c_ppi_chan[i]); - ASSERT(rv == EC_SUCCESS); - - i2c_init_port(i); - } - } -} - -static void dump_i2c_reg(int port) -{ -#ifdef CONFIG_I2C_DEBUG - CPRINTF("port : %01d\n", port); - CPRINTF("Regs :\n"); - CPRINTF(" 1: INTEN : %08x\n", NRF51_TWI_INTEN(port)); - CPRINTF(" 2: ERRORSRC : %08x\n", NRF51_TWI_ERRORSRC(port)); - CPRINTF(" 3: ENABLE : %08x\n", NRF51_TWI_ENABLE(port)); - CPRINTF(" 4: PSELSCL : %08x\n", NRF51_TWI_PSELSCL(port)); - CPRINTF(" 5: PSELSDA : %08x\n", NRF51_TWI_PSELSDA(port)); - CPRINTF(" 6: RXD : %08x\n", NRF51_TWI_RXD(port)); - CPRINTF(" 7: TXD : %08x\n", NRF51_TWI_TXD(port)); - CPRINTF(" 8: FREQUENCY : %08x\n", NRF51_TWI_FREQUENCY(port)); - CPRINTF(" 9: ADDRESS : %08x\n", NRF51_TWI_ADDRESS(port)); - CPRINTF("Events :\n"); - CPRINTF(" STOPPED : %08x\n", NRF51_TWI_STOPPED(port)); - CPRINTF(" RXDRDY : %08x\n", NRF51_TWI_RXDRDY(port)); - CPRINTF(" TXDSENT : %08x\n", NRF51_TWI_TXDSENT(port)); - CPRINTF(" ERROR : %08x\n", NRF51_TWI_ERROR(port)); - CPRINTF(" BB : %08x\n", NRF51_TWI_BB(port)); -#endif /* CONFIG_I2C_DEBUG */ -} - -static void i2c_recover(int port) -{ - /* - * Recovery of the TWI peripheral: - * To recover a TWI peripheral that has been locked up you must use - * the following code. - * After the recover function it is important to reconfigure all - * relevant TWI registers explicitly to ensure that it operates - * correctly. - * TWI0: - * NRF_TWI0->ENABLE = - * TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - * *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 0; - * nrf_delay_us(5); - * *(uint32_t *)(NRF_TWI0_BASE + 0xFFC) = 1; - * NRF_TWI0->ENABLE = - * TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos; - */ - NRF51_TWI_ENABLE(port) = NRF51_TWI_DISABLE_VAL; - NRF51_TWI_POWER(port) = 0; - udelay(5); - NRF51_TWI_POWER(port) = 1; - - i2c_init_port(port); -} - -static void handle_i2c_error(int port, int rv) -{ - if (rv == EC_SUCCESS) - return; - -#ifdef CONFIG_I2C_DEBUG - if (rv != EC_ERROR_TIMEOUT) - CPRINTF("handle_i2c_error %d\n", rv); - else - CPRINTF("handle_i2c_error: Timeout\n"); - - dump_i2c_reg(port); -#endif - - /* This may be a little too heavy handed. */ - i2c_recover(port); -} - -static int i2c_master_write(const int port, const uint16_t slave_addr_flags, - const uint8_t *data, int size, int stop) -{ - int bytes_sent; - int timeout = I2C_TIMEOUT; - - NRF51_TWI_ADDRESS(port) = I2C_GET_ADDR(slave_addr_flags); - - /* Clear the sent bit */ - NRF51_TWI_TXDSENT(port) = 0; - - for (bytes_sent = 0; bytes_sent < size; bytes_sent++) { - /*Send a byte */ - NRF51_TWI_TXD(port) = data[bytes_sent]; - - /* Only send a start for the first byte */ - if (bytes_sent == 0) - NRF51_TWI_STARTTX(port) = 1; - - /* Wait for ACK/NACK */ - timeout = I2C_TIMEOUT; - while (timeout > 0 && NRF51_TWI_TXDSENT(port) == 0 && - NRF51_TWI_ERROR(port) == 0) - timeout--; - - if (timeout == 0) - return EC_ERROR_TIMEOUT; - - if (NRF51_TWI_ERROR(port)) - return EC_ERROR_UNKNOWN; - - /* Clear the sent bit */ - NRF51_TWI_TXDSENT(port) = 0; - } - - if (stop) { - NRF51_TWI_STOPPED(port) = 0; - NRF51_TWI_STOP(port) = 1; - timeout = 10; - while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0) - timeout--; - } - - return EC_SUCCESS; -} - -static int i2c_master_read(const int port, const uint16_t slave_addr_flags, - uint8_t *data, int size) -{ - int curr_byte; - int timeout = I2C_TIMEOUT; - - NRF51_TWI_ADDRESS(port) = I2C_GET_ADDR(slave_addr_flags); - - if (size == 1) /* Last byte: stop after this one. */ - NRF51_PPI_TEP(i2c_ppi_chan[port]) = - (uint32_t)&NRF51_TWI_STOP(port); - else - NRF51_PPI_TEP(i2c_ppi_chan[port]) = - (uint32_t)&NRF51_TWI_SUSPEND(port); - NRF51_PPI_CHENSET = 1 << i2c_ppi_chan[port]; - - NRF51_TWI_RXDRDY(port) = 0; - NRF51_TWI_STARTRX(port) = 1; - - for (curr_byte = 0; curr_byte < size; curr_byte++) { - - /* Wait for data */ - while (timeout > 0 && NRF51_TWI_RXDRDY(port) == 0 && - NRF51_TWI_ERROR(port) == 0) - timeout--; - - if (timeout == 0) - return EC_ERROR_TIMEOUT; - - if (NRF51_TWI_ERROR(port)) - return EC_ERROR_UNKNOWN; - - data[curr_byte] = NRF51_TWI_RXD(port); - NRF51_TWI_RXDRDY(port) = 0; - - /* Second to the last byte: stop next time. */ - if (curr_byte == size-2) - NRF51_PPI_TEP(i2c_ppi_chan[port]) = - (uint32_t)&NRF51_TWI_STOP(port); - - /* - * According to nRF51822-PAN v2.4 (Product Anomaly Notice), - * the I2C locks up when RESUME is triggered too soon. - * "the firmware should ensure that the time between receiving - * the RXDRDY event and trigging the RESUME task is at least - * two times the TWI clock period (i.e. 20 μs at 100 kbps). - * Provided the TWI slave doesn’t do clock stretching during - * the ACK bit, this will be enough to avoid the RESUME task - * hit the end of the ACK bit. If this fails, a recovery of - * the peripheral will be necessary, see i2c_recover. - */ - udelay(20); - NRF51_TWI_RESUME(port) = 1; - } - - timeout = I2C_TIMEOUT; - while (NRF51_TWI_STOPPED(port) == 0 && timeout > 0) - timeout--; - - NRF51_TWI_STOP(port) = 0; - - NRF51_PPI_CHENCLR = 1 << i2c_ppi_chan[port]; - - return EC_SUCCESS; -} - -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int rv = EC_SUCCESS; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - if (out_bytes) - rv = i2c_master_write(port, slave_addr_flags, - out, out_bytes, - in_bytes ? 0 : 1); - if (rv == EC_SUCCESS && in_bytes) - rv = i2c_master_read(port, slave_addr_flags, - in, in_bytes); - - handle_i2c_error(port, rv); - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - diff --git a/chip/nrf51/keyboard_raw.c b/chip/nrf51/keyboard_raw.c deleted file mode 100644 index 779c68454c..0000000000 --- a/chip/nrf51/keyboard_raw.c +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for nRF51 - * - * To make this code portable, we rely heavily on looping over the keyboard - * input and output entries in the board's gpio_list[]. Each set of inputs or - * outputs must be listed in consecutive, increasing order so that scan loops - * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are - * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX). - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* Mask of output pins for driving. */ -static unsigned int col_mask; - -void keyboard_raw_init(void) -{ - int i; - - /* Initialize col_mask */ - col_mask = 0; - for (i = 0; i < keyboard_cols; i++) - col_mask |= gpio_list[GPIO_KB_OUT00 + i].mask; - - /* Ensure interrupts are disabled */ - keyboard_raw_enable_interrupt(0); -} - -void keyboard_raw_task_start(void) -{ - /* - * Enable the interrupt for keyboard matrix inputs. - * One is enough, since they are shared. - */ - gpio_enable_interrupt(GPIO_KB_IN00); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - /* tri-state all first */ - NRF51_GPIO0_OUTSET = col_mask; - - /* drive low for specified pin(s) */ - if (out == KEYBOARD_COLUMN_ALL) - NRF51_GPIO0_OUTCLR = col_mask; - else if (out != KEYBOARD_COLUMN_NONE) - NRF51_GPIO0_OUTCLR = gpio_list[GPIO_KB_OUT00 + out].mask; -} - -test_mockable int keyboard_raw_read_rows(void) -{ - int i; - int state = 0; - - for (i = 0; i < KEYBOARD_ROWS; i++) { - if (NRF51_GPIO0_IN & gpio_list[GPIO_KB_IN00 + i].mask) - state |= 1 << i; - } - - /* Invert it so 0=not pressed, 1=pressed */ - return state ^ 0xff; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - /* - * Clear the PORT event before enabling the interrupt. - */ - NRF51_GPIOTE_PORT = 0; - NRF51_GPIOTE_INTENSET = 1 << NRF51_GPIOTE_PORT_BIT; - } else { - NRF51_GPIOTE_INTENCLR = 1 << NRF51_GPIOTE_PORT_BIT; - } -} - -void keyboard_raw_gpio_interrupt(enum gpio_signal signal) -{ - task_wake(TASK_ID_KEYSCAN); -} diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c deleted file mode 100644 index 016cbf3008..0000000000 --- a/chip/nrf51/ppi.c +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "ppi.h" -#include "registers.h" -#include "util.h" - -#define NRF51_PPI_FIRST_PP_CH NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN -#define NRF51_PPI_LAST_PP_CH NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START - -static uint32_t channels_in_use; -static uint32_t channel_groups_in_use; - -int ppi_request_pre_programmed_channel(int ppi_chan) -{ - ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH && - ppi_chan <= NRF51_PPI_LAST_PP_CH); - - if (channels_in_use & BIT(ppi_chan)) - return EC_ERROR_BUSY; - - channels_in_use |= BIT(ppi_chan); - - return EC_SUCCESS; -} - -int ppi_request_channel(int *ppi_chan) -{ - int chan; - - for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++) - if ((channels_in_use & BIT(chan)) == 0) - break; - - if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS) - return EC_ERROR_BUSY; - - channels_in_use |= BIT(chan); - *ppi_chan = chan; - return EC_SUCCESS; -} - -void ppi_release_channel(int ppi_chan) -{ - channels_in_use &= ~BIT(ppi_chan); -} - -void ppi_release_group(int ppi_group) -{ - channel_groups_in_use &= ~BIT(ppi_group); -} - -int ppi_request_group(int *ppi_group) -{ - int group; - - for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++) - if ((channel_groups_in_use & BIT(group)) == 0) - break; - - if (group == NRF51_PPI_NUM_GROUPS) - return EC_ERROR_BUSY; - - channel_groups_in_use |= BIT(group); - *ppi_group = group; - return EC_SUCCESS; -} diff --git a/chip/nrf51/ppi.h b/chip/nrf51/ppi.h deleted file mode 100644 index bbb74a2cf0..0000000000 --- a/chip/nrf51/ppi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * PPI channels are a way to connect NRF51 EVENTs to TASKs without software - * involvement. They are like SHORTs, except between peripherals. - * - * PPI groups are user-defined sets of channels that can be enabled and disabled - * together. - */ - -/* - * Reserve a pre-programmed PPI channel. - * - * Return EC_SUCCESS if ppi_chan is a pre-programmed channel that was not in - * use, otherwise returns EC_ERROR_BUSY. - */ -int ppi_request_pre_programmed_channel(int ppi_chan); - -/* - * Reserve an available PPI channel. - * - * Return EC_SUCCESS and set the value of ppi_chan to an available PPI - * channel. If no channel is available, return EC_ERROR_BUSY. - */ -int ppi_request_channel(int *ppi_chan); - -/* Release a PPI channel which was reserved with ppi_request_*_channel. */ -void ppi_release_channel(int ppi_chan); - -/* - * Reserve a PPI group. - * - * Return EC_SUCCESS and set the value of ppi_group to an available PPI - * group. If no group is available, return EC_ERROR_BUSY. - */ -int ppi_request_group(int *ppi_group); - -/* Release a PPI channel which was reserved with ppi_request_*_channel. */ -void ppi_release_group(int ppi_group); diff --git a/chip/nrf51/radio.c b/chip/nrf51/radio.c deleted file mode 100644 index af9d029a0d..0000000000 --- a/chip/nrf51/radio.c +++ /dev/null @@ -1,59 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "radio.h" - -int radio_disable(void) -{ - int timeout = 10000; - - NRF51_RADIO_DISABLED = 0; - NRF51_RADIO_DISABLE = 1; - - while (!NRF51_RADIO_DISABLED && timeout > 0) - timeout--; - - if (timeout == 0) - return EC_ERROR_TIMEOUT; - - return EC_SUCCESS; -} - -int radio_init(enum nrf51_radio_mode_t mode) -{ - int err_code = radio_disable(); - - if (mode == BLE_1MBIT) { - NRF51_RADIO_MODE = NRF51_RADIO_MODE_BLE_1MBIT; - - NRF51_RADIO_TIFS = 150; /* Bluetooth 4.1 Vol 6 pg 58 4.1 */ - - /* - * BLE never sends or receives two packets in a row. - * Enabling the radio means we want to transmit or receive. - * After transmission, disable as quickly as possible. - */ - NRF51_RADIO_SHORTS = NRF51_RADIO_SHORTS_READY_START | - NRF51_RADIO_SHORTS_END_DISABLE; - - /* Use factory parameters if available */ - if (!(NRF51_FICR_OVERRIDEEN & NRF51_FICR_OVERRIDEEN_BLE_BIT_N) - ) { - int i; - - for (i = 0; i < 4; i++) { - NRF51_RADIO_OVERRIDE(i) = - NRF51_FICR_BLE_1MBIT(i); - } - NRF51_RADIO_OVERRIDE(4) = NRF51_FICR_BLE_1MBIT(4) | - NRF51_RADIO_OVERRIDE_EN; - } - } else { - return EC_ERROR_UNIMPLEMENTED; - } - - return err_code; -} - diff --git a/chip/nrf51/radio.h b/chip/nrf51/radio.h deleted file mode 100644 index 5b7e764fb9..0000000000 --- a/chip/nrf51/radio.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Radio interface for Chrome EC */ - -#ifndef __NRF51_RADIO_H -#define __NRF51_RADIO_H - -#include "common.h" -#include "compile_time_macros.h" -#include "registers.h" - -#ifndef NRF51_RADIO_MAX_PAYLOAD - #define NRF51_RADIO_MAX_PAYLOAD 253 -#endif - -#define RADIO_DONE (NRF51_RADIO_END == 1) - -enum nrf51_radio_mode_t { - BLE_1MBIT = NRF51_RADIO_MODE_BLE_1MBIT, -}; - -struct nrf51_radio_packet_t { - uint8_t s0; /* First byte */ - uint8_t length; /* Length field */ - uint8_t s1; /* Bits after length */ - uint8_t payload[NRF51_RADIO_MAX_PAYLOAD]; -} __packed; - -int radio_init(enum nrf51_radio_mode_t mode); - -int radio_disable(void); - -#endif /* __NRF51_RADIO_H */ diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c deleted file mode 100644 index 6c20874f4e..0000000000 --- a/chip/nrf51/radio_test.c +++ /dev/null @@ -1,184 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "bluetooth_le.h" /* chan2freq */ -#include "btle_hci_int.h" -#include "console.h" -#include "radio.h" -#include "radio_test.h" -#include "registers.h" -#include "timer.h" -#include "util.h" - -#define BLE_TEST_TYPE_PRBS9 0 -#define BLE_TEST_TYPE_F0 1 -#define BLE_TEST_TYPE_AA 2 -#define BLE_TEST_TYPE_PRBS15 3 -#define BLE_TEST_TYPE_FF 4 -#define BLE_TEST_TYPE_00 5 -#define BLE_TEST_TYPE_0F 6 -#define BLE_TEST_TYPE_55 7 - -#define BLE_TEST_TYPES_IMPLEMENTED 0xf6 /* No PRBS yet */ - -static struct nrf51_ble_packet_t rx_packet; -static struct nrf51_ble_packet_t tx_packet; -static uint32_t rx_end; - -static int test_in_progress; - -void ble_test_stop(void) -{ - test_in_progress = 0; -} - -static uint32_t prbs_lfsr; -static uint32_t prbs_poly; - -/* - * This is a Galois LFSR, the polynomial is the counterpart of the Fibonacci - * LFSR in the doc. It requires fewer XORs to implement in software. - * This also means that the initial value is different. - */ -static uint8_t prbs_next_byte(void) -{ - int i; - int lsb; - uint8_t rv = 0; - - for (i = 0; i < 8; i++) { - lsb = prbs_lfsr & 1; - rv |= lsb << i; - prbs_lfsr = prbs_lfsr >> 1; - if (lsb) - prbs_lfsr ^= prbs_poly; - } - return rv; -} - -void ble_test_fill_tx_packet(int type, int len) -{ - int i; - - tx_packet.s0 = type & 0xf; - tx_packet.length = len; - - switch (type) { - case BLE_TEST_TYPE_PRBS9: - prbs_lfsr = 0xf; - prbs_poly = 0x108; - for (i = 0; i < len; i++) - tx_packet.payload[i] = prbs_next_byte(); - break; - case BLE_TEST_TYPE_PRBS15: - prbs_lfsr = 0xf; - prbs_poly = 0x6000; - for (i = 0; i < len; i++) - tx_packet.payload[i] = prbs_next_byte(); - break; - case BLE_TEST_TYPE_F0: - memset(tx_packet.payload, 0xF0, len); - break; - case BLE_TEST_TYPE_AA: - memset(tx_packet.payload, 0xAA, len); - break; - case BLE_TEST_TYPE_FF: - memset(tx_packet.payload, 0xFF, len); - break; - case BLE_TEST_TYPE_00: - memset(tx_packet.payload, 0x00, len); - break; - case BLE_TEST_TYPE_0F: - memset(tx_packet.payload, 0x0F, len); - break; - case BLE_TEST_TYPE_55: - memset(tx_packet.payload, 0x55, len); - break; - default: - break; - } -} - -static int ble_test_init(int chan) -{ - int rv = radio_init(BLE_1MBIT); - - if (rv) - return HCI_ERR_Hardware_Failure; - - if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL) - return HCI_ERR_Invalid_HCI_Command_Parameters; - - NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */ - /* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */ - /* 0x1_0000_0000_0000_0110_0101_1011 */ - NRF51_RADIO_CRCPOLY = 0x100065B; - NRF51_RADIO_CRCINIT = 0x555555; - - NRF51_RADIO_TXPOWER = NRF51_RADIO_TXPOWER_0_DBM; - - /* The testing address is the inverse of the advertising address. */ - NRF51_RADIO_BASE0 = (~BLE_ADV_ACCESS_ADDRESS) << 8; - - NRF51_RADIO_PREFIX0 = (~BLE_ADV_ACCESS_ADDRESS) >> 24; - - NRF51_RADIO_TXADDRESS = 0; - NRF51_RADIO_RXADDRESSES = 1; - - NRF51_RADIO_PCNF0 = NRF51_RADIO_PCNF0_TEST; - - NRF51_RADIO_PCNF1 = NRF51_RADIO_PCNF1_TEST; - - NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(2*chan + 2402); - - test_in_progress = 1; - return rv; -} - -int ble_test_rx_init(int chan) -{ - NRF51_RADIO_PACKETPTR = (uint32_t)&rx_packet; - return ble_test_init(chan); -} - -int ble_test_tx_init(int chan, int len, int type) -{ - if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 || - (len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS)) - return HCI_ERR_Invalid_HCI_Command_Parameters; - - ble_test_fill_tx_packet(type, len); - NRF51_RADIO_PACKETPTR = (uint32_t)&tx_packet; - - return ble_test_init(chan); -} - -void ble_test_tx(void) -{ - NRF51_RADIO_END = 0; - NRF51_RADIO_TXEN = 1; -} - -int ble_test_rx(void) -{ - int retries = 100; - - NRF51_RADIO_END = 0; - NRF51_RADIO_RXEN = 1; - - do { - retries--; - if (retries <= 0) { - radio_disable(); - return EC_ERROR_TIMEOUT; - } - usleep(100); - } while (!NRF51_RADIO_END); - - rx_end = get_time().le.lo; - - return EC_SUCCESS; -} - diff --git a/chip/nrf51/radio_test.h b/chip/nrf51/radio_test.h deleted file mode 100644 index 591b78a78c..0000000000 --- a/chip/nrf51/radio_test.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Radio test interface for NRF51 - * - * These functions implement parts of the Direct Test Mode functionality in - * the Bluetooth Spec. - */ - -#ifndef __NRF51_RADIO_TEST_H -#define __NRF51_RADIO_TEST_H - -#define BLE_MAX_TEST_PAYLOAD_OCTETS 37 -#define BLE_MAX_TEST_CHANNEL 39 -#define BLE_MIN_TEST_CHANNEL 0 - -#define NRF51_RADIO_PCNF0_TEST NRF51_RADIO_PCNF0_ADV_DATA - -#define BLE_TEST_WHITEN 0 - -#define NRF51_RADIO_PCNF1_TEST \ - NRF51_RADIO_PCNF1_VAL(BLE_MAX_TEST_PAYLOAD_OCTETS, \ - EXTRA_RECEIVE_BYTES, \ - BLE_ACCESS_ADDRESS_BYTES - 1, \ - BLE_TEST_WHITEN) - -/* - * Prepare the radio for transmitting packets. The value of chan must be - * between 0 and 39 inclusive. The maximum length is 37. - */ - -int ble_test_tx_init(int chan, int type, int len); -int ble_test_rx_init(int chan); -void ble_test_tx(void); -int ble_test_rx(void); -void ble_test_stop(void); - -#endif /* __NRF51_RADIO_TEST_H */ diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h deleted file mode 100644 index d41e80c76c..0000000000 --- a/chip/nrf51/registers.h +++ /dev/null @@ -1,720 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for STM32 processor - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" - -/* - * Peripheral IDs - * - * nRF51 has very good design that the peripheral IDs is actually the IRQ#. - * Thus, the following numbers are used in DECLARE_IRQ(), task_enable_irq() - * and task_disable_irq(). - */ -#define NRF51_PERID_POWER 0 -#define NRF51_PERID_CLOCK 0 -#define NRF51_PERID_RADIO 1 -#define NRF51_PERID_USART 2 -#define NRF51_PERID_SPI0 3 -#define NRF51_PERID_TWI0 3 -#define NRF51_PERID_SPI1 4 -#define NRF51_PERID_TWI1 4 -#define NRF51_PERID_SPIS 4 -#define NRF51_PERID_GPIOTE 6 -#define NRF51_PERID_ADC 7 -#define NRF51_PERID_TIMER0 8 -#define NRF51_PERID_TIMER1 9 -#define NRF51_PERID_TIMER2 10 -#define NRF51_PERID_RTC 11 -#define NRF51_PERID_TEMP 12 -#define NRF51_PERID_RNG 13 -#define NRF51_PERID_ECB 14 -#define NRF51_PERID_CCM 15 -#define NRF51_PERID_AAR 16 -#define NRF51_PERID_WDT 17 -#define NRF51_PERID_QDEC 18 -#define NRF51_PERID_LPCOMP 19 -#define NRF51_PERID_NVMC 30 -#define NRF51_PERID_PPI 31 - -/* - * The nRF51 allows any pin to be mapped to any function. This - * doesn't fit well with the notion of the alternate function table. - * Implement an alternate function table. See ./gpio.c. - */ - - /* UART */ -#define NRF51_UART_ALT_FUNC_RTS 0 -#define NRF51_UART_ALT_FUNC_TXD 1 -#define NRF51_UART_ALT_FUNC_CTS 2 -#define NRF51_UART_ALT_FUNC_RXD 3 - /* SPI1 (SPI Master) */ -#define NRF51_SPI0_ALT_FUNC_SCK 4 -#define NRF51_SPI0_ALT_FUNC_MOSI 5 -#define NRF51_SPI0_ALT_FUNC_MISO 6 - /* TWI0 (I2C) */ -#define NRF51_TWI0_ALT_FUNC_SCL 7 -#define NRF51_TWI0_ALT_FUNC_SDA 8 - /* SPI1 (SPI Master) */ -#define NRF51_SPI1_ALT_FUNC_SCK 9 -#define NRF51_SPI1_ALT_FUNC_MOSI 10 -#define NRF51_SPI1_ALT_FUNC_MISO 11 - /* TWI1 (I2C) */ -#define NRF51_TWI1_ALT_FUNC_SCL 12 -#define NRF51_TWI1_ALT_FUNC_SDA 13 - /* SPIS1 (SPI SLAVE) */ -#define NRF51_SPIS1_ALT_FUNC_SCK 14 -#define NRF51_SPIS1_ALT_FUNC_MISO 15 -#define NRF51_SPIS1_ALT_FUNC_MOSI 16 -#define NRF51_SPIS1_ALT_FUNC_CSN 17 - /* QDEC (ROTARY DECODER) */ -#define NRF51_QDEC_ALT_FUNC_LED 18 -#define NRF51_QDEC_ALT_FUNC_A 19 -#define NRF51_QDEC_ALT_FUNC_B 20 - /* LPCOMP (Low Power Comparator) */ -#define NRF51_LPCOMP_ALT_FUNC 21 -#define NRF51_MAX_ALT_FUNCS 22 - -/* - * Configuration Registers - */ - -/* - * FICR - */ -#define NRF51_FICR_BASE 0x10000000 -#define NRF51_FICR_CODEPAGESIZE REG32(NRF51_FICR_BASE + 0x010) -#define NRF51_FICR_CLENR0 REG32(NRF51_FICR_BASE + 0x014) -#define NRF51_FICR_PPFC REG32(NRF51_FICR_BASE + 0x028) -#define NRF51_FICR_NUMRAMBLOCK REG32(NRF51_FICR_BASE + 0x02C) -#define NRF51_FICR_SIZERAMBLOCK(n) REG32(NRF51_FICR_BASE + 0x034 + ((n)*4)) -#define NRF51_FICR_CONFIGID REG32(NRF51_FICR_BASE + 0x05C) -#define NRF51_FICR_DEVICEID(n) REG32(NRF51_FICR_BASE + 0x060 + ((n)*4)) -#define NRF51_FICR_ER(n) REG32(NRF51_FICR_BASE + 0x080 + ((n)*4)) -#define NRF51_FICR_IR(n) REG32(NRF51_FICR_BASE + 0x090 + ((n)*4)) -#define NRF51_FICR_DEVICEADDRTYPE REG32(NRF51_FICR_BASE + 0x0A0) -#define NRF51_FICR_DEVICEADDR(n) REG32(NRF51_FICR_BASE + 0x0A4 + ((n)*4)) -#define NRF51_FICR_OVERRIDEEN REG32(NRF51_FICR_BASE + 0x0AC) -#define NRF51_FICR_BLE_1MBIT(n) REG32(NRF51_FICR_BASE + 0x0EC + ((n)*4)) - -/* DEVICEADDRTYPE */ -#define NRF51_FICR_DEVICEADDRTYPE_RANDOM 1 - -/* OVERRIDEEN */ -#define NRF51_FICR_OVERRIDEEN_NRF_BIT_N 1 -#define NRF51_FICR_OVERRIDEEN_BLE_BIT_N 8 - -/* - * UICR - */ -#define NRF51_UICR_BASE 0x10001000 -#define NRF51_UICR_CLENR0 REG32(NRF51_UICR_BASE + 0x000) -#define NRF51_UICR_RBPCONF REG32(NRF51_UICR_BASE + 0x004) -#define NRF51_UICR_XTALFREQ REG32(NRF51_UICR_BASE + 0x008) -#define NRF51_UICR_FWID REG32(NRF51_UICR_BASE + 0x010) -#define NRF51_UICR_FWID_CUSTOMER(n) REG32(NRF51_UICR_BASE + 0x080 + ((n)*4)) - -#define NRF51_UICR_XTALFREQ_16MHZ 0xFF -#define NRF51_UICR_XTALFREQ_32MHZ 0x00 - -/* - * Devices - */ - -/* - * Power - */ -#define NRF51_POWER_BASE 0x40000000 -/* Tasks */ -#define NRF51_POWER_CONSTLAT REG32(NRF51_POWER_BASE + 0x078) -#define NRF51_POWER_LOWPWR REG32(NRF51_POWER_BASE + 0x07C) -/* Events */ -#define NRF51_POWER_POFWARN REG32(NRF51_POWER_BASE + 0x108) -/* Registers */ -#define NRF51_POWER_INTENSET REG32(NRF51_POWER_BASE + 0x304) -#define NRF51_POWER_INTENCLR REG32(NRF51_POWER_BASE + 0x308) -#define NRF51_POWER_RESETREAS REG32(NRF51_POWER_BASE + 0x400) -#define NRF51_POWER_SYSTEMOFF REG32(NRF51_POWER_BASE + 0x500) -#define NRF51_POWER_POFCON REG32(NRF51_POWER_BASE + 0x510) -#define NRF51_POWER_GPREGRET REG32(NRF51_POWER_BASE + 0x51C) -#define NRF51_POWER_RAMON REG32(NRF51_POWER_BASE + 0x524) -#define NRF51_POWER_RESET REG32(NRF51_POWER_BASE + 0x544) -#define NRF51_POWER_DCDCEN REG32(NRF51_POWER_BASE + 0x578) - -#define NRF51_POWER_RESETREAS_RESETPIN 0x00001 -#define NRF51_POWER_RESETREAS_DOG 0x00002 -#define NRF51_POWER_RESETREAS_SREQ 0x00004 -#define NRF51_POWER_RESETREAS_LOCKUP 0x00008 -#define NRF51_POWER_RESETREAS_OFF 0x10000 -#define NRF51_POWER_RESETREAS_LPCOMP 0x20000 -#define NRF51_POWER_RESETREAS_DIF 0x40000 - - -/* - * Clock - */ -#define NRF51_CLOCK_BASE 0x40000000 -/* Tasks */ -#define NRF51_CLOCK_HFCLKSTART REG32(NRF51_CLOCK_BASE + 0x000) -#define NRF51_CLOCK_HFCLKSTOP REG32(NRF51_CLOCK_BASE + 0x004) -#define NRF51_CLOCK_LFCLKSTART REG32(NRF51_CLOCK_BASE + 0x008) -#define NRF51_CLOCK_LFCLKSTOP REG32(NRF51_CLOCK_BASE + 0x00C) -#define NRF51_CLOCK_CAL REG32(NRF51_CLOCK_BASE + 0x010) -#define NRF51_CLOCK_CTSTART REG32(NRF51_CLOCK_BASE + 0x014) -#define NRF51_CLOCK_CTSTOP REG32(NRF51_CLOCK_BASE + 0x018) -/* Events */ -#define NRF51_CLOCK_HFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x100) -#define NRF51_CLOCK_LFCLKSTARTED REG32(NRF51_CLOCK_BASE + 0x104) -#define NRF51_CLOCK_DONE REG32(NRF51_CLOCK_BASE + 0x10C) -#define NRF51_CLOCK_CCTO REG32(NRF51_CLOCK_BASE + 0x110) -/* Registers */ -#define NRF51_CLOCK_INTENSET REG32(NRF51_CLOCK_BASE + 0x304) -#define NRF51_CLOCK_INTENCLR REG32(NRF51_CLOCK_BASE + 0x308) -#define NRF51_CLOCK_HFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x40C) -#define NRF51_CLOCK_LFCLKSTAT REG32(NRF51_CLOCK_BASE + 0x418) -#define NRF51_CLOCK_LFCLKSRC REG32(NRF51_CLOCK_BASE + 0x518) -#define NRF51_CLOCK_CTIV REG32(NRF51_CLOCK_BASE + 0x538) -#define NRF51_CLOCK_XTALFREQ REG32(NRF51_CLOCK_BASE + 0x550) - -/* - * Radio - */ -#define NRF51_RADIO_BASE 0x40001000 -/* Tasks */ -#define NRF51_RADIO_TXEN REG32(NRF51_RADIO_BASE + 0x000) -#define NRF51_RADIO_RXEN REG32(NRF51_RADIO_BASE + 0x004) -#define NRF51_RADIO_START REG32(NRF51_RADIO_BASE + 0x008) -#define NRF51_RADIO_STOP REG32(NRF51_RADIO_BASE + 0x00C) -#define NRF51_RADIO_DISABLE REG32(NRF51_RADIO_BASE + 0x010) -#define NRF51_RADIO_RSSISTART REG32(NRF51_RADIO_BASE + 0x014) -#define NRF51_RADIO_RSSISTOP REG32(NRF51_RADIO_BASE + 0x018) -#define NRF51_RADIO_BCSTART REG32(NRF51_RADIO_BASE + 0x01C) -#define NRF51_RADIO_BCSTOP REG32(NRF51_RADIO_BASE + 0x020) -/* Events */ -#define NRF51_RADIO_READY REG32(NRF51_RADIO_BASE + 0x100) -#define NRF51_RADIO_ADDRESS REG32(NRF51_RADIO_BASE + 0x104) -#define NRF51_RADIO_PAYLOAD REG32(NRF51_RADIO_BASE + 0x108) -#define NRF51_RADIO_END REG32(NRF51_RADIO_BASE + 0x10C) -#define NRF51_RADIO_DISABLED REG32(NRF51_RADIO_BASE + 0x110) -#define NRF51_RADIO_DEVMATCH REG32(NRF51_RADIO_BASE + 0x114) -#define NRF51_RADIO_DEVMISS REG32(NRF51_RADIO_BASE + 0x118) -#define NRF51_RADIO_RSSIEND REG32(NRF51_RADIO_BASE + 0x11C) -#define NRF51_RADIO_BCMATCH REG32(NRF51_RADIO_BASE + 0x128) -/* Registers */ -#define NRF51_RADIO_SHORTS REG32(NRF51_RADIO_BASE + 0x200) -#define NRF51_RADIO_INTENSET REG32(NRF51_RADIO_BASE + 0x304) -#define NRF51_RADIO_INTENCLR REG32(NRF51_RADIO_BASE + 0x308) -#define NRF51_RADIO_CRCSTATUS REG32(NRF51_RADIO_BASE + 0x400) -#define NRF51_RADIO_RXMATCH REG32(NRF51_RADIO_BASE + 0x408) -#define NRF51_RADIO_RXCRC REG32(NRF51_RADIO_BASE + 0x40C) -#define NRF51_RADIO_DAI REG32(NRF51_RADIO_BASE + 0x410) -#define NRF51_RADIO_PACKETPTR REG32(NRF51_RADIO_BASE + 0x504) -#define NRF51_RADIO_FREQUENCY REG32(NRF51_RADIO_BASE + 0x508) -#define NRF51_RADIO_TXPOWER REG32(NRF51_RADIO_BASE + 0x50C) -#define NRF51_RADIO_MODE REG32(NRF51_RADIO_BASE + 0x510) -#define NRF51_RADIO_PCNF0 REG32(NRF51_RADIO_BASE + 0x514) -#define NRF51_RADIO_PCNF1 REG32(NRF51_RADIO_BASE + 0x518) -#define NRF51_RADIO_BASE0 REG32(NRF51_RADIO_BASE + 0x51C) -#define NRF51_RADIO_BASE1 REG32(NRF51_RADIO_BASE + 0x520) -#define NRF51_RADIO_PREFIX0 REG32(NRF51_RADIO_BASE + 0x524) -#define NRF51_RADIO_PREFIX1 REG32(NRF51_RADIO_BASE + 0x528) -#define NRF51_RADIO_TXADDRESS REG32(NRF51_RADIO_BASE + 0x52C) -#define NRF51_RADIO_RXADDRESSES REG32(NRF51_RADIO_BASE + 0x530) -#define NRF51_RADIO_CRCCNF REG32(NRF51_RADIO_BASE + 0x534) -#define NRF51_RADIO_CRCPOLY REG32(NRF51_RADIO_BASE + 0x538) -#define NRF51_RADIO_CRCINIT REG32(NRF51_RADIO_BASE + 0x53C) -#define NRF51_RADIO_TEST REG32(NRF51_RADIO_BASE + 0x540) -#define NRF51_RADIO_TIFS REG32(NRF51_RADIO_BASE + 0x544) -#define NRF51_RADIO_RSSISAMPLE REG32(NRF51_RADIO_BASE + 0x548) -/* NRF51_RADIO_STATE (0x550) is Broken (PAN 2.4) */ -#define NRF51_RADIO_DATAWHITEIV REG32(NRF51_RADIO_BASE + 0x554) -#define NRF51_RADIO_BCC REG32(NRF51_RADIO_BASE + 0x560) -#define NRF51_RADIO_DAB(n) REG32(NRF51_RADIO_BASE + 0x600 + ((n) * 4)) -#define NRF51_RADIO_DAP(n) REG32(NRF51_RADIO_BASE + 0x620 + ((n) * 4)) -#define NRF51_RADIO_DACNF REG32(NRF51_RADIO_BASE + 0x640) -#define NRF51_RADIO_OVERRIDE(n) REG32(NRF51_RADIO_BASE + 0x724 + ((n) * 4)) -#define NRF51_RADIO_POWER REG32(NRF51_RADIO_BASE + 0xFFC) - -/* Shorts */ -#define NRF51_RADIO_SHORTS_READY_START 0x001 -#define NRF51_RADIO_SHORTS_END_DISABLE 0x002 -#define NRF51_RADIO_SHORTS_DISABLED_TXEN 0x004 -#define NRF51_RADIO_SHORTS_DISABLED_RXEN 0x008 -#define NRF51_RADIO_SHORTS_ADDRESS_RSSISTART 0x010 -/* NRF51_RADIO_SHORTS_END_START (0x20) is Broken (PAN 2.4) */ -#define NRF51_RADIO_SHORTS_ADDRESS_BCSTART 0x040 -#define NRF51_RADIO_SHORTS_DISABLED_RSSISTOP 0x100 - -/* For RADIO.INTEN bits */ -#define NRF51_RADIO_READY_BIT 0 -#define NRF51_RADIO_ADDRESS_BIT 1 -#define NRF51_RADIO_PAYLOAD_BIT 2 -#define NRF51_RADIO_END_BIT 3 -#define NRF51_RADIO_DISABLED_BIT 4 -#define NRF51_RADIO_DEVMATCH_BIT 5 -#define NRF51_RADIO_DEVMISS_BIT 6 -#define NRF51_RADIO_RSSIEND_BIT 7 -#define NRF51_RADIO_BCMATCH_BIT 10 - -/* CRC Status */ -#define NRF51_RADIO_CRCSTATUS_OK 0x1 - -/* Frequency (in MHz) */ -#define NRF51_RADIO_FREQUENCY_VAL(x) ((x) - 2400) - -/* TX Power */ -#define NRF51_RADIO_TXPOWER_POS_4_DBM 0x04 -#define NRF51_RADIO_TXPOWER_0_DBM 0x00 -#define NRF51_RADIO_TXPOWER_NEG_8_DBM 0xFC -#define NRF51_RADIO_TXPOWER_NEG_12_DBM 0xF8 -#define NRF51_RADIO_TXPOWER_NEG_16_DBM 0xF4 -#define NRF51_RADIO_TXPOWER_NEG_20_DBM 0xEC -#define NRF51_RADIO_TXPOWER_NEG_30_DBM 0xD8 - -/* TX Mode */ -#define NRF51_RADIO_MODE_BLE_1MBIT 0x03 - -/* - * PCNF0 and PCNF1 Packet Configuration - * - * The radio unpacks the packet for you according to these settings. - * - * The on-air format is: - * - * |_Preamble_|___Base___|_Prefix_|___S0____|_Length_,_S1_|__Payload__|___| - * 0 <ba_bytes> <1 byte><s0_bytes> <1 byte> <max_bytes> <extra> - * - * The in-memory format is - * - * uint8_t s0[s0_bytes]; - * uint8_t length; - * uint8_t s1; - * uint8_t payload[max_bytes]; - * - * lf_bits is how many bits to store in length - * s1_bits is how many bits to store in s1 - * - * If any one of these lengths are set to zero, the field is omitted in memory. - */ - -#define NRF51_RADIO_PCNF0_LFLEN_SHIFT 0 -#define NRF51_RADIO_PCNF0_S0LEN_SHIFT 8 -#define NRF51_RADIO_PCNF0_S1LEN_SHIFT 16 - -#define NRF51_RADIO_PCNF0_VAL(lf_bits, s0_bytes, s1_bits) \ - ((lf_bits) << NRF51_RADIO_PCNF0_LFLEN_SHIFT | \ - (s0_bytes) << NRF51_RADIO_PCNF0_S0LEN_SHIFT | \ - (s1_bits) << NRF51_RADIO_PCNF0_S1LEN_SHIFT) - -#define NRF51_RADIO_PCNF1_MAXLEN_SHIFT 0 -#define NRF51_RADIO_PCNF1_STATLEN_SHIFT 8 -#define NRF51_RADIO_PCNF1_BALEN_SHIFT 16 -#define NRF51_RADIO_PCNF1_ENDIAN_BIG 0x1000000 -#define NRF51_RADIO_PCNF1_WHITEEN 0x2000000 - -#define NRF51_RADIO_PCNF1_VAL(max_bytes, extra_bytes, ba_bytes, whiten) \ - ((max_bytes) << NRF51_RADIO_PCNF1_MAXLEN_SHIFT | \ - (extra_bytes) << NRF51_RADIO_PCNF1_STATLEN_SHIFT | \ - (ba_bytes) << NRF51_RADIO_PCNF1_BALEN_SHIFT | \ - ((whiten) ? NRF51_RADIO_PCNF1_WHITEEN : 0)) - -/* PREFIX0 */ -#define NRF51_RADIO_PREFIX0_AP0_SHIFT 0 -#define NRF51_RADIO_PREFIX0_AP1_SHIFT 8 -#define NRF51_RADIO_PREFIX0_AP2_SHIFT 16 -#define NRF51_RADIO_PREFIX0_AP3_SHIFT 24 - -/* PREFIX1 */ -#define NRF51_RADIO_PREFIX1_AP4_SHIFT 0 -#define NRF51_RADIO_PREFIX1_AP5_SHIFT 8 -#define NRF51_RADIO_PREFIX1_AP6_SHIFT 16 -#define NRF51_RADIO_PREFIX1_AP7_SHIFT 24 - -/* CRCCNF */ -#define NRF51_RADIO_CRCCNF_SKIP_ADDR 0x100 - -/* TEST */ -#define NRF51_RADIO_TEST_CONST_CARRIER_EN 0x01 -#define NRF51_RADIO_TEST_PLL_LOCK_EN 0x02 - -/* STATE */ -#define NRF51_RADIO_STATE_DISABLED 0 -#define NRF51_RADIO_STATE_RXRU 1 -#define NRF51_RADIO_STATE_RXIDLE 2 -#define NRF51_RADIO_STATE_RX 3 -#define NRF51_RADIO_STATE_RXDISABLE 4 -#define NRF51_RADIO_STATE_TXRU 9 -#define NRF51_RADIO_STATE_TXIDLE 10 -#define NRF51_RADIO_STATE_TX 11 -#define NRF51_RADIO_STATE_TXDISABLE 12 - -/* DACNF */ -#define NRF51_RADIO_DACNF_ENA(n) (1 << (n)) -#define NRF51_RADIO_DACNF_MAX 8 -#define NRF51_RADIO_DACNF_TXADD(n) (1 << ((n)+8)) -#define NRF51_RADIO_TXADD_MAX 8 - -/* OVERRIDE4 */ -#define NRF51_RADIO_OVERRIDE_EN BIT(31) - - -/* - * UART - */ -#define NRF51_UART_BASE 0x40002000 -/* Tasks */ -#define NRF51_UART_STARTRX REG32(NRF51_UART_BASE + 0x000) -#define NRF51_UART_STOPRX REG32(NRF51_UART_BASE + 0x004) -#define NRF51_UART_STARTTX REG32(NRF51_UART_BASE + 0x008) -#define NRF51_UART_STOPTX REG32(NRF51_UART_BASE + 0x00C) -/* Events */ -#define NRF51_UART_RXDRDY REG32(NRF51_UART_BASE + 0x108) -#define NRF51_UART_TXDRDY REG32(NRF51_UART_BASE + 0x11C) -#define NRF51_UART_ERROR REG32(NRF51_UART_BASE + 0x124) -#define NRF51_UART_RXTO REG32(NRF51_UART_BASE + 0x144) -/* Registers */ -#define NRF51_UART_INTENSET REG32(NRF51_UART_BASE + 0x304) -#define NRF51_UART_INTENCLR REG32(NRF51_UART_BASE + 0x308) -#define NRF51_UART_ERRORSRC REG32(NRF51_UART_BASE + 0x480) -#define NRF51_UART_ENABLE REG32(NRF51_UART_BASE + 0x500) -#define NRF51_UART_PSELRTS REG32(NRF51_UART_BASE + 0x508) -#define NRF51_UART_PSELTXD REG32(NRF51_UART_BASE + 0x50C) -#define NRF51_UART_PSELCTS REG32(NRF51_UART_BASE + 0x510) -#define NRF51_UART_PSELRXD REG32(NRF51_UART_BASE + 0x514) -#define NRF51_UART_RXD REG32(NRF51_UART_BASE + 0x518) -#define NRF51_UART_TXD REG32(NRF51_UART_BASE + 0x51C) -#define NRF51_UART_BAUDRATE REG32(NRF51_UART_BASE + 0x524) -#define NRF51_UART_CONFIG REG32(NRF51_UART_BASE + 0x56C) -/* For UART.INTEN bits */ -#define NRF55_UART_RXDRDY_BIT ((0x108 - 0x100) / 4) -#define NRF55_UART_TXDRDY_BIT ((0x11C - 0x100) / 4) - -/* - * TWI (I2C) Instances - */ -#define NRF51_TWI_BASE(port) (0x40003000 + ((port == 0) ? 0 : 0x1000)) -/* Tasks */ -#define NRF51_TWI_STARTRX(port) REG32(NRF51_TWI_BASE(port) + 0x000) -#define NRF51_TWI_STARTTX(port) REG32(NRF51_TWI_BASE(port) + 0x008) -#define NRF51_TWI_STOP(port) REG32(NRF51_TWI_BASE(port) + 0x014) -#define NRF51_TWI_SUSPEND(port) REG32(NRF51_TWI_BASE(port) + 0x01C) -#define NRF51_TWI_RESUME(port) REG32(NRF51_TWI_BASE(port) + 0x020) -/* Events */ -#define NRF51_TWI_STOPPED(port) REG32(NRF51_TWI_BASE(port) + 0x104) -#define NRF51_TWI_RXDRDY(port) REG32(NRF51_TWI_BASE(port) + 0x108) -#define NRF51_TWI_TXDSENT(port) REG32(NRF51_TWI_BASE(port) + 0x11C) -#define NRF51_TWI_ERROR(port) REG32(NRF51_TWI_BASE(port) + 0x124) -#define NRF51_TWI_BB(port) REG32(NRF51_TWI_BASE(port) + 0x138) -/* Registers */ -/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4) */ -#define NRF51_TWI_INTEN(port) REG32(NRF51_TWI_BASE(port) + 0x300) -#define NRF51_TWI_INTENSET(port) REG32(NRF51_TWI_BASE(port) + 0x304) -#define NRF51_TWI_INTENCLR(port) REG32(NRF51_TWI_BASE(port) + 0x308) -#define NRF51_TWI_ERRORSRC(port) REG32(NRF51_TWI_BASE(port) + 0x4C4) -#define NRF51_TWI_ENABLE(port) REG32(NRF51_TWI_BASE(port) + 0x500) -#define NRF51_TWI_PSELSCL(port) REG32(NRF51_TWI_BASE(port) + 0x508) -#define NRF51_TWI_PSELSDA(port) REG32(NRF51_TWI_BASE(port) + 0x50C) -#define NRF51_TWI_RXD(port) REG32(NRF51_TWI_BASE(port) + 0x518) -#define NRF51_TWI_TXD(port) REG32(NRF51_TWI_BASE(port) + 0x51C) -#define NRF51_TWI_FREQUENCY(port) REG32(NRF51_TWI_BASE(port) + 0x524) -#define NRF51_TWI_ADDRESS(port) REG32(NRF51_TWI_BASE(port) + 0x588) -#define NRF51_TWI_POWER(port) REG32(NRF51_TWI_BASE(port) + 0xFFC) - -#define NRF51_TWI_100KBPS 0x01980000 -#define NRF51_TWI_250KBPS 0x40000000 -#define NRF51_TWI_400KBPS 0x06680000 - -#define NRF51_TWI_ENABLE_VAL 0x5 -#define NRF51_TWI_DISABLE_VAL 0x0 - -#define NRF51_TWI_ERRORSRC_ANACK BIT(1) /* Address NACK */ -#define NRF51_TWI_ERRORSRC_DNACK BIT(2) /* Data NACK */ - -/* - * TWI (I2C) Instance 0 - */ -#define NRF51_TWI0_BASE 0x40003000 -/* Tasks */ -#define NRF51_TWI0_STARTRX REG32(NRF51_TWI0_BASE + 0x000) -#define NRF51_TWI0_STARTTX REG32(NRF51_TWI0_BASE + 0x008) -#define NRF51_TWI0_STOP REG32(NRF51_TWI0_BASE + 0x014) -#define NRF51_TWI0_SUSPEND REG32(NRF51_TWI0_BASE + 0x01C) -#define NRF51_TWI0_RESUME REG32(NRF51_TWI0_BASE + 0x020) -/* Events */ -#define NRF51_TWI0_STOPPED REG32(NRF51_TWI0_BASE + 0x104) -#define NRF51_TWI0_RXDRDY REG32(NRF51_TWI0_BASE + 0x108) -#define NRF51_TWI0_TXDSENT REG32(NRF51_TWI0_BASE + 0x11C) -#define NRF51_TWI0_ERROR REG32(NRF51_TWI0_BASE + 0x124) -#define NRF51_TWI0_BB REG32(NRF51_TWI0_BASE + 0x138) -/* Registers */ -/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4) */ -#define NRF51_TWI0_INTENSET REG32(NRF51_TWI0_BASE + 0x304) -#define NRF51_TWI0_INTENCLR REG32(NRF51_TWI0_BASE + 0x308) -#define NRF51_TWI0_ERRORSRC REG32(NRF51_TWI0_BASE + 0x4C4) -#define NRF51_TWI0_ENABLE REG32(NRF51_TWI0_BASE + 0x500) -#define NRF51_TWI0_PSELSCL REG32(NRF51_TWI0_BASE + 0x508) -#define NRF51_TWI0_PSELSDA REG32(NRF51_TWI0_BASE + 0x50C) -#define NRF51_TWI0_RXD REG32(NRF51_TWI0_BASE + 0x518) -#define NRF51_TWI0_TXD REG32(NRF51_TWI0_BASE + 0x51C) -#define NRF51_TWI0_FREQUENCY REG32(NRF51_TWI0_BASE + 0x524) -#define NRF51_TWI0_ADDRESS REG32(NRF51_TWI0_BASE + 0x588) - -/* For TWI0.INTEN bits */ -#define NRF55_TWI0_RXDRDY_BIT ((0x108 - 0x100) / 4) -#define NRF55_TWI0_TXDRDY_BIT ((0x11C - 0x100) / 4) - -/* - * TWI (I2C) Instance 1 - */ -#define NRF51_TWI1_BASE 0x40004000 -/* Tasks */ -#define NRF51_TWI1_STARTRX REG32(NRF51_TWI1_BASE + 0x000) -#define NRF51_TWI1_STARTTX REG32(NRF51_TWI1_BASE + 0x008) -#define NRF51_TWI1_STOP REG32(NRF51_TWI1_BASE + 0x014) -#define NRF51_TWI1_SUSPEND REG32(NRF51_TWI1_BASE + 0x01C) -#define NRF51_TWI1_RESUME REG32(NRF51_TWI1_BASE + 0x020) -/* Events */ -#define NRF51_TWI1_STOPPED REG32(NRF51_TWI1_BASE + 0x104) -#define NRF51_TWI1_RXDRDY REG32(NRF51_TWI1_BASE + 0x108) -#define NRF51_TWI1_TXDSENT REG32(NRF51_TWI1_BASE + 0x11C) -#define NRF51_TWI1_ERROR REG32(NRF51_TWI1_BASE + 0x124) -#define NRF51_TWI1_BB REG32(NRF51_TWI1_BASE + 0x138) -/* Registers */ -/* SHORTS not implemented for TWI (See nRF51822-PAN v2.4) */ -#define NRF51_TWI1_INTENSET REG32(NRF51_TWI1_BASE + 0x304) -#define NRF51_TWI1_INTENCLR REG32(NRF51_TWI1_BASE + 0x308) -#define NRF51_TWI1_ERRORSRC REG32(NRF51_TWI1_BASE + 0x4C4) -#define NRF51_TWI1_ENABLE REG32(NRF51_TWI1_BASE + 0x500) -#define NRF51_TWI1_PSELSCL REG32(NRF51_TWI1_BASE + 0x508) -#define NRF51_TWI1_PSELSDA REG32(NRF51_TWI1_BASE + 0x50C) -#define NRF51_TWI1_RXD REG32(NRF51_TWI1_BASE + 0x518) -#define NRF51_TWI1_TXD REG32(NRF51_TWI1_BASE + 0x51C) -#define NRF51_TWI1_FREQUENCY REG32(NRF51_TWI1_BASE + 0x524) -#define NRF51_TWI1_ADDRESS REG32(NRF51_TWI1_BASE + 0x588) - -/* For TWI1.INTEN bits */ -#define NRF55_TWI1_RXDRDY_BIT ((0x108 - 0x100) / 4) -#define NRF55_TWI1_TXDRDY_BIT ((0x11C - 0x100) / 4) - -/* - * GPIOTE - GPIO Tasks and Events - */ -#define NRF51_GPIOTE_BASE 0x40006000 -/* Tasks */ -#define NRF51_GPIOTE_OUT(n) REG32(NRF51_GPIOTE_BASE + ((n) * 4)) -/* Events */ -#define NRF51_GPIOTE_IN(n) REG32(NRF51_GPIOTE_BASE + 0x100 + ((n) * 4)) -#define NRF51_GPIOTE_PORT REG32(NRF51_GPIOTE_BASE + 0x17C) -/* Registers */ -#define NRF51_GPIOTE_INTENSET REG32(NRF51_GPIOTE_BASE + 0x304) -#define NRF51_GPIOTE_INTENCLR REG32(NRF51_GPIOTE_BASE + 0x308) -#define NRF51_GPIOTE_CONFIG(n) REG32(NRF51_GPIOTE_BASE + 0x510 + ((n) * 4)) -#define NRF51_GPIOTE_POWER REG32(NRF51_GPIOTE_BASE + 0xFFC) - -/* Number of IN events */ -#define NRF51_GPIOTE_IN_COUNT 4 - -/* Bits */ -/* For GPIOTE.INTEN */ -#define NRF51_GPIOTE_IN_BIT(n) (n) -#define NRF51_GPIOTE_PORT_BIT 31 -/* For GPIOTE.CONFIG */ -#define NRF51_GPIOTE_MODE_DISABLED (0<<0) -#define NRF51_GPIOTE_MODE_EVENT BIT(0) -#define NRF51_GPIOTE_MODE_TASK (3<<0) -#define NRF51_GPIOTE_PSEL_POS (8) -#define NRF51_GPIOTE_POLARITY_LOTOHI BIT(16) -#define NRF51_GPIOTE_POLARITY_HITOLO (2<<16) -#define NRF51_GPIOTE_POLARITY_TOGGLE (3<<16) -#define NRF51_GPIOTE_OUTINIT_LOW (0<<20) -#define NRF51_GPIOTE_OUTINIT_HIGH BIT(20) - -/* - * Timer / Counter - */ -#define NRF51_TIMER0_BASE 0x40008000 -#define NRF51_TIMER_BASE(n) (NRF51_TIMER0_BASE + (n) * 0x1000) -#define NRF51_PERID_TIMER(n) (NRF51_PERID_TIMER0 + (n)) -/* Tasks */ -#define NRF51_TIMER_START(n) REG32(NRF51_TIMER_BASE(n) + 0x000) -#define NRF51_TIMER_STOP(n) REG32(NRF51_TIMER_BASE(n) + 0x004) -#define NRF51_TIMER_COUNT(n) REG32(NRF51_TIMER_BASE(n) + 0x008) -#define NRF51_TIMER_CLEAR(n) REG32(NRF51_TIMER_BASE(n) + 0x00C) -#define NRF51_TIMER_CAPTURE(n, c) REG32(NRF51_TIMER_BASE(n) + 0x040 + 4 * (c)) -/* Events */ -#define NRF51_TIMER_COMPARE(n, c) REG32(NRF51_TIMER_BASE(n) + 0x140 + 4 * (c)) -/* Registers */ -#define NRF51_TIMER_SHORTCUT(n) REG32(NRF51_TIMER_BASE(n) + 0x200) -#define NRF51_TIMER_INTENSET(n) REG32(NRF51_TIMER_BASE(n) + 0x304) -#define NRF51_TIMER_INTENCLR(n) REG32(NRF51_TIMER_BASE(n) + 0x308) -#define NRF51_TIMER_MODE(n) REG32(NRF51_TIMER_BASE(n) + 0x504) -#define NRF51_TIMER_BITMODE(n) REG32(NRF51_TIMER_BASE(n) + 0x508) -#define NRF51_TIMER_PRESCALER(n) REG32(NRF51_TIMER_BASE(n) + 0x510) -#define NRF51_TIMER_CC(n, c) REG32(NRF51_TIMER_BASE(n) + 0x540 + 4 * (c)) -/* For Timer.INTEN bits */ -#define NRF51_TIMER_COMPARE_BIT(n) (((0x140 - 0x100) / 4) + (n)) -/* For Timer Shortcuts */ -#define NRF51_TIMER_COMPARE_CLEAR(n) (1 << (n)) -#define NRF51_TIMER_COMPARE_STOP(n) (1 << (8 + (n))) -/* Timer Mode (NRF51_TIMER_MODE) */ -#define NRF51_TIMER_MODE_TIMER 0 /* reset default */ -#define NRF51_TIMER_MODE_COUNTER 1 -/* Prescaler */ -#define NRF51_TIMER_PRESCALER_MASK (0xf) /* range: 0-9, reset default: 4 */ -/* Bit length (NRF51_TIMER_BITMODE) */ -#define NRF51_TIMER_BITMODE_16 0 /* reset default */ -#define NRF51_TIMER_BITMODE_8 1 -#define NRF51_TIMER_BITMODE_24 2 -#define NRF51_TIMER_BITMODE_32 3 - - -/* - * Random Number Generator (RNG) - */ -#define NRF51_RNG_BASE 0x4000D000 -/* Tasks */ -#define NRF51_RNG_START REG32(NRF51_RNG_BASE + 0x000) -#define NRF51_RNG_STOP REG32(NRF51_RNG_BASE + 0x004) -/* Events */ -#define NRF51_RNG_VALRDY REG32(NRF51_RNG_BASE + 0x100) -/* Registers */ -#define NRF51_RNG_SHORTS REG32(NRF51_RNG_BASE + 0x200) -#define NRF51_RNG_INTENSET REG32(NRF51_RNG_BASE + 0x304) -#define NRF51_RNG_INTENCLR REG32(NRF51_RNG_BASE + 0x308) -#define NRF51_RNG_CONFIG REG32(NRF51_RNG_BASE + 0x504) -#define NRF51_RNG_VALUE REG32(NRF51_RNG_BASE + 0x508) -/* For RNG Shortcuts */ -#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0) -/* For RNG Config */ -#define NRF51_RNG_DERCEN BIT(0) - - -/* - * Watchdog Timer (WDT) - */ -#define NRF51_WDT_BASE 0x40010000 -/* Tasks */ -#define NRF51_WDT_START REG32(NRF51_WDT_BASE + 0x000) -/* Events */ -#define NRF51_WDT_TIMEOUT REG32(NRF51_WDT_BASE + 0x100) -/* Registers */ -#define NRF51_WDT_INTENSET REG32(NRF51_WDT_BASE + 0x304) -#define NRF51_WDT_INTENCLR REG32(NRF51_WDT_BASE + 0x308) -#define NRF51_WDT_RUNSTATUS REG32(NRF51_WDT_BASE + 0x400) -#define NRF51_WDT_REQSTATUS REG32(NRF51_WDT_BASE + 0x404) -#define NRF51_WDT_CRV REG32(NRF51_WDT_BASE + 0x504) -#define NRF51_WDT_RREN REG32(NRF51_WDT_BASE + 0x508) -#define NRF51_WDT_CONFIG REG32(NRF51_WDT_BASE + 0x50C) -#define NRF51_WDT_RR(n) REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4)) -#define NRF51_WDT_POWER REG32(NRF51_WDT_BASE + 0xFFC) -/* Bitfields */ -#define NRF51_WDT_RUNSTATUS_RUNNING 1 -#define NRF51_WDT_REQSTATUS_BIT(n) (1<<(n)) -#define NRF51_WDT_RREN_BIT(n) (1<<(n)) -#define NRF51_WDT_CONFIG_SLEEP_PAUSE 0 -#define NRF51_WDT_CONFIG_SLEEP_RUN 1 -#define NRF51_WDT_CONFIG_HALT_PAUSE (0<<4) -#define NRF51_WDT_CONFIG_HALT_RUN BIT(4) - -#define NRF51_WDT_RELOAD_VAL 0x6E524635 - - -/* - * GPIO - */ -#define NRF51_GPIO_BASE 0x50000000 -#define NRF51_GPIO0_BASE (NRF51_GPIO_BASE + 0x500) -#define NRF51_GPIO0_OUT REG32(NRF51_GPIO0_BASE + 0x004) -#define NRF51_GPIO0_OUTSET REG32(NRF51_GPIO0_BASE + 0x008) -#define NRF51_GPIO0_OUTCLR REG32(NRF51_GPIO0_BASE + 0x00C) -#define NRF51_GPIO0_IN REG32(NRF51_GPIO0_BASE + 0x010) -#define NRF51_GPIO0_DIR REG32(NRF51_GPIO0_BASE + 0x014) /* 1 for output */ -#define NRF51_GPIO0_DIRSET REG32(NRF51_GPIO0_BASE + 0x018) -#define NRF51_GPIO0_DIRCLR REG32(NRF51_GPIO0_BASE + 0x01C) -#define NRF51_PIN_BASE (NRF51_GPIO_BASE + 0x700) -#define NRF51_PIN_CNF(n) REG32(NRF51_PIN_BASE + ((n) * 4)) -#define GPIO_0 NRF51_GPIO0_BASE - -#define NRF51_PIN_CNF_DIR_INPUT (0) -#define NRF51_PIN_CNF_DIR_OUTPUT (1) -#define NRF51_PIN_CNF_INPUT_CONNECT (0<<1) -#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1) -#define NRF51_PIN_CNF_PULL_DISABLED (0<<2) -#define NRF51_PIN_CNF_PULLDOWN BIT(2) -#define NRF51_PIN_CNF_PULLUP (3<<2) -/* - * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect - * for example, S0D1 = Standard drive 0, disconnect on 1 - */ -#define NRF51_PIN_CNF_DRIVE_S0S1 (0<<8) -#define NRF51_PIN_CNF_DRIVE_H0S1 BIT(8) -#define NRF51_PIN_CNF_DRIVE_S0H1 (2<<8) -#define NRF51_PIN_CNF_DRIVE_H0H1 (3<<8) -#define NRF51_PIN_CNF_DRIVE_D0S1 (4<<8) -#define NRF51_PIN_CNF_DRIVE_D0H1 (5<<8) -#define NRF51_PIN_CNF_DRIVE_S0D1 (6<<8) -#define NRF51_PIN_CNF_DRIVE_H0D1 (7<<8) - -#define NRF51_PIN_CNF_SENSE_DISABLED (0<<16) -#define NRF51_PIN_CNF_SENSE_HIGH (2<<16) -#define NRF51_PIN_CNF_SENSE_LOW (3<<16) - -#define DUMMY_GPIO_BANK GPIO_0 /* for UNIMPLEMENTED() macro */ - -#define NRF51_PPI_BASE 0x4001F000 -#define NRF51_PPI_CHEN REG32(NRF51_PPI_BASE + 0x500) -#define NRF51_PPI_CHENSET REG32(NRF51_PPI_BASE + 0x504) -#define NRF51_PPI_CHENCLR REG32(NRF51_PPI_BASE + 0x508) -#define NRF51_PPI_EEP(channel) REG32(NRF51_PPI_BASE + 0x510 + channel*8) -#define NRF51_PPI_TEP(channel) REG32(NRF51_PPI_BASE + 0x514 + channel*8) -#define NRF51_PPI_CHG(group) REG32(NRF51_PPI_BASE + 0x800 + group*4) - -#define NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS 16 -#define NRF51_PPI_NUM_GROUPS 4 - -#define NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN 20 -#define NRF51_PPI_CH_TIMER0_CC0__RADIO_RXEN 21 -#define NRF51_PPI_CH_TIMER0_CC1__RADIO_DISABLE 22 -#define NRF51_PPI_CH_RADIO_BCMATCH__AAR_START 23 -#define NRF51_PPI_CH_RADIO_READY__CCM_KSGEN 24 -#define NRF51_PPI_CH_RADIO_ADDR__CCM_CRYPT 25 -#define NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1 26 -#define NRF51_PPI_CH_RADIO_END_TIMER0CC2 27 -#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_TXEN 28 -#define NRF51_PPI_CH_RTC0_COMPARE0__RADIO_RXEN 29 -#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_CLEAR 30 -#define NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START 31 - -#define NRF51_PPI_CH_FIRST NRF51_PPI_CH_TIMER0_CC0__RADIO_TXEN -#define NRF51_PPI_CH_LAST NRF51_PPI_CH_RTC0_COMPARE0__TIMER0_START - - -/* These will be defined in their respective functions if/when they are used. */ -#define NRF51_SPI0_BASE 0x40003000 -#define NRF51_SPI0_PSELSCK REG32(NRF51_SPI0_BASE + 0x508) -#define NRF51_SPI0_PSELMOSI REG32(NRF51_SPI0_BASE + 0x50C) -#define NRF51_SPI0_PSELMISO REG32(NRF51_SPI0_BASE + 0x510) -#define NRF51_SPI1_BASE 0x40004000 -#define NRF51_SPI1_PSELSCK REG32(NRF51_SPI1_BASE + 0x508) -#define NRF51_SPI1_PSELMOSI REG32(NRF51_SPI1_BASE + 0x50C) -#define NRF51_SPI1_PSELMISO REG32(NRF51_SPI1_BASE + 0x510) -#define NRF51_SPIS1_BASE 0x40004000 -#define NRF51_SPIS1_PSELSCK REG32(NRF51_SPIS1_BASE + 0x508) -#define NRF51_SPIS1_PSELMISO REG32(NRF51_SPIS1_BASE + 0x50C) -#define NRF51_SPIS1_PSELMOSI REG32(NRF51_SPIS1_BASE + 0x510) -#define NRF51_SPIS1_PSELCSN REG32(NRF51_SPIS1_BASE + 0x514) -#define NRF51_QDEC_BASE 0x40012000 -#define NRF51_QDEC_PSELLED REG32(NRF51_QDEC_BASE + 0x51C) -#define NRF51_QDEC_PSELA REG32(NRF51_QDEC_BASE + 0x520) -#define NRF51_QDEC_PSELB REG32(NRF51_QDEC_BASE + 0x524) -#define NRF51_LPCOMP_BASE 0x40013000 -#define NRF51_LPCOMP_PSEL REG32(NRF51_LPCOMP_BASE + 0x504) - -#endif /* __CROS_EC_REGISTERS_H */ - diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c deleted file mode 100644 index dc7bff2059..0000000000 --- a/chip/nrf51/system.c +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : hardware specific implementation */ - -#include "common.h" -#include "console.h" -#include "ec_commands.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "cpu.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -const char *system_get_chip_vendor(void) -{ - return "nrf"; -} - -const char *system_get_chip_name(void) -{ - return "nrf51822"; -} - -const char *system_get_chip_revision(void) -{ - return ""; -} - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ - /* Flush console before hibernating */ - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* chip specific standby mode */ - CPRINTS("TODO: implement %s()", __func__); -} - - -static void check_reset_cause(void) -{ - uint32_t flags = 0; - uint32_t raw_cause = NRF51_POWER_RESETREAS; - - if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN) - flags |= EC_RESET_FLAG_RESET_PIN; - - if (raw_cause & NRF51_POWER_RESETREAS_DOG) - flags |= EC_RESET_FLAG_WATCHDOG; - - /* Note that the programmer uses a soft reset in debug mode. */ - if (raw_cause & NRF51_POWER_RESETREAS_SREQ) - flags |= EC_RESET_FLAG_SOFT; - - if (raw_cause & (NRF51_POWER_RESETREAS_OFF | - NRF51_POWER_RESETREAS_LPCOMP)) - flags |= EC_RESET_FLAG_WAKE_PIN; - - if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP | - NRF51_POWER_RESETREAS_DIF)) - flags |= EC_RESET_FLAG_OTHER; - - system_set_reset_flags(flags); - - /* clear it by writing 1's */ - NRF51_POWER_RESETREAS = raw_cause; -} - -static void system_watchdog_reset(void) -{ - if (NRF51_WDT_TIMEOUT != 0) { - /* Hard reset the WDT */ - NRF51_WDT_POWER = 0; - NRF51_WDT_POWER = 1; - } - - /* NRF51_WDT_CONFIG_HALT_RUN breaks this */ - NRF51_WDT_CONFIG = NRF51_WDT_CONFIG_SLEEP_RUN; - - NRF51_WDT_RREN = NRF51_WDT_RREN_BIT(0); - NRF51_WDT_CRV = 3; /* @32KHz */ - NRF51_WDT_START = 1; -} - -void system_reset(int flags) -{ - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - if (flags & SYSTEM_RESET_HARD) - /* Ask the watchdog to trigger a hard reboot */ - system_watchdog_reset(); - else { - /* Use SYSRESETREQ to trigger a soft reboot */ - CPU_NVIC_APINT = 0x05fa0004; - } - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - CPRINTS("TODO: implement %s()", __func__); - return EC_ERROR_UNIMPLEMENTED; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - CPRINTS("TODO: implement %s()", __func__); - return EC_ERROR_UNIMPLEMENTED; -} - -void system_pre_init(void) -{ - check_reset_cause(); -} diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c deleted file mode 100644 index 1f546a2b79..0000000000 --- a/chip/nrf51/uart.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USART driver for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "common.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - - -static int ever_sent; /* if we ever sent byte to TXD? */ -static int init_done; /* Initialization done? */ -static int should_stop; /* Last TX control action */ - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - disable_sleep(SLEEP_MASK_UART); - should_stop = 0; - NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT); - task_trigger_irq(NRF51_PERID_USART); -} - -void uart_tx_stop(void) -{ - NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT); - should_stop = 1; - enable_sleep(SLEEP_MASK_UART); -} - -int uart_tx_ready(void) -{ - /* - * nRF51 design is NOT tx-empty style. Instead, it is if a byte is - * ever transmitted from TxD. This means NRF51_UART_TXDRDY is always - * 0 after reset. So, we use 'ever_sent' to send the first byte. - */ - return NRF51_UART_TXDRDY || (!ever_sent); -} - -int uart_rx_available(void) -{ - return NRF51_UART_RXDRDY; -} - -void uart_tx_flush(void) -{ - while (!uart_tx_ready()) - ; -} - -void uart_write_char(char c) -{ - ever_sent = 1; - NRF51_UART_TXDRDY = 0; - NRF51_UART_TXD = c; - NRF51_UART_STARTTX = 1; -} - -int uart_read_char(void) -{ - NRF51_UART_RXDRDY = 0; - return NRF51_UART_RXD; -} - -/* Interrupt handler for console USART */ -void uart_interrupt(void) -{ -#ifndef CONFIG_UART_RX_DMA - /* - * Read input FIFO until empty. DMA-based receive does this from a - * hook in the UART buffering module. - */ - uart_process_input(); -#endif - - /* Fill output FIFO */ - uart_process_output(); - -#ifndef CONFIG_UART_TX_DMA - if (!should_stop) - NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT); -#endif /* CONFIG_UART_TX_DMA */ - -} -DECLARE_IRQ(NRF51_PERID_USART, uart_interrupt, 2); - - -void uart_init(void) -{ - NRF51_UART_PSELTXD = NRF51_UART_TX_PIN; /* GPIO Port for Tx */ - NRF51_UART_PSELRXD = NRF51_UART_RX_PIN; /* GPIO Port for Rx */ - NRF51_UART_CONFIG = 0; /* disable HW flow control, no parity bit */ - NRF51_UART_BAUDRATE = 0x01d7e000; /* 115200 */ - NRF51_UART_ENABLE = 0x4; /* Enable UART */ - - task_enable_irq(NRF51_PERID_USART); - - NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT); - NRF51_UART_STARTRX = 1; - - init_done = 1; -} diff --git a/chip/nrf51/watchdog.c b/chip/nrf51/watchdog.c deleted file mode 100644 index da947df48e..0000000000 --- a/chip/nrf51/watchdog.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "console.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - - -int watchdog_init(void) -{ - CPRINTS("TODO: implement %s()", __func__); - return EC_ERROR_UNIMPLEMENTED; -} diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c deleted file mode 100644 index d900cbc514..0000000000 --- a/chip/stm32/adc-stm32f0.c +++ /dev/null @@ -1,347 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "adc_chip.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -struct mutex adc_lock; - -struct adc_profile_t { - /* Register values. */ - uint32_t cfgr1_reg; - uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ - uint32_t ier_reg; - /* DMA config. */ - const struct dma_option *dma_option; - /* Size of DMA buffer, in units of ADC_CH_COUNT. */ - int dma_buffer_size; -}; - -#ifdef CONFIG_ADC_PROFILE_SINGLE -static const struct dma_option dma_single = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, - STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT, -}; - -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_13_5_CY -#endif - -static const struct adc_profile_t profile = { - /* Sample all channels once using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - .ier_reg = 0, - .dma_option = &dma_single, - .dma_buffer_size = 1, -}; -#endif - -#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS - -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY -#endif - -static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, - STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, -}; - -static const struct adc_profile_t profile = { - /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | - STM32_ADC_CFGR1_DMACFG, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - /* Fire interrupt at end of sequence. */ - .ier_reg = STM32_ADC_IER_EOSEQIE, - .dma_option = &dma_continuous, - /* Double-buffer our samples. */ - .dma_buffer_size = 2, -}; -#endif - -static void adc_init(const struct adc_t *adc) -{ - /* - * If clock is already enabled, and ADC module is enabled - * then this is a warm reboot and ADC is already initialized. - */ - if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) - return; - - /* Enable ADC clock */ - clock_enable_module(MODULE_ADC, 1); - /* check HSI14 in RCC ? ON by default */ - - /* ADC calibration (done with ADEN = 0) */ - STM32_ADC_CR = STM32_ADC_CR_ADCAL; /* set ADCAL = 1, ADC off */ - /* wait for the end of calibration */ - while (STM32_ADC_CR & STM32_ADC_CR_ADCAL) - ; - - /* Single conversion, right aligned, 12-bit */ - STM32_ADC_CFGR1 = profile.cfgr1_reg; - /* clock is ADCCLK (ADEN must be off when writing this reg) */ - STM32_ADC_CFGR2 = profile.cfgr2_reg; - - /* - * ADC enable (note: takes 4 ADC clocks between end of calibration - * and setting ADEN). - */ - STM32_ADC_CR = STM32_ADC_CR_ADEN; - while (!(STM32_ADC_ISR & STM32_ADC_ISR_ADRDY)) - STM32_ADC_CR = STM32_ADC_CR_ADEN; -} - -static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate) -{ - /* Sampling time */ - if (sample_rate == STM32_ADC_SMPR_DEFAULT || - sample_rate >= STM32_ADC_SMPR_COUNT) - STM32_ADC_SMPR = profile.smpr_reg; - else - STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate); - - /* Select channel to convert */ - STM32_ADC_CHSELR = BIT(ain_id); - - /* Disable DMA */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN; -} - -#ifdef CONFIG_ADC_WATCHDOG - -static int watchdog_ain_id; -static int watchdog_delay_ms; - -static void adc_continuous_read(int ain_id) -{ - adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); - - /* CONT=1 -> continuous mode on */ - STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT; - - /* Start continuous conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ -} - -static void adc_continuous_stop(void) -{ - /* Stop on-going conversion */ - STM32_ADC_CR |= BIT(4); /* ADSTP */ - - /* Wait for conversion to stop */ - while (STM32_ADC_CR & BIT(4)) - ; - - /* CONT=0 -> continuous mode off */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_CONT; -} - -static void adc_interval_read(int ain_id, int interval_ms) -{ - adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); - - /* EXTEN=01 -> hardware trigger detection on rising edge */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) - | STM32_ADC_CFGR1_EXTEN_RISE; - - /* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) | - STM32_ADC_CFGR1_TRG3; - - __hw_timer_enable_clock(TIM_ADC, 1); - - /* Upcounter, counter disabled, update event only on underflow */ - STM32_TIM_CR1(TIM_ADC) = 0x0004; - - /* TRGO on update event */ - STM32_TIM_CR2(TIM_ADC) = 0x0020; - STM32_TIM_SMCR(TIM_ADC) = 0x0000; - - /* Auto-reload value */ - STM32_TIM_ARR(TIM_ADC) = interval_ms & 0xffff; - - /* Set prescaler to tick per millisecond */ - STM32_TIM_PSC(TIM_ADC) = (clock_get_freq() / MSEC) - 1; - - /* Start counting */ - STM32_TIM_CR1(TIM_ADC) |= 1; - - /* Start ADC conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ -} - -static void adc_interval_stop(void) -{ - /* EXTEN=00 -> hardware trigger detection disabled */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK; - - /* Set ADSTP to clear ADSTART */ - STM32_ADC_CR |= BIT(4); /* ADSTP */ - - /* Wait for conversion to stop */ - while (STM32_ADC_CR & BIT(4)) - ; - - /* Stop the timer */ - STM32_TIM_CR1(TIM_ADC) &= ~0x1; -} - -static int adc_watchdog_enabled(void) -{ - return STM32_ADC_CFGR1 & STM32_ADC_CFGR1_AWDEN; -} - -static int adc_enable_watchdog_no_lock(void) -{ - /* Select channel */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_AWDCH_MASK) | - (watchdog_ain_id << 26); - adc_configure(watchdog_ain_id, STM32_ADC_SMPR_DEFAULT); - - /* Clear AWD interrupt flag */ - STM32_ADC_ISR = 0x80; - /* Set Watchdog enable bit on a single channel */ - STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_AWDEN | STM32_ADC_CFGR1_AWDSGL; - /* Enable interrupt */ - STM32_ADC_IER |= STM32_ADC_IER_AWDIE; - - if (watchdog_delay_ms) - adc_interval_read(watchdog_ain_id, watchdog_delay_ms); - else - adc_continuous_read(watchdog_ain_id); - - return EC_SUCCESS; -} - -int adc_enable_watchdog(int ain_id, int high, int low) -{ - int ret; - - mutex_lock(&adc_lock); - - watchdog_ain_id = ain_id; - - /* Set thresholds */ - STM32_ADC_TR = ((high & 0xfff) << 16) | (low & 0xfff); - - ret = adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -static int adc_disable_watchdog_no_lock(void) -{ - if (watchdog_delay_ms) - adc_interval_stop(); - else - adc_continuous_stop(); - - /* Clear Watchdog enable bit */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_AWDEN; - - return EC_SUCCESS; -} - -int adc_disable_watchdog(void) -{ - int ret; - - mutex_lock(&adc_lock); - ret = adc_disable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return ret; -} - -int adc_set_watchdog_delay(int delay_ms) -{ - int resume_watchdog = 0; - - mutex_lock(&adc_lock); - if (adc_watchdog_enabled()) { - resume_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - watchdog_delay_ms = delay_ms; - - if (resume_watchdog) - adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return EC_SUCCESS; -} - -#else /* CONFIG_ADC_WATCHDOG */ - -static int adc_watchdog_enabled(void) { return 0; } -static int adc_enable_watchdog_no_lock(void) { return 0; } -static int adc_disable_watchdog_no_lock(void) { return 0; } - -#endif /* CONFIG_ADC_WATCHDOG */ - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - int restore_watchdog = 0; - - mutex_lock(&adc_lock); - - adc_init(adc); - - if (adc_watchdog_enabled()) { - restore_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - adc_configure(adc->channel, adc->sample_rate); - - /* Clear flags */ - STM32_ADC_ISR = 0xe; - - /* Start conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ - - /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & BIT(2))) - ; - /* read converted value */ - value = STM32_ADC_DR; - - if (restore_watchdog) - adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return value * adc->factor_mul / adc->factor_div + adc->shift; -} - -void adc_disable(void) -{ - STM32_ADC_CR |= STM32_ADC_CR_ADDIS; - /* - * Note that the ADC is not in OFF state immediately. - * Once the ADC is effectively put into OFF state, - * STM32_ADC_CR_ADDIS bit will be cleared by hardware. - */ -} diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c deleted file mode 100644 index 180dc05c3b..0000000000 --- a/chip/stm32/adc-stm32f3.c +++ /dev/null @@ -1,260 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "adc_chip.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ - -#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \ - ((v) << 12) | ((v) << 15) | ((v) << 18) | \ - ((v) << 21)) -#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) - -/* Default ADC sample time = 13.5 cycles */ -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME 2 -#endif - -struct mutex adc_lock; - -static int watchdog_ain_id; - -static inline void adc_set_channel(int sample_id, int channel) -{ - uint32_t mask, val; - volatile uint32_t *sqr_reg; - - if (sample_id < 6) { - mask = 0x1f << (sample_id * 5); - val = channel << (sample_id * 5); - sqr_reg = &STM32_ADC_SQR3; - } else if (sample_id < 12) { - mask = 0x1f << ((sample_id - 6) * 5); - val = channel << ((sample_id - 6) * 5); - sqr_reg = &STM32_ADC_SQR2; - } else { - mask = 0x1f << ((sample_id - 12) * 5); - val = channel << ((sample_id - 12) * 5); - sqr_reg = &STM32_ADC_SQR1; - } - - *sqr_reg = (*sqr_reg & ~mask) | val; -} - -static void adc_configure(int ain_id) -{ - /* Set ADC channel */ - adc_set_channel(0, ain_id); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* Disable scan mode */ - STM32_ADC_CR1 &= ~BIT(8); -} - -static void __attribute__((unused)) adc_configure_all(void) -{ - int i; - - /* Set ADC channels */ - STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; - for (i = 0; i < ADC_CH_COUNT; ++i) - adc_set_channel(i, adc_channels[i].channel); - - /* Enable DMA */ - STM32_ADC_CR2 |= BIT(8); - - /* Enable scan mode */ - STM32_ADC_CR1 |= BIT(8); -} - -static inline int adc_powered(void) -{ - return STM32_ADC_CR2 & BIT(0); -} - -static inline int adc_conversion_ended(void) -{ - return STM32_ADC_SR & BIT(1); -} - -static int adc_watchdog_enabled(void) -{ - return STM32_ADC_CR1 & BIT(23); -} - -static int adc_enable_watchdog_no_lock(void) -{ - /* Fail if watchdog already enabled */ - if (adc_watchdog_enabled()) - return EC_ERROR_UNKNOWN; - - /* Set channel */ - STM32_ADC_SQR3 = watchdog_ain_id; - STM32_ADC_SQR1 = 0; - STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id; - - /* Clear interrupt bit */ - STM32_ADC_SR &= ~0x1; - - /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ - STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* CONT=1 */ - STM32_ADC_CR2 |= BIT(1); - - /* Start conversion */ - STM32_ADC_CR2 |= BIT(0); - - return EC_SUCCESS; -} - -int adc_enable_watchdog(int ain_id, int high, int low) -{ - int ret; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - - watchdog_ain_id = ain_id; - - /* Set thresholds */ - STM32_ADC_HTR = high & 0xfff; - STM32_ADC_LTR = low & 0xfff; - - ret = adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -static int adc_disable_watchdog_no_lock(void) -{ - /* Fail if watchdog not running */ - if (!adc_watchdog_enabled()) - return EC_ERROR_UNKNOWN; - - /* AWDEN=0, AWDIE=0 */ - STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); - - /* CONT=0 */ - STM32_ADC_CR2 &= ~BIT(1); - - return EC_SUCCESS; -} - -int adc_disable_watchdog(void) -{ - int ret; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - ret = adc_disable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - int restore_watchdog = 0; - timestamp_t deadline; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - - if (adc_watchdog_enabled()) { - restore_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - adc_configure(adc->channel); - - /* Clear EOC bit */ - STM32_ADC_SR &= ~BIT(1); - - /* Start conversion (Note: For now only confirmed on F4) */ -#if defined(CHIP_FAMILY_STM32F4) - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; -#else - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; -#endif - - /* Wait for EOC bit set */ - deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; - value = ADC_READ_ERROR; - do { - if (adc_conversion_ended()) { - value = STM32_ADC_DR & ADC_READ_MAX; - break; - } - } while (!timestamp_expired(deadline, NULL)); - - if (restore_watchdog) - adc_enable_watchdog_no_lock(); - - mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; -} - -static void adc_init(void) -{ - /* - * Enable ADC clock. - * APB2 clock is 16MHz. ADC clock prescaler is /2. - * So the ADC clock is 8MHz. - */ - clock_enable_module(MODULE_ADC, 1); - - /* - * ADC clock is divided with respect to AHB, so no delay needed - * here. If ADC clock is the same as AHB, a dummy read on ADC - * register is needed here. - */ - - if (!adc_powered()) { - /* Power on ADC module */ - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; - - /* Reset calibration */ - STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; - while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) - ; - - /* A/D Calibrate */ - STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; - while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) - ; - } - - /* Set right alignment */ - STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; - - /* Set sample time of all channels */ - STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); - STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME); -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c deleted file mode 120000 index 5e375b9dbf..0000000000 --- a/chip/stm32/adc-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -adc-stm32f3.c
\ No newline at end of file diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c deleted file mode 100644 index 199b64c81f..0000000000 --- a/chip/stm32/adc-stm32l.c +++ /dev/null @@ -1,171 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "adc_chip.h" -#include "common.h" -#include "console.h" -#include "clock.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ - -struct mutex adc_lock; - -static int restore_clock; - -static inline void adc_set_channel(int sample_id, int channel) -{ - uint32_t mask, val; - volatile uint32_t *sqr_reg; - int reg_id; - - reg_id = 5 - sample_id / 6; - - mask = 0x1f << ((sample_id % 6) * 5); - val = channel << ((sample_id % 6) * 5); - sqr_reg = &STM32_ADC_SQR(reg_id); - - *sqr_reg = (*sqr_reg & ~mask) | val; -} - -static void adc_configure(int ain_id) -{ - /* Set ADC channel */ - adc_set_channel(0, ain_id); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* Disable scan mode */ - STM32_ADC_CR1 &= ~BIT(8); -} - -static void adc_configure_all(void) -{ - int i; - - /* Set ADC channels */ - STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; - for (i = 0; i < ADC_CH_COUNT; ++i) - adc_set_channel(i, adc_channels[i].channel); - - /* Enable DMA */ - STM32_ADC_CR2 |= BIT(8); - - /* Enable scan mode */ - STM32_ADC_CR1 |= BIT(8); -} - -static inline int adc_powered(void) -{ - return STM32_ADC_SR & BIT(6); /* ADONS */ -} - -static void adc_enable_clock(void) -{ - STM32_RCC_APB2ENR |= BIT(9); - /* ADCCLK = HSI / 2 = 8MHz*/ - STM32_ADC_CCR |= BIT(16); -} - -static void adc_init(void) -{ - /* - * For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled - * for ADC. - * - * Note that we are not powering on ADC on EC initialization because - * STM32L ADC module requires HSI clock. Instead, ADC module is powered - * on/off in adc_prepare()/adc_release(). - */ - - /* Enable ADC clock. */ - adc_enable_clock(); - - if (!adc_powered()) - /* Power on ADC module */ - STM32_ADC_CR2 |= BIT(0); /* ADON */ - - /* Set right alignment */ - STM32_ADC_CR2 &= ~BIT(11); - - /* - * Set sample time of all channels to 16 cycles. - * Conversion takes (12+16)/8M = 3.34 us. - */ - STM32_ADC_SMPR1 = 0x24924892; - STM32_ADC_SMPR2 = 0x24924892; - STM32_ADC_SMPR3 = 0x24924892; -} - -static void adc_prepare(void) -{ - if (!adc_powered()) { - clock_enable_module(MODULE_ADC, 1); - adc_init(); - restore_clock = 1; - } -} - -static void adc_release(void) -{ - if (restore_clock) { - clock_enable_module(MODULE_ADC, 0); - restore_clock = 0; - } - - /* - * Power down the ADC. The ADC consumes a non-trivial amount of power, - * so it's wasteful to leave it on. - */ - if (adc_powered()) - STM32_ADC_CR2 = 0; -} - -static inline int adc_conversion_ended(void) -{ - return STM32_ADC_SR & BIT(1); -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - timestamp_t deadline; - - mutex_lock(&adc_lock); - - adc_prepare(); - - adc_configure(adc->channel); - - /* Clear EOC bit */ - STM32_ADC_SR &= ~BIT(1); - - /* Start conversion */ - STM32_ADC_CR2 |= BIT(30); /* SWSTART */ - - /* Wait for EOC bit set */ - deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; - value = ADC_READ_ERROR; - do { - if (adc_conversion_ended()) { - value = STM32_ADC_DR & ADC_READ_MAX; - break; - } - } while (!timestamp_expired(deadline, NULL)); - - adc_release(); - - mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; -} diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h deleted file mode 100644 index 413653e4d7..0000000000 --- a/chip/stm32/adc_chip.h +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* STM32-specific ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -#include "stdint.h" - -enum stm32_adc_smpr { - STM32_ADC_SMPR_DEFAULT = 0, - STM32_ADC_SMPR_1_5_CY, - STM32_ADC_SMPR_7_5_CY, - STM32_ADC_SMPR_13_5_CY, - STM32_ADC_SMPR_28_5_CY, - STM32_ADC_SMPR_41_5_CY, - STM32_ADC_SMPR_55_5_CY, - STM32_ADC_SMPR_71_5_CY, - STM32_ADC_SMPR_239_5_CY, - STM32_ADC_SMPR_COUNT, -}; - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - int channel; -#ifdef CHIP_FAMILY_STM32F0 - enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ -#endif -}; - -/* - * Boards must provide this list of ADC channel definitions. This must match - * the enum adc_channel list provided by the board. Also, for STM32F0, this - * must be ordered by AIN ID. - */ -extern const struct adc_t adc_channels[]; - -/* Disable ADC module when we don't need it anymore. */ -void adc_disable(void); - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 4095 - -/* Just plain id mapping for code readability */ -#define STM32_AIN(x) (x) - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk deleted file mode 100644 index 807cfd7ebd..0000000000 --- a/chip/stm32/build.mk +++ /dev/null @@ -1,91 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# STM32 chip specific files build -# - -ifeq ($(CHIP_FAMILY),stm32f0) -# STM32F0xx sub-family has a Cortex-M0 ARM core -CORE:=cortex-m0 -# Force ARMv6-M ISA used by the Cortex-M0 -# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M -# without "svc" instruction, but that was short-lived. ARMv6S-M was the option -# with "svc". GCC kept that naming scheme even though the distinction is long -# gone. -CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 -else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4)) -# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 -else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7)) -# STM32FH7xx family has a Cortex-M7 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set (identical to M7) -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 -else -# other STM32 SoCs have a Cortex-M3 ARM core -CORE:=cortex-m -# Force Cortex-M3 subset of instructions -CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3 -endif - -# Select between 16-bit and 32-bit timer for clock source -TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,) -DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4)$(CHIP_FAMILY_STM32H7),-stm32f4,) -SPI_TYPE=$(if $(CHIP_FAMILY_STM32H7),-stm32h7,) - -chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o -chip-$(CONFIG_COMMON_RUNTIME)+=system.o -chip-y+=clock-$(CHIP_FAMILY).o -ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4)) -chip-y+=clock-f.o -endif -chip-$(CONFIG_SPI)+=spi.o -chip-$(CONFIG_SPI_MASTER)+=spi_master$(SPI_TYPE).o -chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o -chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o -chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o -chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o -chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o -chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o -chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o -chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -chip-$(HAS_TASK_CONSOLE)+=uart.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif -chip-$(HAS_TASK_POWERLED)+=power_led.o -chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o -ifdef CONFIG_FLASH_PHYSICAL -chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o -chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o -chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o -endif -chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o -chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o -chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o -chip-$(CONFIG_OTP)+=otp-$(CHIP_FAMILY).o -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_RNG)+=trng.o - -ifeq ($(CHIP_FAMILY),stm32f4) -chip-$(CONFIG_USB)+=usb_dwc.o usb_endpoints.o -chip-$(CONFIG_USB_CONSOLE)+=usb_dwc_console.o -chip-$(CONFIG_USB_POWER)+=usb_power.o -chip-$(CONFIG_STREAM_USB)+=usb_dwc_stream.o -else -chip-$(CONFIG_STREAM_USB)+=usb-stream.o -chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o -chip-$(CONFIG_USB_CONSOLE)+=usb_console.o -chip-$(CONFIG_USB_GPIO)+=usb_gpio.o -chip-$(CONFIG_USB_HID)+=usb_hid.o -chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o -chip-$(CONFIG_USB_HID_TOUCHPAD)+=usb_hid_touchpad.o -chip-$(CONFIG_USB_ISOCHRONOUS)+=usb_isochronous.o -chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o -chip-$(CONFIG_USB_SPI)+=usb_spi.o -endif diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c deleted file mode 100644 index b32b9f3ac0..0000000000 --- a/chip/stm32/charger_detect.c +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Detect what adapter is connected */ - -#include "charge_manager.h" -#include "hooks.h" -#include "registers.h" -#include "timer.h" - -static void enable_usb(void) -{ - /* Enable USB device clock. */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; -} -DECLARE_HOOK(HOOK_INIT, enable_usb, HOOK_PRIO_DEFAULT); - -static void disable_usb(void) -{ - /* Disable USB device clock. */ - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; -} -DECLARE_HOOK(HOOK_SYSJUMP, disable_usb, HOOK_PRIO_DEFAULT); - -static uint16_t detect_type(uint16_t det_type) -{ - STM32_USB_BCDR &= 0; - usleep(1); - STM32_USB_BCDR |= (STM32_USB_BCDR_BCDEN | det_type); - usleep(1); - STM32_USB_BCDR &= ~(STM32_USB_BCDR_BCDEN | det_type); - return STM32_USB_BCDR; -} - - -int charger_detect_get_device_type(void) -{ - uint16_t pdet_result; - - if (!(detect_type(STM32_USB_BCDR_DCDEN) & STM32_USB_BCDR_DCDET)) - return CHARGE_SUPPLIER_PD; - - pdet_result = detect_type(STM32_USB_BCDR_PDEN); - /* TODO: add support for detecting proprietary chargers. */ - if (pdet_result & STM32_USB_BCDR_PDET) { - if (detect_type(STM32_USB_BCDR_SDEN) & STM32_USB_BCDR_SDET) - return CHARGE_SUPPLIER_BC12_DCP; - else - return CHARGE_SUPPLIER_BC12_CDP; - } else if (pdet_result & STM32_USB_BCDR_PS2DET) - return CHARGE_SUPPLIER_PROPRIETARY; - else - return CHARGE_SUPPLIER_BC12_SDP; -} diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c deleted file mode 100644 index 90ada3eeba..0000000000 --- a/chip/stm32/clock-f.c +++ /dev/null @@ -1,498 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "host_command.h" -#include "hwtimer.h" -#include "registers.h" -#include "rtc.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* Convert decimal to BCD */ -static uint8_t u8_to_bcd(uint8_t val) -{ - /* Fast division by 10 (when lacking HW div) */ - uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19; - uint32_t rem = val - quot * 10; - - return rem | (quot << 4); -} - -/* Convert between RTC regs in BCD and seconds */ -static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) -{ - uint32_t sec; - - /* convert the hours field */ - sec = (((rtc_tr & 0x300000) >> 20) * 10 + - ((rtc_tr & 0xf0000) >> 16)) * 3600; - /* convert the minutes field */ - sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60; - /* convert the seconds field */ - sec += ((rtc_tr & 0x70) >> 4) * 10 + (rtc_tr & 0xf); - return sec; -} - -static uint32_t sec_to_rtc_tr(uint32_t sec) -{ - uint32_t rtc_tr; - uint8_t hour; - uint8_t min; - - sec %= SECS_PER_DAY; - /* convert the hours field */ - hour = sec / 3600; - rtc_tr = u8_to_bcd(hour) << 16; - /* convert the minutes field */ - sec -= hour * 3600; - min = sec / 60; - rtc_tr |= u8_to_bcd(min) << 8; - /* convert the seconds field */ - sec -= min * 60; - rtc_tr |= u8_to_bcd(sec); - - return rtc_tr; -} - -/* Register setup before RTC alarm is allowed for update */ -static void pre_work_set_rtc_alarm(void) -{ - rtc_unlock_regs(); - - /* Make sure alarm is disabled */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF)) - ; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; -} - -/* Register setup after RTC alarm is updated */ -static void post_work_set_rtc_alarm(void) -{ - STM32_EXTI_PR = EXTI_RTC_ALR_EVENT; - - /* Enable alarm and alarm interrupt */ - STM32_EXTI_IMR |= EXTI_RTC_ALR_EVENT; - STM32_RTC_CR |= STM32_RTC_CR_ALRAE; - - rtc_lock_regs(); -} - -#ifdef CONFIG_HOSTCMD_RTC -static struct wake_time host_wake_time; - -int is_host_wake_alarm_expired(timestamp_t ts) -{ - return host_wake_time.ts.val && - timestamp_expired(host_wake_time.ts, &ts); -} - -void restore_host_wake_alarm(void) -{ - if (!host_wake_time.ts.val) - return; - - pre_work_set_rtc_alarm(); - - /* Set alarm time */ - STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar; - - post_work_set_rtc_alarm(); -} - -static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) -{ - struct calendar_date time; - uint32_t sec; - - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); - time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); - - sec = date_to_sec(time); - - return sec; -} - -static uint32_t sec_to_rtc_dr(uint32_t sec) -{ - struct calendar_date time; - uint32_t rtc_dr; - - time = sec_to_date(sec); - - rtc_dr = u8_to_bcd(time.year) << 16; - rtc_dr |= u8_to_bcd(time.month) << 8; - rtc_dr |= u8_to_bcd(time.day); - - return rtc_dr; -} -#endif - -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc) -{ - uint32_t sec = 0; -#ifdef CONFIG_HOSTCMD_RTC - sec = rtc_dr_to_sec(rtc->rtc_dr); -#endif - return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) + - rtc_tr_to_sec(rtc->rtc_tr); -} - -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc) -{ - rtc->rtc_dr = 0; -#ifdef CONFIG_HOSTCMD_RTC - rtc->rtc_dr = sec_to_rtc_dr(sec); -#endif - rtc->rtc_tr = sec_to_rtc_tr(sec); - rtc->rtc_ssr = 0; -} - -/* Return sub-10-sec time diff between two rtc readings - * - * Note: this function assumes rtc0 was sampled before rtc1. - * Additionally, this function only looks at the difference mod 10 - * seconds. - */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1) -{ - uint32_t rtc0_val, rtc1_val, diff; - - rtc0_val = (rtc0->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc0->rtc_ssr); - rtc1_val = (rtc1->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc1->rtc_ssr); - diff = rtc1_val; - if (rtc1_val < rtc0_val) { - /* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add - * 10 seconds to get the correct value - */ - diff += 10 * SECOND; - } - diff -= rtc0_val; - return diff; -} - -void rtc_read(struct rtc_time_reg *rtc) -{ - /* - * Read current time synchronously. Each register must be read - * twice with identical values because glitches may occur for reads - * close to the RTCCLK edge. - */ - do { - rtc->rtc_dr = STM32_RTC_DR; - - do { - rtc->rtc_tr = STM32_RTC_TR; - - do { - rtc->rtc_ssr = STM32_RTC_SSR; - } while (rtc->rtc_ssr != STM32_RTC_SSR); - - } while (rtc->rtc_tr != STM32_RTC_TR); - - } while (rtc->rtc_dr != STM32_RTC_DR); -} - -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm) -{ - uint32_t alarm_sec = 0; - uint32_t alarm_us = 0; - - if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) { - reset_rtc_alarm(rtc); - return; - } - - /* Alarm timeout must be within 1 day (86400 seconds) */ - ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY); - - pre_work_set_rtc_alarm(); - rtc_read(rtc); - - /* Calculate alarm time */ - alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s; - - if (delay_us) { - alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us; - alarm_sec = alarm_sec + alarm_us / SECOND; - alarm_us = alarm_us % SECOND; - } - - /* - * If seconds is greater than 1 day, subtract by 1 day to deal with - * 24-hour rollover. - */ - if (alarm_sec >= SECS_PER_DAY) - alarm_sec -= SECS_PER_DAY; - - /* - * Set alarm time in seconds and check for match on - * hours, minutes, and seconds. - */ - STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000; - - /* - * Set alarm time in subseconds and check for match on subseconds. - * If the caller doesn't specify subsecond delay (e.g. host command), - * just align the alarm time to second. - */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; - -#ifdef CONFIG_HOSTCMD_RTC - /* - * If alarm is set by the host, preserve the wake time timestamp - * and alarm registers. - */ - if (save_alarm) { - host_wake_time.ts.val = delay_s * SECOND + get_time().val; - host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR; - } -#endif - post_work_set_rtc_alarm(); -} - -uint32_t get_rtc_alarm(void) -{ - struct rtc_time_reg now; - uint32_t now_sec; - uint32_t alarm_sec; - - if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE)) - return 0; - - rtc_read(&now); - - now_sec = rtc_tr_to_sec(now.rtc_tr); - alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff); - - return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) + - (alarm_sec - now_sec); -} - -void reset_rtc_alarm(struct rtc_time_reg *rtc) -{ - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; - - /* Disable RTC alarm interrupt */ - STM32_EXTI_IMR &= ~EXTI_RTC_ALR_EVENT; - STM32_EXTI_PR = EXTI_RTC_ALR_EVENT; - - /* Clear the pending RTC alarm IRQ in NVIC */ - task_clear_pending_irq(STM32_IRQ_RTC_ALARM); - - /* Read current time */ - rtc_read(rtc); - - rtc_lock_regs(); -} - -void __rtc_alarm_irq(void) -{ - struct rtc_time_reg rtc; - reset_rtc_alarm(&rtc); - -#ifdef CONFIG_HOSTCMD_RTC - /* Wake up the host if there is a saved rtc wake alarm. */ - if (host_wake_time.ts.val) { - host_wake_time.ts.val = 0; - host_set_single_event(EC_HOST_EVENT_RTC); - } -#endif -} -DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); - -__attribute__((weak)) -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_init(void) -{ - /* - * The initial state : - * SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2 - * PLL unlocked, RTC enabled on LSE - */ - - /* - * put 1 Wait-State for flash access to ensure proper reads at 48Mhz - * and enable prefetch buffer. - */ - STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; - -#ifdef CHIP_FAMILY_STM32F4 - /* Enable data and instruction cache. */ - STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN; -#endif - - config_hispeed_clock(); - - rtc_init(); -} - -#ifdef CHIP_FAMILY_STM32F4 -void reset_flash_cache(void) -{ - /* Disable data and instruction cache. */ - STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN); - - /* Reset data and instruction cache */ - STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST; -} -DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT); -#endif - -/*****************************************************************************/ -/* Console commands */ - -void print_system_rtc(enum console_channel ch) -{ - uint32_t sec; - struct rtc_time_reg rtc; - - rtc_read(&rtc); - sec = rtc_to_sec(&rtc); - - cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); -} - -#ifdef CONFIG_CMD_RTC -static int command_system_rtc(int argc, char **argv) -{ - char *e; - uint32_t t; - - if (argc == 3 && !strcasecmp(argv[1], "set")) { - t = strtoi(argv[2], &e, 0); - if (*e) - return EC_ERROR_PARAM2; - rtc_set(t); - } else if (argc > 1) - return EC_ERROR_INVAL; - - print_system_rtc(CC_COMMAND); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set <seconds>]", - "Get/set real-time clock"); - -#ifdef CONFIG_CMD_RTC_ALARM -static int command_rtc_alarm_test(int argc, char **argv) -{ - int s = 1, us = 0; - struct rtc_time_reg rtc; - char *e; - - ccprintf("Setting RTC alarm\n"); - - if (argc > 1) { - s = strtoi(argv[1], &e, 10); - if (*e) - return EC_ERROR_PARAM1; - - } - if (argc > 2) { - us = strtoi(argv[2], &e, 10); - if (*e) - return EC_ERROR_PARAM2; - } - - set_rtc_alarm(s, us, &rtc, 0); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); -#endif /* CONFIG_CMD_RTC_ALARM */ -#endif /* CONFIG_CMD_RTC */ - -/*****************************************************************************/ -/* Host commands */ - -#ifdef CONFIG_HOSTCMD_RTC -static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) -{ - struct ec_response_rtc *r = args->response; - struct rtc_time_reg rtc; - - rtc_read(&rtc); - r->time = rtc_to_sec(&rtc); - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) -{ - const struct ec_params_rtc *p = args->params; - - rtc_set(p->time); - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) -{ - struct rtc_time_reg rtc; - const struct ec_params_rtc *p = args->params; - - /* Alarm timeout must be within 1 day (86400 seconds) */ - if (p->time >= SECS_PER_DAY) - return EC_RES_INVALID_PARAM; - - set_rtc_alarm(p->time, 0, &rtc, 1); - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) -{ - struct ec_response_rtc *r = args->response; - - r->time = get_rtc_alarm(); - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); - -#endif /* CONFIG_HOSTCMD_RTC */ diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h deleted file mode 100644 index 4662b043cb..0000000000 --- a/chip/stm32/clock-f.h +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#ifndef __CROS_EC_CLOCK_F_H -#define __CROS_EC_CLOCK_F_H - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Lock and unlock RTC write access */ -static inline void rtc_lock_regs(void) -{ - STM32_RTC_WPR = 0xff; -} -static inline void rtc_unlock_regs(void) -{ - STM32_RTC_WPR = 0xca; - STM32_RTC_WPR = 0x53; -} - -struct rtc_time_reg { - uint32_t rtc_ssr; /* subseconds */ - uint32_t rtc_tr; /* hours, minutes, seconds */ - uint32_t rtc_dr; /* years, months, dates, week days */ -}; - -/* Save the RTC alarm wake time */ -struct wake_time { - timestamp_t ts; - uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */ -}; - -/* Convert between RTC regs in BCD and seconds */ -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc); - -/* Convert between seconds and RTC regs */ -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc); - -/* Calculate microseconds from rtc sub-second register. */ -int32_t rtcss_to_us(uint32_t rtcss); - -/* Calculate rtc sub-second register value from microseconds. */ -uint32_t us_to_rtcss(int32_t us); - -/* Return sub-10-sec time diff between two rtc readings */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1); - -/* Read RTC values */ -void rtc_read(struct rtc_time_reg *rtc); - -/* Set RTC value */ -void rtc_set(uint32_t sec); - -/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */ -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm); - -/* Clear RTC wakeup */ -void reset_rtc_alarm(struct rtc_time_reg *rtc); - -/* - * Return the remaining seconds before the RTC alarm goes off. - * Sub-seconds are ignored. Returns 0 if alarm is not set. - */ -uint32_t get_rtc_alarm(void); - -/* RTC init */ -void rtc_init(void); - -/* Init clock blocks and functionality */ -void clock_init(void); - -/* Init high speed clock config */ -void config_hispeed_clock(void); - -/* Get timer clock frequency (for STM32 only) */ -int clock_get_timer_freq(void); - -/* - * Return 1 if host_wake_time is nonzero and the saved host_wake_time - * is expired at a given time, ts. - */ -int is_host_wake_alarm_expired(timestamp_t ts); - -/* Set RTC wakeup based on the value saved in host_wake_time */ -void restore_host_wake_alarm(void); - -#endif /* __CROS_EC_CLOCK_F_H */ diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c deleted file mode 100644 index 98afba9100..0000000000 --- a/chip/stm32/clock-stm32f0.c +++ /dev/null @@ -1,507 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* use 48Mhz USB-synchronized High-speed oscillator */ -#define HSI48_CLOCK 48000000 - -/* use PLL at 38.4MHz as system clock. */ -#define PLL_CLOCK 38400000 - -/* Low power idle statistics */ -#ifdef CONFIG_LOW_POWER_IDLE -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* - * minimum delay to enter stop mode - * - * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low - * power mode is 5 us + PLL locking time is 200us. - * - * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm - * in the past, it will never wake up and cause a watchdog. - * For STM32F3, we are using HSE, which requires additional time to start up. - * Therefore, the latency for STM32F3 is set longer. - * - * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is - * called and the host alarm is actually restored. In practice, the max latency - * is measured as ~600us. 1000us should be conservative enough to guarantee - * we won't miss the host alarm. - */ -#ifdef CHIP_VARIANT_STM32F373 -#define STOP_MODE_LATENCY 500 /* us */ -#elif defined(CHIP_VARIANT_STM32F05X) -#define STOP_MODE_LATENCY 300 /* us */ -#elif (CPU_CLOCK == PLL_CLOCK) -#define STOP_MODE_LATENCY 300 /* us */ -#else -#define STOP_MODE_LATENCY 50 /* us */ -#endif -#define SET_RTC_MATCH_DELAY 200 /* us */ - -#ifdef CONFIG_HOSTCMD_RTC -#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */ -#endif - -#endif /* CONFIG_LOW_POWER_IDLE */ - -/* - * RTC clock frequency (By default connected to LSI clock) - * - * The LSI on any given chip can be between 30 kHz to 60 kHz. - * Without calibration, LSI frequency may be off by as much as 50%. - * - * Set synchronous clock freq to (RTC clock source / 2) to maximize - * subsecond resolution. Set asynchronous clock to 1 Hz. - */ - -#define RTC_PREDIV_A 1 -#ifdef CONFIG_STM32_CLOCK_LSE -#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */ -/* GCD(RTC_FREQ, 1000000) */ -#define RTC_GCD 64 -#else /* LSI clock, 40kHz-ish */ -#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ -/* GCD(RTC_FREQ, 1000000) */ -#define RTC_GCD 20000 -#endif -#define RTC_PREDIV_S (RTC_FREQ - 1) - -/* - * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms - * for conversion calculations to fit in 32 bits. - */ -#define US_GCD (1000000 / RTC_GCD) -#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD) - -int32_t rtcss_to_us(uint32_t rtcss) -{ - return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD; -} - -uint32_t us_to_rtcss(int32_t us) -{ - return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD; -} - -void config_hispeed_clock(void) -{ -#ifdef CHIP_FAMILY_STM32F3 - /* Ensure that HSE is ON */ - if (!(STM32_RCC_CR & BIT(17))) { - /* Enable HSE */ - STM32_RCC_CR |= BIT(16); - /* Wait for HSE to be ready */ - while (!(STM32_RCC_CR & BIT(17))) - ; - } - - /* - * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK - * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz - * ADCCLK = PCLK / 6 = 4MHz - * USB uses SYSCLK = 48MHz - */ - STM32_RCC_CFGR = 0x0041a400; - - /* Enable the PLL */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until the PLL is ready */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL */ - STM32_RCC_CFGR |= 0x2; - - /* Wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; -/* F03X and F05X and F070 don't have HSI48 */ -#elif defined(CHIP_VARIANT_STM32F03X) || \ -defined(CHIP_VARIANT_STM32F05X) || \ -defined(CHIP_VARIANT_STM32F070) - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & 0xc) == 0x8) - return; - - /* Ensure that HSI is ON */ - if (!(STM32_RCC_CR & (1<<1))) { - /* Enable HSI */ - STM32_RCC_CR |= (1<<0); - /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR & (1<<1))) - ; - } - - /* - * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz - * therefore PCLK = FCLK = SYSCLK = 48MHz - */ - /* Switch the PLL source to HSI/2 */ - STM32_RCC_CFGR &= ~(0x00018000); - - /* - * Specify HSI/2 clock as input clock to PLL and set PLL (*12). - */ - STM32_RCC_CFGR |= 0x00280000; - - /* Enable the PLL. */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until PLL is ready. */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL. */ - STM32_RCC_CFGR |= 0x2; - - /* wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; -#else - /* Ensure that HSI48 is ON */ - if (!(STM32_RCC_CR2 & BIT(17))) { - /* Enable HSI */ - STM32_RCC_CR2 |= BIT(16); - /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR2 & BIT(17))) - ; - } - -#if (CPU_CLOCK == HSI48_CLOCK) - /* - * HSI48 = 48MHz, no prescaler, no MCO, no PLL - * therefore PCLK = FCLK = SYSCLK = 48MHz - * USB uses HSI48 = 48MHz - */ - -#ifdef CONFIG_USB - /* - * Configure and enable Clock Recovery System - * - * Since we are running from the internal RC HSI48 clock, the CSR - * is needed to guarantee an accurate 48MHz clock for USB. - * - * The default values configure the CRS to use the periodic USB SOF - * as the SYNC signal for calibrating the HSI48. - * - */ - - /* Enable Clock Recovery System */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS; - - /* Enable automatic trimming */ - STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN; - - /* Enable oscillator clock for the frequency error counter */ - STM32_CRS_CR |= STM32_CRS_CR_CEN; -#endif - - /* switch SYSCLK to HSI48 */ - STM32_RCC_CFGR = 0x00000003; - - /* wait until the HSI48 is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0xc) - ; - -#elif (CPU_CLOCK == PLL_CLOCK) - /* - * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK - * therefore PCLK = FCLK = SYSCLK = 38.4MHz - * USB uses HSI48 = 48MHz - */ - - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & 0xc) == 0x8) - return; - - /* - * Specify HSI48 clock as input clock to PLL and set PLL multiplier - * and divider. - */ - STM32_RCC_CFGR = 0x00098000; - STM32_RCC_CFGR2 = 0x4; - - /* Enable the PLL. */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until PLL is ready. */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL. */ - STM32_RCC_CFGR |= 0x2; - - /* wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; - -#else -#error "CPU_CLOCK must be either 48MHz or 38.4MHz" -#endif -#endif -} - -#ifdef CONFIG_HIBERNATE -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) -{ - struct rtc_time_reg rtc; - - if (seconds || microseconds) - set_rtc_alarm(seconds, microseconds, &rtc, 0); - - /* interrupts off now */ - asm volatile("cpsid i"); - -#ifdef CONFIG_HIBERNATE_WAKEUP_PINS - /* enable the wake up pins */ - STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS; -#endif - STM32_PWR_CR |= 0xe; - CPU_SCB_SYSCTRL |= 0x4; - /* go to Standby mode */ - asm("wfi"); - - /* we should never reach that point */ - while (1) - ; -} -#endif - -#ifdef CONFIG_HOSTCMD_RTC -static void restore_host_wake_alarm_deferred(void) -{ - restore_host_wake_alarm(); -} -DECLARE_DEFERRED(restore_host_wake_alarm_deferred); -#endif - -#ifdef CONFIG_LOW_POWER_IDLE - -void clock_refresh_console_in_use(void) -{ -} - -void __idle(void) -{ - timestamp_t t0; - uint32_t rtc_diff; - int next_delay, margin_us; - struct rtc_time_reg rtc0, rtc1; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - -#ifdef CONFIG_LOW_POWER_IDLE_LIMITED - if (idle_is_disabled()) - goto en_int; -#endif - - if (DEEP_SLEEP_ALLOWED && -#ifdef CONFIG_HOSTCMD_RTC - /* - * Don't go to deep sleep mode if we might miss the - * wake alarm that the host requested. Note that the - * host alarm always aligns to second. Considering the - * worst case, we have to ensure alarm won't go off - * within RESTORE_HOST_ALARM_LATENCY + 1 second after - * EC exits deep sleep mode. - */ - !is_host_wake_alarm_expired( - (timestamp_t)(next_delay + t0.val + SECOND + - RESTORE_HOST_ALARM_LATENCY)) && -#endif - (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { - /* Deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - uart_enable_wakeup(1); - - /* Set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, - &rtc0, 0); - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - uart_enable_wakeup(0); - - /* - * By default only HSI 8MHz is enabled here. Re-enable - * high-speed clock if in use. - */ - config_hispeed_clock(); - - /* Fast forward timer according to RTC counter */ - reset_rtc_alarm(&rtc1); - rtc_diff = get_rtc_diff(&rtc0, &rtc1); - t0.val = t0.val + rtc_diff; - force_time(t0); - -#ifdef CONFIG_HOSTCMD_RTC - hook_call_deferred( - &restore_host_wake_alarm_deferred_data, 0); -#endif - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += rtc_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - rtc_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Idle overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* Normal idle : only CPU clock stopped */ - asm("wfi"); - } -#ifdef CONFIG_LOW_POWER_IDLE_LIMITED -en_int: -#endif - asm volatile("cpsie i"); - } -} -#endif /* CONFIG_LOW_POWER_IDLE */ - -int clock_get_freq(void) -{ - return CPU_CLOCK; -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t dummy __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - dummy = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - if (module == MODULE_ADC) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN; - else - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN; - return; - } -} - -void rtc_init(void) -{ - rtc_unlock_regs(); - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) - ; - - /* Enable RTC alarm interrupt */ - STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; - STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; - task_enable_irq(STM32_IRQ_RTC_ALARM); - - rtc_lock_regs(); -} - -#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) -void rtc_set(uint32_t sec) -{ - struct rtc_time_reg rtc; - - sec_to_rtc(sec, &rtc); - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - STM32_RTC_TR = rtc.rtc_tr; - STM32_RTC_DR = rtc.rtc_dr; - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - - rtc_lock_regs(); -} -#endif - -#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME) -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_CMD_IDLE_STATS */ -#endif diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c deleted file mode 120000 index be91154e52..0000000000 --- a/chip/stm32/clock-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -clock-stm32f0.c
\ No newline at end of file diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c deleted file mode 100644 index 1d1eff91e0..0000000000 --- a/chip/stm32/clock-stm32f4.c +++ /dev/null @@ -1,294 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ -#define RTC_PREDIV_A 39 -#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */ -#else -/* LSI clock is 40kHz-ish */ -#define RTC_PREDIV_A 1 -#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ -#endif -#define RTC_PREDIV_S (RTC_FREQ - 1) -#define US_PER_RTC_TICK (1000000 / RTC_FREQ) - -int32_t rtcss_to_us(uint32_t rtcss) -{ - return ((RTC_PREDIV_S - rtcss) * US_PER_RTC_TICK); -} - -uint32_t us_to_rtcss(int32_t us) -{ - return (RTC_PREDIV_S - (us / US_PER_RTC_TICK)); -} - -static void wait_for_ready(volatile uint32_t *cr_reg, - uint32_t enable, uint32_t ready) -{ - /* Ensure that clock source is ON */ - if (!(*cr_reg & ready)) { - /* Enable clock */ - *cr_reg |= enable; - /* Wait for ready */ - while (!(*cr_reg & ready)) - ; - } -} - -void config_hispeed_clock(void) -{ -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - int srcclock = CONFIG_STM32_CLOCK_HSE_HZ; - int clk_check_mask = STM32_RCC_CR_HSERDY; - int clk_enable_mask = STM32_RCC_CR_HSEON; -#else - int srcclock = STM32F4_HSI_CLOCK; - int clk_check_mask = STM32_RCC_CR_HSIRDY; - int clk_enable_mask = STM32_RCC_CR_HSION; -#endif - int plldiv, pllinputclock; - int pllmult, vcoclock; - int systemclock; - int usbdiv; - int i2sdiv; - - int ahbpre, apb1pre, apb2pre; - int rtcdiv = 0; - - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) == - STM32_RCC_CFGR_SWS_PLL) - return; - - /* Ensure that HSE/HSI is ON */ - wait_for_ready(&(STM32_RCC_CR), clk_enable_mask, clk_check_mask); - - /* PLL input must be between 1-2MHz, near 2 */ - /* Valid values 2-63 */ - plldiv = (srcclock + STM32F4_PLL_REQ - 1) / STM32F4_PLL_REQ; - pllinputclock = srcclock / plldiv; - - /* PLL output clock: Must be 100-432MHz */ - pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock; - vcoclock = pllinputclock * pllmult; - - /* CPU/System clock */ - systemclock = vcoclock / STM32F4_PLLP_DIV; - /* USB clock = 48MHz exactly */ - usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ; - assert(vcoclock / usbdiv == STM32F4_USB_REQ); - - /* SYSTEM/I2S: same system clock */ - i2sdiv = (vcoclock + (systemclock / 2)) / systemclock; - - /* All IO clocks at STM32F4_IO_CLOCK - * For STM32F446: max 45 MHz - * For STM32F412: max 50 MHz - */ - /* AHB Prescalar */ - ahbpre = STM32F4_AHB_PRE; - /* NOTE: If apbXpre is not 0, timers are x2 clocked. RM0390 Fig. 13 - * One should define STM32F4_TIMER_CLOCK when apbXpre is not 0. - * STM32F4_TIMER_CLOCK is used for hwtimer in EC. */ - apb1pre = STM32F4_APB1_PRE; - apb2pre = STM32F4_APB2_PRE; - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - /* RTC clock = 1MHz */ - rtcdiv = (CONFIG_STM32_CLOCK_HSE_HZ + (STM32F4_RTC_REQ / 2)) - / STM32F4_RTC_REQ; -#endif - /* Switch SYSCLK to PLL, setup prescalars. - * EC codebase doesn't understand multiple clock domains - * so we enforce a clock config that keeps AHB = APB1 = APB2 - * allowing ec codebase assumptions about consistent clock - * rates to remain true. - * - * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz - * MCO outputs are selected here but are not changeable later. - * A CONFIG may be needed if other boards have different MCO - * requirements. - */ - STM32_RCC_CFGR = - (2 << 30) | /* MCO2 <- HSE */ - (0 << 27) | /* MCO2 div / 4 */ - (6 << 24) | /* MCO1 div / 4 */ - (3 << 21) | /* MCO1 <- PLL */ - CFGR_RTCPRE(rtcdiv) | - CFGR_PPRE2(apb2pre) | - CFGR_PPRE1(apb1pre) | - CFGR_HPRE(ahbpre) | - STM32_RCC_CFGR_SW_PLL; - - /* Set up PLL */ - STM32_RCC_PLLCFGR = - PLLCFGR_PLLM(plldiv) | - PLLCFGR_PLLN(pllmult) | - PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | -#if defined(CONFIG_STM32_CLOCK_HSE_HZ) - PLLCFGR_PLLSRC_HSE | -#else - PLLCFGR_PLLSRC_HSI | -#endif - PLLCFGR_PLLQ(usbdiv) | - PLLCFGR_PLLR(i2sdiv); - - wait_for_ready(&(STM32_RCC_CR), - STM32_RCC_CR_PLLON, STM32_RCC_CR_PLLRDY); - - /* Wait until the PLL is the clock source */ - if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) == - STM32_RCC_CFGR_SWS_PLL) - ; - - /* Setup RTC Clock input */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE); -#else - /* Ensure that LSI is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); - - STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); -#endif -} - -int clock_get_timer_freq(void) -{ - return STM32F4_TIMER_CLOCK; -} - -int clock_get_freq(void) -{ - return STM32F4_IO_CLOCK; -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t dummy __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - dummy = STM32_DMA_GET_ISR(0); - } else { /* APB */ - while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - if (module == MODULE_USB) { - if (enable) { - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN; - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN | - STM32_RCC_AHB1ENR_OTGHSULPIEN; - } else { - STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN; - STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN & - ~STM32_RCC_AHB1ENR_OTGHSULPIEN; - } - return; - } else if (module == MODULE_I2C) { - if (enable) { - /* Enable clocks to I2C modules if necessary */ - STM32_RCC_APB1ENR |= - STM32_RCC_I2C1EN | STM32_RCC_I2C2EN - | STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; - STM32_RCC_DCKCFGR2 = - (STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK) - | DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); - } else { - STM32_RCC_APB1ENR &= - ~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | - STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN); - } - return; - } else if (module == MODULE_ADC) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADC1EN; - else - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADC1EN; - return; - } -} - -void rtc_init(void) -{ - rtc_unlock_regs(); - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars: Needs two separate writes. */ - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S; - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) - | (RTC_PREDIV_A << 16); - - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) - ; - - /* Enable RTC alarm interrupt */ - STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; - STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; - task_enable_irq(STM32_IRQ_RTC_ALARM); - - rtc_lock_regs(); -} - -#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) -void rtc_set(uint32_t sec) -{ - struct rtc_time_reg rtc; - - sec_to_rtc(sec, &rtc); - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - STM32_RTC_TR = rtc.rtc_tr; - STM32_RTC_DR = rtc.rtc_dr; - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - - rtc_lock_regs(); -} -#endif diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c deleted file mode 100644 index f41a76b87a..0000000000 --- a/chip/stm32/clock-stm32h7.c +++ /dev/null @@ -1,452 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) - -/* High-speed oscillator default is 64 MHz */ -#define STM32_HSI_CLOCK 64000000 -/* Low-speed oscillator is 32-Khz */ -#define STM32_LSI_CLOCK 32000 - -/* - * LPTIM is a 16-bit counter clocked by LSI - * with /4 prescaler (2^2): period 125 us, full range ~8s - */ -#define LPTIM_PRESCALER_LOG2 2 -/* - * LPTIM_PRESCALER and LPTIM_PERIOD_US have to be signed, because we compare - * them to an int to decide whether to go to deep sleep. Simply using BIT() - * makes them unsigned, which causes a bug in deep sleep behavior. - * TODO(b/140538084): Explain exactly what the bug is. - */ -#define LPTIM_PRESCALER ((int)BIT(LPTIM_PRESCALER_LOG2)) -#define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER)) - -/* - * PLL1 configuration: - * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP - * = 64 / 4 * 50 / 2 - * = 400 Mhz - * System clock = 400 Mhz - * HPRE = /2 => AHB/Timer clock = 200 Mhz - */ -#if !defined(PLL1_DIVM) && !defined(PLL1_DIVN) && !defined(PLL1_DIVP) -#define PLL1_DIVM 4 -#define PLL1_DIVN 50 -#define PLL1_DIVP 2 -#endif -#define PLL1_FREQ (STM32_HSI_CLOCK / PLL1_DIVM * PLL1_DIVN / PLL1_DIVP) - -/* Flash latency settings for AHB/ACLK at 64 Mhz and Vcore in VOS1 range */ -#define FLASH_ACLK_64MHZ (STM32_FLASH_ACR_WRHIGHFREQ_85MHZ | \ - (0 << STM32_FLASH_ACR_LATENCY_SHIFT)) -/* Flash latency settings for AHB/ACLK at 200 Mhz and Vcore in VOS1 range */ -#define FLASH_ACLK_200MHZ (STM32_FLASH_ACR_WRHIGHFREQ_285MHZ | \ - (2 << STM32_FLASH_ACR_LATENCY_SHIFT)) - -enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ - OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ - OSC_PLL, /* PLL */ -}; - -static int freq = STM32_HSI_CLOCK; -static int current_osc = OSC_HSI; - -int clock_get_freq(void) -{ - return freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t dummy __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - dummy = STM32_GPIO_IDR(GPIO_A); - } else { /* APB */ - while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -static void clock_flash_latency(uint32_t target_acr) -{ - STM32_FLASH_ACR(0) = target_acr; - while (STM32_FLASH_ACR(0) != target_acr) - ; -} - -static void clock_enable_osc(enum clock_osc osc) -{ - uint32_t ready; - uint32_t on; - - switch (osc) { - case OSC_HSI: - ready = STM32_RCC_CR_HSIRDY; - on = STM32_RCC_CR_HSION; - break; - case OSC_PLL: - ready = STM32_RCC_CR_PLL1RDY; - on = STM32_RCC_CR_PLL1ON; - break; - default: - return; - } - - if (!(STM32_RCC_CR & ready)) { - STM32_RCC_CR |= on; - while (!(STM32_RCC_CR & ready)) - ; - } -} - -static void clock_switch_osc(enum clock_osc osc) -{ - uint32_t sw; - uint32_t sws; - - switch (osc) { - case OSC_HSI: - sw = STM32_RCC_CFGR_SW_HSI; - sws = STM32_RCC_CFGR_SWS_HSI; - break; - case OSC_PLL: - sw = STM32_RCC_CFGR_SW_PLL1; - sws = STM32_RCC_CFGR_SWS_PLL1; - break; - default: - return; - } - - STM32_RCC_CFGR = sw; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws) - ; -} - -static void switch_voltage_scale(uint32_t vos) -{ - STM32_PWR_D3CR &= ~STM32_PWR_D3CR_VOSMASK; - STM32_PWR_D3CR |= vos; - while (!(STM32_PWR_D3CR & STM32_PWR_D3CR_VOSRDY)) - ; -} - -static void clock_set_osc(enum clock_osc osc) -{ - if (osc == current_osc) - return; - - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - case OSC_HSI: - /* Switch to HSI */ - clock_switch_osc(osc); - freq = STM32_HSI_CLOCK; - /* Restore /1 HPRE (AHB prescaler) */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; - /* Use more optimized flash latency settings for 64-MHz ACLK */ - clock_flash_latency(FLASH_ACLK_64MHZ); - /* Turn off the PLL1 to save power */ - STM32_RCC_CR &= ~STM32_RCC_CR_PLL1ON; - switch_voltage_scale(STM32_PWR_D3CR_VOS3); - break; - - case OSC_PLL: - switch_voltage_scale(STM32_PWR_D3CR_VOS1); - /* Configure PLL1 using 64 Mhz HSI as input */ - STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI | - STM32_RCC_PLLCKSEL_DIVM1(PLL1_DIVM); - /* in integer mode, wide range VCO with 16Mhz input, use divP */ - STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE - | STM32_RCC_PLLCFG_PLL1RGE_8M_16M - | STM32_RCC_PLLCFG_DIVP1EN; - STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(PLL1_DIVP) - | STM32_RCC_PLLDIV_DIVN(PLL1_DIVN); - /* turn on PLL1 and wait that it's ready */ - clock_enable_osc(OSC_PLL); - /* Put /2 on HPRE (AHB prescaler) to keep at the 200Mhz max */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; - freq = PLL1_FREQ / 2; - /* Increase flash latency before transition the clock */ - clock_flash_latency(FLASH_ACLK_200MHZ); - /* Switch to PLL */ - clock_switch_osc(OSC_PLL); - break; - default: - break; - } - - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); -} - -void clock_enable_module(enum module_id module, int enable) -{ - /* Assume we have a single task using MODULE_FAST_CPU */ - if (module == MODULE_FAST_CPU) { - /* the PLL would be off in low power mode, disable it */ - if (enable) - disable_sleep(SLEEP_MASK_PLL); - else - enable_sleep(SLEEP_MASK_PLL); - clock_set_osc(enable ? OSC_PLL : OSC_HSI); - } -} - -#ifdef CONFIG_LOW_POWER_IDLE -/* Low power idle statistics */ -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */ -#define STOP_MODE_LATENCY 50 /* us */ - -static void low_power_init(void) -{ - /* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */ - STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R & - ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) - | STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; - - /* configure LPTIM1 as our 1-Khz low power timer in STOP mode */ - STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1; - STM32_LPTIM_CR(1) = 0; /* ensure it's disabled before configuring */ - STM32_LPTIM_CFGR(1) = LPTIM_PRESCALER_LOG2 << 9; /* Prescaler /4 */ - STM32_LPTIM_IER(1) = STM32_LPTIM_INT_CMPM; /* Compare int for wake-up */ - /* Start the 16-bit free-running counter */ - STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE; - STM32_LPTIM_ARR(1) = 0xFFFF; - STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE | STM32_LPTIM_CR_CNTSTRT; - task_enable_irq(STM32_IRQ_LPTIM1); - - /* Wake-up interrupts from EXTI for USART and LPTIM */ - STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */ - STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ - - /* optimize power vs latency in STOP mode */ - STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) - | STM32_PWR_CR_SVOS5 - | STM32_PWR_CR_FLPS; -} - -void clock_refresh_console_in_use(void) -{ -} - -void lptim_interrupt(void) -{ - STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM; -} -DECLARE_IRQ(STM32_IRQ_LPTIM1, lptim_interrupt, 2); - -static uint16_t lptim_read(void) -{ - uint16_t cnt; - - do { - cnt = STM32_LPTIM_CNT(1); - } while (cnt != STM32_LPTIM_CNT(1)); - - return cnt; -} - -static void set_lptim_event(int delay_us, uint16_t *lptim_cnt) -{ - uint16_t cnt = lptim_read(); - - STM32_LPTIM_CMP(1) = cnt + MIN(delay_us / LPTIM_PERIOD_US - 1, 0xffff); - /* clean-up previous event */ - STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM; - *lptim_cnt = cnt; -} - -void __idle(void) -{ - timestamp_t t0; - int next_delay; - int margin_us, t_diff; - uint16_t lptim0; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - - if (DEEP_SLEEP_ALLOWED && - next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) { - /* deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - uart_enable_wakeup(1); - - /* set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_lptim_event(next_delay - STOP_MODE_LATENCY, - &lptim0); - - /* ensure outstanding memory transactions complete */ - asm volatile("dsb"); - - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - /* fast forward timer according to low power counter */ - if (STM32_PWR_CPUCR & STM32_PWR_CPUCR_STOPF) { - uint16_t lptim_dt = lptim_read() - lptim0; - - t_diff = (int)lptim_dt * LPTIM_PERIOD_US; - t0.val = t0.val + t_diff; - force_time(t0); - /* clear STOPF flag */ - STM32_PWR_CPUCR |= STM32_PWR_CPUCR_CSSF; - } else { /* STOP entry was aborted, no fixup */ - t_diff = 0; - } - - uart_enable_wakeup(0); - - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += t_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - t_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* normal idle : only CPU clock stopped */ - asm("wfi"); - } - asm volatile("cpsie i"); - } -} - -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_CMD_IDLE_STATS */ -#endif /* CONFIG_LOW_POWER_IDLE */ - -void clock_init(void) -{ - /* - * STM32H743 Errata 2.2.15: - * 'Reading from AXI SRAM might lead to data read corruption' - * - * limit concurrent read access on AXI master to 1. - */ - STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE; - - /* - * Lock (SCUEN=0) power configuration with the LDO enabled. - * - * The STM32H7 Reference Manual says: - * The lower byte of this register is written once after POR and shall - * be written before changing VOS level or ck_sys clock frequency. - * - * The interesting side-effect of this that while the LDO is enabled by - * default at startup, if we enter STOP mode without locking it the MCU - * seems to freeze forever. - */ - STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN; - /* - * Ensure the SPI is always clocked at the same frequency - * by putting it on the fixed 64-Mhz HSI clock. - * per_ck is clocked directly by the HSI (as per the default settings). - */ - STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R & - ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | - STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) - | STM32_RCC_D2CCIP1R_SPI123SEL_PERCK - | STM32_RCC_D2CCIP1R_SPI45SEL_HSI; - - /* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */ - clock_flash_latency(FLASH_ACLK_64MHZ); - - /* Ensure that LSI is ON to clock LPTIM1 and IWDG */ - STM32_RCC_CSR |= STM32_RCC_CSR_LSION; - while (!(STM32_RCC_CSR & STM32_RCC_CSR_LSIRDY)) - ; - -#ifdef CONFIG_LOW_POWER_IDLE - low_power_init(); -#endif -} - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI); - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL); - else - return EC_ERROR_PARAM1; - } - ccprintf("Clock frequency is now %d Hz\n", freq); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | pll", "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c deleted file mode 100644 index 9c88e8be12..0000000000 --- a/chip/stm32/clock-stm32l.c +++ /dev/null @@ -1,381 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "registers.h" -#include "util.h" - -#ifdef CONFIG_STM32L_FAKE_HIBERNATE -#include "extpower.h" -#include "keyboard_config.h" -#include "lid_switch.h" -#include "power.h" -#include "power_button.h" -#include "system.h" -#include "task.h" - -static int fake_hibernate; -#endif - -/* High-speed oscillator is 16 MHz */ -#define HSI_CLOCK 16000000 -/* - * MSI is 2 MHz (default) 1 MHz, depending on ICSCR setting. We use 1 MHz - * because it's the lowest clock rate we can still run 115200 baud serial - * for the debug console. - */ -#define MSI_2MHZ_CLOCK BIT(21) -#define MSI_1MHZ_CLOCK BIT(20) - -enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed oscillator */ - OSC_MSI, /* Med-speed oscillator @ 1 MHz */ -}; - -static int freq; -static int current_osc; - -int clock_get_freq(void) -{ - return freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t dummy __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - dummy = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -/** - * Set which oscillator is used for the clock - * - * @param osc Oscillator to use - */ -static void clock_set_osc(enum clock_osc osc) -{ - uint32_t tmp_acr; - - if (osc == current_osc) - return; - - if (current_osc != OSC_INIT) - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - case OSC_HSI: - /* Ensure that HSI is ON */ - if (!(STM32_RCC_CR & STM32_RCC_CR_HSIRDY)) { - /* Enable HSI */ - STM32_RCC_CR |= STM32_RCC_CR_HSION; - /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR & STM32_RCC_CR_HSIRDY)) - ; - } - - /* Disable LPSDSR */ - STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; - - /* - * Set the recommended flash settings for 16MHz clock. - * - * The 3 bits must be programmed strictly sequentially. - * Also, follow the RM to check 64-bit access and latency bit - * after writing those bits to the FLASH_ACR register. - */ - tmp_acr = STM32_FLASH_ACR; - /* Enable 64-bit access */ - tmp_acr |= STM32_FLASH_ACR_ACC64; - STM32_FLASH_ACR = tmp_acr; - /* Check ACC64 bit == 1 */ - while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64)) - ; - - /* Enable Prefetch Buffer */ - tmp_acr |= STM32_FLASH_ACR_PRFTEN; - STM32_FLASH_ACR = tmp_acr; - - /* Flash 1 wait state */ - tmp_acr |= STM32_FLASH_ACR_LATENCY; - STM32_FLASH_ACR = tmp_acr; - /* Check LATENCY bit == 1 */ - while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY)) - ; - - /* Switch to HSI */ - STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI; - /* RM says to check SWS bits to make sure HSI is the sysclock */ - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_HSI) - ; - - /* Disable MSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_MSION; - - freq = HSI_CLOCK; - break; - - case OSC_MSI: - /* Switch to MSI @ 1MHz */ - STM32_RCC_ICSCR = - (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; - /* Ensure that MSI is ON */ - if (!(STM32_RCC_CR & STM32_RCC_CR_MSIRDY)) { - /* Enable MSI */ - STM32_RCC_CR |= STM32_RCC_CR_MSION; - /* Wait for MSI to be ready */ - while (!(STM32_RCC_CR & STM32_RCC_CR_MSIRDY)) - ; - } - - /* Switch to MSI */ - STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI; - /* RM says to check SWS bits to make sure MSI is the sysclock */ - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_MSI) - ; - - /* - * Set the recommended flash settings for <= 2MHz clock. - * - * The 3 bits must be programmed strictly sequentially. - * Also, follow the RM to check 64-bit access and latency bit - * after writing those bits to the FLASH_ACR register. - */ - tmp_acr = STM32_FLASH_ACR; - /* Flash 0 wait state */ - tmp_acr &= ~STM32_FLASH_ACR_LATENCY; - STM32_FLASH_ACR = tmp_acr; - /* Check LATENCY bit == 0 */ - while (STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY) - ; - - /* Disable prefetch Buffer */ - tmp_acr &= ~STM32_FLASH_ACR_PRFTEN; - STM32_FLASH_ACR = tmp_acr; - - /* Disable 64-bit access */ - tmp_acr &= ~STM32_FLASH_ACR_ACC64; - STM32_FLASH_ACR = tmp_acr; - /* Check ACC64 bit == 0 */ - while (STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64) - ; - - /* Disable HSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_HSION; - - /* Enable LPSDSR */ - STM32_PWR_CR |= STM32_PWR_CR_LPSDSR; - - freq = MSI_1MHZ_CLOCK; - break; - - default: - break; - } - - /* Notify modules of frequency change unless we're initializing */ - if (current_osc != OSC_INIT) { - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); - } else { - current_osc = osc; - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - static uint32_t clock_mask; - int new_mask; - - if (enable) - new_mask = clock_mask | BIT(module); - else - new_mask = clock_mask & ~BIT(module); - - /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) { - - /* Flush UART before switching clock speed */ - cflush(); - - clock_set_osc(new_mask ? OSC_HSI : OSC_MSI); - } - - clock_mask = new_mask; -} - -#ifdef CONFIG_STM32L_FAKE_HIBERNATE -/* - * This is for NOT having enough hibernate (more precisely, the stand-by mode) - * wake-up source pin. STM32L100 supports 3 wake-up source pins: - * - * WKUP1 (PA0) -- used for ACOK_PMU - * WKUP2 (PC13) -- used for LID_OPEN - * WKUP3 (PE6) -- cannot be used due to IC package. - * - * However, we need the power button as a wake-up source as well and there is - * no available pin for us (we don't want to move the ACOK_PMU pin). - * - * Fortunately, the STM32L is low-power enough so that we don't need the - * super-low-power mode. So, we fake this hibernate mode and accept the - * following wake-up source. - * - * RTC alarm (faked as well). - * Power button - * Lid open - * AC detected - * - * The original issue is here: crosbug.com/p/25435. - */ -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - fake_hibernate = 1; - -#ifdef CONFIG_POWER_COMMON - /* - * A quick hack to stop annoying messages from charger task. - * - * When the battery is under 3%, the power task would call - * power_off() to shutdown AP. However, the power_off() would - * notify the HOOK_CHIPSET_SHUTDOWN, where the last hook is - * charge_shutdown() and it hibernates the power task (infinite - * loop -- not real CPU hibernate mode). Unfortunately, the - * charger task is still running. It keeps generating annoying - * log message. - * - * Thus, the hack is to set the power state machine (before we - * enter infinite loop) so that the charger task thinks the AP - * is off and stops generating messages. - */ - power_set_state(POWER_G3); -#endif - - /* - * Change keyboard outputs to high-Z to reduce power draw. - * We don't need corresponding code to change them back, - * because fake hibernate is always exited with a reboot. - * - * A little hacky to do this here. - */ - for (i = GPIO_KB_OUT00; i < GPIO_KB_OUT00 + KEYBOARD_COLS_MAX; i++) - gpio_set_flags(i, GPIO_INPUT); - - ccprints("fake hibernate. waits for power button/lid/RTC/AC"); - cflush(); - - if (seconds || microseconds) { - if (seconds) - sleep(seconds); - if (microseconds) - usleep(microseconds); - } else { - while (1) - task_wait_event(-1); - } - - ccprints("fake RTC alarm fires. resets EC"); - cflush(); - system_reset(SYSTEM_RESET_HARD); -} - -static void fake_hibernate_power_button_hook(void) -{ - if (fake_hibernate && lid_is_open() && !power_button_is_pressed()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook, - HOOK_PRIO_DEFAULT); - -static void fake_hibernate_lid_hook(void) -{ - if (fake_hibernate && lid_is_open()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_LID_CHANGE, fake_hibernate_lid_hook, HOOK_PRIO_DEFAULT); - -static void fake_hibernate_ac_hook(void) -{ - if (fake_hibernate && extpower_is_present()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_AC_CHANGE, fake_hibernate_ac_hook, HOOK_PRIO_DEFAULT); -#endif - -void clock_init(void) -{ - /* - * The initial state : - * SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2 - * PLL unlocked, RTC enabled on LSE - */ - - /* Switch to high-speed oscillator */ - clock_set_osc(1); -} - -static void clock_chipset_startup(void) -{ - /* Return to full speed */ - clock_enable_module(MODULE_CHIPSET, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT); - -static void clock_chipset_shutdown(void) -{ - /* Drop to lower clock speed if no other module requires full speed */ - clock_enable_module(MODULE_CHIPSET, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI); - else if (!strcasecmp(argv[1], "msi")) - clock_set_osc(OSC_MSI); - else - return EC_ERROR_PARAM1; - } - - ccprintf("Clock frequency is now %d Hz\n", freq); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi", - "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c deleted file mode 100644 index 182abcafca..0000000000 --- a/chip/stm32/clock-stm32l4.c +++ /dev/null @@ -1,397 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "registers.h" -#include "util.h" - -/* High-speed oscillator is 16 MHz */ -#define STM32_HSI_CLOCK 16000000 -/* Multi-speed oscillator is 4 MHz by default */ -#define STM32_MSI_CLOCK 4000000 - -enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed internal oscillator */ - OSC_MSI, /* Multi-speed internal oscillator */ -#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ - OSC_HSE, /* High-speed external oscillator */ -#endif - OSC_PLL, /* PLL */ -}; - -static int freq = STM32_MSI_CLOCK; -static int current_osc; - -int clock_get_freq(void) -{ - return freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t dummy __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - dummy = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - dummy = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -static void clock_enable_osc(enum clock_osc osc) -{ - uint32_t ready; - uint32_t on; - - switch (osc) { - case OSC_HSI: - ready = STM32_RCC_CR_HSIRDY; - on = STM32_RCC_CR_HSION; - break; - case OSC_MSI: - ready = STM32_RCC_CR_MSIRDY; - on = STM32_RCC_CR_MSION; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - ready = STM32_RCC_CR_HSERDY; - on = STM32_RCC_CR_HSEON; - break; -#endif - case OSC_PLL: - ready = STM32_RCC_CR_PLLRDY; - on = STM32_RCC_CR_PLLON; - break; - default: - return; - } - - if (!(STM32_RCC_CR & ready)) { - /* Enable HSI */ - STM32_RCC_CR |= on; - /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR & ready)) - ; - } -} - -/* Switch system clock oscillator */ -static void clock_switch_osc(enum clock_osc osc) -{ - uint32_t sw; - uint32_t sws; - - switch (osc) { - case OSC_HSI: - sw = STM32_RCC_CFGR_SW_HSI; - sws = STM32_RCC_CFGR_SWS_HSI; - break; - case OSC_MSI: - sw = STM32_RCC_CFGR_SW_MSI; - sws = STM32_RCC_CFGR_SWS_MSI; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - sw = STM32_RCC_CFGR_SW_HSE; - sws = STM32_RCC_CFGR_SWS_HSE; - break; -#endif - case OSC_PLL: - sw = STM32_RCC_CFGR_SW_PLL; - sws = STM32_RCC_CFGR_SWS_PLL; - break; - default: - return; - } - - STM32_RCC_CFGR = sw; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws) - ; -} - -/* - * Configure PLL for HSE - * - * 1. Disable the PLL by setting PLLON to 0 in RCC_CR. - * 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. - * 3. Change the desired parameter. - * 4. Enable the PLL again by setting PLLON to 1. - * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN - * in RCC_PLLCFGR. - */ -static int stm32_configure_pll(enum clock_osc osc, - uint8_t m, uint8_t n, uint8_t r) -{ - uint32_t val; - int f; - - /* 1 */ - STM32_RCC_CR &= ~STM32_RCC_CR_PLLON; - - /* 2 */ - while (STM32_RCC_CR & STM32_RCC_CR_PLLRDY) - ; - - /* 3 */ - val = STM32_RCC_PLLCFGR; - - val &= ~STM32_RCC_PLLCFGR_PLLSRC_MASK; - switch (osc) { - case OSC_HSI: - val |= STM32_RCC_PLLCFGR_PLLSRC_HSI; - f = STM32_HSI_CLOCK; - break; - case OSC_MSI: - val |= STM32_RCC_PLLCFGR_PLLSRC_MSI; - f = STM32_MSI_CLOCK; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - val |= STM32_RCC_PLLCFGR_PLLSRC_HSE; - f = STM32_HSE_CLOCK; - break; -#endif - default: - return -1; - } - - ASSERT(m > 0 && m < 9); - val &= ~STM32_RCC_PLLCFGR_PLLM_MASK; - val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_SHIFT; - - /* Max and min values are from TRM */ - ASSERT(n > 7 && n < 87); - val &= ~STM32_RCC_PLLCFGR_PLLN_MASK; - val |= n << STM32_RCC_PLLCFGR_PLLN_SHIFT; - - val &= ~STM32_RCC_PLLCFGR_PLLR_MASK; - switch (r) { - case 2: - val |= 0 << STM32_RCC_PLLCFGR_PLLR_SHIFT; - break; - case 4: - val |= 1 << STM32_RCC_PLLCFGR_PLLR_SHIFT; - break; - case 6: - val |= 2 << STM32_RCC_PLLCFGR_PLLR_SHIFT; - break; - case 8: - val |= 3 << STM32_RCC_PLLCFGR_PLLR_SHIFT; - break; - default: - return -1; - } - - STM32_RCC_PLLCFGR = val; - - /* 4 */ - clock_enable_osc(OSC_PLL); - - /* 5 */ - val = STM32_RCC_PLLCFGR; - val |= 1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT; - STM32_RCC_PLLCFGR = val; - - /* (f * n) shouldn't overflow based on their max values */ - return (f * n / m / r); -} - -/** - * Set system clock oscillator - * - * @param osc Oscillator to use - * @param pll_osc Source oscillator for PLL. Ignored if osc is not PLL. - */ -static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) -{ - uint32_t val; - - if (osc == current_osc) - return; - - if (current_osc != OSC_INIT) - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - case OSC_HSI: - /* Ensure that HSI is ON */ - clock_enable_osc(osc); - - /* Disable LPSDSR */ - STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; - - /* Switch to HSI */ - clock_switch_osc(osc); - - /* Disable MSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_MSION; - - freq = STM32_HSI_CLOCK; - break; - - case OSC_MSI: - /* Switch to MSI @ 1MHz */ - STM32_RCC_ICSCR = - (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; - /* Ensure that MSI is ON */ - clock_enable_osc(osc); - - /* Switch to MSI */ - clock_switch_osc(osc); - - /* Disable HSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_HSION; - - /* Enable LPSDSR */ - STM32_PWR_CR |= STM32_PWR_CR_LPSDSR; - - freq = STM32_MSI_CLOCK; - break; - -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - /* Ensure that HSE is stable */ - clock_enable_osc(osc); - - /* Switch to HSE */ - clock_switch_osc(osc); - - /* Disable other clock sources */ - STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION | - STM32_RCC_CR_PLLON); - - freq = STM32_HSE_CLOCK; - - break; -#endif - case OSC_PLL: - /* Ensure that source clock is stable */ - clock_enable_osc(pll_osc); - - /* Configure PLLCFGR */ - freq = stm32_configure_pll(pll_osc, STM32_PLLM, - STM32_PLLN, STM32_PLLR); - ASSERT(freq > 0); - - /* Adjust flash latency as instructed in TRM */ - val = STM32_FLASH_ACR; - val &= ~STM32_FLASH_ACR_LATENCY_MASK; - /* Flash 4 wait state. TODO: Should depend on freq. */ - val |= 4 << STM32_FLASH_ACR_LATENCY_SHIFT; - STM32_FLASH_ACR = val; - while (STM32_FLASH_ACR != val) - ; - - /* Switch to PLL */ - clock_switch_osc(osc); - - /* TODO: Disable other sources */ - break; - default: - break; - } - - /* Notify modules of frequency change unless we're initializing */ - if (current_osc != OSC_INIT) { - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); - } else { - current_osc = osc; - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - static uint32_t clock_mask; - int new_mask; - - if (enable) - new_mask = clock_mask | BIT(module); - else - new_mask = clock_mask & ~BIT(module); - - /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) { - - /* Flush UART before switching clock speed */ - cflush(); - - clock_set_osc(new_mask ? OSC_HSI : OSC_MSI, OSC_INIT); - } - - clock_mask = new_mask; -} - -void clock_init(void) -{ -#ifdef STM32_HSE_CLOCK - clock_set_osc(OSC_PLL, OSC_HSE); -#else - clock_set_osc(OSC_HSI, OSC_INIT); -#endif -} - -static void clock_chipset_startup(void) -{ - /* Return to full speed */ - clock_enable_module(MODULE_CHIPSET, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT); - -static void clock_chipset_shutdown(void) -{ - /* Drop to lower clock speed if no other module requires full speed */ - clock_enable_module(MODULE_CHIPSET, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI, OSC_INIT); - else if (!strcasecmp(argv[1], "msi")) - clock_set_osc(OSC_MSI, OSC_INIT); -#ifdef STM32_HSE_CLOCK - else if (!strcasecmp(argv[1], "hse")) - clock_set_osc(OSC_HSE, OSC_INIT); - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL, OSC_HSE); -#else - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL, OSC_HSI); -#endif - else - return EC_ERROR_PARAM1; - } - - ccprintf("Clock frequency is now %d Hz\n", freq); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi" -#ifdef STM32_HSE_CLOCK - " | hse | pll" -#endif - , - "Set clock frequency"); diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h deleted file mode 100644 index 84266cdbfc..0000000000 --- a/chip/stm32/config-stm32f03x.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifdef CHIP_VARIANT_STM32F03X8 -#define CONFIG_FLASH_SIZE 0x00010000 -#define CONFIG_RAM_SIZE 0x00002000 -#else -#define CONFIG_FLASH_SIZE 0x00008000 -#define CONFIG_RAM_SIZE 0x00001000 -#endif - -/* Memory mapping */ -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h deleted file mode 100644 index cab7b62d50..0000000000 --- a/chip/stm32/config-stm32f05x.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE (64 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h deleted file mode 100644 index 199aef3361..0000000000 --- a/chip/stm32/config-stm32f07x.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE (128 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t -#define CONFIG_USB_RAM_ACCESS_SIZE 2 diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h deleted file mode 100644 index 3da8a342f2..0000000000 --- a/chip/stm32/config-stm32f09x.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -/* - * Flash physical size: 256KB - * Write protect sectors: 31 4KB sectors, one 132KB sector - */ -#define CONFIG_FLASH_SIZE 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* - * STM32F09x flash layout: - * - RO image starts at the beginning of flash: sector 0 ~ 29 - * - PSTATE immediately follows the RO image: sector 30 - * - RW image starts at 0x1f00: sector 31 - * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30 - * - Unprotected region consists of second half of RW image - * - * PSTATE(4KB) - * | - * (124KB) v (132KB) - * |<-----Protected Region------>|<------Unprotected Region----->| - * |<--------RO image--------->| |<----------RW image----------->| - * 0 (120KB) ^ ^ - * | | - * | 31(132KB sector) - * | - * 30 - * - */ - -#define _SECTOR_4KB (4 * 1024) -#define _SECTOR_132KB (132 * 1024) - -/* The EC uses one sector to emulate persistent state */ -#define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB -#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _SECTOR_132KB - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 32 -#define WP_BANK_COUNT 31 -#define PSTATE_BANK 30 -#define PSTATE_BANK_COUNT 1 - diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h deleted file mode 100644 index b77b1d98a6..0000000000 --- a/chip/stm32/config-stm32f373.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x2000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 81 - -/* STM32F3 uses the older 4 byte aligned access mechanism */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32f446.h b/chip/stm32/config-stm32f446.h deleted file mode 100644 index ee43b4fb9b..0000000000 --- a/chip/stm32/config-stm32f446.h +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE (512 * 1024) - -/* 3 regions type: 16K, 64K and 128K */ -#define SIZE_16KB (16 * 1024) -#define SIZE_64KB (64 * 1024) -#define SIZE_128KB (128 * 1024) -#define CONFIG_FLASH_REGION_TYPE_COUNT 3 -#define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB) - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* minimum write size for 3.3V. 1 for 1.8V */ -#define STM32_FLASH_WRITE_SIZE_1800 1 -#define STM32_FLASH_WS_DIV_1800 16000000 -#define STM32_FLASH_WRITE_SIZE_3300 4 -#define STM32_FLASH_WS_DIV_3300 30000000 - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00020000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (256 * 1024) -#define CONFIG_RW_MEM_OFF (256 * 1024) -#define CONFIG_RW_SIZE (256 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Use OTP regions */ -#define CONFIG_OTP - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 97 diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h deleted file mode 100644 index 665bec36bf..0000000000 --- a/chip/stm32/config-stm32f76x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE (2048 * 1024) - -/* 3 regions type: 32K, 128K and 256K */ -#define SIZE_32KB (32 * 1024) -#define SIZE_128KB (128 * 1024) -#define SIZE_256KB (256 * 1024) -#define CONFIG_FLASH_REGION_TYPE_COUNT 3 -#define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB) - -/* Erasing 256K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* minimum write size for 3.3V. 1 for 1.8V */ -#define STM32_FLASH_WRITE_SIZE_1800 1 -#define STM32_FLASH_WS_DIV_1800 16000000 -#define STM32_FLASH_WRITE_SIZE_3300 4 -#define STM32_FLASH_WS_DIV_3300 30000000 - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/ -/* SRAM1: 368kB 0x20020000 - 0x2007BFFF */ -/* SRAM2: 16kB 0x2007C000 - 0x2007FFFF */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00080000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (1024 * 1024) -#define CONFIG_RW_MEM_OFF (1024 * 1024) -#define CONFIG_RW_SIZE (1024 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 109 diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h deleted file mode 100644 index 399e6a6f1a..0000000000 --- a/chip/stm32/config-stm32h7x3.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE (2048 * 1024) -#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ -/* always use 256-bit writes due to ECC */ -#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 - -/* - * What the code is calling 'bank' is really the size of the block used for - * write-protected, here it's 128KB sector (same as erase size). - */ -#define CONFIG_FLASH_BANK_SIZE (128 * 1024) - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* ITCM-RAM: 64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */ -/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */ -/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */ -/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */ -/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */ -/* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */ -/* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */ -/* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */ -#define CONFIG_RAM_BASE 0x24000000 -#define CONFIG_RAM_SIZE 0x00080000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE / 2) -#define CONFIG_RW_SIZE (512 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* - * Cannot use PSTATE: - * 128kB blocks are too large and ECC prevents re-writing PSTATE word. - */ -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 150 - -/* the Cortex-M7 core has 'standard' ARMv7-M caches */ -#define CONFIG_ARMV7M_CACHE -/* Use the MPU to configure cacheability */ -#define CONFIG_MPU -/* Store in uncached buffers for DMA transfers in ahb4 region */ -#define CONFIG_CHIP_UNCACHED_REGION ahb4 -/* Override MPU attribute settings to match the chip requirements */ -/* Code is Normal memory type / non-shareable / write-through */ -#define MPU_ATTR_FLASH_MEMORY 0x02 -/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */ -#define MPU_ATTR_INTERNAL_SRAM 0x0B diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h deleted file mode 100644 index 579e31cb5b..0000000000 --- a/chip/stm32/config-stm32l100.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ - -/* - * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at - * a time), but that's really slow, and older host interfaces which can't ask - * about the ideal size would then end up writing in that mode instead of the - * faster page mode. So lie about the write size for now. Once all software - * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1 - * of EC_CMD_GET_FLASH_INFO, we can remove this workaround. - */ -#define CONFIG_FLASH_WRITE_SIZE 0x0080 - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002800 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 45 - -/* Flash erases to 0, not 1 */ -#define CONFIG_FLASH_ERASED_VALUE32 0 - -/* Use DMA for UART receive */ -#define CONFIG_UART_RX_DMA - -/* Fake hibernate mode */ -#define CONFIG_STM32L_FAKE_HIBERNATE - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h deleted file mode 100644 index afdc241e96..0000000000 --- a/chip/stm32/config-stm32l15x.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ - -/* - * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at - * a time), but that's really slow, and older host interfaces which can't ask - * about the ideal size would then end up writing in that mode instead of the - * faster page mode. So lie about the write size for now. Once all software - * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1 - * of EC_CMD_GET_FLASH_INFO, we can remove this workaround. - */ -#define CONFIG_FLASH_WRITE_SIZE 0x0080 - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 45 - -/* Lots of RAM, so use bigger UART buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Use DMA for UART receive */ -#define CONFIG_UART_RX_DMA - -/* Flash erases to 0, not 1 */ -#define CONFIG_FLASH_ERASED_VALUE32 0 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h deleted file mode 100644 index e9f3e04c53..0000000000 --- a/chip/stm32/config-stm32l442.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00040000 /* 256 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -/* - * SRAM1 (48kB) at 0x20000000 - * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) - * so they are contiguous. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 82 diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h deleted file mode 100644 index 9f6b35b8b1..0000000000 --- a/chip/stm32/config-stm32l476.h +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -#define CONFIG_RAM_BASE 0x20000000 -/* Only using SRAM1. SRAM2 (32 KB) is ignored. */ -#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 82 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h deleted file mode 100644 index d0223aba09..0000000000 --- a/chip/stm32/config_chip.h +++ /dev/null @@ -1,152 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#ifdef CHIP_FAMILY_STM32F0 -/* CPU core BFD configuration */ -#include "core/cortex-m0/config_core.h" -/* IRQ priorities */ -#define STM32_IRQ_EXT0_1_PRIORITY 1 -#define STM32_IRQ_EXT2_3_PRIORITY 1 -#define STM32_IRQ_EXTI4_15_PRIORITY 1 -#else -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" -#endif - -/* Default to UART 1 for EC console */ -#define CONFIG_UART_CONSOLE 1 - -/* Use variant specific configuration for flash / UART / IRQ */ -/* STM32F03X8 it itself a variant of STM32F03X with non-default flash sizes */ -#ifdef CHIP_VARIANT_STM32F03X8 -#define CHIP_VARIANT_STM32F03X -#endif - -/* Number of I2C ports, can be overridden in variant */ -#define I2C_PORT_COUNT 2 - -#if defined(CHIP_VARIANT_STM32L476) -#include "config-stm32l476.h" -#elif defined(CHIP_VARIANT_STM32L15X) -#include "config-stm32l15x.h" -#elif defined(CHIP_VARIANT_STM32L100) -#include "config-stm32l100.h" -#elif defined(CHIP_VARIANT_STM32L442) -#include "config-stm32l442.h" -#elif defined(CHIP_VARIANT_STM32F76X) -#include "config-stm32f76x.h" -#elif defined(CHIP_FAMILY_STM32F4) -/* STM32F4 family */ -#include "config-stm32f446.h" -#elif defined(CHIP_VARIANT_STM32F373) -#include "config-stm32f373.h" -#elif defined(CHIP_VARIANT_STM32F09X) -/* STM32F09xx */ -#include "config-stm32f09x.h" -#elif defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F070) -/* STM32F07xx */ -#include "config-stm32f07x.h" -#elif defined(CHIP_VARIANT_STM32F05X) -/* STM32F05xx */ -#include "config-stm32f05x.h" -#elif defined(CHIP_VARIANT_STM32F03X) -/* STM32F03x */ -#include "config-stm32f03x.h" -#elif defined(CHIP_VARIANT_STM32H7X3) -#include "config-stm32h7x3.h" -#else -#error "Unsupported chip variant" -#endif - -#define CONFIG_PROGRAM_MEMORY_BASE 0x08000000 - -/* Memory-mapped internal flash */ -#define CONFIG_INTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE - -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE - -#if !defined(CHIP_FAMILY_STM32F4) && \ - !defined(CHIP_FAMILY_STM32F7) && \ - !defined(CHIP_FAMILY_STM32H7) && \ - !defined(CHIP_VARIANT_STM32F09X) -/* Compute the rest of the flash params from these */ -#include "config_std_internal_flash.h" -#endif - -/* Additional special purpose regions (USB RAM and other special SRAMs) */ -#define CONFIG_CHIP_MEMORY_REGIONS - -/* System stack size */ -#if defined(CHIP_VARIANT_STM32F05X) -#define CONFIG_STACK_SIZE 768 -#else -#define CONFIG_STACK_SIZE 1024 -#endif - -/* Idle task stack size */ -#define IDLE_TASK_STACK_SIZE 256 - -/* Smaller task stack size */ -#define SMALLER_TASK_STACK_SIZE 384 - -/* Default task stack size */ -#define TASK_STACK_SIZE 488 - -/* Larger task stack size, for hook task */ -#define LARGER_TASK_STACK_SIZE 640 - -/* Even bigger */ -#define VENTI_TASK_STACK_SIZE 768 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* - * Use a timer to print a watchdog warning event before the actual watchdog - * timer fires. This is needed on STM32, where the independent watchdog has no - * early warning feature and the windowed watchdog has a very short period. - */ -#define CONFIG_WATCHDOG_HELP - -/* Use DMA */ -#define CONFIG_DMA - -/* STM32 features RTC (optional feature) */ -#define CONFIG_RTC - -/* Number of peripheral request signals per DMA channel */ -#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 - -/* - * Use DMA for UART transmit for all platforms. DMA for UART receive is - * enabled on a per-chip basis because it doesn't seem to work reliably on - * STM32F (see crosbug.com/p/24141). - */ -#define CONFIG_UART_TX_DMA - -#ifndef CHIP_FAMILY_STM32H7 -/* Flash protection applies to the next boot, not the current one */ -#define CONFIG_FLASH_PROTECT_NEXT_BOOT -#endif /* !CHIP_FAMILY_STM32H7 */ - -/* Chip needs to do custom pre-init */ -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_NAME_BY_PIN(port, index) #port#index -#define GPIO_PIN(port, index) GPIO_##port, BIT(index) -#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) - -/* Prescaler values for PLL. Currently used only by STM32L476. */ -#define STM32_PLLM 0 -#define STM32_PLLN 0 -#define STM32_PLLR 0 - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h deleted file mode 100644 index 2a50d5760e..0000000000 --- a/chip/stm32/crc_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CRC_HW_H -#define __CROS_EC_CRC_HW_H -/* CRC-32 hardware implementation with USB constants */ - -#include "clock.h" -#include "registers.h" - -static inline void crc32_init(void) -{ - /* switch on CRC controller */ - STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */ - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); - /* reset CRC state */ - STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT - | STM32_CRC_CR_REV_IN_WORD; - while (STM32_CRC_CR & 1) - ; -} - -static inline void crc32_hash32(uint32_t val) -{ - STM32_CRC_DR = val; -} - -static inline void crc32_hash16(uint16_t val) -{ - STM32_CRC_DR16 = val; -} - -static inline uint32_t crc32_result(void) -{ - return STM32_CRC_DR ^ 0xFFFFFFFF; -} - -#endif /* __CROS_EC_CRC_HW_H */ diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c deleted file mode 100644 index c4e151692c..0000000000 --- a/chip/stm32/debug_printf.c +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Synchronous UART debug printf */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "printf.h" -#include "registers.h" -#include "util.h" - -static int debug_txchar(void *context, int c) -{ - if (c == '\n') { - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; - STM32_USART_TDR(UARTN_BASE) = '\r'; - } - - /* Wait for space to transmit */ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; - STM32_USART_TDR(UARTN_BASE) = c; - - return 0; -} - - - -void debug_printf(const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); -} - -#ifdef CONFIG_COMMON_RUNTIME -void cflush(void) -{ - /* Wait for transmit complete */ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)) - ; -} - -int cputs(enum console_channel channel, const char *outstr) -{ - debug_printf(outstr); - - return 0; -} - -void panic_puts(const char *outstr) -{ - debug_printf(outstr); - cflush(); -} - -int cprintf(enum console_channel channel, const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - return 0; -} - -void panic_printf(const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - cflush(); -} - -int cprints(enum console_channel channel, const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - debug_printf("\n"); - - return 0; -} - -void uart_init(void) -{ - /* Enable USART1 clock */ - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; - /* set baudrate */ - STM32_USART_BRR(UARTN_BASE) = - DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE); - /* UART enabled, 8 Data bits, oversampling x16, no parity */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; - /* 1 stop bit, no fancy stuff */ - STM32_USART_CR2(UARTN_BASE) = 0x0000; - /* DMA disabled, special modes disabled, error interrupt disabled */ - STM32_USART_CR3(UARTN_BASE) = 0x0000; - - /* Configure GPIOs */ - gpio_config_module(MODULE_UART, 1); -} -#endif diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h deleted file mode 100644 index 6091cfc7fc..0000000000 --- a/chip/stm32/debug_printf.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Synchronous UART debug printf */ - -#ifndef __CROS_EC_DEBUG_H -#define __CROS_EC_DEBUG_H - -#ifdef CONFIG_DEBUG_PRINTF -__attribute__((__format__(__printf__, 1, 2))) -void debug_printf(const char *format, ...); -#else -#define debug_printf(...) -#endif - -#endif /* __CROS_EC_DEBUG_H */ diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c deleted file mode 100644 index abb33befda..0000000000 --- a/chip/stm32/dma-stm32f4.c +++ /dev/null @@ -1,334 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) - -stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS }; - -/* Callback data to use when IRQ fires */ -static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ -} dma_irq[STM32_DMAS_TOTAL_COUNT]; - -/** - * Return the IRQ for the DMA stream - * - * @param stream stream number - * @return IRQ for the stream - */ -static int dma_get_irq(enum dma_channel stream) -{ - if (stream < STM32_DMA1_STREAM6) - return STM32_IRQ_DMA1_STREAM0 + stream; - if (stream == STM32_DMA1_STREAM7) - return STM32_IRQ_DMA1_STREAM7; - if (stream < STM32_DMA2_STREAM5) - return STM32_IRQ_DMA2_STREAM0 + stream - STM32_DMA2_STREAM0; - else - return STM32_IRQ_DMA2_STREAM5 + stream - STM32_DMA2_STREAM5; -} - -stm32_dma_regs_t *dma_get_ctrl(enum dma_channel stream) -{ - return STM32_DMA_REGS[stream / STM32_DMAS_COUNT]; -} - -stm32_dma_stream_t *dma_get_channel(enum dma_channel stream) -{ - stm32_dma_regs_t *dma = dma_get_ctrl(stream); - - return &dma->stream[stream % STM32_DMAS_COUNT]; -} - -#ifdef CHIP_FAMILY_STM32H7 -void dma_select_channel(enum dma_channel channel, uint8_t req) -{ - STM2_DMAMUX_CxCR(DMAMUX1, channel) = req; -} -#endif - -void dma_disable(enum dma_channel ch) -{ - stm32_dma_stream_t *stream = dma_get_channel(ch); - - if (stream->scr & STM32_DMA_CCR_EN) { - stream->scr &= ~STM32_DMA_CCR_EN; - while (stream->scr & STM32_DMA_CCR_EN) - ; - } -} - -void dma_disable_all(void) -{ - int ch; - - for (ch = 0; ch < STM32_DMAS_TOTAL_COUNT; ch++) - dma_disable(ch); -} - -/** - * Prepare a stream for use and start it - * - * @param stream stream to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register. - */ -static void prepare_stream(enum dma_channel stream, unsigned count, - void *periph, void *memory, unsigned flags) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; - - dma_disable(stream); - dma_clear_isr(stream); - - /* Following the order in DocID026448 Rev 1 (RM0383) p181 */ - dma_stream->spar = (uint32_t)periph; - dma_stream->sm0ar = (uint32_t)memory; - dma_stream->sndtr = count; - dma_stream->scr = ccr; - ccr |= flags & STM32_DMA_CCR_CHANNEL_MASK; - dma_stream->scr = ccr; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; - ccr |= flags; - dma_stream->scr = ccr; -} - -void dma_go(stm32_dma_stream_t *stream) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - stream->scr |= STM32_DMA_CCR_EN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the stream for transmit. - */ - prepare_stream(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | - option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) -{ - stm32_dma_stream_t *stream = dma_get_channel(option->channel); - - prepare_stream(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | - option->flags); - dma_go(stream); -} - -int dma_bytes_done(stm32_dma_stream_t *stream, int orig_count) -{ - /* - * Note that we're intentionally not checking that DMA is enabled here - * because there is a race when the hardware stops the transfer: - * - * From Section 9.3.14 DMA transfer completion in RM0402 Rev 5 - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf: - * If the stream is configured in non-circular mode, after the end of - * the transfer (that is when the number of data to be transferred - * reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is - * cleared by Hardware) and no DMA request is served unless the software - * reprograms the stream and re-enables it (by setting the EN bit in the - * DMA_SxCR register). - * - * See http://b/132444384 for full details. - */ - return orig_count - stream->sndtr; -} - -bool dma_is_enabled(stm32_dma_stream_t *stream) -{ - return (stream->scr & STM32_DMA_CCR_EN); -} - -#ifdef CONFIG_DMA_HELP -void dma_dump(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n", - dma_stream->scr, dma_stream->sndtr, dma_stream->spar, - dma_stream->sm0ar, dma_stream->sfcr); - CPRINTF("stream %d, isr=%x, ifcr=%x\n", - stream, - STM32_DMA_GET_ISR(stream), - STM32_DMA_GET_IFCR(stream)); -} - -void dma_check(enum dma_channel stream, char *buf) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - int count; - int i; - - count = dma_stream->sndtr; - CPRINTF("c=%d\n", count); - udelay(100 * MSEC); - CPRINTF("c=%d\n", dma_stream->sndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); - udelay(100 * MSEC); - CPRINTF("c=%d\n", dma_stream->sndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); -} - -/* Run a check of memory-to-memory DMA */ -void dma_test(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - uint32_t ctrl; - char periph[32], memory[32]; - unsigned count = sizeof(periph); - int i; - - memset(memory, '\0', sizeof(memory)); - for (i = 0; i < count; i++) - periph[i] = 10 + i; - - dma_clear_isr(stream); - /* Following the order in Doc ID 15965 Rev 5 p194 */ - dma_stream->spar = (uint32_t)periph; - dma_stream->sm0ar = (uint32_t)memory; - dma_stream->sndtr = count; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; - ctrl = STM32_DMA_CCR_PL_MEDIUM; - dma_stream->scr = ctrl; - - ctrl |= STM32_DMA_CCR_MINC; - ctrl |= STM32_DMA_CCR_DIR_M2M; - ctrl |= STM32_DMA_CCR_PINC; - - dma_stream->scr = ctrl; - dma_dump(stream); - dma_stream->scr = ctrl | STM32_DMA_CCR_EN; - - for (i = 0; i < count; i++) - CPRINTF("%d/%d ", periph[i], memory[i]); - CPRINTF("\ncount=%d\n", dma_stream->sndtr); - dma_dump(stream); -} -#endif /* CONFIG_DMA_HELP */ - -void dma_init(void) -{ - STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1 | STM32_RCC_HB1_DMA2; -} - -int dma_wait(enum dma_channel stream) -{ - timestamp_t deadline; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while ((STM32_DMA_GET_ISR(stream) & STM32_DMA_TCIF) == 0) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -static inline void _dma_wake_callback(void *cb_data) -{ - task_id_t id = (task_id_t)(int)cb_data; - - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_DMA_TC, 0); -} - -void dma_enable_tc_interrupt(enum dma_channel stream) -{ - dma_enable_tc_interrupt_callback(stream, _dma_wake_callback, - (void *)(int)task_get_current()); -} - -void dma_enable_tc_interrupt_callback(enum dma_channel stream, - void (*callback)(void *), - void *callback_data) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - dma_irq[stream].cb = callback; - dma_irq[stream].cb_data = callback_data; - - dma_stream->scr |= STM32_DMA_CCR_TCIE; - task_enable_irq(dma_get_irq(stream)); -} - -void dma_disable_tc_interrupt(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - dma_stream->scr &= ~STM32_DMA_CCR_TCIE; - task_disable_irq(dma_get_irq(stream)); - - dma_irq[stream].cb = NULL; - dma_irq[stream].cb_data = NULL; -} - -void dma_clear_isr(enum dma_channel stream) -{ - STM32_DMA_SET_IFCR(stream, STM32_DMA_ALL); -} - -#ifdef CONFIG_DMA_DEFAULT_HANDLERS -#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) -#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) -#define DECLARE_DMA_IRQ(dma, x) \ - void STM32_DMA_FCT(dma, x)(void) \ - { \ - dma_clear_isr(STM32_DMA_IDX(dma, x)); \ - if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ - (*dma_irq[STM32_DMA_IDX(dma, x)].cb) \ - (dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ - STM32_DMA_FCT(dma, x), 1); - -DECLARE_DMA_IRQ(1, 0); -DECLARE_DMA_IRQ(1, 1); -DECLARE_DMA_IRQ(1, 2); -DECLARE_DMA_IRQ(1, 3); -DECLARE_DMA_IRQ(1, 4); -DECLARE_DMA_IRQ(1, 5); -DECLARE_DMA_IRQ(1, 6); -DECLARE_DMA_IRQ(1, 7); -DECLARE_DMA_IRQ(2, 0); -DECLARE_DMA_IRQ(2, 1); -DECLARE_DMA_IRQ(2, 2); -DECLARE_DMA_IRQ(2, 3); -DECLARE_DMA_IRQ(2, 4); -DECLARE_DMA_IRQ(2, 5); -DECLARE_DMA_IRQ(2, 6); -DECLARE_DMA_IRQ(2, 7); - -#endif /* CONFIG_DMA_DEFAULT_HANDLERS */ - diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c deleted file mode 100644 index 5fb7c4c9a6..0000000000 --- a/chip/stm32/dma.c +++ /dev/null @@ -1,374 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) - -/* Callback data to use when IRQ fires */ -static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ -} dma_irq[STM32_DMAC_COUNT]; - - -/** - * Return the IRQ for the DMA channel - * - * @param channel Channel number - * @return IRQ for the channel - */ -static int dma_get_irq(enum dma_channel channel) -{ -#ifdef CHIP_FAMILY_STM32F0 - if (channel == STM32_DMAC_CH1) - return STM32_IRQ_DMA_CHANNEL_1; - - return channel > STM32_DMAC_CH3 ? - STM32_IRQ_DMA_CHANNEL_4_7 : - STM32_IRQ_DMA_CHANNEL_2_3; -#else - if (channel < STM32_DMAC_PER_CTLR) - return STM32_IRQ_DMA_CHANNEL_1 + channel; - else - return STM32_IRQ_DMA2_CHANNEL1 + - (channel - STM32_DMAC_PER_CTLR); -#endif -} - -/* - * Note, you must decrement the channel value by 1 from what is specified - * in the datasheets, as they index from 1 and this indexes from 0! - */ -stm32_dma_chan_t *dma_get_channel(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - - return &dma->chan[channel % STM32_DMAC_PER_CTLR]; -} - -#ifdef STM32_DMA_CSELR -void dma_select_channel(enum dma_channel channel, unsigned char stream) -{ - /* Local channel # starting from 0 on each DMA controller */ - const unsigned char ch = channel % STM32_DMAC_PER_CTLR; - const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL; - const unsigned char mask = BIT(shift) - 1; - uint32_t val; - - ASSERT(ch < STM32_DMAC_PER_CTLR); - ASSERT(stream <= mask); - val = STM32_DMA_CSELR(channel) & ~(mask << ch * shift); - STM32_DMA_CSELR(channel) = val | (stream << ch * shift); -} -#endif - -void dma_disable(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - if (chan->ccr & STM32_DMA_CCR_EN) - chan->ccr &= ~STM32_DMA_CCR_EN; -} - -void dma_disable_all(void) -{ - int ch; - - for (ch = 0; ch < STM32_DMAC_COUNT; ch++) { - stm32_dma_chan_t *chan = dma_get_channel(ch); - chan->ccr &= ~STM32_DMA_CCR_EN; - } -} - -/** - * Prepare a channel for use and start it - * - * @param chan Channel to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register, normally: - * STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx - * 0 for rx - */ -static void prepare_channel(enum dma_channel channel, unsigned count, - void *periph, void *memory, unsigned flags) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; - - dma_disable(channel); - dma_clear_isr(channel); - - /* Following the order in Doc ID 15965 Rev 5 p194 */ - chan->cpar = (uint32_t)periph; - chan->cmar = (uint32_t)memory; - chan->cndtr = count; - chan->ccr = ccr; - ccr |= flags; - chan->ccr = ccr; -} - -void dma_go(stm32_dma_chan_t *chan) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - chan->ccr |= STM32_DMA_CCR_EN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the channel for transmit. - */ - prepare_channel(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | - option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) -{ - stm32_dma_chan_t *chan = dma_get_channel(option->channel); - prepare_channel(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | option->flags); - dma_go(chan); -} - -int dma_bytes_done(stm32_dma_chan_t *chan, int orig_count) -{ - return orig_count - chan->cndtr; -} - -bool dma_is_enabled(stm32_dma_chan_t *chan) -{ - return (chan->ccr & STM32_DMA_CCR_EN); -} - -#ifdef CONFIG_DMA_HELP -void dma_dump(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - stm32_dma_chan_t *chan = dma_get_channel(channel); - - CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, - chan->cndtr, chan->cpar, chan->cmar); - CPRINTF("chan %d, isr=%x, ifcr=%x\n", - channel, - (dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf, - (dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf); -} - -void dma_check(enum dma_channel channel, char *buf) -{ - stm32_dma_chan_t *chan; - int count; - int i; - - chan = dma_get_channel(channel); - count = chan->cndtr; - CPRINTF("c=%d\n", count); - udelay(100 * MSEC); - CPRINTF("c=%d\n", chan->cndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); - udelay(100 * MSEC); - CPRINTF("c=%d\n", chan->cndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); -} - -/* Run a check of memory-to-memory DMA */ -void dma_test(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - uint32_t ctrl; - char periph[16], memory[16]; - unsigned count = sizeof(periph); - int i; - - memset(memory, '\0', sizeof(memory)); - for (i = 0; i < count; i++) - periph[i] = 10 + i; - - /* Following the order in Doc ID 15965 Rev 5 p194 */ - chan->cpar = (uint32_t)periph; - chan->cmar = (uint32_t)memory; - chan->cndtr = count; - ctrl = STM32_DMA_CCR_PL_MEDIUM; - chan->ccr = ctrl; - - ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */; - ctrl |= STM32_DMA_CCR_MEM2MEM; - ctrl |= STM32_DMA_CCR_PINC; -/* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ -/* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ - chan->ccr = ctrl; - chan->ccr = ctrl | STM32_DMA_CCR_EN; - - for (i = 0; i < count; i++) - CPRINTF("%d/%d ", periph[i], memory[i]); - CPRINTF("\ncount=%d\n", chan->cndtr); -} -#endif /* CONFIG_DMA_HELP */ - -void dma_init(void) -{ -#if defined(CHIP_FAMILY_STM32L4) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN; -#else - STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1; -#endif -#ifdef CHIP_FAMILY_STM32F3 - STM32_RCC_AHBENR |= STM32_RCC_HB_DMA2; -#endif - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -int dma_wait(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - const uint32_t mask = STM32_DMA_ISR_TCIF(channel); - timestamp_t deadline; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while ((dma->isr & mask) != mask) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -static inline void _dma_wake_callback(void *cb_data) -{ - task_id_t id = (task_id_t)(int)cb_data; - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_DMA_TC, 0); -} - -void dma_enable_tc_interrupt(enum dma_channel channel) -{ - dma_enable_tc_interrupt_callback(channel, _dma_wake_callback, - (void *)(int)task_get_current()); -} - -void dma_enable_tc_interrupt_callback(enum dma_channel channel, - void (*callback)(void *), - void *callback_data) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - dma_irq[channel].cb = callback; - dma_irq[channel].cb_data = callback_data; - - chan->ccr |= STM32_DMA_CCR_TCIE; - task_enable_irq(dma_get_irq(channel)); -} - -void dma_disable_tc_interrupt(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - chan->ccr &= ~STM32_DMA_CCR_TCIE; - task_disable_irq(dma_get_irq(channel)); - - dma_irq[channel].cb = NULL; - dma_irq[channel].cb_data = NULL; -} - -void dma_clear_isr(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - - dma->ifcr |= STM32_DMA_ISR_ALL(channel); -} - -#ifdef CONFIG_DMA_DEFAULT_HANDLERS -#ifdef CHIP_FAMILY_STM32F0 -void dma_event_interrupt_channel_1(void) -{ - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) { - dma_clear_isr(STM32_DMAC_CH1); - if (dma_irq[STM32_DMAC_CH1].cb != NULL) - (*dma_irq[STM32_DMAC_CH1].cb) - (dma_irq[STM32_DMAC_CH1].cb_data); - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1); - -void dma_event_interrupt_channel_2_3(void) -{ - int i; - - for (i = STM32_DMAC_CH2; i <= STM32_DMAC_CH3; i++) { - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { - dma_clear_isr(i); - if (dma_irq[i].cb != NULL) - (*dma_irq[i].cb)(dma_irq[i].cb_data); - } - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1); - -void dma_event_interrupt_channel_4_7(void) -{ - int i; - const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT); - - for (i = STM32_DMAC_CH4; i <= max_chan; i++) { - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { - dma_clear_isr(i); - if (dma_irq[i].cb != NULL) - (*dma_irq[i].cb)(dma_irq[i].cb_data); - } - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1); - -#else /* !CHIP_FAMILY_STM32F0 */ - -#define DECLARE_DMA_IRQ(x) \ - void CONCAT2(dma_event_interrupt_channel_, x)(void) \ - { \ - dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ - if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ - (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \ - (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ - CONCAT2(dma_event_interrupt_channel_, x), 1); - -DECLARE_DMA_IRQ(1); -DECLARE_DMA_IRQ(2); -DECLARE_DMA_IRQ(3); -DECLARE_DMA_IRQ(4); -DECLARE_DMA_IRQ(5); -DECLARE_DMA_IRQ(6); -DECLARE_DMA_IRQ(7); -#ifdef CHIP_FAMILY_STM32F3 -DECLARE_DMA_IRQ(9); -DECLARE_DMA_IRQ(10); -#endif - -#endif /* CHIP_FAMILY_STM32F0 */ -#endif /* CONFIG_DMA_DEFAULT_HANDLERS */ diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c deleted file mode 100644 index 14182c54a4..0000000000 --- a/chip/stm32/flash-f.c +++ /dev/null @@ -1,769 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common flash memory module for STM32F and STM32F0 */ - -#include <stdbool.h> -#include "battery.h" -#include "console.h" -#include "clock.h" -#include "flash.h" -#include "flash-f.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* - * While flash write / erase is in progress, the stm32 CPU core is mostly - * non-functional, due to the inability to fetch instructions from flash. - * This may greatly increase interrupt latency. - */ - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_WRITE_TIMEOUT_US 16000 -/* 20ms < tERASE < 40ms on F0/F3, for 1K / 2K sector size. */ -#define FLASH_ERASE_TIMEOUT_US 40000 - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -#if !defined(CHIP_FAMILY_STM32F4) -#error "CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE should work with all STM32F " -"series chips, but has not been tested" -#endif /* !CHIP_FAMILY_STM32F4 */ -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/* Forward declarations */ -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -static enum flash_rdp_level flash_physical_get_rdp_level(void); -static int flash_physical_set_rdp_level(enum flash_rdp_level level); -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_WRITE_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int wait_busy(void) -{ - int timeout = calculate_flash_timeout(); - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && timeout-- > 0) - udelay(CYCLE_PER_FLASH_LOOP); - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - - -/* - * We at least unlock the control register lock. - * We may also unlock other locks. - */ -enum extra_lock_type { - NO_EXTRA_LOCK = 0, - OPT_LOCK = 1, -}; - -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* Always unlock CR if needed */ - if (STM32_FLASH_CR & FLASH_CR_LOCK) { - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; - } - /* unlock option memory if required */ - if ((locks & OPT_LOCK) && STM32_FLASH_OPT_LOCKED) { - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; - } - - /* Re-enable bus fault handler */ - ignore_bus_fault(0); - - if ((locks & OPT_LOCK) && STM32_FLASH_OPT_LOCKED) - return EC_ERROR_UNKNOWN; - if (STM32_FLASH_CR & FLASH_CR_LOCK) - return EC_ERROR_UNKNOWN; - return EC_SUCCESS; -} - -static void lock(void) -{ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* FLASH_CR_OPTWRE was set by writing the keys in unlock(). */ - STM32_FLASH_CR &= ~FLASH_CR_OPTWRE; -#endif - STM32_FLASH_CR |= FLASH_CR_LOCK; -} - -#ifdef CHIP_FAMILY_STM32F4 -static int write_optb(uint32_t mask, uint32_t value) -{ - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - /* The target byte is the value we want to write. */ - if ((STM32_FLASH_OPTCR & mask) == value) - return EC_SUCCESS; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - STM32_FLASH_OPTCR = (STM32_FLASH_OPTCR & ~mask) | value; - STM32_FLASH_OPTCR |= FLASH_OPTSTRT; - - rv = wait_busy(); - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} -#else -static int write_optb(int byte, uint8_t value); -/* - * Option byte organization - * - * [31:24] [23:16] [15:8] [7:0] - * - * 0x1FFF_F800 nUSER USER nRDP RDP - * - * 0x1FFF_F804 nData1 Data1 nData0 Data0 - * - * 0x1FFF_F808 nWRP1 WRP1 nWRP0 WRP0 - * - * 0x1FFF_F80C nWRP3 WRP2 nWRP2 WRP2 - * - * Note that the variable with n prefix means the complement. - */ -static uint8_t read_optb(int byte) -{ - return *(uint8_t *)(STM32_OPTB_BASE + byte); -} - -static int erase_optb(void) -{ - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - /* Must be set in 2 separate lines. */ - STM32_FLASH_CR |= FLASH_CR_OPTER; - STM32_FLASH_CR |= FLASH_CR_STRT; - - rv = wait_busy(); - - STM32_FLASH_CR &= ~FLASH_CR_OPTER; - - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} - -static int write_optb(int byte, uint8_t value); -/* - * Since the option byte erase is WHOLE erase, this function is to keep - * rest of bytes, but make this byte 0xff. - * Note that this could make a recursive call to write_optb(). - */ -static int preserve_optb(int byte) -{ - int i, rv; - uint8_t optb[8]; - - /* The byte has been reset, no need to run preserve. */ - if (*(uint16_t *)(STM32_OPTB_BASE + byte) == 0xffff) - return EC_SUCCESS; - - for (i = 0; i < ARRAY_SIZE(optb); ++i) - optb[i] = read_optb(i * 2); - - optb[byte / 2] = 0xff; - - rv = erase_optb(); - if (rv) - return rv; - for (i = 0; i < ARRAY_SIZE(optb); ++i) { - rv = write_optb(i * 2, optb[i]); - if (rv) - return rv; - } - - return EC_SUCCESS; -} - -static int write_optb(int byte, uint8_t value) -{ - volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte); - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - /* The target byte is the value we want to write. */ - if (*(uint8_t *)hword == value) - return EC_SUCCESS; - - /* Try to erase that byte back to 0xff. */ - rv = preserve_optb(byte); - if (rv) - return rv; - - /* The value is 0xff after erase. No need to write 0xff again. */ - if (value == 0xff) - return EC_SUCCESS; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - /* set OPTPG bit */ - STM32_FLASH_CR |= FLASH_CR_OPTPG; - - *hword = ((~value) << STM32_OPTB_COMPL_SHIFT) | value; - - /* reset OPTPG bit */ - STM32_FLASH_CR &= ~FLASH_CR_OPTPG; - - rv = wait_busy(); - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} -#endif - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -/** - * @return true if RDP (read protection) Level 1 or 2 enabled, false otherwise - */ -bool is_flash_rdp_enabled(void) -{ - enum flash_rdp_level level = flash_physical_get_rdp_level(); - - if (level == FLASH_RDP_LEVEL_INVALID) { - CPRINTS("ERROR: unable to read RDP level"); - return false; - } - - return level != FLASH_RDP_LEVEL_0; -} -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_write(int offset, int size, const char *data) -{ -#if CONFIG_FLASH_WRITE_SIZE == 1 - uint8_t *address = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint8_t quantum = 0; -#elif CONFIG_FLASH_WRITE_SIZE == 2 - uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint16_t quantum = 0; -#elif CONFIG_FLASH_WRITE_SIZE == 4 - uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint32_t quantum = 0; -#else -#error "CONFIG_FLASH_WRITE_SIZE not supported." -#endif - int res = EC_SUCCESS; - int timeout = calculate_flash_timeout(); - - if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP; - - /* set PG bit */ - STM32_FLASH_CR |= FLASH_CR_PG; - - for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) { - int i; - - for (i = CONFIG_FLASH_WRITE_SIZE - 1, quantum = 0; i >= 0; i--) - quantum = (quantum << 8) + data[i]; - data += CONFIG_FLASH_WRITE_SIZE; - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing with interrupt disabled. - */ - watchdog_reload(); - - /* wait to be ready */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); - i++) - ; - - /* write the data */ - *address++ = quantum; - - /* Wait for writes to complete */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); - i++) - ; - - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* Check for error conditions - erase failed, voltage error, - * protection error */ - if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR &= ~FLASH_CR_PG; - - lock(); - - return res; -} - -int flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int sector_size; - int timeout_us; -#ifdef CHIP_FAMILY_STM32F4 - int sector = flash_bank_index(offset); - /* we take advantage of sector_size == erase_size */ - if ((sector < 0) || (flash_bank_index(offset + size) < 0)) - return EC_ERROR_INVAL; /* Invalid range */ -#endif - - if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP; - - /* set SER/PER bit */ - STM32_FLASH_CR |= FLASH_CR_PER; - - while (size > 0) { - timestamp_t deadline; -#ifdef CHIP_FAMILY_STM32F4 - sector_size = flash_bank_size(sector); - /* Timeout: from spec, proportional to the size - * inversely proportional to the write size. - */ - timeout_us = sector_size * 4 / CONFIG_FLASH_WRITE_SIZE; -#else - sector_size = CONFIG_FLASH_ERASE_SIZE; - timeout_us = FLASH_ERASE_TIMEOUT_US; -#endif - /* Do nothing if already erased */ - if (flash_is_erased(offset, sector_size)) - goto next_sector; -#ifdef CHIP_FAMILY_STM32F4 - /* select page to erase */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) | - (sector << STM32_FLASH_CR_SNB_OFFSET); -#else - /* select page to erase */ - STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; -#endif - /* set STRT bit : start erase */ - STM32_FLASH_CR |= FLASH_CR_STRT; - - deadline.val = get_time().val + timeout_us; - /* Wait for erase to complete */ - watchdog_reload(); - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - usleep(timeout_us/100); - } - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } -next_sector: - size -= sector_size; - offset += sector_size; -#ifdef CHIP_FAMILY_STM32F4 - sector++; -#endif - } - -exit_er: - /* reset SER/PER bit */ - STM32_FLASH_CR &= ~FLASH_CR_PER; - - lock(); - - return res; -} - -#ifdef CHIP_FAMILY_STM32F4 -static int flash_physical_get_protect_at_boot(int block) -{ - /* 0: Write protection active on sector i. */ - return !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)); -} - -static int flash_physical_protect_at_boot_update_rdp_pstate(uint32_t new_flags) -{ -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) - int rv = EC_SUCCESS; - - bool rdp_enable = (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) != 0; - - /* - * This is intentionally a one-way latch. Once we have enabled RDP - * Level 1, we will only allow going back to Level 0 using the - * bootloader (e.g., "stm32mon -U") since transitioning from Level 1 to - * Level 0 triggers a mass erase. - */ - if (rdp_enable) - rv = flash_physical_set_rdp_level(FLASH_RDP_LEVEL_1); - - return rv; -#else - return EC_SUCCESS; -#endif -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - int block; - int original_val, val; - - original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL; - - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; - block++) { - int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - - if (block >= WP_BANK_OFFSET && - block < WP_BANK_OFFSET + WP_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT; -#ifdef CONFIG_FLASH_PROTECT_RW - else - protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - - if (protect) - val &= ~BIT(block); - else - val |= 1 << block; - } - if (original_val != val) { - write_optb(STM32_FLASH_nWRP_ALL, - val << STM32_FLASH_nWRP_OFFSET); - } - - - return flash_physical_protect_at_boot_update_rdp_pstate(new_flags); -} - -static void unprotect_all_blocks(void) -{ - write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL); -} - -#else /* CHIP_FAMILY_STM32F4 */ -static int flash_physical_get_protect_at_boot(int block) -{ - uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8)); - return (!(val & (1 << (block % 8)))) ? 1 : 0; -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - int block; - int i; - int original_val[4], val[4]; - - for (i = 0; i < 4; ++i) - original_val[i] = val[i] = read_optb(i * 2 + 8); - - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; - block++) { - int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4; - - if (block >= WP_BANK_OFFSET && - block < WP_BANK_OFFSET + WP_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT; -#ifdef CONFIG_ROLLBACK - else if (block >= ROLLBACK_BANK_OFFSET && - block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif -#ifdef CONFIG_FLASH_PROTECT_RW - else - protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - - if (protect) - val[byte_off] = val[byte_off] & (~(1 << (block % 8))); - else - val[byte_off] = val[byte_off] | (1 << (block % 8)); - } - - for (i = 0; i < 4; ++i) - if (original_val[i] != val[i]) - write_optb(i * 2 + 8, val[i]); - -#ifdef CONFIG_FLASH_READOUT_PROTECTION - /* - * Set a permanent protection by increasing RDP to level 1, - * trying to unprotected the flash will trigger a full erase. - */ - write_optb(0, 0x11); -#endif - - return EC_SUCCESS; -} - -static void unprotect_all_blocks(void) -{ - int i; - - for (i = 4; i < 8; ++i) - write_optb(i * 2, 0xff); -} -#endif - -/** - * Check if write protect register state is inconsistent with RO_AT_BOOT and - * ALL_AT_BOOT state. - * - * @return zero if consistent, non-zero if inconsistent. - */ -static int registers_need_reset(void) -{ - uint32_t flags = flash_get_protect(); - int i; - int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0; - int ro_wp_region_start = WP_BANK_OFFSET; - int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT; - - for (i = ro_wp_region_start; i < ro_wp_region_end; i++) - if (flash_physical_get_protect_at_boot(i) != ro_at_boot) - return 1; - return 0; -} - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -/** - * Set Flash RDP (read protection) level. - * - * @note Does not take effect until reset. - * - * @param level new RDP (read protection) level to set - * @return EC_SUCCESS on success, other on failure - */ -int flash_physical_set_rdp_level(enum flash_rdp_level level) -{ - uint32_t reg_level; - - switch (level) { - case FLASH_RDP_LEVEL_0: - /* - * Asserting by default since we don't want to inadvertently - * go from Level 1 to Level 0, which triggers a mass erase. - * Remove assert if you want to use it. - */ - ASSERT(false); - reg_level = FLASH_OPTCR_RDP_LEVEL_0; - break; - case FLASH_RDP_LEVEL_1: - reg_level = FLASH_OPTCR_RDP_LEVEL_1; - break; - case FLASH_RDP_LEVEL_2: - /* - * Asserting by default since it's permanent (there is no - * way to reverse). Remove assert if you want to use it. - */ - ASSERT(false); - reg_level = FLASH_OPTCR_RDP_LEVEL_2; - break; - default: - return EC_ERROR_INVAL; - } - - return write_optb(FLASH_OPTCR_RDP_MASK, reg_level); -} - -/** - * @return On success, current flash read protection level. - * On failure, FLASH_RDP_LEVEL_INVALID - */ -enum flash_rdp_level flash_physical_get_rdp_level(void) -{ - uint32_t level = (STM32_FLASH_OPTCR & FLASH_OPTCR_RDP_MASK); - - switch (level) { - case FLASH_OPTCR_RDP_LEVEL_0: - return FLASH_RDP_LEVEL_0; - case FLASH_OPTCR_RDP_LEVEL_1: - return FLASH_RDP_LEVEL_1; - case FLASH_OPTCR_RDP_LEVEL_2: - return FLASH_RDP_LEVEL_2; - default: - return FLASH_RDP_LEVEL_INVALID; - } -} -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/*****************************************************************************/ -/* High-level APIs */ - -int flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = flash_get_protect(); - int need_reset = 0; - - -#ifdef CHIP_FAMILY_STM32F4 - unlock(NO_EXTRA_LOCK); - /* Set the proper write size */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) | - (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) << - STM32_FLASH_CR_PSIZE_OFFSET; - lock(); -#endif - if (flash_physical_restore_state()) - return EC_SUCCESS; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - flash_physical_protect_at_boot( - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (registers_need_reset()) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - * - * TODO(crosbug.com/p/23798): this seems really similar - * to the check above. One of them should be able to - * go away. - */ - flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else { - if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unprotect_all_blocks(); - need_reset = 1; - } - } - - if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ALL_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { - /* - * ALL_AT_BOOT and ALL_NOW should be both set or both unset - * at boot. If they are not, it must be that the chip requires - * OBL_LAUNCH to be set to reload option bytes. Let's reset - * the system with OBL_LAUNCH set. - * This assumes OBL_LAUNCH is used for hard reset in - * chip/stm32/system.c. - */ - need_reset = 1; - } - -#ifdef CONFIG_FLASH_PROTECT_RW - if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_RW_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { - /* RW_AT_BOOT and RW_NOW do not match. */ - need_reset = 1; - } -#endif - -#ifdef CONFIG_ROLLBACK - if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { - /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ - need_reset = 1; - } -#endif - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h deleted file mode 100644 index cbbe6ec86f..0000000000 --- a/chip/stm32/flash-f.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_STM32_FLASH_F_H -#define __CROS_EC_STM32_FLASH_F_H - -#include <stdbool.h> - -enum flash_rdp_level { - FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ - FLASH_RDP_LEVEL_0, /**< No read protection. */ - FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in - * bootloader mode or JTAG attached. - * Changing to Level 0 from this level - * triggers mass erase. - */ - FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent - * and can never be disabled. - */ -}; - -bool is_flash_rdp_enabled(void); - -#endif /* __CROS_EC_STM32_FLASH_F_H */ diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c deleted file mode 100644 index e2ff2c779c..0000000000 --- a/chip/stm32/flash-stm32f0.c +++ /dev/null @@ -1,173 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for Chrome EC */ - -#include "common.h" -#include "flash.h" -#include "registers.h" -#include "util.h" - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_get_protect(int block) -{ - return !(STM32_FLASH_WRPR & BIT(block)); -} - -/* - * Note: This does not need to update _NOW flags, as get_protect_flags - * in common code already does so. - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01); -#if CONFIG_FLASH_SIZE > 64 * 1024 - uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23); -#endif - - /* - * We only need to return detailed flags if we want to protect RW or - * ROLLBACK independently (EC_FLASH_PROTECT_RO_AT_BOOT should be set - * by pstate logic). - */ -#if defined(CONFIG_FLASH_PROTECT_RW) || defined(CONFIG_ROLLBACK) - /* Flags that must be set for each region. */ - const int mask_flags[] = { - [FLASH_REGION_RW] = EC_FLASH_PROTECT_RW_AT_BOOT, - [FLASH_REGION_RO] = EC_FLASH_PROTECT_RO_AT_BOOT, -#ifdef CONFIG_ROLLBACK - [FLASH_REGION_ROLLBACK] = EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, -#endif - }; - - /* - * Sets up required mask for wrp01/23 registers: for protection to be - * set, values set in the mask must be zeros, values in the mask << 8 - * must be ones. - * - * Note that these masks are actually static, and could be precomputed - * at build time to save flash space. - */ - uint32_t wrp_mask[FLASH_REGION_COUNT][2]; - int i; - int shift = 0; - int reg = 0; - - memset(wrp_mask, 0, sizeof(wrp_mask)); - - /* Scan flash protection */ - for (i = 0; i < PHYSICAL_BANKS; i++) { - /* Default: RW. */ - int region = FLASH_REGION_RW; - - if (i >= WP_BANK_OFFSET && - i < WP_BANK_OFFSET + WP_BANK_COUNT) - region = FLASH_REGION_RO; -#ifdef CONFIG_ROLLBACK - if (i >= ROLLBACK_BANK_OFFSET && - i < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - region = FLASH_REGION_ROLLBACK; -#endif - - switch (i) { - case 8: -#if CONFIG_FLASH_SIZE > 64 * 1024 - case 24: -#endif - shift += 8; - break; -#if CONFIG_FLASH_SIZE > 64 * 1024 - case 16: - reg = 1; - shift = 0; - break; -#endif - } - - wrp_mask[region][reg] |= 1 << shift; - shift++; - } - - for (i = 0; i < FLASH_REGION_COUNT; i++) { - if (!(wrp01 & wrp_mask[i][0]) && - (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) -#if CONFIG_FLASH_SIZE > 64 * 1024 - if (!(wrp23 & wrp_mask[i][1]) && - (wrp23 & wrp_mask[i][1] << 8) == - (wrp_mask[i][1] << 8)) -#endif - flags |= mask_flags[i]; - } -#endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */ - - if (wrp01 == 0xff00ff00) -#if CONFIG_FLASH_SIZE > 64 * 1024 - if (wrp23 == 0xff00ff00) -#endif - flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; - - return flags; -} - -int flash_physical_protect_now(int all) -{ - return EC_ERROR_INVAL; -} - -int flash_physical_restore_state(void) -{ - /* Nothing to restore */ - return 0; -} - -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | -#ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | -#endif -#ifdef CONFIG_ROLLBACK - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_ROLLBACK_NOW | -#endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * ALL/RW at-boot state can be set if WP GPIO is asserted and can always - * be cleared. - */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; - -#ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - -#ifdef CONFIG_ROLLBACK - if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif - - return ret; -} diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c deleted file mode 100644 index 20c5c65438..0000000000 --- a/chip/stm32/flash-stm32f3.c +++ /dev/null @@ -1,209 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for stm32f3 and stm32f4 */ - -#include <stdbool.h> -#include "common.h" -#include "flash.h" -#include "flash-f.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "panic.h" - -/*****************************************************************************/ -/* Physical layer APIs */ -#ifdef CHIP_VARIANT_STM32F76X -/* - * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB - */ -struct ec_flash_bank const flash_bank_array[] = { - { - .count = 4, - .size_exp = __fls(SIZE_32KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_32KB), - .protect_size_exp = __fls(SIZE_32KB), - }, - { - .count = 1, - .size_exp = __fls(SIZE_128KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_128KB), - .protect_size_exp = __fls(SIZE_128KB), - }, - { - .count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB, - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .size_exp = __fls(SIZE_256KB), - .erase_size_exp = __fls(SIZE_256KB), - .protect_size_exp = __fls(SIZE_256KB), - }, -}; -#elif defined(CHIP_FAMILY_STM32F4) -/* - * STM32F412xE has 512 KB flash - * 8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB - * - * STM32F412xG has 1 MB flash - * 12 "erase" sectors (1024 KB) : - * 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB - * - * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf - */ -struct ec_flash_bank const flash_bank_array[] = { - { - .count = 4, - .size_exp = __fls(SIZE_16KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_16KB), - .protect_size_exp = __fls(SIZE_16KB), - }, - { - .count = 1, - .size_exp = __fls(SIZE_64KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_64KB), - .protect_size_exp = __fls(SIZE_64KB), - }, - { - .count = (CONFIG_FLASH_SIZE - SIZE_128KB) / SIZE_128KB, - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .size_exp = __fls(SIZE_128KB), - .erase_size_exp = __fls(SIZE_128KB), - .protect_size_exp = __fls(SIZE_128KB), - }, -}; -#endif - -/* Flag indicating whether we have locked down entire flash */ -static int entire_flash_locked; - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -/* The previous write protect state before sys jump */ -struct flash_wp_state { - int entire_flash_locked; -}; - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_get_protect(int block) -{ - return (entire_flash_locked || -#if defined(CHIP_FAMILY_STM32F3) - !(STM32_FLASH_WRPR & BIT(block)) -#elif defined(CHIP_FAMILY_STM32F4) - !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) -#endif - ); -} - -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - /* Read all-protected state from our shadow copy */ - if (entire_flash_locked) - flags |= EC_FLASH_PROTECT_ALL_NOW; - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) - if (is_flash_rdp_enabled()) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; -#endif - - return flags; -} - -int flash_physical_protect_now(int all) -{ - if (all) { - /* - * Lock by writing a wrong key to FLASH_KEYR. This triggers a - * bus fault, so we need to disable bus fault handler while - * doing this. - * - * This incorrect key fault causes the flash to become - * permanently locked until reset, a correct keyring write - * will not unlock it. In this way we can implement system - * write protect. - */ - ignore_bus_fault(1); - STM32_FLASH_KEYR = 0xffffffff; - ignore_bus_fault(0); - - entire_flash_locked = 1; - - return EC_SUCCESS; - } - - /* No way to protect just the RO flash until next boot */ - return EC_ERROR_INVAL; -} - -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) - entire_flash_locked = prev->entire_flash_locked; - return 1; - } - - return 0; -} - -/*****************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - struct flash_wp_state state; - - state.entire_flash_locked = entire_flash_locked; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c deleted file mode 120000 index 6ff8130e17..0000000000 --- a/chip/stm32/flash-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -flash-stm32f3.c
\ No newline at end of file diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c deleted file mode 100644 index 5f5d1ef528..0000000000 --- a/chip/stm32/flash-stm32h7.c +++ /dev/null @@ -1,512 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Flash memory module for STM32H7 family */ - -#include "common.h" -#include "clock.h" -#include "cpu.h" -#include "flash.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 2 - -/* Flash 256-bit word programming timeout. */ -#define FLASH_TIMEOUT_US 600 - -/* - * Flash 128-KB block erase timeout. - * Datasheet says maximum is about 4 seconds in x8. - * Real delay seems to be: < 1 second in x64, < 2 seconds in x8. - */ -#define FLASH_ERASE_TIMEOUT_US (4200 * MSEC) - -/* - * Option bytes programming timeout. - * No specification, real delay seems to be around 300ms. - */ -#define FLASH_OPT_PRG_TIMEOUT_US (1000 * MSEC) - -/* - * All variants have 2 banks (as in parallel hardware / controllers) - * not what is called 'bank' in the common code (ie Write-Protect sectors) - * both have the same number of 128KB blocks. - */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE / 2) -#define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) -#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) - -/* - * We can tune the power consumption vs erase/write speed - * by default, go fast (and consume current) - */ -#define DEFAULT_PSIZE FLASH_CR_PSIZE_DWORD - -/* Can no longer write/erase flash until next reboot */ -static int access_disabled; -/* Can no longer modify write-protection in option bytes until next reboot */ -static int option_disabled; -/* Is physical flash stuck protected? (avoid reboot loop) */ -static int stuck_locked; - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int unlock(int bank) -{ - /* unlock CR only if needed */ - if (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) { - /* - * We may have already locked the flash module and get a bus - * fault in the attempt to unlock. Need to disable bus fault - * handler now. - */ - ignore_bus_fault(1); - - STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY2; - asm volatile("dsb; isb"); - ignore_bus_fault(0); - } - - return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static void lock(int bank) -{ - STM32_FLASH_CR(bank) |= FLASH_CR_LOCK; -} - -static int unlock_optb(void) -{ - if (option_disabled) - return EC_ERROR_ACCESS_DENIED; - - if (unlock(0)) - return EC_ERROR_UNKNOWN; - - /* - * Always use bank 0 flash controller as there is only one option bytes - * set for both banks. - */ - if (STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK) { - /* - * We may have already locked the flash module and get a bus - * fault in the attempt to unlock. Need to disable bus fault - * handler now. - */ - ignore_bus_fault(1); - - STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2; - asm volatile("dsb; isb"); - ignore_bus_fault(0); - } - - return STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static int commit_optb(void) -{ - /* might use this before timer_init, cannot use get_time/usleep */ - int timeout = (FLASH_OPT_PRG_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); - - STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART; - - while (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_BUSY && timeout-- > 0) - ; - - STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK; - lock(0); - - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - -static void protect_blocks(uint32_t blocks) -{ - if (unlock_optb()) - return; - STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK); - STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK) - & BLOCKS_HWBANK_MASK); - commit_optb(); -} - -/* - * If RDP as PSTATE option is defined, use that as 'Write Protect enabled' flag: - * it makes no sense to be able to unlock RO, as that'd allow flashing - * arbitrary RO that could read back all flash. - * - * crbug.com/888109: Do not copy this code over to other STM32 chips without - * understanding the full implications. - * - * If RDP is not defined, use the option bytes RSS1 bit. - * TODO(crbug.com/888104): Validate that using RSS1 for this purpose is safe. - */ -#ifndef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE -#error "crbug.com/888104: Using RSS1 for write protect PSTATE may not be safe." -#endif -static int is_wp_enabled(void) -{ -#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) - != FLASH_OPTSR_RDP_LEVEL_0; -#else - return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1); -#endif -} - -static int set_wp(int enabled) -{ - int rv; - - rv = unlock_optb(); - if (rv) - return rv; - -#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - if (enabled) { - /* Enable RDP level 1. */ - STM32_FLASH_OPTSR_PRG(0) = - (STM32_FLASH_OPTSR_PRG(0) & ~FLASH_OPTSR_RDP_MASK) | - FLASH_OPTSR_RDP_LEVEL_1; - } -#else - if (enabled) - STM32_FLASH_OPTSR_PRG(0) |= FLASH_OPTSR_RSS1; - else - STM32_FLASH_OPTSR_PRG(0) &= ~FLASH_OPTSR_RSS1; -#endif - - return commit_optb(); -} - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_write(int offset, int size, const char *data) -{ - int res = EC_SUCCESS; - int bank = offset / HWBANK_SIZE; - uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int timeout = calculate_flash_timeout(); - int i; - int unaligned = (uint32_t)data & (CONFIG_FLASH_WRITE_SIZE - 1); - uint32_t *data32 = (void *)data; - - if (access_disabled) - return EC_ERROR_ACCESS_DENIED; - - /* work on a single hardware bank at a time */ - if ((offset + size - 1) / HWBANK_SIZE != bank) - return EC_ERROR_INVAL; - - if (unlock(bank) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; - - /* select write parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; - - /* set PG bit */ - STM32_FLASH_CR(bank) |= FLASH_CR_PG; - - for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing. - */ - watchdog_reload(); - - /* write a 256-bit flash word */ - if (unaligned) { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++, - data += 4) - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - } else { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++) - *address++ = *data32++; - } - - /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR(bank) & - (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++) - ; - - if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR(bank) &= ~FLASH_CR_PG; - - lock(bank); - -#ifdef CONFIG_ARMV7M_CACHE - /* Invalidate D-cache, to make sure we do not read back stale data. */ - cpu_clean_invalidate_dcache(); -#endif - - return res; -} - -int flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int bank = offset / HWBANK_SIZE; - int last = (offset + size) / CONFIG_FLASH_ERASE_SIZE; - int sect; - - if (access_disabled) - return EC_ERROR_ACCESS_DENIED; - - /* work on a single hardware bank at a time */ - if ((offset + size - 1) / HWBANK_SIZE != bank) - return EC_ERROR_INVAL; - - if (unlock(bank) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; - - /* select erase parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; - - for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) { - timestamp_t deadline; - - /* select page to erase and PER bit */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) - & ~FLASH_CR_SNB_MASK) - | FLASH_CR_SER | FLASH_CR_SNB(sect); - - /* set STRT bit : start erase */ - STM32_FLASH_CR(bank) |= FLASH_CR_STRT; - - /* - * Reload the watchdog timer to avoid watchdog reset during a - * long erase operation. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_ERASE_TIMEOUT_US; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR(bank) & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - usleep(5000); - } - if (STM32_FLASH_SR(bank) & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* reset SER bit */ - STM32_FLASH_CR(bank) &= ~(FLASH_CR_SER | FLASH_CR_SNB_MASK); - - lock(bank); - -#ifdef CONFIG_ARMV7M_CACHE - /* Invalidate D-cache, to make sure we do not read back stale data. */ - cpu_clean_invalidate_dcache(); -#endif - - return res; -} - -int flash_physical_get_protect(int block) -{ - int bank = block / BLOCKS_PER_HWBANK; - int index = block % BLOCKS_PER_HWBANK; - - return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index)); -} - -/* - * Note: This does not need to update _NOW flags, as flash_get_protect - * in common code already does so. - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - if (access_disabled) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - if (is_wp_enabled()) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* Check if blocks were stuck locked at pre-init */ - if (stuck_locked) - flags |= EC_FLASH_PROTECT_ERROR_STUCK; - - return flags; -} - -#define WP_RANGE(start, count) (((1 << (count)) - 1) << (start)) -#define RO_WP_RANGE WP_RANGE(WP_BANK_OFFSET, WP_BANK_COUNT) - -int flash_physical_protect_now(int all) -{ - protect_blocks(RO_WP_RANGE); - - /* - * Lock the option bytes or the full access by writing a wrong - * key to FLASH_*KEYR. This triggers a bus fault, so we need to - * disable bus fault handler while doing this. - * - * This incorrect key fault causes the flash to become - * permanently locked until reset, a correct keyring write - * will not unlock it. - */ - ignore_bus_fault(1); - - if (all) { - /* cannot do any write/erase access until next reboot */ - STM32_FLASH_KEYR(0) = 0xffffffff; - STM32_FLASH_KEYR(1) = 0xffffffff; - access_disabled = 1; - } - /* cannot modify the WP bits in the option bytes until reboot */ - STM32_FLASH_OPTKEYR(0) = 0xffffffff; - option_disabled = 1; - asm volatile("dsb; isb"); - ignore_bus_fault(0); - - return EC_SUCCESS; -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - int new_wp_enable = !!(new_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - - if (is_wp_enabled() != new_wp_enable) - return set_wp(new_wp_enable); - - return EC_SUCCESS; -} - -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = flash_get_protect(); - uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - /* - * Write protect is asserted. If we want RO flash protected, - * protect it now. - */ - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv; - - rv = flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); - if (rv) - return rv; - - /* Re-read flags */ - prot_flags = flash_get_protect(); - } - } else { - /* Don't want RO flash protected */ - unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW; - } - - /* If there are no unwanted flags, done */ - if (!(prot_flags & unwanted_prot_flags)) - return EC_SUCCESS; - - /* - * If the last reboot was a power-on reset, it should have cleared - * write-protect. If it didn't, then the flash write protect registers - * have been permanently committed and we can't fix that. - */ - if (reset_flags & EC_RESET_FLAG_POWER_ON) { - stuck_locked = 1; - return EC_ERROR_ACCESS_DENIED; - } - - /* Otherwise, do a hard boot to clear the flash protection registers */ - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - /* That doesn't return, so if we're still here that's an error */ - return EC_ERROR_UNKNOWN; -} diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c deleted file mode 100644 index a151a26cf8..0000000000 --- a/chip/stm32/flash-stm32l.c +++ /dev/null @@ -1,480 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "flash.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status. - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_TIMEOUT_MS 16 - -static int flash_timeout_loop; - -/** - * Lock all the locks. - */ -static void lock(void) -{ - ignore_bus_fault(1); - - STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK | - STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK; - - ignore_bus_fault(0); -} - -/** - * Unlock the specified locks. - */ -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* Unlock PECR if needed */ - if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) { - STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY1; - STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY2; - } - - /* Fail if it didn't unlock */ - if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) { - ignore_bus_fault(0); - return EC_ERROR_ACCESS_DENIED; - } - - /* Unlock program memory if required */ - if ((locks & STM32_FLASH_PECR_PRG_LOCK) && - (STM32_FLASH_PECR & STM32_FLASH_PECR_PRG_LOCK)) { - STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY1; - STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY2; - } - - /* Unlock option memory if required */ - if ((locks & STM32_FLASH_PECR_OPT_LOCK) && - (STM32_FLASH_PECR & STM32_FLASH_PECR_OPT_LOCK)) { - STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY2; - } - - ignore_bus_fault(0); - - /* Successful if we unlocked everything we wanted */ - if (!(STM32_FLASH_PECR & (locks | STM32_FLASH_PECR_PE_LOCK))) - return EC_SUCCESS; - - /* Otherwise relock everything and return error */ - lock(); - return EC_ERROR_ACCESS_DENIED; -} - -/** - * Read an option byte word. - * - * Option bytes are stored in pairs in 32-bit registers; the upper 16 bits is - * the 1's compliment of the lower 16 bits. - */ -static uint16_t read_optb(int offset) -{ - return REG16(STM32_OPTB_BASE + offset); -} - -/** - * Write an option byte word. - * - * Requires OPT_LOCK unlocked. - */ -static void write_optb(int offset, uint16_t value) -{ - REG32(STM32_OPTB_BASE + offset) = - (uint32_t)value | ((uint32_t)(~value) << 16); -} - -/** - * Read the at-boot protection option bits. - */ -static uint32_t read_optb_wrp(void) -{ - return read_optb(STM32_OPTB_WRP1L) | - ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); -} - -/** - * Write the at-boot protection option bits. - */ -static void write_optb_wrp(uint32_t value) -{ - write_optb(STM32_OPTB_WRP1L, (uint16_t)value); - write_optb(STM32_OPTB_WRP1H, value >> 16); -} - -/** - * Write data to flash. - * - * This function lives in internal RAM, as we cannot read flash during writing. - * You must not call other functions from this one or declare it static. - */ -void __attribute__((section(".iram.text"))) - iram_flash_write(uint32_t *addr, uint32_t *data) -{ - int i; - - /* Wait for ready */ - for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop); i++) - ; - - /* Set PROG and FPRG bits */ - STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG; - - /* Send words for the half page */ - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); i++) - *addr++ = *data++; - - /* Wait for writes to complete */ - for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop); - i++) - ; - - /* Disable PROG and FPRG bits */ - STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG); -} - -int flash_physical_write(int offset, int size, const char *data) -{ - uint32_t *data32 = (uint32_t *)data; - uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int res = EC_SUCCESS; - int word_mode = 0; - int i; - - /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size | (uint32_t)(uintptr_t)data) & 3) - return EC_ERROR_INVAL; - - /* Unlock program area */ - res = unlock(STM32_FLASH_PECR_PRG_LOCK); - if (res) - goto exit_wr; - - /* Clear previous error status */ - STM32_FLASH_SR = 0xf00; - - /* - * If offset and size aren't on word boundaries, do word writes. This - * is slower, but since we claim to the outside world that writes must - * be half-page size, the only code which hits this path is writing - * pstate (which is just writing one word). - */ - if ((offset | size) & (CONFIG_FLASH_WRITE_SIZE - 1)) - word_mode = 1; - - /* Update flash timeout based on current clock speed */ - flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) / - CYCLE_PER_FLASH_LOOP; - - while (size > 0) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing with interrupt disabled. - */ - watchdog_reload(); - - if (word_mode) { - /* Word write */ - *address++ = *data32++; - - /* Wait for writes to complete */ - for (i = 0; ((STM32_FLASH_SR & 9) != 8) && - (i < flash_timeout_loop); i++) - ; - - size -= sizeof(uint32_t); - } else { - /* Half page write */ - interrupt_disable(); - iram_flash_write(address, data32); - interrupt_enable(); - address += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); - data32 += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); - size -= CONFIG_FLASH_WRITE_SIZE; - } - - if (STM32_FLASH_SR & 1) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* - * Check for error conditions: erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & 0xf00) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Relock program lock */ - lock(); - - return res; -} - -int flash_physical_erase(int offset, int size) -{ - uint32_t *address; - int res = EC_SUCCESS; - - res = unlock(STM32_FLASH_PECR_PRG_LOCK); - if (res) - return res; - - /* Clear previous error status */ - STM32_FLASH_SR = 0xf00; - - /* Set PROG and ERASE bits */ - STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE; - - for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { - timestamp_t deadline; - - /* Do nothing if already erased */ - if (flash_is_erased((uint32_t)address - - CONFIG_PROGRAM_MEMORY_BASE, - CONFIG_FLASH_ERASE_SIZE)) - continue; - - /* Start erase */ - *address = 0x00000000; - - /* - * Reload the watchdog timer to avoid watchdog reset during - * multi-page erase operations. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_TIMEOUT_MS * MSEC; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR & 1) && - (get_time().val < deadline.val)) { - usleep(300); - } - if (STM32_FLASH_SR & 1) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions: erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & 0xF00) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* Disable program and erase, and relock PECR */ - STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE); - lock(); - - return res; -} - -int flash_physical_get_protect(int block) -{ - /* - * If the entire flash interface is locked, then all blocks are - * protected until reboot. - */ - if (flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW) - return 1; - - /* Check the active write protect status */ - return STM32_FLASH_WRPR & BIT(block); -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - uint32_t prot; - uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; - int rv; - - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - return EC_ERROR_UNIMPLEMENTED; - - /* Read the current protection status */ - prot = read_optb_wrp(); - - /* Set/clear bits */ - if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) - prot |= mask; - else - prot &= ~mask; - - if (prot == read_optb_wrp()) - return EC_SUCCESS; /* No bits changed */ - - /* Unlock option bytes */ - rv = unlock(STM32_FLASH_PECR_OPT_LOCK); - if (rv) - return rv; - - /* Update them */ - write_optb_wrp(prot); - - /* Relock */ - lock(); - - return EC_SUCCESS; -} - -int flash_physical_force_reload(void) -{ - int rv = unlock(STM32_FLASH_PECR_OPT_LOCK); - - if (rv) - return rv; - - /* Force a reboot; this should never return. */ - STM32_FLASH_PECR = STM32_FLASH_PECR_OBL_LAUNCH; - while (1) - ; - - return EC_ERROR_UNKNOWN; -} - -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - /* - * Try to unlock PECR; if that fails, then all flash is protected for - * the current boot. - */ - if (unlock(STM32_FLASH_PECR_PE_LOCK)) - flags |= EC_FLASH_PROTECT_ALL_NOW; - lock(); - - return flags; -} - -int flash_physical_protect_now(int all) -{ - if (all) { - /* Re-lock the registers if they're unlocked */ - lock(); - - /* Prevent unlocking until reboot */ - ignore_bus_fault(1); - STM32_FLASH_PEKEYR = 0; - ignore_bus_fault(0); - - return EC_SUCCESS; - } else { - /* No way to protect just the RO flash until next boot */ - return EC_ERROR_INVAL; - } -} - -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = flash_get_protect(); - int need_reset = 0; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (prot_flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - */ - flash_protect_at_boot(prot_flags & - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT)) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unlock(STM32_FLASH_PECR_OPT_LOCK); - write_optb_wrp(0); - lock(); - need_reset = 1; - } - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/flash-stm32l4.c b/chip/stm32/flash-stm32l4.c deleted file mode 100644 index c138780d34..0000000000 --- a/chip/stm32/flash-stm32l4.c +++ /dev/null @@ -1,531 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Flash memory module for STM32L4 family */ - -#include "common.h" -#include "clock.h" -#include "flash.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_TIMEOUT_US 48000 - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int wait_while_busy(void) -{ - int timeout = calculate_flash_timeout(); - - while (STM32_FLASH_SR & FLASH_SR_BUSY && timeout-- > 0) - ; - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* unlock CR if needed */ - if (STM32_FLASH_CR & FLASH_CR_LOCK) { - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; - } - /* unlock option memory if required */ - if ((locks & FLASH_CR_OPTLOCK) && - (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; - } - - /* Re-enable bus fault handler */ - ignore_bus_fault(0); - - return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static void lock(void) -{ - STM32_FLASH_CR = FLASH_CR_LOCK; -} - -/* - * Option byte organization - * - * [63:56][55:48][47:40][39:32] [31:24][23:16][15: 8][ 7: 0] - * +--------------+-------------------+------+ +-------------------+------+ - * | 0x1FFF7800 | nUSER | nRDP | | USER | RDP | - * +--------------+------------+------+------+ +------------+------+------+ - * | 0x1FFF7808 | | nPCROP1_STRT| | | PCROP1_STRT | - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7810 | | nPCROP1_END | | | PCROP1_END | - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7818 | |nWRP1A| |nWRP1A| | | WRP1A| | WRP1A| - * | | |_END | |_STRT | | | _END | | _STRT| - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7820 | |nWRP1B| |nWRP1B| | | WRP1B| | WRP1B| - * | | |_END | |_STRT | | | _END | | _STRT| - * +--------------+------------+-------------+ +------------+-------------+ - * - * Note that the variable with n prefix means the complement. - */ -static int unlock_optb(void) -{ - int rv; - - rv = wait_while_busy(); - if (rv) - return rv; - - rv = unlock(FLASH_CR_OPTLOCK); - if (rv) - return rv; - - return EC_SUCCESS; -} - -static int commit_optb(void) -{ - int rv; - - STM32_FLASH_CR |= FLASH_CR_OPTSTRT; - - rv = wait_while_busy(); - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} - -static void unprotect_all_blocks(void) -{ - unlock_optb(); - STM32_FLASH_WRP1AR = FLASH_WRP_RANGE_DISABLED; - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE_DISABLED; - commit_optb(); -} - -int flash_physical_protect_at_boot(uint32_t new_flags) -{ - uint32_t ro_range = FLASH_WRP_RANGE_DISABLED; - uint32_t rb_rw_range = FLASH_WRP_RANGE_DISABLED; - /* - * WRP1AR is storing the write-protection range for the RO region. - * WRP1BR is storing the write-protection range for the - * rollback and RW regions. - */ - if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_RO_AT_BOOT)) - ro_range = FLASH_WRP_RANGE(WP_BANK_OFFSET, - WP_BANK_OFFSET + WP_BANK_COUNT); - - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) { - rb_rw_range = FLASH_WRP_RANGE(WP_BANK_OFFSET + WP_BANK_COUNT, - PHYSICAL_BANKS); - } else { - uint8_t strt = WP_BANK_OFFSET + WP_BANK_COUNT; - uint8_t end = FLASH_WRP_END(FLASH_WRP_RANGE_DISABLED); -#ifdef CONFIG_ROLLBACK - if (new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) { - strt = ROLLBACK_BANK_OFFSET; - end = ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT; - } else { - strt = ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT; - } -#endif /* !CONFIG_ROLLBACK */ -#ifdef CONFIG_FLASH_PROTECT_RW - if (new_flags & EC_FLASH_PROTECT_RW_AT_BOOT) - end = PHYSICAL_BANKS; -#endif /* CONFIG_FLASH_PROTECT_RW */ - - if (end != FLASH_WRP_END(FLASH_WRP_RANGE_DISABLED)) - rb_rw_range = FLASH_WRP_RANGE(strt, end); - } - - unlock_optb(); -#ifdef CONFIG_FLASH_READOUT_PROTECTION - /* - * Set a permanent protection by increasing RDP to level 1, - * trying to unprotected the flash will trigger a full erase. - */ - STM32_FLASH_OPTR = (STM32_FLASH_OPTR & ~0xff) | 0x11; -#endif - STM32_FLASH_WRP1AR = ro_range; - STM32_FLASH_WRP1BR = rb_rw_range; - commit_optb(); - - return EC_SUCCESS; -} - -/** - * Check if write protect register state is inconsistent with RO_AT_BOOT and - * ALL_AT_BOOT state. - * - * @return zero if consistent, non-zero if inconsistent. - */ -static int registers_need_reset(void) -{ - uint32_t flags = flash_get_protect(); - int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0; - /* - * The RO region is write-protected by the WRP1AR range, - * it starts at page WP_BANK_OFFSET for WP_BANK_COUNT pages. - */ - uint32_t wrp1ar = STM32_OPTB_WRP1AR; - uint32_t ro_range = ro_at_boot ? - FLASH_WRP_RANGE(WP_BANK_OFFSET, WP_BANK_OFFSET + WP_BANK_COUNT) - : FLASH_WRP_RANGE_DISABLED; - - return ro_range != (wrp1ar & FLASH_WRP_MASK); -} - -/*****************************************************************************/ -/* Physical layer APIs */ - -int flash_physical_write(int offset, int size, const char *data) -{ - uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int res = EC_SUCCESS; - int timeout = calculate_flash_timeout(); - int i; - int unaligned = (uint32_t)data & (CONFIG_FLASH_WRITE_SIZE - 1); - uint32_t *data32 = (void *)data; - - if (unlock(FLASH_CR_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ERR_MASK; - - /* set PG bit */ - STM32_FLASH_CR |= FLASH_CR_PG; - - for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing. - */ - watchdog_reload(); - - /* wait to be ready */ - for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); - i++) - ; - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* write the 2 words */ - if (unaligned) { - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - *address++ = (uint32_t)data[4] | (data[5] << 8) - | (data[6] << 16) | (data[7] << 24); - data += CONFIG_FLASH_WRITE_SIZE; - } else { - *address++ = *data32++; - *address++ = *data32++; - } - - /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); - i++) - ; - - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error. - */ - if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR &= ~FLASH_CR_PG; - - lock(); - - return res; -} - -int flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int pg; - int last; - - if (unlock(FLASH_CR_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ERR_MASK; - - last = (offset + size) / CONFIG_FLASH_ERASE_SIZE; - for (pg = offset / CONFIG_FLASH_ERASE_SIZE; pg < last; pg++) { - timestamp_t deadline; - - /* select page to erase and PER bit */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) - | FLASH_CR_PER | FLASH_CR_PNB(pg); - - /* set STRT bit : start erase */ - STM32_FLASH_CR |= FLASH_CR_STRT; - - /* - * Reload the watchdog timer to avoid watchdog reset during a - * long erase operation. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_TIMEOUT_US; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - usleep(300); - } - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* reset PER bit */ - STM32_FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PNB_MASK); - - lock(); - - return res; -} - -int flash_physical_get_protect(int block) -{ - uint32_t wrp1ar = STM32_FLASH_WRP1AR; - uint32_t wrp1br = STM32_FLASH_WRP1BR; - - return ((block >= FLASH_WRP_START(wrp1ar)) && - (block < FLASH_WRP_END(wrp1ar))) || - ((block >= FLASH_WRP_START(wrp1br)) && - (block < FLASH_WRP_END(wrp1br))); -} - -/* - * Note: This does not need to update _NOW flags, as get_protect_flags - * in common code already does so. - */ -uint32_t flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - uint32_t wrp1ar = STM32_OPTB_WRP1AR; - uint32_t wrp1br = STM32_OPTB_WRP1BR; - - /* RO region protection range is in WRP1AR range */ - if (wrp1ar == FLASH_WRP_RANGE(WP_BANK_OFFSET, - WP_BANK_OFFSET + WP_BANK_COUNT)) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; - /* Rollback and RW regions protection range is in WRP1BR range */ - if (wrp1br != FLASH_WRP_RANGE_DISABLED) { - int end = FLASH_WRP_END(wrp1br); - int strt = FLASH_WRP_START(wrp1br); - -#ifdef CONFIG_ROLLBACK - if (strt <= ROLLBACK_BANK_OFFSET && - end >= ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - flags |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif /* CONFIG_ROLLBACK */ -#ifdef CONFIG_FLASH_PROTECT_RW - if (end == PHYSICAL_BANKS) - flags |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif /* CONFIG_FLASH_PROTECT_RW */ - if (end == PHYSICAL_BANKS && - strt == WP_BANK_OFFSET + WP_BANK_COUNT && - flags & EC_FLASH_PROTECT_RO_AT_BOOT) - flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; - } - - return flags; -} - -int flash_physical_protect_now(int all) -{ - return EC_ERROR_INVAL; -} - -uint32_t flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | -#ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | -#endif -#ifdef CONFIG_ROLLBACK - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_ROLLBACK_NOW | -#endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * ALL/RW at-boot state can be set if WP GPIO is asserted and can always - * be cleared. - */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; - -#ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - -#ifdef CONFIG_ROLLBACK - if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif - - return ret; -} - -int flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = flash_get_protect(); - int need_reset = 0; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - flash_physical_protect_at_boot( - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (registers_need_reset()) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - * - * TODO(crosbug.com/p/23798): this seems really similar - * to the check above. One of them should be able to - * go away. - */ - flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else { - if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unprotect_all_blocks(); - need_reset = 1; - } - } - - if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_ALL_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { - /* - * ALL_AT_BOOT and ALL_NOW should be both set or both unset - * at boot. If they are not, it must be that the chip requires - * OBL_LAUNCH to be set to reload option bytes. Let's reset - * the system with OBL_LAUNCH set. - * This assumes OBL_LAUNCH is used for hard reset in - * chip/stm32/system.c. - */ - need_reset = 1; - } - -#ifdef CONFIG_FLASH_PROTECT_RW - if ((flash_physical_get_valid_flags() & EC_FLASH_PROTECT_RW_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { - /* RW_AT_BOOT and RW_NOW do not match. */ - need_reset = 1; - } -#endif - -#ifdef CONFIG_ROLLBACK - if ((flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { - /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ - need_reset = 1; - } -#endif - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c deleted file mode 100644 index 55628cb6d4..0000000000 --- a/chip/stm32/gpio-f0-l.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * GPIO module for Chrome EC - * - * These functions are shared by the STM32F0 and STM32L variants. - */ - -#include "common.h" -#include "gpio_chip.h" -#include "registers.h" -#include "util.h" - -static uint32_t expand_to_2bit_mask(uint32_t mask) -{ - uint32_t mask_out = 0; - while (mask) { - int bit = get_next_bit(&mask); - mask_out |= 3 << (bit * 2); - } - return mask_out; -} - -int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) -{ - uint32_t flags = 0; - uint32_t val = 0; - const uint32_t mask2 = expand_to_2bit_mask(mask); - - /* Only one bit must be set. */ - if ((mask != (mask & -mask)) || (mask == 0)) - return 0; - - /* Check output type. */ - val = STM32_GPIO_PUPDR(port) & mask2; - if (val == (0x55555555 & mask2)) - flags |= GPIO_PULL_UP; - if (val == (0xaaaaaaaa & mask2)) - flags |= GPIO_PULL_DOWN; - - if (STM32_GPIO_OTYPER(port) & mask) - flags |= GPIO_OPEN_DRAIN; - - /* Check mode. */ - val = STM32_GPIO_MODER(port) & mask2; - if (val == (0x55555555 & mask2)) - flags |= GPIO_OUTPUT; - if (val == (0xFFFFFFFF & mask2)) - flags |= GPIO_ANALOG; - if (val == (0x0 & mask2)) - flags |= GPIO_INPUT; - if (val == (0xaaaaaaaa & mask2)) - flags |= GPIO_ALTERNATE; - - if (flags & GPIO_OUTPUT) { - if (STM32_GPIO_ODR(port) & mask) - flags |= GPIO_HIGH; - else - flags |= GPIO_LOW; - } - - - if (STM32_EXTI_RTSR & mask) - flags |= GPIO_INT_F_RISING; - if (STM32_EXTI_RTSR & mask) - flags |= GPIO_INT_F_RISING; - - return flags; -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - /* Bitmask for registers with 2 bits per GPIO pin */ - const uint32_t mask2 = expand_to_2bit_mask(mask); - uint32_t val; - - /* Set up pullup / pulldown */ - val = STM32_GPIO_PUPDR(port) & ~mask2; - if (flags & GPIO_PULL_UP) - val |= 0x55555555 & mask2; /* Pull Up = 01 */ - else if (flags & GPIO_PULL_DOWN) - val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ - STM32_GPIO_PUPDR(port) = val; - - /* - * Select open drain first, so that we don't glitch the signal when - * changing the line to an output. - */ - if (flags & GPIO_OPEN_DRAIN) - STM32_GPIO_OTYPER(port) |= mask; - else - STM32_GPIO_OTYPER(port) &= ~mask; - - val = STM32_GPIO_MODER(port) & ~mask2; - if (flags & GPIO_OUTPUT) { - /* - * Set pin level first to avoid glitching. This is harmless on - * STM32L because the set/reset register isn't connected to the - * output drivers until the pin is made an output. - */ - if (flags & GPIO_HIGH) - STM32_GPIO_BSRR(port) = mask; - else if (flags & GPIO_LOW) - STM32_GPIO_BSRR(port) = mask << 16; - - /* General purpose, MODE = 01 */ - val |= 0x55555555 & mask2; - STM32_GPIO_MODER(port) = val; - - } else if (flags & GPIO_ANALOG) { - /* Analog, MODE=11 */ - val |= 0xFFFFFFFF & mask2; - STM32_GPIO_MODER(port) = val; - } else if (flags & GPIO_INPUT) { - /* Input, MODE=00 */ - STM32_GPIO_MODER(port) = val; - } else if (flags & GPIO_ALTERNATE) { - /* Alternate, MODE=10 */ - val |= 0xaaaaaaaa & mask2; - STM32_GPIO_MODER(port) = val; - } - - /* Set up interrupts if necessary */ - ASSERT(!(flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))); - if (flags & GPIO_INT_F_RISING) - STM32_EXTI_RTSR |= mask; - if (flags & GPIO_INT_F_FALLING) - STM32_EXTI_FTSR |= mask; - /* Interrupt is enabled by gpio_enable_interrupt() */ -} - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - /* Ensure that the func parameter isn't overflowed */ - BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX); - - int bit; - uint32_t half; - uint32_t afr; - uint32_t moder = STM32_GPIO_MODER(port); - - if (func == GPIO_ALT_FUNC_NONE) { - /* Return to normal GPIO function, defaulting to input. */ - while (mask) { - bit = get_next_bit(&mask); - moder &= ~(0x3 << (bit * 2)); - } - STM32_GPIO_MODER(port) = moder; - return; - } - - /* Low half of the GPIO bank */ - half = mask & 0xff; - afr = STM32_GPIO_AFRL(port); - while (half) { - bit = get_next_bit(&half); - afr &= ~(0xf << (bit * 4)); - afr |= func << (bit * 4); - moder &= ~(0x3 << (bit * 2 + 0)); - moder |= 0x2 << (bit * 2 + 0); - } - STM32_GPIO_AFRL(port) = afr; - - /* High half of the GPIO bank */ - half = (mask >> 8) & 0xff; - afr = STM32_GPIO_AFRH(port); - while (half) { - bit = get_next_bit(&half); - afr &= ~(0xf << (bit * 4)); - afr |= func << (bit * 4); - moder &= ~(0x3 << (bit * 2 + 16)); - moder |= 0x2 << (bit * 2 + 16); - } - STM32_GPIO_AFRH(port) = afr; - STM32_GPIO_MODER(port) = moder; -} diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c deleted file mode 100644 index d7e7aa4391..0000000000 --- a/chip/stm32/gpio-stm32f0.c +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x7e0000; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0_1); - task_enable_irq(STM32_IRQ_EXTI2_3); - task_enable_irq(STM32_IRQ_EXTI4_15); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c deleted file mode 100644 index bfc2631de8..0000000000 --- a/chip/stm32/gpio-stm32f3.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x7e0000; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c deleted file mode 100644 index 4a4e095a71..0000000000 --- a/chip/stm32/gpio-stm32f4.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -int gpio_required_clocks(void) -{ - const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" - ); - - /* - * If no ports are in use, then system_is_reboot_warm - * may not be valid. - */ - ASSERT(gpio_ports_used); - - return gpio_ports_used; -} - -void gpio_enable_clocks(void) -{ - /* Enable only ports that are referenced in the gpio.inc */ - STM32_RCC_AHB1ENR |= gpio_required_clocks(); - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c deleted file mode 100644 index a2fb97225d..0000000000 --- a/chip/stm32/gpio-stm32h7.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* Enable all GPIOs clocks */ - STM32_RCC_AHB4ENR |= STM32_RCC_AHB4ENR_GPIOMASK; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); - -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c deleted file mode 100644 index 52c424eea0..0000000000 --- a/chip/stm32/gpio-stm32l.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x3f; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c deleted file mode 100644 index b5c4940454..0000000000 --- a/chip/stm32/gpio-stm32l4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); - -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c deleted file mode 100644 index bb45f0e388..0000000000 --- a/chip/stm32/gpio.c +++ /dev/null @@ -1,175 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio_chip.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -/* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) -/* For each EXTI bit, record which GPIO entry is using it */ -static uint8_t exti_events[16]; - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - const struct unused_pin_info *u = unused_pin_list; - int is_warm = system_is_reboot_warm(); - int i; - - /* Required to configure external IRQ lines (SYSCFG_EXTICRn) */ -#ifdef CHIP_FAMILY_STM32H7 - STM32_RCC_APB4ENR |= STM32_RCC_SYSCFGEN; -#else - STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN; -#endif - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* Disable all GPIO EXTINTs (EXTINT0..15) left enabled after sysjump. */ - STM32_EXTI_IMR &= ~0xFFFF; - - if (!is_warm) - gpio_enable_clocks(); - - /* Set all GPIOs to defaults */ - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - /* Set up GPIO based on flags */ - gpio_set_flags_by_mask(g->port, g->mask, flags); - } - - /* Configure optional unused pins for low power optimization. */ - for (i = 0; i < unused_pin_count; i++, u++) { - /* - * Configure unused pins as ANALOG INPUT to save power. - * For more info, please see - * "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY" - * ("AN4365") section 1.2.6 and section 7.3.12 of the STM32F412 - * reference manual. - */ - if (IS_ENABLED(CHIP_FAMILY_STM32F4)) - gpio_set_flags_by_mask(u->port, u->mask, GPIO_ANALOG); - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return !!(STM32_GPIO_IDR(gpio_list[signal].port) & - gpio_list[signal].mask); -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - STM32_GPIO_BSRR(gpio_list[signal].port) = - gpio_list[signal].mask << (value ? 0 : 16); -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - const struct gpio_info *g_old = gpio_list; - - uint32_t bit, group, shift, bank; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - bit = GPIO_MASK_TO_NUM(g->mask); - - g_old += exti_events[bit]; - - if ((exti_events[bit]) && (exti_events[bit] != signal)) { - CPRINTS("Overriding %s with %s on EXTI%d", - g_old->name, g->name, bit); - } - exti_events[bit] = signal; - - group = bit / 4; - shift = (bit % 4) * 4; - bank = (g->port - STM32_GPIOA_BASE) / 0x400; - - STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) & - ~(0xF << shift)) | (bank << shift); - STM32_EXTI_IMR |= g->mask; - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - uint32_t bit; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - STM32_EXTI_IMR &= ~g->mask; - - bit = GPIO_MASK_TO_NUM(g->mask); - - exti_events[bit] = 0; - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - STM32_EXTI_PR |= g->mask; - - return EC_SUCCESS; -} - -/*****************************************************************************/ -/* Interrupt handler */ - -void __keep gpio_interrupt(void) -{ - int bit; - /* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */ - uint32_t pending = STM32_EXTI_PR & 0xFFFF; - uint8_t signal; - - STM32_EXTI_PR = pending; - - while (pending) { - bit = get_next_bit(&pending); - signal = exti_events[bit]; - if (signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } -} -#ifdef CHIP_FAMILY_STM32F0 -DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY); -DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY); -DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY); -#endif diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h deleted file mode 100644 index a5b642fb05..0000000000 --- a/chip/stm32/gpio_chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CHIP_STM32_GPIO_CHIP_H -#define __CROS_EC_CHIP_STM32_GPIO_CHIP_H - -#include "include/gpio.h" - -/** - * Enable GPIO peripheral clocks. - */ -void gpio_enable_clocks(void); - -/** - * Return gpio port clocks that are necessary to support - * the pins in gpio.inc. - */ -int gpio_required_clocks(void); - -#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c deleted file mode 100644 index 02ebaf0355..0000000000 --- a/chip/stm32/hwtimer.c +++ /dev/null @@ -1,454 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -/* - * Trigger select mapping for slave timer from master timer. This is - * unfortunately not very straightforward; there's no tidy way to do this - * algorithmically. To avoid burning memory for a lookup table, use macros to - * compute the offset. This also has the benefit that compilation will fail if - * an unsupported master/slave pairing is used. - */ -#ifdef CHIP_FAMILY_STM32F0 -/* - * Slave Master - * 1 15 2 3 17 - * 2 1 15 3 14 - * 3 1 2 15 14 - * 15 2 3 16 17 - * -------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_1_MASTER_15 0 -#define STM32_TIM_TS_SLAVE_1_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_1_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_1_MASTER_17 3 -#define STM32_TIM_TS_SLAVE_2_MASTER_1 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_15 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_1 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_15 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_15_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_15_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_15_MASTER_16 2 -#define STM32_TIM_TS_SLAVE_15_MASTER_17 3 -#elif defined(CHIP_FAMILY_STM32F3) -/* - * Slave Master - * 2 19 15 3 14 - * 3 19 2 5 14 - * 4 19 2 3 15 - * 5 2 3 4 15 - * 12 4 5 13 14 - * 19 2 3 15 16 - * --------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_2_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_15 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_5 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_4_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_4_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_4_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_4_MASTER_15 3 -#define STM32_TIM_TS_SLAVE_5_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_5_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_5_MASTER_4 2 -#define STM32_TIM_TS_SLAVE_5_MASTER_15 3 -#define STM32_TIM_TS_SLAVE_12_MASTER_4 0 -#define STM32_TIM_TS_SLAVE_12_MASTER_5 1 -#define STM32_TIM_TS_SLAVE_12_MASTER_13 2 -#define STM32_TIM_TS_SLAVE_12_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_19_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_19_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_19_MASTER_15 2 -#define STM32_TIM_TS_SLAVE_19_MASTER_16 3 -#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ -/* - * Slave Master - * 1 15 2 3 4 (STM32F100 only) - * 2 9 10 3 4 - * 3 9 2 11 4 - * 4 10 2 3 9 - * 9 2 3 10 11 (STM32L15x only) - * -------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_1_MASTER_15 0 -#define STM32_TIM_TS_SLAVE_1_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_1_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_1_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_2_MASTER_9 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_10 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_9 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_11 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_4_MASTER_10 0 -#define STM32_TIM_TS_SLAVE_4_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_4_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_4_MASTER_9 3 -#define STM32_TIM_TS_SLAVE_9_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_9_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_9_MASTER_10 2 -#define STM32_TIM_TS_SLAVE_9_MASTER_11 3 -#endif /* !CHIP_FAMILY_STM32F0 */ -#define TSMAP(slave, master) \ - CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master) - -/* - * Timers are defined per board. This gives us flexibility to work around - * timers which are dedicated to board-specific PWM sources. - */ -#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) -#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) -#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) - -/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ -#if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1) -#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_BRK_UP_TRG -#else /* !(TIM_WATCHDOG == 1) */ -#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_CC -#endif /* !(TIM_WATCHDOG == 1) */ - -#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) -#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG) - -static uint32_t last_deadline; - -void __hw_clock_event_set(uint32_t deadline) -{ - last_deadline = deadline; - - if ((deadline >> 16) > STM32_TIM_CNT(TIM_CLOCK_MSB)) { - /* first set a match on the MSB */ - STM32_TIM_CCR1(TIM_CLOCK_MSB) = deadline >> 16; - /* disable LSB match */ - STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK_MSB) = ~2; - STM32_TIM_SR(TIM_CLOCK_LSB) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK_MSB) |= 2; - } - /* - * In the unlikely case where the MSB has increased and matched - * the deadline MSB before we set the match interrupt, as the STM - * hardware timer won't trigger an interrupt, we fall back to the - * following LSB event code to set another interrupt. - */ - if ((deadline >> 16) == STM32_TIM_CNT(TIM_CLOCK_MSB)) { - /* we can set a match on the LSB only */ - STM32_TIM_CCR1(TIM_CLOCK_LSB) = deadline & 0xffff; - /* disable MSB match */ - STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK_MSB) = ~2; - STM32_TIM_SR(TIM_CLOCK_LSB) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK_LSB) |= 2; - } - /* - * If the LSB deadline is already in the past and won't trigger an - * interrupt, the common code in process_timers will deal with the - * expired timer and automatically set the next deadline, we don't need - * to do anything here. - */ -} - -uint32_t __hw_clock_event_get(void) -{ - return last_deadline; -} - -void __hw_clock_event_clear(void) -{ - /* Disable the match interrupts */ - STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2; - STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2; -} - -uint32_t __hw_clock_source_read(void) -{ - uint32_t hi; - uint32_t lo; - - /* Ensure the two half-words are coherent */ - do { - hi = STM32_TIM_CNT(TIM_CLOCK_MSB); - lo = STM32_TIM_CNT(TIM_CLOCK_LSB); - } while (hi != STM32_TIM_CNT(TIM_CLOCK_MSB)); - - return (hi << 16) | lo; -} - -void __hw_clock_source_set(uint32_t ts) -{ - STM32_TIM_CNT(TIM_CLOCK_MSB) = ts >> 16; - STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff; -} - -void __hw_clock_source_irq(void) -{ - uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB); - - /* Clear status */ - STM32_TIM_SR(TIM_CLOCK_LSB) = 0; - STM32_TIM_SR(TIM_CLOCK_MSB) = 0; - - /* - * Find expired timers and set the new timer deadline - * signal overflow if the 16-bit MSB counter has overflowed. - */ - process_timers(stat_tim_msb & 0x01); -} -DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1); -DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1); - -void __hw_timer_enable_clock(int n, int enable) -{ - volatile uint32_t *reg; - uint32_t mask = 0; - - /* - * Mapping of timers to reg/mask is split into a few different ranges, - * some specific to individual chips. - */ -#if defined(CHIP_FAMILY_STM32F0) - if (n == 1) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM1; - } -#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - if (n >= 9 && n <= 11) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM9 << (n - 9); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) - if (n >= 15 && n <= 17) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM15 << (n - 15); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - if (n == 14) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM14; - } -#endif - -#if defined(CHIP_FAMILY_STM32F3) - if (n == 12 || n == 13) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM12 << (n - 12); - } - if (n == 18) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM18; - } - if (n == 19) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM19; - } -#endif - - if (n >= 2 && n <= 7) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM2 << (n - 2); - } - - if (!mask) - return; - - if (enable) - *reg |= mask; - else - *reg &= ~mask; -} - -static void update_prescaler(void) -{ - /* - * Pre-scaler value : - * TIM_CLOCK_LSB is counting microseconds; - * TIM_CLOCK_MSB is counting every TIM_CLOCK_LSB overflow. - * - * This will take effect at the next update event (when the current - * prescaler counter ticks down, or if forced via EGR). - */ - STM32_TIM_PSC(TIM_CLOCK_MSB) = 0; - STM32_TIM_PSC(TIM_CLOCK_LSB) = (clock_get_timer_freq() / SECOND) - 1; -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); - -int __hw_clock_source_init(uint32_t start_t) -{ - /* - * we use 2 chained 16-bit counters to emulate a 32-bit one : - * TIM_CLOCK_MSB is the MSB (Slave) - * TIM_CLOCK_LSB is the LSB (Master) - */ - - /* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */ - __hw_timer_enable_clock(TIM_CLOCK_MSB, 1); - __hw_timer_enable_clock(TIM_CLOCK_LSB, 1); - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Upcounter, counter disabled, update event only - * on overflow. - */ - STM32_TIM_CR1(TIM_CLOCK_MSB) = 0x0004; - STM32_TIM_CR1(TIM_CLOCK_LSB) = 0x0004; - /* - * TIM_CLOCK_LSB (master mode) generates a periodic trigger signal on - * each UEV - */ - STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000; - STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020; - - STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | - (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); - STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000; - - /* Auto-reload value : 16-bit free-running counters */ - STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff; - STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff; - - /* Update prescaler */ - update_prescaler(); - - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_CLOCK_MSB) = 0x0001; - STM32_TIM_EGR(TIM_CLOCK_LSB) = 0x0001; - - /* Set up the overflow interrupt on TIM_CLOCK_MSB */ - STM32_TIM_DIER(TIM_CLOCK_MSB) = 0x0001; - STM32_TIM_DIER(TIM_CLOCK_LSB) = 0x0000; - - /* Start counting */ - STM32_TIM_CR1(TIM_CLOCK_MSB) |= 1; - STM32_TIM_CR1(TIM_CLOCK_LSB) |= 1; - - /* Override the count with the start value now that counting has - * started. */ - __hw_clock_source_set(start_t); - - /* Enable timer interrupts */ - task_enable_irq(IRQ_MSB); - task_enable_irq(IRQ_LSB); - - return IRQ_LSB; -} - -#ifdef CONFIG_WATCHDOG_HELP - -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - /* clear status */ - timer->sr = 0; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked)); -void IRQ_HANDLER(IRQ_WD)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0,pc}\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ - -void hwtimer_setup_watchdog(void) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - /* Enable clock */ - __hw_timer_enable_clock(TIM_WATCHDOG, 1); - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Down counter, counter disabled, update - * event only on overflow. - */ - timer->cr1 = 0x0014 | BIT(7); - - /* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */ - timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4); - - /* - * The auto-reload value is based on the period between rollovers for - * TIM_CLOCK_LSB. Since TIM_CLOCK_LSB runs at 1MHz, it will overflow - * in 65.536ms. We divide our required watchdog period by this amount - * to obtain the number of times TIM_CLOCK_LSB can overflow before we - * generate an interrupt. - */ - timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16); - - /* count on every TIM_CLOCK_LSB overflow */ - timer->psc = 0; - - /* Reload the pre-scaler from arr when it goes below zero */ - timer->egr = 0x0000; - - /* setup the overflow interrupt */ - timer->dier = 0x0001; - - /* Start counting */ - timer->cr1 |= 1; - - /* Enable timer interrupts */ - task_enable_irq(IRQ_WD); -} - -void hwtimer_reset_watchdog(void) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - timer->cnt = timer->arr; -} - -#endif /* defined(CONFIG_WATCHDOG) */ diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c deleted file mode 100644 index a2e6ab8f42..0000000000 --- a/chip/stm32/hwtimer32.c +++ /dev/null @@ -1,289 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware 32-bit timer driver */ - -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) - -void __hw_clock_event_set(uint32_t deadline) -{ - /* set the match on the deadline */ - STM32_TIM32_CCR1(TIM_CLOCK32) = deadline; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK32) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK32) |= 2; -} - -uint32_t __hw_clock_event_get(void) -{ - return STM32_TIM32_CCR1(TIM_CLOCK32); -} - -void __hw_clock_event_clear(void) -{ - /* Disable the match interrupts */ - STM32_TIM_DIER(TIM_CLOCK32) &= ~2; -} - -uint32_t __hw_clock_source_read(void) -{ - return STM32_TIM32_CNT(TIM_CLOCK32); -} - -void __hw_clock_source_set(uint32_t ts) -{ - STM32_TIM32_CNT(TIM_CLOCK32) = ts; -} - -void __hw_clock_source_irq(void) -{ - uint32_t stat_tim = STM32_TIM_SR(TIM_CLOCK32); - - /* Clear status */ - STM32_TIM_SR(TIM_CLOCK32) = 0; - - /* - * Find expired timers and set the new timer deadline - * signal overflow if the update interrupt flag is set. - */ - process_timers(stat_tim & 0x01); -} -DECLARE_IRQ(IRQ_TIM(TIM_CLOCK32), __hw_clock_source_irq, 1); - -void __hw_timer_enable_clock(int n, int enable) -{ - volatile uint32_t *reg; - uint32_t mask = 0; - - /* - * Mapping of timers to reg/mask is split into a few different ranges, - * some specific to individual chips. - */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) - if (n == 1) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM1; - } -#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - if (n >= 9 && n <= 11) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM9 << (n - 9); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) - if (n >= 15 && n <= 17) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM15 << (n - 15); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ -defined(CHIP_FAMILY_STM32H7) - if (n == 14) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM14; - } -#endif - -#if defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32H7) - if (n == 12 || n == 13) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM12 << (n - 12); - } -#endif -#if defined(CHIP_FAMILY_STM32F3) - if (n == 18) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM18; - } - if (n == 19) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM19; - } -#endif - if (n >= 2 && n <= 7) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM2 << (n - 2); - } - - if (!mask) - return; - - if (enable) - *reg |= mask; - else - *reg &= ~mask; -} - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32H7) -/* for families using a variable clock feeding the timer */ -static void update_prescaler(void) -{ - uint32_t t; - /* - * Pre-scaler value : - * the timer is incrementing every microsecond - */ - STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1; - /* - * Forcing reloading the pre-scaler, - * but try to maintain a sensible time-keeping while triggering - * the update event. - */ - interrupt_disable(); - /* Ignore the next update */ - STM32_TIM_DIER(TIM_CLOCK32) &= ~0x0001; - /* - * prepare to reload the counter with the current value - * to avoid rolling backward the microsecond counter. - */ - t = STM32_TIM32_CNT(TIM_CLOCK32) + 1; - /* issue an update event, reloads the pre-scaler and the counter */ - STM32_TIM_EGR(TIM_CLOCK32) = 0x0001; - /* clear the 'spurious' update unless we were going to roll-over */ - if (t) - STM32_TIM_SR(TIM_CLOCK32) = ~1; - /* restore a sensible time value */ - STM32_TIM32_CNT(TIM_CLOCK32) = t; - /* restore roll-over events */ - STM32_TIM_DIER(TIM_CLOCK32) |= 0x0001; - interrupt_enable(); - -#ifdef CONFIG_WATCHDOG_HELP - /* Watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC)- 1; -#endif /* CONFIG_WATCHDOG_HELP */ -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); -#endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || CHIP_FAMILY_STM32H7 */ - -int __hw_clock_source_init(uint32_t start_t) -{ - /* Enable TIM peripheral block clocks */ - __hw_timer_enable_clock(TIM_CLOCK32, 1); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Upcounter, counter disabled, update event only - * on overflow. - */ - STM32_TIM_CR1(TIM_CLOCK32) = 0x0004; - /* No special configuration */ - STM32_TIM_CR2(TIM_CLOCK32) = 0x0000; - STM32_TIM_SMCR(TIM_CLOCK32) = 0x0000; - - /* Auto-reload value : 32-bit free-running counter */ - STM32_TIM32_ARR(TIM_CLOCK32) = 0xffffffff; - - /* Update prescaler to increment every microsecond */ - STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1; - - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_CLOCK32) = 0x0001; - - /* Set up the overflow interrupt */ - STM32_TIM_DIER(TIM_CLOCK32) = 0x0001; - - /* Start counting */ - STM32_TIM_CR1(TIM_CLOCK32) |= 1; - - /* Override the count with the start value now that counting has - * started. */ - __hw_clock_source_set(start_t); - - /* Enable timer interrupts */ - task_enable_irq(IRQ_TIM(TIM_CLOCK32)); - - return IRQ_TIM(TIM_CLOCK32); -} - -#ifdef CONFIG_WATCHDOG_HELP - -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) - -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - /* clear status */ - STM32_TIM_SR(TIM_WATCHDOG) = 0; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked)); -void IRQ_HANDLER(IRQ_WD)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0,pc}\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ - -void hwtimer_setup_watchdog(void) -{ - /* Enable clock */ - __hw_timer_enable_clock(TIM_WATCHDOG, 1); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Up counter, counter disabled, update - * event only on overflow. - */ - STM32_TIM_CR1(TIM_WATCHDOG) = 0x0004; - /* No special configuration */ - STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000; - STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000; - - /* AUto-reload value */ - STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; - - /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC) - 1; - - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001; - - /* setup the overflow interrupt */ - STM32_TIM_DIER(TIM_WATCHDOG) = 0x0001; - STM32_TIM_SR(TIM_WATCHDOG) = 0; - - /* Start counting */ - STM32_TIM_CR1(TIM_WATCHDOG) |= 1; - - /* Enable timer interrupts */ - task_enable_irq(IRQ_WD); -} - -void hwtimer_reset_watchdog(void) -{ - STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000; -} - -#endif /* CONFIG_WATCHDOG_HELP */ diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c deleted file mode 100644 index a4db7ee456..0000000000 --- a/chip/stm32/i2c-stm32f0.c +++ /dev/null @@ -1,633 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "hwtimer.h" -#include "i2c.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "usb_pd_tcpc.h" -#include "usb_pd_tcpm.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_SLAVE STM32_IRQ_I2C1 -#else -#define IRQ_SLAVE STM32_IRQ_I2C2 -#endif -#endif - - -/* I2C port state data */ -struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER; -} - -/* timingr register values for supported input clks / i2c clk rates */ -static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ -}; - -/** - * Wait for ISR register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_isr(int port, int mask) -{ - uint32_t start = __hw_clock_source_read(); - uint32_t delta = 0; - - do { - int isr = STM32_I2C_ISR(port); - - /* Check for errors */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) - return EC_ERROR_UNKNOWN; - - /* Check for desired mask */ - if ((isr & mask) == mask) - return EC_SUCCESS; - - delta = __hw_clock_source_read() - start; - - /** - * Depending on the bus speed, busy loop for a while before - * sleeping and letting other things run. - */ - if (delta >= busyloop_us[pdata[port].freq]) - usleep(100); - } while (delta < pdata[port].timeout_us); - - return EC_ERROR_TIMEOUT; -} - -/* Supported i2c input clocks */ -enum stm32_i2c_clk_src { - I2C_CLK_SRC_48MHZ = 0, - I2C_CLK_SRC_8MHZ = 1, - I2C_CLK_SRC_COUNT, -}; - -/* timingr register values for supported input clks / i2c clk rates */ -static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { - [I2C_CLK_SRC_48MHZ] = { - [I2C_FREQ_1000KHZ] = 0x50100103, - [I2C_FREQ_400KHZ] = 0x50330609, - [I2C_FREQ_100KHZ] = 0xB0421214, - }, - [I2C_CLK_SRC_8MHZ] = { - [I2C_FREQ_1000KHZ] = 0x00100306, - [I2C_FREQ_400KHZ] = 0x00310309, - [I2C_FREQ_100KHZ] = 0x10420f13, - }, -}; - -static void i2c_set_freq_port(const struct i2c_port_t *p, - enum stm32_i2c_clk_src src, - enum i2c_freq freq) -{ - int port = p->port; - const uint32_t *regs = timingr_regs[src]; - - /* Disable port */ - STM32_I2C_CR1(port) = 0; - STM32_I2C_CR2(port) = 0; - /* Set clock frequency */ - STM32_I2C_TIMINGR(port) = regs[freq]; - /* Enable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; - - pdata[port].freq = freq; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; - enum i2c_freq freq; - - /* Enable clocks to I2C modules if necessary */ - if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) - STM32_RCC_APB1ENR |= 1 << (21 + port); - - if (port == STM32_I2C1_PORT) { -#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) && \ -defined(CONFIG_LOW_POWER_IDLE) && \ -(I2C_PORT_EC == STM32_I2C1_PORT) - /* - * Use HSI (8MHz) for i2c clock. This allows smooth wakeup - * from STOP mode since HSI is only clock running immediately - * upon exit from STOP mode. - */ - STM32_RCC_CFGR3 &= ~0x10; - src = I2C_CLK_SRC_8MHZ; -#else - /* Use SYSCLK for i2c clock. */ - STM32_RCC_CFGR3 |= 0x10; -#endif - } - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set clock frequency */ - switch (p->kbps) { - case 1000: - freq = I2C_FREQ_1000KHZ; - break; - case 400: - freq = I2C_FREQ_400KHZ; - break; - case 100: - freq = I2C_FREQ_100KHZ; - break; - default: /* unknown speed, defaults to 100kBps */ - CPRINTS("I2C bad speed %d kBps", p->kbps); - freq = I2C_FREQ_100KHZ; - } - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p, src, freq); - - /* Set up default timeout */ - i2c_set_timeout(port, 0); -} - -/*****************************************************************************/ -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -/* Host command slave */ -/* - * Buffer for received host command packets (including prefix byte on request, - * and result/size on response). After any protocol-specific headers, the - * buffers must be 32-bit aligned. - */ -static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + - CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; -static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); -static int host_i2c_resp_port; -static int tx_pending; -static int tx_index, tx_end; -static struct host_packet i2c_packet; - -static void i2c_send_response_packet(struct host_packet *pkt) -{ - int size = pkt->response_size; - uint8_t *out = host_buffer; - - /* Ignore host command in-progress */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result and size to first two bytes. */ - *out++ = pkt->driver_result; - *out++ = size; - - /* host_buffer data range */ - tx_index = 0; - tx_end = size + 2; - - /* - * Set the transmitter to be in 'not full' state to keep sending - * '0xec' in the event loop. Because of this, the master i2c - * doesn't need to snoop the response stream to abort transaction. - */ - STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; -} - -/* Process the command in the i2c host buffer */ -static void i2c_process_command(void) -{ - char *buff = host_buffer; - - /* - * TODO(crosbug.com/p/29241): Combine this functionality with the - * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one - * host command i2c process function which handles all protocol - * versions. - */ - i2c_packet.send_response = i2c_send_response_packet; - - i2c_packet.request = (const void *)(&buff[1]); - i2c_packet.request_temp = params_copy; - i2c_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; - - /* - * Stuff response at buff[2] to leave the first two bytes of - * buffer available for the result and size to send over i2c. Note - * that this 2-byte offset and the 2-byte offset from host_buffer - * add up to make the response buffer 32-bit aligned. - */ - i2c_packet.response = (void *)(&buff[2]); - i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; - i2c_packet.response_size = 0; - - if (*buff >= EC_COMMAND_PROTOCOL_3) { - i2c_packet.driver_result = EC_RES_SUCCESS; - } else { - /* Only host command protocol 3 is supported. */ - i2c_packet.driver_result = EC_RES_INVALID_HEADER; - } - host_packet_receive(&i2c_packet); -} - -#ifdef TCPCI_I2C_SLAVE -static void i2c_send_tcpc_response(int len) -{ - /* host_buffer data range, beyond this length, will return 0xec */ - tx_index = 0; - tx_end = len; - - /* enable transmit interrupt and use irq to send data back */ - STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; -} - -static void i2c_process_tcpc_command(int read, int addr, int len) -{ - tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0], - i2c_send_tcpc_response); -} -#endif - -static void i2c_event_handler(int port) -{ - int i2c_isr; - static int rx_pending, buf_idx; -#ifdef TCPCI_I2C_SLAVE - int addr; -#endif - - i2c_isr = STM32_I2C_ISR(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a slave allowing clock - * stretching and in non-SMBus mode. - */ - if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | - STM32_I2C_ICR_ARLOCF; - } - - /* Transfer matched our slave address */ - if (i2c_isr & STM32_I2C_ISR_ADDR) { - if (i2c_isr & STM32_I2C_ISR_DIR) { - /* Transmitter slave */ - /* Clear transmit buffer */ - STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; - - /* Enable txis interrupt to start response */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; - } else { - /* Receiver slave */ - buf_idx = 0; - rx_pending = 1; - } - - /* Clear ADDR bit by writing to ADDRCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; - /* Inhibit sleep mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* Receiver full event */ - if (i2c_isr & STM32_I2C_ISR_RXNE) - host_buffer[buf_idx++] = STM32_I2C_RXDR(port); - - /* Stop condition on bus */ - if (i2c_isr & STM32_I2C_ISR_STOP) { -#ifdef TCPCI_I2C_SLAVE - /* - * if tcpc is being addressed, and we received a stop - * while rx is pending, then this is a write only to - * the tcpc. - */ - addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port)); - if (rx_pending && ADDR_IS_TCPC(addr)) - i2c_process_tcpc_command(0, addr, buf_idx); -#endif - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear STOPF bit by writing to STOPCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* Master requested STOP or RESTART */ - if (i2c_isr & STM32_I2C_ISR_NACK) { - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - /* Clear NACK */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; - /* Resend last byte on RESTART */ - if (port == I2C_PORT_EC && tx_index) - tx_index--; - } - - /* Transmitter empty event */ - if (i2c_isr & STM32_I2C_ISR_TXIS) { - if (port == I2C_PORT_EC) { /* host is waiting for PD response */ - if (tx_pending) { - if (tx_index < tx_end) { - STM32_I2C_TXDR(port) = - host_buffer[tx_index++]; - } else { - STM32_I2C_TXDR(port) = 0xec; - /* - * Set tx_index = 0 to prevent NACK - * handler resending last buffer byte. - */ - tx_index = 0; - tx_end = 0; - /* No pending data */ - tx_pending = 0; - } - } else if (rx_pending) { - host_i2c_resp_port = port; - /* - * Disable TXIS interrupt, transmission will - * be prepared by host command task. - */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - -#ifdef TCPCI_I2C_SLAVE - addr = STM32_I2C_ISR_ADDCODE( - STM32_I2C_ISR(port)); - if (ADDR_IS_TCPC(addr)) - i2c_process_tcpc_command(1, addr, - buf_idx); - else -#endif - i2c_process_command(); - - /* Reset host buffer after end of transfer */ - rx_pending = 0; - tx_pending = 1; - } else { - STM32_I2C_TXDR(port) = 0xec; - } - } - } -} -void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } -DECLARE_IRQ(IRQ_SLAVE, i2c2_event_interrupt, 2); -#endif - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - int rv = EC_SUCCESS; - int i; - int xfer_start = flags & I2C_XFER_START; - int xfer_stop = flags & I2C_XFER_STOP; - -#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT) - if (port == CONFIG_I2C_SCL_GATE_PORT && - slave_addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) - gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1); -#endif - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - /* Clear status */ - if (xfer_start) { - uint32_t cr2 = STM32_I2C_CR2(port); - - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - STM32_I2C_CR2(port) = 0; - if (cr2 & STM32_I2C_CR2_RELOAD) { - /* - * If I2C_XFER_START flag is on and we've set RELOAD=1 - * in previous chip_i2c_xfer() call. Then we are - * probably in the middle of an i2c transaction. - * - * In this case, we need to clear the RELOAD bit and - * wait for Transfer Complete (TC) flag, to make sure - * the chip is not expecting another NBYTES data, And - * send repeated-start correctly. - */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - } - - if (out_bytes || !in_bytes) { - /* - * Configure the write transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we are starting, then set START bit. - */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < out_bytes; i++) { - rv = wait_isr(port, STM32_I2C_ISR_TXIS); - if (rv) - goto xfer_exit; - /* Write next data byte */ - STM32_I2C_TXDR(port) = out[i]; - } - } - if (in_bytes) { - if (out_bytes) { /* wait for completion of the write */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - /* - * Configure the read transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we were just transmitting, we need to - * set START bit to send (re)start and begin read transaction. - */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < in_bytes; i++) { - /* Wait for receive buffer not empty */ - rv = wait_isr(port, STM32_I2C_ISR_RXNE); - if (rv) - goto xfer_exit; - - in[i] = STM32_I2C_RXDR(port); - } - } - - /* - * If we are stopping, then we already set AUTOEND and we should - * wait for the stop bit to be transmitted. Otherwise, we set - * the RELOAD bit and we should wait for transfer complete - * reload (TCR). - */ - rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); - if (rv) - goto xfer_exit; - -xfer_exit: - /* clear status */ - if (xfer_stop) - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - - /* On error, queue a stop condition */ - if (rv) { - /* queue a STOP condition */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; - /* wait for it to take effect */ - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - /* re-initialize the controller */ - STM32_I2C_CR2(port) = 0; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; - udelay(10); - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } - -#ifdef CONFIG_I2C_SCL_GATE_ADDR - if (port == CONFIG_I2C_SCL_GATE_PORT && - slave_addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) - gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0); -#endif - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; -#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) - /* - * If using low power idle and EC port is I2C1, then set I2C1 to wake - * from STOP mode on address match. Note, this only works on I2C1 and - * only if the clock to I2C1 is HSI 8MHz. - */ - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; -#endif - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1); -#ifdef TCPCI_I2C_SLAVE - /* - * Configure TCPC address with OA2[1] masked so that we respond - * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. - */ - STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100 - | (I2C_GET_ADDR(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); -#endif - task_enable_irq(IRQ_SLAVE); -#endif -} - diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c deleted file mode 120000 index ce8523ea90..0000000000 --- a/chip/stm32/i2c-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -i2c-stm32f0.c
\ No newline at end of file diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c deleted file mode 100644 index 8c08395edd..0000000000 --- a/chip/stm32/i2c-stm32f4.c +++ /dev/null @@ -1,1010 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_SLAVE_EV STM32_IRQ_I2C1_EV -#define IRQ_SLAVE_ER STM32_IRQ_I2C1_ER -#else -#define IRQ_SLAVE_EV STM32_IRQ_I2C2_EV -#define IRQ_SLAVE_ER STM32_IRQ_I2C2_ER -#endif -#endif - -/* Define I2C blocks available in stm32f4: - * We have standard ST I2C blocks and a "fast mode plus" I2C block, - * which do not share the same registers or functionality. So we'll need - * two sets of functions to handle this for stm32f4. In stm32f446, we - * only have one FMP block so we'll hardcode its port number. - */ -#define STM32F4_FMPI2C_PORT 3 - -static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)}, - {STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)}, - {STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)}, -}; - -static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)}, - {STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)}, - {STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)}, -}; - -/* Callback for ISR to wake task on DMA complete. */ -static inline void _i2c_dma_wake_callback(void *cb_data, int port) -{ - task_id_t id = (task_id_t)(int)cb_data; - - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_I2C_COMPLETION(port), 0); -} - -/* Each callback is hardcoded to an I2C channel. */ -static void _i2c_dma_wake_callback_0(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 0); -} - -static void _i2c_dma_wake_callback_1(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 1); -} - -static void _i2c_dma_wake_callback_2(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 2); -} - -static void _i2c_dma_wake_callback_3(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 3); -} - -/* void (*callback)(void *) */ -static void (*i2c_callbacks[I2C_PORT_COUNT])(void *) = { - _i2c_dma_wake_callback_0, - _i2c_dma_wake_callback_1, - _i2c_dma_wake_callback_2, - _i2c_dma_wake_callback_3, -}; - -/* Enable the I2C interrupt callback for this port. */ -void i2c_dma_enable_tc_interrupt(enum dma_channel stream, int port) -{ - dma_enable_tc_interrupt_callback(stream, i2c_callbacks[port], - (void *)(int)task_get_current()); -} - -/** - * Wait for SR1 register to contain the specified mask of 0 or 1. - * - * @param port I2C port - * @param mask mask of bits of interest - * @param val desired value of bits of interest - * @param poll uS poll frequency - * - * @return EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -#define SET 0xffffffff -#define UNSET 0 -static int wait_sr1_poll(int port, int mask, int val, int poll) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER; - - while (get_time().val < timeout) { - int sr1 = STM32_I2C_SR1(port); - - /* Check for errors */ - if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR | - STM32_I2C_SR1_AF)) { - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((sr1 & mask) == (val & mask)) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(poll); - } - - CPRINTS("I2C timeout: p:%d m:%x", port, mask); - return EC_ERROR_TIMEOUT; -} - -/* Wait for SR1 register to contain the specified mask of ones */ -static int wait_sr1(int port, int mask) -{ - return wait_sr1_poll(port, mask, SET, 100); -} - - -/** - * Send a start condition and slave address on the specified port. - * - * @param port I2C port - * @param slave_addr Slave address, with LSB set for receive-mode - * - * @return Non-zero if error. - */ -static int send_start(const int port, const uint16_t slave_addr_8bit) -{ - int rv; - - /* Send start bit */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_START; - rv = wait_sr1_poll(port, STM32_I2C_SR1_SB, SET, 1); - if (rv) - return I2C_ERROR_FAILED_START; - - /* Write slave address */ - STM32_I2C_DR(port) = slave_addr_8bit; - rv = wait_sr1_poll(port, STM32_I2C_SR1_ADDR, SET, 1); - if (rv) - return rv; - - /* Read SR2 to clear ADDR bit */ - rv = STM32_I2C_SR2(port); - - return EC_SUCCESS; -} - -/** - * Find the i2c port structure associated with the port. - * - * @return i2c_port_t * associated with this port number. - */ -static const struct i2c_port_t *find_port(int port) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) { - if (p->port == port) - return p; - } - CPRINTS("I2C port %d invalid! Crashing now.", port); - return NULL; -} - -/** - * Wait for ISR register to contain the specified mask. - * - * @param port I2C port - * @param mask mask of bits of interest - * @param val desired value of bits of interest - * @param poll uS poll frequency - * - * @return EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER; - - while (get_time().val < timeout) { - int isr = STM32_FMPI2C_ISR(port); - - /* Check for errors */ - if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | - FMPI2C_ISR_NACKF)) { - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((isr & mask) == (val & mask)) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(poll); - } - - CPRINTS("FMPI2C timeout p:%d, m:0x%08x", port, mask); - return EC_ERROR_TIMEOUT; -} - -/* Wait for ISR register to contain the specified mask of ones */ -static int wait_fmpi2c_isr(int port, int mask) -{ - return wait_fmpi2c_isr_poll(port, mask, SET, 100); -} - -/** - * Send a start condition and slave address on the specified port. - * - * @param port I2C port - * @param slave_addr Slave address - * @param size bytes to transfer - * @param is_read read, or write? - * - * @return Non-zero if error. - */ -static int send_fmpi2c_start(const int port, const uint16_t slave_addr_8bit, - int size, int is_read) -{ - uint32_t reg; - - /* Send start bit */ - reg = STM32_FMPI2C_CR2(port); - reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK | - FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP); - reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | - slave_addr_8bit | FMPI2C_CR2_SIZE(size) | - (is_read ? FMPI2C_CR2_RD_WRN : 0); - STM32_FMPI2C_CR2(port) = reg; - - return EC_SUCCESS; -} - -/** - * Set i2c clock rate.. - * - * @param p I2C port struct - */ -static void i2c_set_freq_port(const struct i2c_port_t *p) -{ - int port = p->port; - int freq = clock_get_freq(); - - if (p->port == STM32F4_FMPI2C_PORT) { - int prescalar; - int actual; - uint32_t reg; - - /* FMP I2C clock set. */ - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - prescalar = (freq / (p->kbps * 1000 * - (0x12 + 1 + 0xe + 1 + 1))) - 1; - actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1)); - - reg = FMPI2C_TIMINGR_SCLL(0x12) | - FMPI2C_TIMINGR_SCLH(0xe) | - FMPI2C_TIMINGR_PRESC(prescalar); - STM32_FMPI2C_TIMINGR(port) = reg; - - CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", - port, p->kbps, prescalar, actual, reg); - - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - udelay(10); - } else { - /* Force peripheral reset and disable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) = 0; - - /* Set clock frequency */ - if (p->kbps > 100) { - STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); - } else { - STM32_I2C_CCR(port) = STM32_I2C_CCR_FM - | STM32_I2C_CCR_DUTY - | (freq / (16 + 9 * MSEC * p->kbps)); - } - STM32_I2C_CR2(port) = freq / SECOND; - STM32_I2C_TRISE(port) = freq / SECOND + 1; - - /* Enable port */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - - /* Configure GPIOs, clocks */ - gpio_config_module(MODULE_I2C, 1); - clock_enable_module(MODULE_I2C, 1); - - if (p->port == STM32F4_FMPI2C_PORT) { - /* FMP I2C block */ - /* Set timing (?) */ - STM32_FMPI2C_TIMINGR(port) = TIMINGR_THE_RIGHT_VALUE; - udelay(10); - /* Device enable */ - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - /* Need to wait 3 APB cycles */ - udelay(10); - /* Device only. */ - STM32_FMPI2C_OAR1(port) = 0; - STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_AUTOEND; - } else { - STM32_I2C_CR1(port) |= STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_SWRST; - udelay(10); - } - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p); -} - -/*****************************************************************************/ -/* Interface */ - -/** - * Clear status regs on the specified I2C port. - * - * @param port the I2c port - */ -static void fmpi2c_clear_regs(int port) -{ - /* Clear status */ - STM32_FMPI2C_ICR(port) = 0xffffffff; - - /* Clear start, stop, NACK, etc. bits to get us in a known state */ - STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK | - FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK); -} - -/** - * Perform an i2c transaction - * - * @param port i2c port to use - * @param slave_addr the i2c slave addr - * @param out source buffer for data - * @param out_bytes bytes of data to write - * @param in destination buffer for data - * @param in_bytes bytes of data to read - * @param flags user cached I2C state - * - * @return EC_SUCCESS on success. - */ -static int chip_fmpi2c_xfer(const int port, const uint16_t slave_addr_8bit, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - ASSERT(!started); - - if (STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY) { - CPRINTS("fmpi2c port %d busy", port); - return EC_ERROR_BUSY; - } - - fmpi2c_clear_regs(port); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - rv = send_fmpi2c_start( - port, slave_addr_8bit, out_bytes, FMPI2C_WRITE); - if (rv) - goto xfer_exit; - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_TXIS); - if (rv) - goto xfer_exit; - - /* Write next data byte */ - STM32_FMPI2C_TXDR(port) = out[i]; - } - - /* Wait for transaction STOP. */ - wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF); - } - - if (in_bytes) { - int rv_start; - const struct dma_option *dma = dma_rx_option + port; - - dma_start_rx(dma, in_bytes, in); - i2c_dma_enable_tc_interrupt(dma->channel, port); - - rv_start = send_fmpi2c_start( - port, slave_addr_8bit, in_bytes, FMPI2C_READ); - if (rv_start) - goto xfer_exit; - - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_RXNE); - if (rv) - goto xfer_exit; - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN; - - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); - if (rv & TASK_EVENT_I2C_COMPLETION(port)) - rv = EC_SUCCESS; - else - rv = EC_ERROR_TIMEOUT; - - dma_disable(dma->channel); - dma_disable_tc_interrupt(dma->channel); - - /* Validate i2c is STOPped */ - if (!rv) - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF); - - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN; - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_STOP; - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p; - - CPRINTS("chip_fmpi2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - p = find_port(port); - i2c_unwedge(port); - i2c_init_port(p); - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY)) - break; - usleep(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - usleep(10); - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - } - - return rv; -} - - -/** - * Clear status regs on the specified I2C port. - * - * @param port the I2c port - */ -static void i2c_clear_regs(int port) -{ - /* - * Clear status - * - * TODO(crosbug.com/p/29314): should check for any leftover error - * status, and reset the port if present. - */ - STM32_I2C_SR1(port) = 0; - - /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); -} - -/***************************************************************************** - * Exported functions declared in i2c.h - */ - -/* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - const struct i2c_port_t *p = find_port(port); - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - ASSERT(!started); - - if (p->port == STM32F4_FMPI2C_PORT) { - return chip_fmpi2c_xfer(port, addr_8bit, - out, out_bytes, - in, in_bytes, flags); - } - - i2c_clear_regs(port); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - rv = send_start(port, addr_8bit); - if (rv) - goto xfer_exit; - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - /* Write next data byte */ - STM32_I2C_DR(port) = out[i]; - - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - } - - /* If no input bytes, queue stop condition */ - if (!in_bytes && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - } - - if (in_bytes) { - int rv_start; - - const struct dma_option *dma = dma_rx_option + port; - - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_POS; - dma_start_rx(dma, in_bytes, in); - i2c_dma_enable_tc_interrupt(dma->channel, port); - - /* Setup ACK/POS before sending start as per user manual */ - if (in_bytes == 2) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS; - else if (in_bytes != 1) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK; - - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_STOP; - - STM32_I2C_CR2(port) |= STM32_I2C_CR2_LAST; - STM32_I2C_CR2(port) |= STM32_I2C_CR2_DMAEN; - - rv_start = send_start(port, addr_8bit | 0x01); - - if ((in_bytes == 1) && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - if (!rv_start) { - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); - if (rv & TASK_EVENT_I2C_COMPLETION(port)) - rv = EC_SUCCESS; - else - rv = EC_ERROR_TIMEOUT; - } - - dma_disable(dma->channel); - dma_disable_tc_interrupt(dma->channel); - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; - /* Disable ack */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - - if (rv_start) - rv = rv_start; - - /* Send stop. */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_LAST; - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p; - - CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - p = find_port(port); - i2c_unwedge(port); - i2c_init_port(p); - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY)) - break; - usleep(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - usleep(10); - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -/*****************************************************************************/ -/* Hooks */ - -#ifdef CONFIG_I2C_MASTER -/* Handle CPU clock changing frequency */ -static void i2c_freq_change(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_set_freq_port(p); -} - -/* Handle an upcoming frequency change. */ -static void i2c_pre_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Lock I2C ports so freq change can't interrupt an I2C transaction */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 1); -} -DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT); - -/* Handle a frequency change */ -static void i2c_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - i2c_freq_change(); - - /* Unlock I2C ports we locked in pre-freq change hook */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 0); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); -#endif - -/*****************************************************************************/ -/* Slave */ -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -/* Host command slave */ -/* - * Buffer for received host command packets (including prefix byte on request, - * and result/size on response). After any protocol-specific headers, the - * buffers must be 32-bit aligned. - */ -static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + - CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; -static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); -static int host_i2c_resp_port; -static int tx_pending; -static int tx_index, tx_end; -static struct host_packet i2c_packet; - -static void i2c_send_response_packet(struct host_packet *pkt) -{ - int size = pkt->response_size; - uint8_t *out = host_buffer; - - /* Ignore host command in-progress */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result and size to first two bytes. */ - *out++ = pkt->driver_result; - *out++ = size; - - /* host_buffer data range */ - tx_index = 0; - tx_end = size + 2; - - /* - * Set the transmitter to be in 'not full' state to keep sending - * '0xec' in the event loop. Because of this, the master i2c - * doesn't need to snoop the response stream to abort transaction. - */ - STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN; -} - -/* Process the command in the i2c host buffer */ -static void i2c_process_command(void) -{ - char *buff = host_buffer; - - /* - * TODO(crosbug.com/p/29241): Combine this functionality with the - * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one - * host command i2c process function which handles all protocol - * versions. - */ - i2c_packet.send_response = i2c_send_response_packet; - - i2c_packet.request = (const void *)(&buff[1]); - i2c_packet.request_temp = params_copy; - i2c_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; - - /* - * Stuff response at buff[2] to leave the first two bytes of - * buffer available for the result and size to send over i2c. Note - * that this 2-byte offset and the 2-byte offset from host_buffer - * add up to make the response buffer 32-bit aligned. - */ - i2c_packet.response = (void *)(&buff[2]); - i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; - i2c_packet.response_size = 0; - - if (*buff >= EC_COMMAND_PROTOCOL_3) { - i2c_packet.driver_result = EC_RES_SUCCESS; - } else { - /* Only host command protocol 3 is supported. */ - i2c_packet.driver_result = EC_RES_INVALID_HEADER; - } - host_packet_receive(&i2c_packet); -} - -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS -static void i2c_send_board_response(int len) -{ - /* host_buffer data range, beyond this length, will return 0xec */ - tx_index = 0; - tx_end = len; - - /* enable transmit interrupt and use irq to send data back */ - STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN; -} - -static void i2c_process_board_command(int read, int addr, int len) -{ - board_i2c_process(read, addr, len, &host_buffer[0], - i2c_send_board_response); -} -#endif - -static void i2c_event_handler(int port) -{ - volatile uint32_t i2c_cr1; - volatile uint32_t i2c_sr2; - volatile uint32_t i2c_sr1; - static int rx_pending, buf_idx; - static uint16_t addr_8bit; - - volatile uint32_t dummy __attribute__((unused)); - - i2c_cr1 = STM32_I2C_CR1(port); - i2c_sr2 = STM32_I2C_SR2(port); - i2c_sr1 = STM32_I2C_SR1(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a slave allowing clock - * stretching and in non-SMBus mode. - */ - if (i2c_sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR)) { - rx_pending = 0; - tx_pending = 0; - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; - /* Clear error status bits */ - STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO | - STM32_I2C_SR1_BERR); - } - - /* Transfer matched our slave address */ - if (i2c_sr1 & STM32_I2C_SR1_ADDR) { - addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ? - STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe; - if (i2c_sr2 & STM32_I2C_SR2_TRA) { - /* Transmitter slave */ - i2c_sr1 |= STM32_I2C_SR1_TXE; -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - if (!rx_pending && !tx_pending) { - tx_pending = 1; - i2c_process_board_command(1, addr_8bit, 0); - } -#endif - } else { - /* Receiver slave */ - buf_idx = 0; - rx_pending = 1; - } - - /* Enable buffer interrupt to start receive/response */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN; - /* Clear ADDR bit */ - dummy = STM32_I2C_SR1(port); - dummy = STM32_I2C_SR2(port); - /* Inhibit stop mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* I2C in slave transmitter */ - if (i2c_sr2 & STM32_I2C_SR2_TRA) { - if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_TXE)) { - if (tx_pending) { - if (tx_index < tx_end) { - STM32_I2C_DR(port) = - host_buffer[tx_index++]; - } else { - STM32_I2C_DR(port) = 0xec; - tx_index = 0; - tx_end = 0; - tx_pending = 0; - } - } else if (rx_pending) { - host_i2c_resp_port = port; - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - if ((addr_8bit >> 1) == - I2C_GET_ADDR( - CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS)) - i2c_process_board_command(1, addr_8bit, - buf_idx); - else -#endif - i2c_process_command(); - /* Reset host buffer */ - rx_pending = 0; - tx_pending = 1; - } else { - STM32_I2C_DR(port) = 0xec; - } - } - } else { /* I2C in slave receiver */ - if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_RXNE)) - host_buffer[buf_idx++] = STM32_I2C_DR(port); - } - - /* STOPF or AF */ - if (i2c_sr1 & (STM32_I2C_SR1_STOPF | STM32_I2C_SR1_AF)) { - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; - -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - if (rx_pending && - (addr_8b >> 1) == - I2C_GET_ADDR(CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS)) - i2c_process_board_command(0, addr_8bit, buf_idx); -#endif - rx_pending = 0; - tx_pending = 0; - - /* Clear AF */ - STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF; - /* Clear STOPF: read SR1 and write CR1 */ - dummy = STM32_I2C_SR1(port); - STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* Enable again */ - if (!(i2c_cr1 & STM32_I2C_CR1_PE)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; -} -void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } -DECLARE_IRQ(IRQ_SLAVE_EV, i2c_event_interrupt, 2); -DECLARE_IRQ(IRQ_SLAVE_ER, i2c_event_interrupt, 2); -#endif - - -/* Init all available i2c ports */ -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - /* Enable ACK */ - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK; - /* Enable interrupts */ - STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN - | STM32_I2C_CR2_ITERREN; - /* Setup host command slave */ - STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14 - | (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1); -#ifdef CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS - STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL - | (I2C_GET_ADDR(CONFIG_BOARD_I2C_SLAVE_ADDR_FLAGS) << 1); -#endif - task_enable_irq(IRQ_SLAVE_EV); - task_enable_irq(IRQ_SLAVE_ER); -#endif -} diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c deleted file mode 100644 index 80d3434c74..0000000000 --- a/chip/stm32/i2c-stm32l.c +++ /dev/null @@ -1,424 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST - -/* - * Transmit timeout in microseconds - * - * In theory we shouldn't have a timeout here (at least when we're in slave - * mode). The slave is supposed to wait forever for the master to read bytes. - * ...but we're going to keep the timeout to make sure we're robust. It may in - * fact be needed if the host resets itself mid-read. - * - * NOTE: One case where this timeout is useful is when the battery - * flips out. The battery may flip out and hold lines low for up to - * 25ms. If we just wait it will eventually let them go. - */ -#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) - -/* - * Delay 5us in bitbang mode. That gives us roughly 5us low and 5us high or - * a frequency of 100kHz. - */ -#define I2C_BITBANG_HALF_CYCLE_US 5 - -#ifdef CONFIG_I2C_DEBUG -static void dump_i2c_reg(int port, const char *what) -{ - CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s", - STM32_I2C_CR1(port), - STM32_I2C_CR2(port), - STM32_I2C_SR1(port), - STM32_I2C_SR2(port), - what); -} -#else -static inline void dump_i2c_reg(int port, const char *what) -{ -} -#endif - -/** - * Wait for SR1 register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_sr1(int port, int mask) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER; - - while (get_time().val < timeout) { - int sr1 = STM32_I2C_SR1(port); - - /* Check for errors */ - if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR | - STM32_I2C_SR1_AF)) { - dump_i2c_reg(port, "wait_sr1 failed"); - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((sr1 & mask) == mask) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(100); - } - - return EC_ERROR_TIMEOUT; -} - -/** - * Send a start condition and slave address on the specified port. - * - * @param port I2C port - * @param slave_addr Slave address, with LSB set for receive-mode - * - * @return Non-zero if error. - */ -static int send_start(int port, uint16_t slave_addr_8bit) -{ - int rv; - - /* Send start bit */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_START; - dump_i2c_reg(port, "sent start"); - rv = wait_sr1(port, STM32_I2C_SR1_SB); - if (rv) - return I2C_ERROR_FAILED_START; - - /* Write slave address */ - STM32_I2C_DR(port) = slave_addr_8bit & 0xff; - rv = wait_sr1(port, STM32_I2C_SR1_ADDR); - if (rv) - return rv; - - /* Read SR2 to clear ADDR bit */ - rv = STM32_I2C_SR2(port); - - dump_i2c_reg(port, "wrote addr"); - - return EC_SUCCESS; -} - -static void i2c_set_freq_port(const struct i2c_port_t *p) -{ - int port = p->port; - int freq = clock_get_freq(); - - /* Force peripheral reset and disable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) = 0; - - /* Set clock frequency */ - STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); - STM32_I2C_CR2(port) = freq / SECOND; - STM32_I2C_TRISE(port) = freq / SECOND + 1; - - /* Enable port */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - - /* Enable clocks to I2C modules if necessary */ - if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) - STM32_RCC_APB1ENR |= 1 << (21 + port); - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p); -} - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, - const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - dump_i2c_reg(port, "xfer start"); - - /* - * Clear status - * - * TODO(crosbug.com/p/29314): should check for any leftover error - * status, and reset the port if present. - */ - STM32_I2C_SR1(port) = 0; - - /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - if (!started) { - rv = send_start(port, addr_8bit); - if (rv) - goto xfer_exit; - } - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - /* Write next data byte */ - STM32_I2C_DR(port) = out[i]; - dump_i2c_reg(port, "wrote data"); - - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - } - - /* Need repeated start condition before reading */ - started = 0; - - /* If no input bytes, queue stop condition */ - if (!in_bytes && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - } - - if (in_bytes) { - /* Setup ACK/POS before sending start as per user manual */ - if (in_bytes == 2) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS; - else if (in_bytes != 1) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK; - - if (!started) { - rv = send_start(port, addr_8bit | 0x01); - if (rv) - goto xfer_exit; - } - - if (in_bytes == 1) { - /* Set stop immediately after ADDR cleared */ - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - rv = wait_sr1(port, STM32_I2C_SR1_RXNE); - if (rv) - goto xfer_exit; - - in[0] = STM32_I2C_DR(port); - } else if (in_bytes == 2) { - /* Wait till the shift register is full */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - in[0] = STM32_I2C_DR(port); - in[1] = STM32_I2C_DR(port); - } else { - /* Read all but last three */ - for (i = 0; i < in_bytes - 3; i++) { - /* Wait for receive buffer not empty */ - rv = wait_sr1(port, STM32_I2C_SR1_RXNE); - if (rv) - goto xfer_exit; - - dump_i2c_reg(port, "read data"); - in[i] = STM32_I2C_DR(port); - dump_i2c_reg(port, "post read data"); - } - - /* Wait for BTF (data N-2 in DR, N-1 in shift) */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - /* No more acking */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - in[i++] = STM32_I2C_DR(port); - - /* Wait for BTF (data N-1 in DR, N in shift) */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - /* If this is the last byte, queue stop condition */ - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - /* Read the last two bytes */ - in[i++] = STM32_I2C_DR(port); - in[i++] = STM32_I2C_DR(port); - } - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - dump_i2c_reg(port, "stop after error"); - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p = i2c_ports; - CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - i2c_unwedge(port); - - for (i = 0; i < i2c_ports_used; i++, p++) { - if (p->port == port) { - i2c_init_port(p); - break; - } - } - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -/*****************************************************************************/ -/* Hooks */ - -/* Handle CPU clock changing frequency */ -static void i2c_freq_change(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_set_freq_port(p); -} - -static void i2c_pre_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Lock I2C ports so freq change can't interrupt an I2C transaction */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 1); -} -DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT); -static void i2c_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - i2c_freq_change(); - - /* Unlock I2C ports we locked in pre-freq change hook */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 0); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); -} - -/*****************************************************************************/ -/* Console commands */ - -static int command_i2cdump(int argc, char **argv) -{ - dump_i2c_reg(I2C_PORT_MASTER, "dump"); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, - NULL, - "Dump I2C regs"); diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c deleted file mode 100644 index 66bd063499..0000000000 --- a/chip/stm32/i2c-stm32l4.c +++ /dev/null @@ -1,464 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "printf.h" -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "i2c.h" -#include "registers.h" - -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS -#define I2C_SLAVE_ERROR_CODE 0xec -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_SLAVE STM32_IRQ_I2C1 -#else -#define IRQ_SLAVE STM32_IRQ_I2C2 -#endif -#endif - -/* I2C port state data */ -struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER; -} - -/* timing register values for supported input clks / i2c clk rates */ -static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ -}; - -/** - * Wait for ISR register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_isr(int port, int mask) -{ - uint32_t start = __hw_clock_source_read(); - uint32_t delta = 0; - - do { - int isr = STM32_I2C_ISR(port); - - /* Check for errors */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) - return EC_ERROR_UNKNOWN; - - /* Check for desired mask */ - if ((isr & mask) == mask) - return EC_SUCCESS; - - delta = __hw_clock_source_read() - start; - - /** - * Depending on the bus speed, busy loop for a while before - * sleeping and letting other things run. - */ - if (delta >= busyloop_us[pdata[port].freq]) - usleep(100); - } while (delta < pdata[port].timeout_us); - - return EC_ERROR_TIMEOUT; -} - -/* We are only using sysclk, which is 40MHZ */ -enum stm32_i2c_clk_src { - I2C_CLK_SRC_40MHZ = 0, - I2C_CLK_SRC_COUNT, -}; - -/* timing register values for supported input clks / i2c clk rates - * - * These values are calculated using ST's STM32cubeMX tool - */ -static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { - [I2C_CLK_SRC_40MHZ] = { - [I2C_FREQ_1000KHZ] = 0x00100618, - [I2C_FREQ_400KHZ] = 0x00301347, - [I2C_FREQ_100KHZ] = 0x003087FF, - }, -}; - -static void i2c_set_freq_port(const struct i2c_port_t *p, - enum stm32_i2c_clk_src src, - enum i2c_freq freq) -{ - int port = p->port; - const uint32_t *regs = timingr_regs[src]; - - /* Disable port */ - STM32_I2C_CR1(port) = 0; - STM32_I2C_CR2(port) = 0; - /* Set clock frequency */ - STM32_I2C_TIMINGR(port) = regs[freq]; - /* Enable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; - - pdata[port].freq = freq; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - uint32_t mask; - uint8_t shift; - enum stm32_i2c_clk_src src = I2C_CLK_SRC_40MHZ; - enum i2c_freq freq; - - /* Enable clocks to I2C modules if necessary */ - if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) - STM32_RCC_APB1ENR |= 1 << (21 + port); - - /* Select sysclk as source */ - mask = STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2); - shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + (port * 2); - STM32_RCC_CCIPR &= ~mask; - STM32_RCC_CCIPR |= STM32_RCC_CCIPR_I2C_SYSCLK << shift; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set clock frequency */ - switch (p->kbps) { - case 1000: - freq = I2C_FREQ_1000KHZ; - break; - case 400: - freq = I2C_FREQ_400KHZ; - break; - case 100: - freq = I2C_FREQ_100KHZ; - break; - default: /* unknown speed, defaults to 100kBps */ - CPRINTS("I2C bad speed %d kBps", p->kbps); - freq = I2C_FREQ_100KHZ; - } - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p, src, freq); - - /* Set up default timeout */ - i2c_set_timeout(port, 0); -} - -/*****************************************************************************/ - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - -static void i2c_event_handler(int port) -{ - /* Variables tracking the handler state. - * TODO: Should have as many sets of these variables as the number - * of slave ports. - */ - static int rx_pending, rx_idx; - static int tx_pending, tx_idx, tx_end; - static uint8_t slave_buffer[I2C_MAX_HOST_PACKET_SIZE + 2]; - int isr = STM32_I2C_ISR(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a slave allowing clock - * stretching and in non-SMBus mode. - */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF - | STM32_I2C_ICR_ARLOCF; - } - - /* Transfer matched our slave address */ - if (isr & STM32_I2C_ISR_ADDR) { - if (isr & STM32_I2C_ISR_DIR) { - /* Transmitter slave */ - /* Clear transmit buffer */ - STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; - - if (rx_pending) - /* RESTART */ - i2c_data_received(port, slave_buffer, rx_idx); - tx_end = i2c_set_response(port, slave_buffer, rx_idx); - tx_idx = 0; - rx_pending = 0; - tx_pending = 1; - - /* Enable txis interrupt to start response */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; - } else { - /* Receiver slave */ - rx_idx = 0; - rx_pending = 1; - tx_pending = 0; - } - - /* Clear ADDR bit by writing to ADDRCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; - /* Inhibit stop mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - /* - * Receive buffer not empty - * - * When a master finishes sending data, it'll set STOP bit. It causes - * the slave to receive RXNE and STOP interrupt at the same time. So, - * we need to process RXNE first, then handle STOP. - */ - if (isr & STM32_I2C_ISR_RXNE) - slave_buffer[rx_idx++] = STM32_I2C_RXDR(port); - - /* Stop condition on bus */ - if (isr & STM32_I2C_ISR_STOP) { - if (rx_pending) - i2c_data_received(port, slave_buffer, rx_idx); - tx_idx = 0; - tx_end = 0; - rx_pending = 0; - tx_pending = 0; - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear STOPF bit by writing to STOPCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_SLAVE); - } - - if (isr & STM32_I2C_ISR_NACK) { - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - /* Clear NACK */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; - } - - /* Transmitter empty event */ - if (isr & STM32_I2C_ISR_TXIS) { - if (port == I2C_PORT_EC) { - if (tx_pending) { - if (tx_idx < tx_end) { - STM32_I2C_TXDR(port) = - slave_buffer[tx_idx++]; - } else { - STM32_I2C_TXDR(port) - = I2C_SLAVE_ERROR_CODE; - tx_idx = 0; - tx_end = 0; - tx_pending = 0; - } - } else { - STM32_I2C_TXDR(port) = I2C_SLAVE_ERROR_CODE; - } - } - } -} - -void i2c_event_interrupt(void) -{ - i2c_event_handler(I2C_PORT_EC); -} -DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2); -#endif - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_GET_ADDR(slave_addr_flags) << 1; - int rv = EC_SUCCESS; - int i; - int xfer_start = flags & I2C_XFER_START; - int xfer_stop = flags & I2C_XFER_STOP; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - /* Clear status */ - if (xfer_start) { - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - STM32_I2C_CR2(port) = 0; - } - - if (out_bytes || !in_bytes) { - /* - * Configure the write transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we are starting, then set START bit. - */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < out_bytes; i++) { - rv = wait_isr(port, STM32_I2C_ISR_TXIS); - if (rv) - goto xfer_exit; - /* Write next data byte */ - STM32_I2C_TXDR(port) = out[i]; - } - } - if (in_bytes) { - if (out_bytes) { /* wait for completion of the write */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - /* - * Configure the read transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we were just transmitting, we need to - * set START bit to send (re)start and begin read transaction. - */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < in_bytes; i++) { - /* Wait for receive buffer not empty */ - rv = wait_isr(port, STM32_I2C_ISR_RXNE); - if (rv) - goto xfer_exit; - - in[i] = STM32_I2C_RXDR(port); - } - } - - /* - * If we are stopping, then we already set AUTOEND and we should - * wait for the stop bit to be transmitted. Otherwise, we set - * the RELOAD bit and we should wait for transfer complete - * reload (TCR). - */ - rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); - if (rv) - goto xfer_exit; - -xfer_exit: - /* clear status */ - if (xfer_stop) - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - - /* On error, queue a stop condition */ - if (rv) { - /* queue a STOP condition */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; - /* wait for it to take effect */ - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - /* re-initialize the controller */ - STM32_I2C_CR2(port) = 0; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; - udelay(10); - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g)) - /* If no SCL pin is defined, return 1 to appear idle. */ - return 1; - - return gpio_get_level(g); -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g)) - /* If no SDA pin is defined, return 1 to appear idle. */ - return 1; - - return gpio_get_level(g); -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - -#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_GET_ADDR(CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS) << 1); - task_enable_irq(IRQ_SLAVE); -#endif -} diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c deleted file mode 100644 index 219676968a..0000000000 --- a/chip/stm32/keyboard_raw.c +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for STM32 - * - * To make this code portable, we rely heavily on looping over the keyboard - * input and output entries in the board's gpio_list[]. Each set of inputs or - * outputs must be listed in consecutive, increasing order so that scan loops - * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are - * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX). - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* Mask of external interrupts on input lines */ -static unsigned int irq_mask; - -static const uint32_t kb_out_ports[] = { KB_OUT_PORT_LIST }; - -static void set_irq_mask(void) -{ - int i; - - for (i = GPIO_KB_IN00; i < GPIO_KB_IN00 + KEYBOARD_ROWS; i++) - irq_mask |= gpio_list[i].mask; -} - -void keyboard_raw_init(void) -{ - /* Determine EXTI_PR mask to use for the board */ - set_irq_mask(); - - /* Ensure interrupts are disabled in EXTI_PR */ - keyboard_raw_enable_interrupt(0); -} - -void keyboard_raw_task_start(void) -{ - /* Enable interrupts for keyboard matrix inputs */ - gpio_enable_interrupt(GPIO_KB_IN00); - gpio_enable_interrupt(GPIO_KB_IN01); - gpio_enable_interrupt(GPIO_KB_IN02); - gpio_enable_interrupt(GPIO_KB_IN03); - gpio_enable_interrupt(GPIO_KB_IN04); - gpio_enable_interrupt(GPIO_KB_IN05); - gpio_enable_interrupt(GPIO_KB_IN06); - gpio_enable_interrupt(GPIO_KB_IN07); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - int i, done = 0; - - for (i = 0; i < ARRAY_SIZE(kb_out_ports); i++) { - uint32_t bsrr = 0; - int j; - - for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) { - if (gpio_list[j].port != kb_out_ports[i]) - continue; - - if (out == KEYBOARD_COLUMN_ALL) { - /* drive low (clear bit) */ - bsrr |= gpio_list[j].mask << 16; - } else if (out == KEYBOARD_COLUMN_NONE) { - /* put output in hi-Z state (set bit) */ - bsrr |= gpio_list[j].mask; - } else if (j - GPIO_KB_OUT00 == out) { - /* - * Drive specified output low, others => hi-Z. - * - * To avoid conflict, tri-state all outputs - * first, then assert specified output. - */ - keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE); - bsrr |= gpio_list[j].mask << 16; - done = 1; - break; - } - } - - #ifdef CONFIG_KEYBOARD_COL2_INVERTED - if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask)) - bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask); - #endif - - if (bsrr) - STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr; - - if (done) - break; - } -} - -test_mockable int keyboard_raw_read_rows(void) -{ - int i; - unsigned int port, prev_port = 0; - int state = 0; - uint16_t port_val = 0; - - for (i = 0; i < KEYBOARD_ROWS; i++) { - port = gpio_list[GPIO_KB_IN00 + i].port; - if (port != prev_port) { - port_val = STM32_GPIO_IDR(port); - prev_port = port; - } - - if (port_val & gpio_list[GPIO_KB_IN00 + i].mask) - state |= 1 << i; - } - - /* Invert it so 0=not pressed, 1=pressed */ - return state ^ 0xff; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - /* - * Assert all outputs would trigger un-wanted interrupts. - * Clear them before enable interrupt. - */ - STM32_EXTI_PR |= irq_mask; - STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ - } else { - STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ - } -} - -void keyboard_raw_gpio_interrupt(enum gpio_signal signal) -{ - task_wake(TASK_ID_KEYSCAN); -} diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc deleted file mode 100644 index 2381c511f2..0000000000 --- a/chip/stm32/memory_regions.inc +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifdef CONFIG_USB_RAM_SIZE -REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \ - CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2) -#endif /* CONFIG_USB_RAM_SIZE */ -#ifdef CHIP_VARIANT_STM32H7X3 -REGION(itcm, wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */ -REGION(dtcm, rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */ -REGION(ahb, rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */ -REGION(ahb4, rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */ -REGION(backup, rw, 0x38800000, 0x01000) /* Backup RAM: 4kB */ -#endif /* CHIP_VARIANT_STM32H7X3 */ diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c deleted file mode 100644 index a993af7042..0000000000 --- a/chip/stm32/otp-stm32f4.c +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* OTP implementation for STM32F411 */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "otp.h" -#include "registers.h" -#include "util.h" - -/* - * OTP is only used for saving the USB serial number. - */ -#ifdef CONFIG_SERIALNO_LEN -/* Which block to use */ -#define OTP_SERIAL_BLOCK 0 -#define OTP_SERIAL_ADDR \ - REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) - -/* Number of word used in the block */ -#define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t)) -BUILD_ASSERT(CONFIG_SERIALNO_LEN % sizeof(uint32_t) == 0); -BUILD_ASSERT(OTP_SERIAL_BLOCK_SIZE < STM32_OTP_BLOCK_SIZE); - -/* - * Write an OTP block - * - * @param block block to write. - * @param size Number of words to write. - * @param data Destination buffer for data. - */ -static int otp_write(uint8_t block, int size, const char *data) -{ - if (block >= STM32_OTP_BLOCK_NB) - return EC_ERROR_PARAM1; - if (size >= STM32_OTP_BLOCK_SIZE) - return EC_ERROR_PARAM2; - return flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) - - CONFIG_PROGRAM_MEMORY_BASE, - size * sizeof(uint32_t), data); -} - -/* - * Check if an OTP block is protected. - * - * @param block protected block. - * @return non-zero if that block is read only. - */ -static int otp_get_protect(uint8_t block) -{ - uint32_t lock; - - lock = REG32(STM32_OTP_LOCK(block)); - return ((lock & STM32_OPT_LOCK_MASK(block)) == 0); -} - -/* - * Set a particular OTP block as read only. - * - * @param block block to protect. - */ -static int otp_set_protect(uint8_t block) -{ - int rv; - uint32_t lock; - - if (otp_get_protect(block)) - return EC_SUCCESS; - - lock = REG32(STM32_OTP_LOCK(block)); - lock &= ~STM32_OPT_LOCK_MASK(block); - rv = flash_physical_write(STM32_OTP_LOCK(block) - - CONFIG_PROGRAM_MEMORY_BASE, - sizeof(uint32_t), (char *)&lock); - if (rv) - return rv; - else - return EC_SUCCESS; -} - -const char *otp_read_serial(void) -{ - int i; - - for (i = 0; i < OTP_SERIAL_BLOCK_SIZE; i++) { - if (OTP_SERIAL_ADDR[i] != -1) - return (char *)OTP_SERIAL_ADDR; - } - return NULL; -} - -int otp_write_serial(const char *serialno) -{ - int i, ret; - char otp_serial[CONFIG_SERIALNO_LEN]; - - if (otp_get_protect(OTP_SERIAL_BLOCK)) - return EC_ERROR_ACCESS_DENIED; - - /* Copy in serialno. */ - for (i = 0; i < CONFIG_SERIALNO_LEN - 1; i++) { - otp_serial[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - for (; i < CONFIG_SERIALNO_LEN; i++) - otp_serial[i] = 0; - - ret = otp_write(OTP_SERIAL_BLOCK, OTP_SERIAL_BLOCK_SIZE, otp_serial); - if (ret == EC_SUCCESS) - return otp_set_protect(OTP_SERIAL_BLOCK); - else - return ret; -} -#endif diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c deleted file mode 100644 index 508745199f..0000000000 --- a/chip/stm32/power_led.c +++ /dev/null @@ -1,162 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Keyboard power button LED state machine. - * - * This sets up TIM_POWER_LED to drive the power button LED so that the duty - * cycle can range from 0-100%. When the lid is closed or turned off, then the - * PWM is disabled and the GPIO is reconfigured to minimize leakage voltage. - * - * In suspend mode, duty cycle transitions progressively slower from 0% - * to 100%, and progressively faster from 100% back down to 0%. This - * results in a breathing effect. It takes about 2sec for a full cycle. - */ - -#include "clock.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "power_led.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ -#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ -#define LED_STEP_PERCENT 4 /* Incremental value of each step */ - -static enum powerled_state led_state = POWERLED_STATE_ON; -static int power_led_percent = 100; - -void powerled_set_state(enum powerled_state new_state) -{ - led_state = new_state; - /* Wake up the task */ - task_wake(TASK_ID_POWERLED); -} - -static void power_led_set_duty(int percent) -{ - ASSERT((percent >= 0) && (percent <= 100)); - power_led_percent = percent; - pwm_set_duty(PWM_CH_POWER_LED, percent); -} - -static void power_led_use_pwm(void) -{ - pwm_enable(PWM_CH_POWER_LED, 1); - power_led_set_duty(100); -} - -static void power_led_manual_off(void) -{ - pwm_enable(PWM_CH_POWER_LED, 0); - - /* - * Reconfigure GPIO as a floating input. Alternatively we could - * configure it as an open-drain output and set it to high impedance, - * but reconfiguring as an input had better results in testing. - */ - gpio_config_module(MODULE_POWER_LED, 0); -} - -/** - * Return the timeout period (in us) for the current step. - */ -static int power_led_step(void) -{ - int state_timeout = 0; - static enum { DOWN = -1, UP = 1 } dir = UP; - - if (0 == power_led_percent) { - dir = UP; - state_timeout = LED_HOLD_TIME; - } else if (100 == power_led_percent) { - dir = DOWN; - state_timeout = LED_HOLD_TIME; - } else { - /* - * Decreases timeout as duty cycle percentage approaches - * 0%, increase as it approaches 100%. - */ - state_timeout = LED_STATE_TIMEOUT_MIN + - LED_STATE_TIMEOUT_MIN * (power_led_percent / 33); - } - - /* - * The next duty cycle will take effect after the timeout has - * elapsed for this duty cycle and the power LED task calls this - * function again. - */ - power_led_set_duty(power_led_percent); - power_led_percent += dir * LED_STEP_PERCENT; - - return state_timeout; -} - -void power_led_task(void) -{ - while (1) { - int state_timeout = -1; - - switch (led_state) { - case POWERLED_STATE_ON: - /* - * "ON" implies driving the LED using the PWM with a - * duty duty cycle of 100%. This produces a softer - * brightness than setting the GPIO to solid ON. - */ - power_led_use_pwm(); - power_led_set_duty(100); - state_timeout = -1; - break; - case POWERLED_STATE_OFF: - /* Reconfigure GPIO to disable the LED */ - power_led_manual_off(); - state_timeout = -1; - break; - case POWERLED_STATE_SUSPEND: - /* Drive using PWM with variable duty cycle */ - power_led_use_pwm(); - state_timeout = power_led_step(); - break; - default: - break; - } - - task_wait_event(state_timeout); - } -} - -#define CONFIG_CMD_POWERLED -#ifdef CONFIG_CMD_POWERLED -static int command_powerled(int argc, char **argv) -{ - enum powerled_state state; - - if (argc != 2) - return EC_ERROR_INVAL; - - if (!strcasecmp(argv[1], "off")) - state = POWERLED_STATE_OFF; - else if (!strcasecmp(argv[1], "on")) - state = POWERLED_STATE_ON; - else if (!strcasecmp(argv[1], "suspend")) - state = POWERLED_STATE_SUSPEND; - else - return EC_ERROR_INVAL; - - powerled_set_state(state); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(powerled, command_powerled, - "[off | on | suspend]", - "Change power LED state"); -#endif diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c deleted file mode 100644 index 8a263b272b..0000000000 --- a/chip/stm32/pwm.c +++ /dev/null @@ -1,163 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for STM32 */ - -#include "clock.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "system.h" -#include "util.h" - -/* Bitmap of currently active PWM channels. 1 bit per channel. */ -static uint32_t using_pwm; - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - - ASSERT((percent >= 0) && (percent <= 100)); - tim->ccr[pwm->channel] = percent; -} - -int pwm_get_duty(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - return tim->ccr[pwm->channel]; -} - -static void pwm_configure(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - volatile unsigned *ccmr = NULL; - /* Default frequency = 100 Hz */ - int frequency = pwm->frequency ? pwm->frequency : 100; - uint16_t ccer; - - if (using_pwm & BIT(ch)) - return; - - /* Enable timer */ - __hw_timer_enable_clock(pwm->tim.id, 1); - - /* Disable counter during setup */ - tim->cr1 = 0x0000; - - /* - * CPU clock / PSC determines how fast the counter operates. - * ARR determines the wave period, CCRn determines duty cycle. - * Thus, frequency = cpu_freq / PSC / ARR. so: - * - * frequency = cpu_freq / (cpu_freq/10000 + 1) / (99 + 1) = 100 Hz. - */ - tim->psc = clock_get_freq() / (frequency * 100) - 1; - tim->arr = 99; - - if (pwm->channel <= 2) /* Channel ID starts from 1 */ - ccmr = &tim->ccmr1; - else - ccmr = &tim->ccmr2; - - /* Output, PWM mode 1, preload enable */ - if (pwm->channel & 0x1) - *ccmr = (6 << 4) | BIT(3); - else - *ccmr = (6 << 12) | BIT(11); - - /* Output enable. Set active high/low. */ - if (pwm->flags & PWM_CONFIG_ACTIVE_LOW) - ccer = 3 << (pwm->channel * 4 - 4); - else - ccer = 1 << (pwm->channel * 4 - 4); - - /* Enable complementary output, if present. */ - if (pwm->flags & PWM_CONFIG_COMPLEMENTARY_OUTPUT) - ccer |= (ccer << 2); - - tim->ccer = ccer; - - /* - * Main output enable. - * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't - * harmful on STM32L. - */ - tim->bdtr |= BIT(15); - - /* Generate update event to force loading of shadow registers */ - tim->egr |= 1; - - /* Enable auto-reload preload, start counting */ - tim->cr1 |= BIT(7) | BIT(0); - - atomic_or(&using_pwm, 1 << ch); - - /* Prevent sleep */ - disable_sleep(SLEEP_MASK_PWM); -} - -static void pwm_disable(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - - if ((using_pwm & BIT(ch)) == 0) - return; - - /* Main output disable */ - tim->bdtr &= ~BIT(15); - - /* Disable counter */ - tim->cr1 &= ~0x1; - - /* Disable timer clock */ - __hw_timer_enable_clock(pwm->tim.id, 0); - - /* Allow sleep */ - enable_sleep(SLEEP_MASK_PWM); - - atomic_clear(&using_pwm, 1 << ch); - - /* Unless another PWM is active... Then prevent sleep */ - if (using_pwm) - disable_sleep(SLEEP_MASK_PWM); -} - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - if (enabled) - pwm_configure(ch); - else - pwm_disable(ch); -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - return using_pwm & BIT(ch); -} - -static void pwm_reconfigure(enum pwm_channel ch) -{ - atomic_clear(&using_pwm, 1 << ch); - pwm_configure(ch); -} - -/** - * Handle clock frequency change - */ -static void pwm_freq_change(void) -{ - int i; - for (i = 0; i < PWM_CH_COUNT; ++i) - if (pwm_get_enabled(i)) - pwm_reconfigure(i); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, pwm_freq_change, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h deleted file mode 100644 index baa793090a..0000000000 --- a/chip/stm32/pwm_chip.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* STM32-specific PWM module for Chrome EC */ - -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* - * Timer powering the PWM channel. Must use STM32_TIM(x) to - * initialize - */ - struct { - int id; - uintptr_t base; - } tim; - /* Channel ID within the timer */ - int channel; - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; - /* PWM frequency (Hz) */ - int frequency; -}; - -extern const struct pwm_t pwm_channels[]; - -/* Macro to fill in both timer ID and register base */ -#define STM32_TIM(x) {x, STM32_TIM_BASE(x)} - -/* Plain ID mapping for readability */ -#define STM32_TIM_CH(x) (x) - -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h deleted file mode 100644 index 4985c16783..0000000000 --- a/chip/stm32/registers-stm32f0.h +++ /dev/null @@ -1,957 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F0 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F03X - * - STM32F05X - * - STM32F070 - * - STM32F07X - * - STM32F09X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_WAKEUP 2 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 3 -#define STM32_IRQ_RCC 4 -#define STM32_IRQ_EXTI0_1 5 -#define STM32_IRQ_EXTI2_3 6 -#define STM32_IRQ_EXTI4_15 7 -#define STM32_IRQ_TSC 8 -#define STM32_IRQ_DMA_CHANNEL_1 9 -#define STM32_IRQ_DMA_CHANNEL_2_3 10 -#define STM32_IRQ_DMA_CHANNEL_4_7 11 -#define STM32_IRQ_ADC_COMP 12 -#define STM32_IRQ_TIM1_BRK_UP_TRG 13 -#define STM32_IRQ_TIM1_CC 14 -#define STM32_IRQ_TIM2 15 -#define STM32_IRQ_TIM3 16 -#define STM32_IRQ_TIM6_DAC 17 -#define STM32_IRQ_TIM7 18 -#define STM32_IRQ_TIM14 19 -#define STM32_IRQ_TIM15 20 -#define STM32_IRQ_TIM16 21 -#define STM32_IRQ_TIM17 22 -#define STM32_IRQ_I2C1 23 -#define STM32_IRQ_I2C2 24 -#define STM32_IRQ_SPI1 25 -#define STM32_IRQ_SPI2 26 -#define STM32_IRQ_USART1 27 -#define STM32_IRQ_USART2 28 -#define STM32_IRQ_USART3_4 29 -#define STM32_IRQ_CEC_CAN 30 -#define STM32_IRQ_USB 31 -/* aliases for easier code sharing */ -#define STM32_IRQ_COMP STM32_IRQ_ADC_COMP -#define STM32_IRQ_USB_LP STM32_IRQ_USB - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40010000 - -#define STM32_DBGMCU_BASE 0x40015800 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFF800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) -/* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) -/* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ - -#define STM32_RCC_HB_DMA1 BIT(0) -/* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 20 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_ISR_ADRDY BIT(0) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_IER_AWDIE BIT(7) -#define STM32_ADC_IER_OVRIE BIT(4) -#define STM32_ADC_IER_EOSEQIE BIT(3) -#define STM32_ADC_IER_EOCIE BIT(2) -#define STM32_ADC_IER_EOSMPIE BIT(1) -#define STM32_ADC_IER_ADRDYIE BIT(0) - -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADDIS BIT(1) -#define STM32_ADC_CR_ADCAL BIT(31) -#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) -/* Analog watchdog channel selection */ -#define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26) -#define STM32_ADC_CFGR1_AWDEN BIT(23) -#define STM32_ADC_CFGR1_AWDSGL BIT(22) -/* Selects single vs continuous */ -#define STM32_ADC_CFGR1_CONT BIT(13) -/* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC_CFGR1_OVRMOD BIT(12) -/* External trigger polarity selection */ -#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) -#define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10) -#define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10) -#define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10) -#define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10) -/* External trigger selection */ -#define STM32_ADC_CFGR1_TRG0 (0 << 6) -#define STM32_ADC_CFGR1_TRG1 (1 << 6) -#define STM32_ADC_CFGR1_TRG2 (2 << 6) -#define STM32_ADC_CFGR1_TRG3 (3 << 6) -#define STM32_ADC_CFGR1_TRG4 (4 << 6) -#define STM32_ADC_CFGR1_TRG5 (5 << 6) -#define STM32_ADC_CFGR1_TRG6 (6 << 6) -#define STM32_ADC_CFGR1_TRG7 (7 << 6) -#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) -/* Selects circular vs one-shot */ -#define STM32_ADC_CFGR1_DMACFG BIT(1) -#define STM32_ADC_CFGR1_DMAEN BIT(0) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) -/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) - -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) - -#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) - -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, -#if !defined(CHIP_VARIANT_STM32F03X) && !defined(CHIP_VARIANT_STM32F05X) - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, - -#else /* stm32f03x and stm32f05x have only 5 channels */ - STM32_DMAC_COUNT = 5, -#endif -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#ifdef CHIP_VARIANT_STM32F09X -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) -#else -#define STM32_DMA_REGS(channel) STM32_DMA1_REGS -#endif - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h deleted file mode 100644 index b7e3cfc8af..0000000000 --- a/chip/stm32/registers-stm32f3.h +++ /dev/null @@ -1,1013 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F3 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F373 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_USB_HP 74 -#define STM32_IRQ_USB_LP 75 -#else -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 -#endif - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_COMP 64 -#else -#define STM32_IRQ_COMP 22 -#endif - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40010000 - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFF800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) -/* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) -/* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ - -#define STM32_RCC_HB_DMA1 BIT(0) -/* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 64 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) -#endif - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) - -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) - -#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24) -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_COMP_CMP2OUTSEL_TIM4_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM4_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM16_BRK (1 << 24) -#else -#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#endif -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) - -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM5_IC4 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM15_BRK (1 << 8) -#else -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#endif -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, -#ifdef CHIP_VARIANT_STM32F373 - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - - STM32_DMAC_COUNT = 10, -#else - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, -#endif -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h deleted file mode 100644 index 452737254a..0000000000 --- a/chip/stm32/registers-stm32f4.h +++ /dev/null @@ -1,1158 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F4 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F411 - * - STM32F412 - * - STM32F41X - * - STM32F446 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - -#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F412) -#define CHIP_VARIANT_STM32F41X -#endif - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) -/* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#if defined(CHIP_VARIANT_STM32F446) -/* Required or recommended clocks for stm32f446 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 42000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 336000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x8 -#define STM32F4_APB1_PRE 0x0 -#define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) - -#elif defined(CHIP_VARIANT_STM32F412) -/* Required or recommended clocks for stm32f412 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 384000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x0 -#define STM32F4_APB1_PRE 0x4 -#define STM32F4_APB2_PRE 0x4 -#define STM32_FLASH_ACR_LATENCY (3 << 0) - -#elif defined(CHIP_VARIANT_STM32F411) -/* Required or recommended clocks for stm32f411 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 384000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x8 -#define STM32F4_APB1_PRE 0x0 -#define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) - -#elif defined(CHIP_VARIANT_STM32F76X) -/* Required or recommended clocks for stm32f767/769 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ -#define STM32F4_VCO_CLOCK 360000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ -#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ -#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) - -#else -#error "No valid clocks defined" -#endif - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) -/* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) -/* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) -/* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) - -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) -/* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) -/* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -/* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) -/* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) -/* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) -/* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) - -/* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ - FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define FLASH_OPTCR_RDP_SHIFT (8) -#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) -/* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 -#define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, -#ifdef CHIP_VARIANT_STM32F41X - STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6, - STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX, - STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX, -#endif - -#ifdef CHIP_VARIANT_STM32F41X - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2, -#else - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1, -#endif - - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h deleted file mode 100644 index 2245d6775f..0000000000 --- a/chip/stm32/registers-stm32f7.h +++ /dev/null @@ -1,1082 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F7 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F76X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#ifdef CHIP_VARIANT_STM32F76X -/* Required or recommended clocks for stm32f767/769 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ -#define STM32F4_VCO_CLOCK 360000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ -#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ -#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) -#else -#error "No valid clocks defined" -#endif - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) -/* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) -/* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) -/* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) - -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) -/* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) -/* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -/* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) -/* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) -/* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) -/* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) -/* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ - FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define STM32_FLASH_RDP_MASK (0xFF << 8) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 -#define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, - STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6, - STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX, - STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX, - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2, - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h deleted file mode 100644 index 895957d378..0000000000 --- a/chip/stm32/registers-stm32h7.h +++ /dev/null @@ -1,1224 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32H7 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32H7X3 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - -#define STM32_IRQ_LPTIM1 93 -#define STM32_IRQ_TIM15 116 -#define STM32_IRQ_TIM16 117 -#define STM32_IRQ_TIM17 118 -#define STM32_IRQ_LPTIM2 138 -#define STM32_IRQ_LPTIM3 139 -#define STM32_IRQ_LPTIM4 140 -#define STM32_IRQ_LPTIM5 141 - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ - -#define STM32_GPV_BASE 0x51000000 - -#define STM32_DBGMCU_BASE 0x5C001000 - -#define STM32_BDMA_BASE 0x58025400 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 -#define STM32_DMA2D_BASE 0x52001000 -#define STM32_DMAMUX1_BASE 0x40020800 -#define STM32_DMAMUX2_BASE 0x58025800 -#define STM32_MDMA_BASE 0x52000000 - -#define STM32_EXTI_BASE 0x58000000 - -#define STM32_FLASH_REGS_BASE 0x52002000 - -#define STM32_GPIOA_BASE 0x58020000 -#define STM32_GPIOB_BASE 0x58020400 -#define STM32_GPIOC_BASE 0x58020800 -#define STM32_GPIOD_BASE 0x58020C00 -#define STM32_GPIOE_BASE 0x58021000 -#define STM32_GPIOF_BASE 0x58021400 -#define STM32_GPIOG_BASE 0x58021800 -#define STM32_GPIOH_BASE 0x58021C00 -#define STM32_GPIOI_BASE 0x58022000 -#define STM32_GPIOJ_BASE 0x58022400 -#define STM32_GPIOK_BASE 0x58022800 - -#define STM32_IWDG_BASE 0x58004800 - -#define STM32_LPTIM1_BASE 0x40002400 -#define STM32_LPTIM2_BASE 0x58002400 -#define STM32_LPTIM3_BASE 0x58002800 -#define STM32_LPTIM4_BASE 0x58002C00 -#define STM32_LPTIM5_BASE 0x58003000 - -#define STM32_PWR_BASE 0x58024800 -#define STM32_RCC_BASE 0x58024400 -#define STM32_RNG_BASE 0x48021800 -#define STM32_RTC_BASE 0x58004000 - -#define STM32_SYSCFG_BASE 0x58000400 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 -#define STM32_SPI4_BASE 0x40013400 -#define STM32_SPI5_BASE 0x40015000 - -#define STM32_TIM1_BASE 0x40010000 -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM8_BASE 0x40010400 -#define STM32_TIM12_BASE 0x40001800 -#define STM32_TIM13_BASE 0x40001c00 -#define STM32_TIM14_BASE 0x40002000 -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 - -#define STM32_UNIQUE_ID_BASE 0x1ff1e800 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 -#define STM32_USART7_BASE 0x40007800 -#define STM32_USART8_BASE 0x40007C00 - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_CR3_BYPASS BIT(0) -#define STM32_PWR_CR3_LDOEN BIT(1) -#define STM32_PWR_CR3_SCUEN BIT(2) -#define STM32_PWR_CR3_VBE BIT(8) -#define STM32_PWR_CR3_VBRS BIT(9) -#define STM32_PWR_CR3_USB33DEN BIT(24) -#define STM32_PWR_CR3_USBREGEN BIT(25) -#define STM32_PWR_CR3_USB33RDY BIT(26) -#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) -#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) -#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) -#define STM32_PWR_CPUCR_STOPF BIT(5) -#define STM32_PWR_CPUCR_SBF BIT(6) -#define STM32_PWR_CPUCR_SBF_D1 BIT(7) -#define STM32_PWR_CPUCR_SBF_D2 BIT(8) -#define STM32_PWR_CPUCR_CSSF BIT(9) -#define STM32_PWR_CPUCR_RUN_D3 BIT(11) -#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_D3CR_VOS1 (3 << 14) -#define STM32_PWR_D3CR_VOS2 (2 << 14) -#define STM32_PWR_D3CR_VOS3 (1 << 14) -#define STM32_PWR_D3CR_VOSMASK (3 << 14) -#define STM32_PWR_D3CR_VOSRDY (1 << 13) -#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) -#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) -#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) -#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) -#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) -#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) -#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) -#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) -#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) -#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) -#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) -#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) -#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) -#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) -#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) -#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) -#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) - -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) - -#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_HASHEN BIT(5) -#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) -#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) -#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff -#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) -#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) -#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) -#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) -#define STM32_RCC_SYSCFGEN BIT(1) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) -#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) -#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) -#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) -#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) -#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) -/* Aliases */ -#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR - -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(2) -#define STM32_RCC_CR_CSION BIT(7) -#define STM32_RCC_CR_CSIRDY BIT(8) -#define STM32_RCC_CR_HSI48ON BIT(12) -#define STM32_RCC_CR_HSI48RDY BIT(13) -#define STM32_RCC_CR_PLL1ON BIT(24) -#define STM32_RCC_CR_PLL1RDY BIT(25) -#define STM32_RCC_CR_PLL2ON BIT(26) -#define STM32_RCC_CR_PLL2RDY BIT(27) -#define STM32_RCC_CR_PLL3ON BIT(28) -#define STM32_RCC_CR_PLL3RDY BIT(29) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_CSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 3) -#define STM32_RCC_CFGR_SWS_CSI (1 << 3) -#define STM32_RCC_CFGR_SWS_HSE (2 << 3) -#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) -#define STM32_RCC_CFGR_SWS_MASK (3 << 3) -#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) -#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) -#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) -#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) -#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) -#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) -#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) -#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) -#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) -#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) -#define STM32_RCC_PLLDIV_DIVN(n) (((n) - 1) << 0) -#define STM32_RCC_PLLDIV_DIVP(p) (((p) - 1) << 9) -#define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) -#define STM32_RCC_PLLDIV_DIVR(r) (((r) - 1) << 24) -#define STM32_RCC_PLLFRAC(n) ((n) << 3) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) -#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) -#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) -#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) -#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - -/* Peripheral bits for APB1ENR regs */ -#define STM32_RCC_PB1_LPTIM1 BIT(9) - -/* Peripheral bits for APB2ENR regs */ -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM2 BIT(1) -#define STM32_RCC_PB2_USART1 BIT(4) -#define STM32_RCC_PB2_SPI1 BIT(12) -#define STM32_RCC_PB2_SPI4 BIT(13) -#define STM32_RCC_PB2_TIM15 BIT(16) -#define STM32_RCC_PB2_TIM16 BIT(17) -#define STM32_RCC_PB2_TIM17 BIT(18) - -/* Peripheral bits for AHB1/2/3/4ENR regs */ -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB3_MDMA BIT(0) -#define STM32_RCC_HB4_BDMA BIT(21) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_RSR -#define RESET_CAUSE_WDG 0x14000000 -#define RESET_CAUSE_SFT 0x01000000 -#define RESET_CAUSE_POR 0x00800000 -#define RESET_CAUSE_PIN 0x00400000 -#define RESET_CAUSE_OTHER 0xfffe0000 -#define RESET_CAUSE_RMVF 0x00010000 -/* Power cause in PWR CPUCR register (Standby&Stop modes) */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR -#define RESET_CAUSE_SBF 0x00000040 -#define RESET_CAUSE_SBF_CLR 0x00000200 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint32_t cr1; - uint32_t cr2; - uint32_t cfg1; - uint32_t cfg2; - uint32_t ier; - uint32_t sr; - uint32_t ifcr; - uint32_t _pad0; - uint32_t txdr; - uint32_t _pad1[3]; - uint32_t rxdr; - uint32_t _pad2[3]; - uint32_t crcpoly; - uint32_t rxcrcr; - uint32_t txcrcr; - uint32_t udrdr; -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_SPE BIT(0) -#define STM32_SPI_CR1_CSTART BIT(9) -#define STM32_SPI_CR1_SSI BIT(12) -#define STM32_SPI_CR1_DIV(div) ((div) << 28) -#define STM32_SPI_CFG1_DATASIZE(n) (((n) - 1) << 0) -#define STM32_SPI_CFG1_FTHLV(n) (((n) - 1) << 5) -#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) -#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) -#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) -#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) -#define STM32_SPI_CFG1_RXDMAEN BIT(14) -#define STM32_SPI_CFG1_TXDMAEN BIT(15) -#define STM32_SPI_CFG1_CRCSIZE(n) (((n) - 1) << 16) -#define STM32_SPI_CFG2_MSTR BIT(22) -#define STM32_SPI_CFG2_SSM BIT(26) -#define STM32_SPI_CFG2_AFCNTR BIT(31) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_UDR BIT(5) -#define STM32_SPI_SR_FRLVL (3 << 13) -#define STM32_SPI_SR_TXC BIT(12) - -/* --- Debug --- */ -#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) -#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) -#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) -#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) -/* Alias */ -#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ - -/* --- Flash --- */ -#define STM32_FLASH_REG(bank, offset) REG32(((bank) ? 0x100 : 0) + \ - STM32_FLASH_REGS_BASE + (offset)) - -#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4) - -#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) -#define FLASH_CR_LOCK BIT(0) -#define FLASH_CR_PG BIT(1) -#define FLASH_CR_SER BIT(2) -#define FLASH_CR_BER BIT(3) -#define FLASH_CR_PSIZE_BYTE (0 << 4) -#define FLASH_CR_PSIZE_HWORD (1 << 4) -#define FLASH_CR_PSIZE_WORD (2 << 4) -#define FLASH_CR_PSIZE_DWORD (3 << 4) -#define FLASH_CR_PSIZE_MASK (3 << 4) -#define FLASH_CR_FW BIT(6) -#define FLASH_CR_STRT BIT(7) -#define FLASH_CR_SNB(sec) (((sec) & 0x7) << 8) -#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) -#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_WBNE BIT(1) -#define FLASH_SR_QW BIT(2) -#define FLASH_SR_CRC_BUSY BIT(3) -#define FLASH_SR_EOP BIT(16) -#define FLASH_SR_WRPERR BIT(17) -#define FLASH_SR_PGSERR BIT(18) -#define FLASH_SR_STRBERR BIT(19) -#define FLASH_SR_INCERR BIT(21) -#define FLASH_SR_OPERR BIT(22) -#define FLASH_SR_RDPERR BIT(23) -#define FLASH_SR_RDSERR BIT(24) -#define FLASH_SR_SNECCERR BIT(25) -#define FLASH_SR_DBECCERR BIT(26) -#define FLASH_SR_CRCEND BIT(27) -#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) -#define FLASH_CCR_ERR_MASK (FLASH_SR_WRPERR | FLASH_SR_PGSERR \ - | FLASH_SR_STRBERR | FLASH_SR_INCERR \ - | FLASH_SR_OPERR | FLASH_SR_RDPERR \ - | FLASH_SR_RDSERR | FLASH_SR_SNECCERR \ - | FLASH_SR_DBECCERR) -#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) -#define FLASH_OPTCR_OPTLOCK BIT(0) -#define FLASH_OPTCR_OPTSTART BIT(1) -#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) -#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) -#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ -#define FLASH_OPTSR_RDP_MASK (0xFF << 8) -#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) -/* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) -#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) -#define FLASH_OPTSR_RSS1 BIT(26) -#define FLASH_OPTSR_RSS2 BIT(27) -#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) -#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) -#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) -#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) -#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) -#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) -#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) -#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) -#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) -#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) -#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) -#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) -#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) -#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) - -/* --- External Interrupts --- */ -#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) -#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) -#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) -#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) -#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) -#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) -#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) -#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) -#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) -#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) -#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) -#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) -#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) -#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) -#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) -#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) -#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) -#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) -#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) -#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) -#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) -#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) -#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) -/* Aliases */ -#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 -#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 -#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 -#define STM32_EXTI_PR STM32_EXTI_CPUPR1 - - -/* --- ADC --- */ - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, - - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1, - - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - -/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */ -/* DMAMUX1/2 registers */ -#define DMAMUX1 0 -#define DMAMUX2 1 -#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE \ - : STM32_DMAMUX1_BASE) -#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) -#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) -#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) -#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) -#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) -#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) -#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) - -enum dmamux1_request { - DMAMUX1_REQ_ADC1 = 9, - DMAMUX1_REQ_ADC2 = 10, - DMAMUX1_REQ_TIM1_CH1 = 11, - DMAMUX1_REQ_TIM1_CH2 = 12, - DMAMUX1_REQ_TIM1_CH3 = 13, - DMAMUX1_REQ_TIM1_CH4 = 14, - DMAMUX1_REQ_TIM1_UP = 15, - DMAMUX1_REQ_TIM1_TRIG = 16, - DMAMUX1_REQ_TIM1_COM = 17, - DMAMUX1_REQ_TIM2_CH1 = 18, - DMAMUX1_REQ_TIM2_CH2 = 19, - DMAMUX1_REQ_TIM2_CH3 = 20, - DMAMUX1_REQ_TIM2_CH4 = 21, - DMAMUX1_REQ_TIM2_UP = 22, - DMAMUX1_REQ_TIM3_CH1 = 23, - DMAMUX1_REQ_TIM3_CH2 = 24, - DMAMUX1_REQ_TIM3_CH3 = 25, - DMAMUX1_REQ_TIM3_CH4 = 26, - DMAMUX1_REQ_TIM3_UP = 27, - DMAMUX1_REQ_TIM3_TRIG = 28, - DMAMUX1_REQ_TIM4_CH1 = 29, - DMAMUX1_REQ_TIM4_CH2 = 30, - DMAMUX1_REQ_TIM4_CH3 = 31, - DMAMUX1_REQ_TIM4_UP = 32, - DMAMUX1_REQ_I2C1_RX = 33, - DMAMUX1_REQ_I2C1_TX = 34, - DMAMUX1_REQ_I2C2_RX = 35, - DMAMUX1_REQ_I2C2_TX = 36, - DMAMUX1_REQ_SPI1_RX = 37, - DMAMUX1_REQ_SPI1_TX = 38, - DMAMUX1_REQ_SPI2_RX = 39, - DMAMUX1_REQ_SPI2_TX = 40, - DMAMUX1_REQ_USART1_RX = 41, - DMAMUX1_REQ_USART1_TX = 42, - DMAMUX1_REQ_USART2_RX = 43, - DMAMUX1_REQ_USART2_TX = 44, - DMAMUX1_REQ_USART3_RX = 45, - DMAMUX1_REQ_USART3_TX = 46, - DMAMUX1_REQ_TIM8_CH1 = 47, - DMAMUX1_REQ_TIM8_CH2 = 48, - DMAMUX1_REQ_TIM8_CH3 = 49, - DMAMUX1_REQ_TIM8_CH4 = 50, - DMAMUX1_REQ_TIM8_UP = 51, - DMAMUX1_REQ_TIM8_TRIG = 52, - DMAMUX1_REQ_TIM8_COM = 53, - DMAMUX1_REQ_TIM5_CH1 = 55, - DMAMUX1_REQ_TIM5_CH2 = 56, - DMAMUX1_REQ_TIM5_CH3 = 57, - DMAMUX1_REQ_TIM5_CH4 = 58, - DMAMUX1_REQ_TIM5_UP = 59, - DMAMUX1_REQ_TIM5_TRIG = 60, - DMAMUX1_REQ_SPI3_RX = 61, - DMAMUX1_REQ_SPI3_TX = 62, - DMAMUX1_REQ_UART4_RX = 63, - DMAMUX1_REQ_UART4_TX = 64, - DMAMUX1_REQ_USART5_RX = 65, - DMAMUX1_REQ_UART5_TX = 66, - DMAMUX1_REQ_DAC1 = 67, - DMAMUX1_REQ_DAC2 = 68, - DMAMUX1_REQ_TIM6_UP = 69, - DMAMUX1_REQ_TIM7_UP = 70, - DMAMUX1_REQ_USART6_RX = 71, - DMAMUX1_REQ_USART6_TX = 72, - DMAMUX1_REQ_I2C3_RX = 73, - DMAMUX1_REQ_I2C3_TX = 74, - DMAMUX1_REQ_DCMI = 75, - DMAMUX1_REQ_CRYP_IN = 76, - DMAMUX1_REQ_CRYP_OUT = 77, - DMAMUX1_REQ_HASH_IN = 78, - DMAMUX1_REQ_UART7_RX = 79, - DMAMUX1_REQ_UART7_TX = 80, - DMAMUX1_REQ_UART8_RX = 81, - DMAMUX1_REQ_UART8_TX = 82, - DMAMUX1_REQ_SPI4_RX = 83, - DMAMUX1_REQ_SPI4_TX = 84, - DMAMUX1_REQ_SPI5_RX = 85, - DMAMUX1_REQ_SPI5_TX = 86, - DMAMUX1_REQ_SAI1_A = 87, - DMAMUX1_REQ_SAI1_B = 88, - DMAMUX1_REQ_SAI2_A = 89, - DMAMUX1_REQ_SAI2_B = 90, - DMAMUX1_REQ_SWPMI_RX = 91, - DMAMUX1_REQ_SWPMI_TX = 92, - DMAMUX1_REQ_SPDIFRX_DT = 93, - DMAMUX1_REQ_SPDIFRX_CS = 94, - DMAMUX1_REQ_TIM15_CH1 = 105, - DMAMUX1_REQ_TIM15_UP = 106, - DMAMUX1_REQ_TIM15_TRIG = 107, - DMAMUX1_REQ_TIM15_COM = 108, - DMAMUX1_REQ_TIM16_CH1 = 109, - DMAMUX1_REQ_TIM16_UP = 110, - DMAMUX1_REQ_TIM17_CH1 = 111, - DMAMUX1_REQ_TIM17_UP = 112, - DMAMUX1_REQ_SAI3_A = 113, - DMAMUX1_REQ_SAI3_B = 114, - DMAMUX1_REQ_ADC3 = 115, -}; - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h deleted file mode 100644 index 37b31ac302..0000000000 --- a/chip/stm32/registers-stm32l.h +++ /dev/null @@ -1,871 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32L family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32L100 - * - STM32L15X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40007C00 - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ -#define STM32_GPIOG_BASE 0x40021C00 -#define STM32_GPIOH_BASE 0x40021400 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1ff80000 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ -#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ -#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) -/* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) - -/* --- GPIO --- */ - - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_MSION BIT(8) -#define STM32_RCC_CR_MSIRDY BIT(9) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) - -#define STM32_RCC_HB_DMA1 BIT(24) -#define STM32_RCC_PB2_TIM9 BIT(2) -#define STM32_RCC_PB2_TIM10 BIT(3) -#define STM32_RCC_PB2_TIM11 BIT(4) -#define STM32_RCC_PB1_USB BIT(23) - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(1) -#define STM32_FLASH_ACR_ACC64 BIT(2) -#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_PECR_PE_LOCK BIT(0) -#define STM32_FLASH_PECR_PRG_LOCK BIT(1) -#define STM32_FLASH_PECR_OPT_LOCK BIT(2) -#define STM32_FLASH_PECR_PROG BIT(3) -#define STM32_FLASH_PECR_ERASE BIT(9) -#define STM32_FLASH_PECR_FPRG BIT(10) -#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF -#define STM32_FLASH_PEKEYR_KEY2 0x02030405 -#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF -#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 -#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP 0x00 -#define STM32_OPTB_USER 0x04 -#define STM32_OPTB_WRP1L 0x08 -#define STM32_OPTB_WRP1H 0x0c -#define STM32_OPTB_WRP2L 0x10 -#define STM32_OPTB_WRP2H 0x14 -#define STM32_OPTB_WRP3L 0x18 -#define STM32_OPTB_WRP3H 0x1c - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) -#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) -#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) -#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) -#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) - -#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) - -#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) -#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) -#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) -#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) -#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) -#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) -#define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21) -#define STM32_COMP_OUTSEL_NONE (7 << 21) - -#define STM32_COMP_INSEL_NONE (0 << 18) -#define STM32_COMP_INSEL_PB3 (1 << 18) -#define STM32_COMP_INSEL_VREF (2 << 18) -#define STM32_COMP_INSEL_VREF34 (3 << 18) -#define STM32_COMP_INSEL_VREF12 (4 << 18) -#define STM32_COMP_INSEL_VREF14 (5 << 18) -#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) -#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) - -#define STM32_COMP_WNDWE BIT(17) -#define STM32_COMP_VREFOUTEN BIT(16) -#define STM32_COMP_CMP2OUT BIT(13) -#define STM32_COMP_SPEED_FAST BIT(12) - -#define STM32_COMP_CMP1OUT BIT(7) -#define STM32_COMP_CMP1EN BIT(4) - -#define STM32_COMP_400KPD BIT(3) -#define STM32_COMP_10KPD BIT(2) -#define STM32_COMP_400KPU BIT(1) -#define STM32_COMP_10KPU BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#define STM32_DMA_REGS(channel) STM32_DMA1_REGS - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h deleted file mode 100644 index e775dfe8a3..0000000000 --- a/chip/stm32/registers-stm32l4.h +++ /dev/null @@ -1,956 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32L4 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32L442 - * - STM32L476 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_MSION BIT(0) -#define STM32_RCC_CR_MSIRDY BIT(1) -#define STM32_RCC_CR_HSION BIT(8) -#define STM32_RCC_CR_HSIRDY BIT(10) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_PLLCFGR_PLLSRC_SHIFT (0) -#define STM32_RCC_PLLCFGR_PLLSRC_NONE (0 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_MSI (1 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_HSI (2 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE (3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_MASK (3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLM_SHIFT (4) -#define STM32_RCC_PLLCFGR_PLLM_MASK (0x7 << STM32_RCC_PLLCFGR_PLLM_SHIFT) -#define STM32_RCC_PLLCFGR_PLLN_SHIFT (8) -#define STM32_RCC_PLLCFGR_PLLN_MASK (0x7f << STM32_RCC_PLLCFGR_PLLN_SHIFT) -#define STM32_RCC_PLLCFGR_PLLREN_SHIFT (24) -#define STM32_RCC_PLLCFGR_PLLREN_MASK (1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT) -#define STM32_RCC_PLLCFGR_PLLR_SHIFT (25) -#define STM32_RCC_PLLCFGR_PLLR_MASK (3 << STM32_RCC_PLLCFGR_PLLR_SHIFT) - -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB2ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB2ENR_RNGEN BIT(18) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) -#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) -#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) -#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) -#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) -#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) -#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) -#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) -#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) -#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) - -/* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) - -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) - -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) - -#define STM32_RCC_CRRCR_HSI48ON BIT(0) -#define STM32_RCC_CRRCR_HSI48RDY BIT(1) -#define STM32_RCC_CRRCR_HSI48CAL_MASK (0x1ff << 7) - -#define STM32_RCC_PB2_TIM1 BIT(11) -#define STM32_RCC_PB2_TIM8 BIT(13) - -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) -#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) -#define FLASH_WRP_START(val) ((val) & 0xff) -#define FLASH_WRP_END(val) (((val) >> 16) & 0xff) -#define FLASH_WRP_RANGE(strt, end) (((end) << 16) | (strt)) -#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(0xFF, 0x00) -#define FLASH_WRP_MASK FLASH_WRP_RANGE(0xFF, 0xFF) - -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - - -/* --- ADC --- */ - -/* --- Comparators --- */ - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - STM32_DMAC_COUNT = 14, -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h deleted file mode 100644 index 08b9d61e20..0000000000 --- a/chip/stm32/registers.h +++ /dev/null @@ -1,483 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32 family of chips - * - * This header file should only contain register definitions and - * functionality that are common to all STM32 chips. - * Any chip/family specific macros must be placed in their family - * specific registers file, which is conditionally included at the - * end of this file. - * Include this file directly for all STM32 register definitions. - * - * ### History and Reasoning ### - * In a time before chip family register file separation, - * long long ago, there lived a single file called `registers.h`, - * which housed register definitions for all STM32 chip family and variants. - * This poor file was 3000 lines of register macros and C definitions, - * swiss-cheesed by nested preprocessor conditional logic. - * Adding a single new chip variant required splitting multiple, - * already nested, conditional sections throughout the file. - * Readability was on the difficult side and refactoring was dangerous. - * - * The number of STM32 variants had outgrown the single registers file model. - * The minor gains of sharing a set of registers between a subset of chip - * variants no longer outweighed the complexity of the following operations: - * - Adding a new chip variant or variant feature - * - Determining if a register was properly setup for a variant or if it - * was simply not unset - * - * To strike a balance between shared registers and chip specific registers, - * the registers.h file remains a place for common definitions, but family - * specific definitions were moved to their own files. - * These family specific files contain a much reduced level of preprocessor - * logic for variant specific registers. - * - * See https://crrev.com/c/1674679 to witness the separation steps. - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) -#define STM32_USART_REG(base, offset) REG32((base) + (offset)) - -#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) - -/* --- TIMERS --- */ -#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) - -#define STM32_TIM_REG(n, offset) \ - REG16(STM32_TIM_BASE(n) + (offset)) -#define STM32_TIM_REG32(n, offset) \ - REG32(STM32_TIM_BASE(n) + (offset)) - -#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN BIT(0) -#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) -#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) -#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) -#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) -#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG BIT(0) -#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE BIT(2) -/* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ -#define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) -#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) -#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) -#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) -#define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2) -#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) -#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) -#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) -#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) -#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) -#define STM32_TIM_CCER_CC1E BIT(0) -#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) -#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) -#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) -#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) -#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) -#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) -#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) -#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) -#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE BIT(15) -#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) -#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) -#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) - -#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4) - -#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) -#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) -#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) -#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) -#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) -#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) -/* Timer registers as struct */ -struct timer_ctlr { - unsigned cr1; - unsigned cr2; - unsigned smcr; - unsigned dier; - - unsigned sr; - unsigned egr; - unsigned ccmr1; - unsigned ccmr2; - - unsigned ccer; - unsigned cnt; - unsigned psc; - unsigned arr; - - unsigned ccr[5]; /* ccr[0] = reserved30 */ - - unsigned bdtr; - unsigned dcr; - unsigned dmar; - - unsigned or; -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct timer_ctlr timer_ctlr_t; - -/* --- Low power timers --- */ -#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) - -#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) - -#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) -#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) -#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN BIT(6) -#define STM32_LPTIM_INT_UP BIT(5) -#define STM32_LPTIM_INT_ARROK BIT(4) -#define STM32_LPTIM_INT_CMPOK BIT(3) -#define STM32_LPTIM_INT_EXTTRIG BIT(2) -#define STM32_LPTIM_INT_ARRM BIT(1) -#define STM32_LPTIM_INT_CMPM BIT(0) -#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) -#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE BIT(4) -#define STM32_LPTIM_CR_COUNTRST BIT(3) -#define STM32_LPTIM_CR_CNTSTRT BIT(2) -#define STM32_LPTIM_CR_SNGSTRT BIT(1) -#define STM32_LPTIM_CR_ENABLE BIT(0) -#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) -#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) -#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) -#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) - -/* --- GPIO --- */ - -#define GPIO_A STM32_GPIOA_BASE -#define GPIO_B STM32_GPIOB_BASE -#define GPIO_C STM32_GPIOC_BASE -#define GPIO_D STM32_GPIOD_BASE -#define GPIO_E STM32_GPIOE_BASE -#define GPIO_F STM32_GPIOF_BASE -#define GPIO_G STM32_GPIOG_BASE -#define GPIO_H STM32_GPIOH_BASE -#define GPIO_I STM32_GPIOI_BASE -#define GPIO_J STM32_GPIOJ_BASE -#define GPIO_K STM32_GPIOK_BASE - -#define DUMMY_GPIO_BANK GPIO_A - - -/* --- I2C --- */ -#define STM32_I2C1_PORT 0 -#define STM32_I2C2_PORT 1 -#define STM32_I2C3_PORT 2 -#define STM32_FMPI2C4_PORT 3 - -#define stm32_i2c_reg(port, offset) \ - ((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset))) -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR_LPSDSR (1 << 0) -#define STM32_PWR_CR_FLPS (1 << 9) -#define STM32_PWR_CR_SVOS5 (1 << 14) -#define STM32_PWR_CR_SVOS4 (2 << 14) -#define STM32_PWR_CR_SVOS3 (3 << 14) -#define STM32_PWR_CR_SVOS_MASK (3 << 14) - -/* RTC domain control register */ -#define STM32_RCC_BDCR_BDRST BIT(16) -#define STM32_RCC_BDCR_RTCEN BIT(15) -#define STM32_RCC_BDCR_LSERDY BIT(1) -#define STM32_RCC_BDCR_LSEON BIT(0) -#define BDCR_RTCSEL_MASK ((0x3) << 8) -#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) -#define BDCR_SRC_LSE 0x1 -#define BDCR_SRC_LSI 0x2 -#define BDCR_SRC_HSE 0x3 -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_TIM2 BIT(0) -#define STM32_RCC_PB1_TIM3 BIT(1) -#define STM32_RCC_PB1_TIM4 BIT(2) -#define STM32_RCC_PB1_TIM5 BIT(3) -#define STM32_RCC_PB1_TIM6 BIT(4) -#define STM32_RCC_PB1_TIM7 BIT(5) -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ -#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ -#define STM32_RCC_PB1_WWDG BIT(11) -#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ -#define STM32_RCC_PB1_SPI2 BIT(14) -#define STM32_RCC_PB1_SPI3 BIT(15) -#define STM32_RCC_PB1_USART2 BIT(17) -#define STM32_RCC_PB1_USART3 BIT(18) -#define STM32_RCC_PB1_USART4 BIT(19) -#define STM32_RCC_PB1_USART5 BIT(20) -#define STM32_RCC_PB2_SPI1 BIT(12) -/* Reset causes definitions */ - -/* --- Watchdogs --- */ - -#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) -#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) -#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) - -#define STM32_WWDG_TB_8 (3 << 7) -#define STM32_WWDG_EWI BIT(9) - -#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) -#define STM32_IWDG_KR_UNLOCK 0x5555 -#define STM32_IWDG_KR_RELOAD 0xaaaa -#define STM32_IWDG_KR_START 0xcccc -#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) -#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) -#define STM32_IWDG_RLR_MAX 0x0fff -#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) -#define STM32_IWDG_SR_WVU BIT(2) -#define STM32_IWDG_SR_RVU BIT(1) -#define STM32_IWDG_SR_PVU BIT(0) -#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) - -/* --- Real-Time Clock --- */ -/* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) -/* --- Routing interface --- */ -/* STM32L1xx only */ -#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) -#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) -#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) -#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) -#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) -#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) -#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) -#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) -#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) -#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) -#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) -#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) -#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) -#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) -#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) -#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) -#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) -#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) -#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) -#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) -#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) - -/* --- DAC --- */ -#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) -#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) -#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) -#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) -#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) -#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) -#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) -#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) -#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) -#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) -#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) -#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) -#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) -#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) - -#define STM32_DAC_CR_DMAEN2 BIT(28) -#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) -#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) -#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) -#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) -#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) -#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) -#define STM32_DAC_CR_TSEL2_MASK (7 << 19) -#define STM32_DAC_CR_TEN2 BIT(18) -#define STM32_DAC_CR_BOFF2 BIT(17) -#define STM32_DAC_CR_EN2 BIT(16) -#define STM32_DAC_CR_DMAEN1 BIT(12) -#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) -#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) -#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) -#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) -#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) -#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) -#define STM32_DAC_CR_TSEL1_MASK (7 << 3) -#define STM32_DAC_CR_TEN1 BIT(2) -#define STM32_DAC_CR_BOFF1 BIT(1) -#define STM32_DAC_CR_EN1 BIT(0) -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ - -#if defined(CHIP_FAMILY_STM32F0) -#include "registers-stm32f0.h" -#elif defined(CHIP_FAMILY_STM32F3) -#include "registers-stm32f3.h" -#elif defined(CHIP_FAMILY_STM32F4) -#include "registers-stm32f4.h" -#elif defined(CHIP_FAMILY_STM32F7) -#include "registers-stm32f7.h" -#elif defined(CHIP_FAMILY_STM32H7) -#include "registers-stm32h7.h" -#elif defined(CHIP_FAMILY_STM32L) -#include "registers-stm32l.h" -#elif defined(CHIP_FAMILY_STM32L4) -#include "registers-stm32l4.h" -#else -#error "Unsupported chip family" -#endif - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c deleted file mode 100644 index 78ff064dbd..0000000000 --- a/chip/stm32/spi.c +++ /dev/null @@ -1,742 +0,0 @@ -/* - * Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI driver for Chrome EC. - * - * This uses DMA to handle transmission and reception. - */ - -#include "chipset.h" -#include "clock.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "link_defs.h" -#include "registers.h" -#include "spi.h" -#include "stm32-dma.h" -#include "system.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) - -/* SPI FIFO registers */ -#ifdef CHIP_FAMILY_STM32H7 -#define SPI_TXDR REG8(&STM32_SPI1_REGS->txdr) -#define SPI_RXDR REG8(&STM32_SPI1_REGS->rxdr) -#else -#define SPI_TXDR STM32_SPI1_REGS->dr -#define SPI_RXDR STM32_SPI1_REGS->dr -#endif - -/* DMA channel option */ -static const struct dma_option dma_tx_option = { - STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) -#endif -}; - -static const struct dma_option dma_rx_option = { - STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) -#endif -}; - -/* - * Timeout to wait for SPI request packet - * - * This affects the slowest SPI clock we can support. A delay of 8192 us - * permits a 512-byte request at 500 KHz, assuming the master starts sending - * bytes as soon as it asserts chip select. That's as slow as we would - * practically want to run the SPI interface, since running it slower - * significantly impacts firmware update times. - */ -#define SPI_CMD_RX_TIMEOUT_US 8192 - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/* - * Offset of output parameters needs to account for pad and framing bytes and - * one last past-end byte at the end so any additional bytes clocked out by - * the AP will have a known and identifiable value. - */ -#define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2) -#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ -/* - * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size, and 512 bytes - * of flash data. - */ -#define SPI_MAX_REQUEST_SIZE 0x220 -#define SPI_MAX_RESPONSE_SIZE 0x220 - -/* - * The AP blindly clocks back bytes over the SPI interface looking for a - * framing byte. So this preamble must always precede the actual response - * packet. Search for "spi-frame-header" in U-boot to see how that's - * implemented. - * - * The preamble must be 32-bit aligned so that the response buffer is also - * 32-bit aligned. - */ -static const uint8_t out_preamble[4] = { - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_FRAME_START, /* This is the byte which matters */ -}; - -/* - * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg - * buffer. This seems to be dynamic because the F0 family needs to send it 4 - * times in order to make sure it actually stays at the repeating byte after DMA - * ends. - * - * See crosbug.com/p/31390 - */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) -#define EC_SPI_PAST_END_LENGTH 4 -#else -#define EC_SPI_PAST_END_LENGTH 1 -#endif - -/* - * Our input and output buffers. These must be large enough for our largest - * message, including protocol overhead, and must be 32-bit aligned. - */ -static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) + - EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; -static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached; -static uint8_t enabled; -#ifdef CONFIG_SPI_PROTOCOL_V2 -static struct host_cmd_handler_args args; -#endif -static struct host_packet spi_packet; - -/* - * This is set if SPI NSS raises to high while EC is still processing a - * command. - */ -static int setup_transaction_later; - -enum spi_state { - /* SPI not enabled (initial state, and when chipset is off) */ - SPI_STATE_DISABLED = 0, - - /* Setting up receive DMA */ - SPI_STATE_PREPARE_RX, - - /* Ready to receive next request */ - SPI_STATE_READY_TO_RX, - - /* Receiving request */ - SPI_STATE_RECEIVING, - - /* Processing request */ - SPI_STATE_PROCESSING, - - /* Sending response */ - SPI_STATE_SENDING, - - /* - * Received bad data - transaction started before we were ready, or - * packet header from host didn't parse properly. Ignoring received - * data. - */ - SPI_STATE_RX_BAD, -} state; - -/** - * Wait until we have received a certain number of bytes - * - * Watch the DMA receive channel until it has the required number of bytes, - * or a timeout occurs - * - * We keep an eye on the NSS line - if this goes high then the transaction is - * over so there is no point in trying to receive the bytes. - * - * @param rxdma RX DMA channel to watch - * @param needed Number of bytes that are needed - * @param nss GPIO signal for NSS control line - * @return 0 if bytes received, -1 if we hit a timeout or NSS went high - */ -static int wait_for_bytes(dma_chan_t *rxdma, int needed, - enum gpio_signal nss) -{ - timestamp_t deadline; - - ASSERT(needed <= sizeof(in_msg)); - deadline.val = 0; - while (1) { - if (dma_bytes_done(rxdma, sizeof(in_msg)) >= needed) - return 0; - if (gpio_get_level(nss)) - return -1; - if (!deadline.val) { - deadline = get_time(); - deadline.val += SPI_CMD_RX_TIMEOUT_US; - } - if (timestamp_expired(deadline, NULL)) - return -1; - } -} - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/** - * Send a reply on a given port. - * - * The format of a reply is as per the command interface, with a number of - * preamble bytes before it. - * - * The format of a reply is a sequence of bytes: - * - * <hdr> <status> <len> <msg bytes> <sum> [<preamble byte>...] - * - * The hdr byte is just a tag to indicate that the real message follows. It - * signals the end of any preamble required by the interface. - * - * The length is the entire packet size, including the header, length bytes, - * message payload, checksum, and postamble byte. - * - * The preamble is at least 2 bytes, but can be longer if the STM takes ages - * to react to the incoming message. Since we send our first byte as the AP - * sends us the command, we clearly can't send anything sensible for that - * byte. The second byte must be written to the output register just when the - * command byte is ready (I think), so we can't do anything there either. - * Any processing we do may increase this delay. That's the reason for the - * preamble. - * - * It is interesting to note that it seems to be possible to run the SPI - * interface faster than the CPU clock with this approach. - * - * We keep an eye on the NSS line - if this goes high then the transaction is - * over so there is no point in trying to send the reply. - * - * @param txdma TX DMA channel to send on - * @param status Status result to send - * @param msg_ptr Message payload to send, which normally starts - * SPI_PROTO2_OFFSET bytes into out_msg - * @param msg_len Number of message bytes to send - */ -static void reply(dma_chan_t *txdma, - enum ec_status status, char *msg_ptr, int msg_len) -{ - char *msg = out_msg; - int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET; - int sum, i; - - ASSERT(msg_len + SPI_PROTO2_OVERHEAD <= sizeof(out_msg)); - - /* Add our header bytes - the first one might not actually be sent */ - msg[0] = EC_SPI_PROCESSING; - msg[1] = EC_SPI_FRAME_START; - msg[2] = status; - msg[3] = msg_len & 0xff; - - /* - * Calculate the checksum; includes the status and message length bytes - * but not the pad and framing bytes since those are stripped by the AP - * driver. - */ - sum = status + msg_len; - for (i = 0; i < msg_len; i++) { - int ch = msg_ptr[i]; - sum += ch; - if (need_copy) - msg[i + SPI_PROTO2_OFFSET] = ch; - } - - /* Add the checksum and get ready to send */ - msg[SPI_PROTO2_OFFSET + msg_len] = sum & 0xff; - msg[SPI_PROTO2_OFFSET + msg_len + 1] = EC_SPI_PAST_END; - dma_prepare_tx(&dma_tx_option, msg_len + SPI_PROTO2_OVERHEAD, msg); - - /* Kick off the DMA to send the data */ - dma_go(txdma); -} -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - -/** - * Sends a byte over SPI without DMA - * - * This is mostly used when we want to relay status bytes to the AP while we're - * receiving the message and we're thinking about it. - * - * @note It may be sent 0, 1, or >1 times, depending on whether the host clocks - * the bus or not. Basically, the EC is saying "if you ask me what my status is, - * you'll get this value. But you're not required to ask, or you can ask - * multiple times." - * - * @param byte status byte to send, one of the EC_SPI_* #defines from - * ec_commands.h - */ -static void tx_status(uint8_t byte) -{ - stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS; - - SPI_TXDR = byte; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* It sends the byte 4 times in order to be sure it bypassed the FIFO - * from the STM32F0 line. - */ - spi->dr = byte; - spi->dr = byte; - spi->dr = byte; -#elif defined(CHIP_FAMILY_STM32H7) - spi->udrdr = byte; -#endif -} - -/** - * Get ready to receive a message from the master. - * - * Set up our RX DMA and disable our TX DMA. Set up the data output so that - * we will send preamble bytes. - */ -static void setup_for_transaction(void) -{ - stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS; - volatile uint8_t dummy __attribute__((unused)); - - /* clear this as soon as possible */ - setup_transaction_later = 0; - -#ifndef CHIP_FAMILY_STM32H7 /* H7 is not ready to set status here */ - /* Not ready to receive yet */ - tx_status(EC_SPI_NOT_READY); -#endif - - /* We are no longer actively processing a transaction */ - state = SPI_STATE_PREPARE_RX; - - /* Stop sending response, if any */ - dma_disable(STM32_DMAC_SPI1_TX); - - /* - * Read dummy bytes in case there are some pending; this prevents the - * receive DMA from getting that byte right when we start it. - */ - dummy = SPI_RXDR; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */ - dummy = spi->dr; - dummy = spi->dr; - dummy = spi->dr; -#endif - - /* Start DMA */ - dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg); - - /* Ready to receive */ - state = SPI_STATE_READY_TO_RX; - tx_status(EC_SPI_OLD_READY); - -#ifdef CHIP_FAMILY_STM32H7 - spi->cr1 |= STM32_SPI_CR1_SPE; -#endif -} - -/* Forward declaration */ -static void spi_init(void); - -/* - * If a setup_for_transaction() was postponed, call it now. - * Note that setup_for_transaction() cancels Tx DMA. - */ -static void check_setup_transaction_later(void) -{ - if (setup_transaction_later) { - spi_init(); /* Fix for bug chrome-os-partner:31390 */ - /* - * 'state' is set to SPI_STATE_READY_TO_RX. Somehow AP - * de-asserted the SPI NSS during the handler was running. - * Thus, the pending result will be dropped anyway. - */ - } -} - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/** - * Called for V2 protocol to indicate that a command has completed - * - * Some commands can continue for a while. This function is called by - * host_command when it completes. - * - */ -static void spi_send_response(struct host_cmd_handler_args *args) -{ - enum ec_status result = args->result; - dma_chan_t *txdma; - - /* - * If we're not processing, then the AP has already terminated the - * transaction, and won't be listening for a response. - */ - if (state != SPI_STATE_PROCESSING) - return; - - /* state == SPI_STATE_PROCESSING */ - - if (args->response_size > args->response_max) - result = EC_RES_INVALID_RESPONSE; - - /* Transmit the reply */ - txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - reply(txdma, result, args->response, args->response_size); - - /* - * Before the state is set to SENDING, any CS de-assertion would - * set setup_transaction_later to 1. - */ - state = SPI_STATE_SENDING; - check_setup_transaction_later(); -} -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - -/** - * Called to send a response back to the host. - * - * Some commands can continue for a while. This function is called by - * host_command when it completes. - * - */ -static void spi_send_response_packet(struct host_packet *pkt) -{ - dma_chan_t *txdma; - - /* - * If we're not processing, then the AP has already terminated the - * transaction, and won't be listening for a response. - */ - if (state != SPI_STATE_PROCESSING) - return; - - /* state == SPI_STATE_PROCESSING */ - - /* Append our past-end byte, which we reserved space for. */ - ((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* Make sure we are going to be outputting it properly when the DMA - * ends due to the TX FIFO bug on the F0. See crosbug.com/p/31390 - */ - ((uint8_t *)pkt->response)[pkt->response_size + 1] = EC_SPI_PAST_END; - ((uint8_t *)pkt->response)[pkt->response_size + 2] = EC_SPI_PAST_END; - ((uint8_t *)pkt->response)[pkt->response_size + 3] = EC_SPI_PAST_END; -#endif - - /* Transmit the reply */ - txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size - + EC_SPI_PAST_END_LENGTH, out_msg); - dma_go(txdma); -#ifdef CHIP_FAMILY_STM32H7 - /* clear any previous underrun */ - STM32_SPI1_REGS->ifcr = STM32_SPI_SR_UDR; -#endif /* CHIP_FAMILY_STM32H7 */ - - /* - * Before the state is set to SENDING, any CS de-assertion would - * set setup_transaction_later to 1. - */ - state = SPI_STATE_SENDING; - check_setup_transaction_later(); -} - -/** - * Handle an event on the NSS pin - * - * A falling edge of NSS indicates that the master is starting a new - * transaction. A rising edge indicates that we have finished. - * - * @param signal GPIO signal for the NSS pin - */ -void spi_event(enum gpio_signal signal) -{ - dma_chan_t *rxdma; - uint16_t i; - - /* If not enabled, ignore glitches on NSS */ - if (!enabled) - return; - - /* Check chip select. If it's high, the AP ended a transaction. */ - if (gpio_get_level(GPIO_SPI1_NSS)) { - enable_sleep(SLEEP_MASK_SPI); - - /* - * If the buffer is still used by the host command, postpone - * the DMA rx setup. - */ - if (state == SPI_STATE_PROCESSING) { - setup_transaction_later = 1; - return; - } - - /* Set up for the next transaction */ - spi_init(); /* Fix for bug chrome-os-partner:31390 */ - return; - } - disable_sleep(SLEEP_MASK_SPI); - - /* Chip select is low = asserted */ - if (state != SPI_STATE_READY_TO_RX) { - /* - * AP started a transaction but we weren't ready for it. - * Tell AP we weren't ready, and ignore the received data. - */ - CPRINTS("SPI not ready"); - tx_status(EC_SPI_NOT_READY); - state = SPI_STATE_RX_BAD; - return; - } - - /* We're now inside a transaction */ - state = SPI_STATE_RECEIVING; - tx_status(EC_SPI_RECEIVING); - rxdma = dma_get_channel(STM32_DMAC_SPI1_RX); - - /* Wait for version, command, length bytes */ - if (wait_for_bytes(rxdma, 3, GPIO_SPI1_NSS)) - goto spi_event_error; - - if (in_msg[0] == EC_HOST_REQUEST_VERSION) { - /* Protocol version 3 */ - struct ec_host_request *r = (struct ec_host_request *)in_msg; - int pkt_size; - - /* Wait for the rest of the command header */ - if (wait_for_bytes(rxdma, sizeof(*r), GPIO_SPI1_NSS)) - goto spi_event_error; - - /* - * Check how big the packet should be. We can't just wait to - * see how much data the host sends, because it will keep - * sending dummy data until we respond. - */ - pkt_size = host_request_expected_size(r); - if (pkt_size == 0 || pkt_size > sizeof(in_msg)) - goto spi_event_error; - - /* Wait for the packet data */ - if (wait_for_bytes(rxdma, pkt_size, GPIO_SPI1_NSS)) - goto spi_event_error; - - spi_packet.send_response = spi_send_response_packet; - - spi_packet.request = in_msg; - spi_packet.request_temp = NULL; - spi_packet.request_max = sizeof(in_msg); - spi_packet.request_size = pkt_size; - - /* Response must start with the preamble */ - memcpy(out_msg, out_preamble, sizeof(out_preamble)); - spi_packet.response = out_msg + sizeof(out_preamble); - /* Reserve space for the preamble and trailing past-end byte */ - spi_packet.response_max = sizeof(out_msg) - - sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH; - spi_packet.response_size = 0; - - spi_packet.driver_result = EC_RES_SUCCESS; - - /* Move to processing state */ - state = SPI_STATE_PROCESSING; - tx_status(EC_SPI_PROCESSING); - - host_packet_receive(&spi_packet); - return; - - } else if (in_msg[0] >= EC_CMD_VERSION0) { -#ifdef CONFIG_SPI_PROTOCOL_V2 - /* - * Protocol version 2 - * - * TODO(crosbug.com/p/20257): Remove once kernel supports - * version 3. - */ - -#ifdef CHIP_FAMILY_STM32F0 - CPRINTS("WARNING: Protocol version 2 is not supported on the F0" - " line due to crosbug.com/p/31390"); -#endif - - args.version = in_msg[0] - EC_CMD_VERSION0; - args.command = in_msg[1]; - args.params_size = in_msg[2]; - - /* Wait for parameters */ - if (wait_for_bytes(rxdma, 3 + args.params_size, GPIO_SPI1_NSS)) - goto spi_event_error; - - /* - * Params are not 32-bit aligned in protocol version 2. As a - * workaround, move them to the beginning of the input buffer - * so they are aligned. - */ - if (args.params_size) - memmove(in_msg, in_msg + 3, args.params_size); - - args.params = in_msg; - args.send_response = spi_send_response; - - /* Allow room for the header bytes */ - args.response = out_msg + SPI_PROTO2_OFFSET; - args.response_max = sizeof(out_msg) - SPI_PROTO2_OVERHEAD; - args.response_size = 0; - args.result = EC_RES_SUCCESS; - - /* Move to processing state */ - state = SPI_STATE_PROCESSING; - tx_status(EC_SPI_PROCESSING); - - host_command_received(&args); - return; -#else /* !defined(CONFIG_SPI_PROTOCOL_V2) */ - /* Protocol version 2 is deprecated. */ - CPRINTS("ERROR: Protocol V2 is not supported!"); -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - } - - spi_event_error: - /* Error, timeout, or protocol we can't handle. Ignore data. */ - tx_status(EC_SPI_RX_BAD_DATA); - state = SPI_STATE_RX_BAD; - CPRINTS("SPI rx bad data"); - - CPRINTF("in_msg=["); - for (i = 0; i < dma_bytes_done(rxdma, sizeof(in_msg)); i++) - CPRINTF("%02x ", in_msg[i]); - CPRINTF("]\n"); -} - -static void spi_chipset_startup(void) -{ - /* Enable pullup and interrupts on NSS */ - gpio_set_flags(GPIO_SPI1_NSS, GPIO_INT_BOTH | GPIO_PULL_UP); - - /* Set SPI pins to alternate function */ - gpio_config_module(MODULE_SPI, 1); - - /* Set up for next transaction */ - setup_for_transaction(); - - enabled = 1; -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, spi_chipset_startup, HOOK_PRIO_DEFAULT); - -static void spi_chipset_shutdown(void) -{ - enabled = 0; - state = SPI_STATE_DISABLED; - - /* Disable pullup and interrupts on NSS */ - gpio_set_flags(GPIO_SPI1_NSS, GPIO_INPUT); - - /* Set SPI pins to inputs so we don't leak power when AP is off */ - gpio_config_module(MODULE_SPI, 0); - - /* Allow deep sleep when AP off */ - enable_sleep(SLEEP_MASK_SPI); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, spi_chipset_shutdown, HOOK_PRIO_DEFAULT); - -static void spi_init(void) -{ - stm32_spi_regs_t *spi = STM32_SPI1_REGS; - uint8_t was_enabled = enabled; - - /* Reset the SPI Peripheral to clear any existing weird states. */ - /* Fix for bug chrome-os-partner:31390 */ - enabled = 0; - state = SPI_STATE_DISABLED; - STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1; - STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1; - - /* 40 MHz pin speed */ - STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00; - - /* Enable clocks to SPI1 module */ - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Select the right DMA request for the variants using it. - * This is not required for STM32F4 since the channel (aka request) is - * set directly in the respective dma_option. In fact, it would be - * overridden in dma-stm32f4::prepare_stream(). - */ -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(STM32_DMAC_SPI1_TX, 1); - dma_select_channel(STM32_DMAC_SPI1_RX, 1); -#elif defined(CHIP_FAMILY_STM32H7) - dma_select_channel(STM32_DMAC_SPI1_TX, DMAMUX1_REQ_SPI1_TX); - dma_select_channel(STM32_DMAC_SPI1_RX, DMAMUX1_REQ_SPI1_RX); -#endif - /* - * Enable rx/tx DMA and get ready to receive our first transaction and - * "disable" FIFO by setting event to happen after only 1 byte - */ -#ifdef CHIP_FAMILY_STM32H7 - spi->cfg2 = 0; - spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | - STM32_SPI_CFG1_CRCSIZE(8) | - STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN | - STM32_SPI_CFG1_UDRCFG_CONST | - STM32_SPI_CFG1_UDRDET_BEGIN_FRM; - spi->cr1 = 0; -#else /* !CHIP_FAMILY_STM32H7 */ - spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); - - /* Enable the SPI peripheral */ - spi->cr1 |= STM32_SPI_CR1_SPE; -#endif /* !CHIP_FAMILY_STM32H7 */ - - gpio_enable_interrupt(GPIO_SPI1_NSS); - - /* - * If we were already enabled or chipset is already on, - * prepare for transaction - */ - if (was_enabled || chipset_in_state(CHIPSET_STATE_ON)) - spi_chipset_startup(); -} -DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI); - -/** - * Get protocol information - */ -static enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); -#ifdef CONFIG_SPI_PROTOCOL_V2 - r->protocol_versions |= BIT(2); -#endif - r->protocol_versions |= BIT(3); - r->max_request_packet_size = SPI_MAX_REQUEST_SIZE; - r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE; - r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; - - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - spi_get_protocol_info, - EC_VER_MASK(0)); diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c deleted file mode 100644 index 6f661b72bf..0000000000 --- a/chip/stm32/spi_master-stm32h7.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI master driver. - */ - -#include "common.h" -#include "dma.h" -#include "gpio.h" -#include "shared_mem.h" -#include "spi.h" -#include "stm32-dma.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* SPI ports are used as master */ -static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - STM32_SPI1_REGS, -#endif - STM32_SPI2_REGS, - STM32_SPI3_REGS, - STM32_SPI4_REGS, -}; - -/* DMA request mapping on channels */ -static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER - DMAMUX1_REQ_SPI1_TX, -#endif - DMAMUX1_REQ_SPI2_TX, - DMAMUX1_REQ_SPI3_TX, - DMAMUX1_REQ_SPI4_TX, -}; -static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER - DMAMUX1_REQ_SPI1_RX, -#endif - DMAMUX1_REQ_SPI2_RX, - DMAMUX1_REQ_SPI3_RX, - DMAMUX1_REQ_SPI4_RX, -}; - -static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; - -#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) - -static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -#endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -}; - -static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -#endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -}; - -static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; - -/** - * Initialize SPI module, registers, and clocks - * - * - port: which port to initialize. - */ -static void spi_master_config(int port) -{ - int i, div = 0; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Set SPI master, baud rate, and software slave control. - */ - for (i = 0; i < spi_devices_used; i++) - if ((spi_devices[i].port == port) && - (div < spi_devices[i].div)) - div = spi_devices[i].div; - - spi->cr1 = STM32_SPI_CR1_SSI; - spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM - | STM32_SPI_CFG2_AFCNTR; - spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) - | STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CR1_DIV(div); - - dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]); -} - -static int spi_master_initialize(int port) -{ - int i; - - spi_master_config(port); - - for (i = 0; i < spi_devices_used; i++) { - if (spi_devices[i].port != port) - continue; - /* Drive SS high */ - gpio_set_level(spi_devices[i].gpio_cs, 1); - } - - /* Set flag */ - spi_enabled[port] = 1; - - return EC_SUCCESS; -} - -/** - * Shutdown SPI module - */ -static int spi_master_shutdown(int port) -{ - int rv = EC_SUCCESS; - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* Set flag */ - spi_enabled[port] = 0; - - /* Disable DMA streams */ - dma_disable(dma_tx_option[port].channel); - dma_disable(dma_rx_option[port].channel); - - /* Disable SPI */ - spi->cr1 &= ~STM32_SPI_CR1_SPE; - - /* Disable DMA buffers */ - spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN); - - return rv; -} - -int spi_enable(int port, int enable) -{ - if (enable == spi_enabled[port]) - return EC_SUCCESS; - if (enable) - return spi_master_initialize(port); - else - return spi_master_shutdown(port); -} - -static int spi_dma_start(int port, const uint8_t *txdata, - uint8_t *rxdata, int len) -{ - dma_chan_t *txdma; - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Workaround for STM32H7 errata: without resetting the SPI controller, - * the RX DMA requests will happen too early on the 2nd transfer. - */ - STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4; - STM32_RCC_APB2RSTR = 0; - dma_clear_isr(dma_tx_option[port].channel); - dma_clear_isr(dma_rx_option[port].channel); - /* restore proper SPI configuration registers. */ - spi_master_config(port); - - spi->cr2 = len; - spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN; - /* Set up RX DMA */ - if (rxdata) - dma_start_rx(&dma_rx_option[port], len, rxdata); - - /* Set up TX DMA */ - if (txdata) { - txdma = dma_get_channel(dma_tx_option[port].channel); - dma_prepare_tx(&dma_tx_option[port], len, txdata); - dma_go(txdma); - } - - spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN; - spi->cr1 |= STM32_SPI_CR1_SPE; - spi->cr1 |= STM32_SPI_CR1_CSTART; - - return EC_SUCCESS; -} - -static inline bool dma_is_enabled_(const struct dma_option *option) -{ - return dma_is_enabled(dma_get_channel(option->channel)); -} - -static int spi_dma_wait(int port) -{ - timestamp_t timeout; - stm32_spi_regs_t *spi = SPI_REGS[port]; - int rv = EC_SUCCESS; - - /* Wait for DMA transmission to complete */ - if (dma_is_enabled_(&dma_tx_option[port])) { - rv = dma_wait(dma_tx_option[port].channel); - if (rv) - return rv; - - timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC; - /* Wait for FIFO empty and BSY bit clear */ - while (!(spi->sr & (STM32_SPI_SR_TXC))) - if (get_time().val > timeout.val) - return EC_ERROR_TIMEOUT; - - /* Disable TX DMA */ - dma_disable(dma_tx_option[port].channel); - } - - /* Wait for DMA reception to complete */ - if (dma_is_enabled_(&dma_rx_option[port])) { - rv = dma_wait(dma_rx_option[port].channel); - if (rv) - return rv; - - timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC; - /* Wait for FRLVL[1:0] to indicate FIFO empty */ - while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE)) - if (get_time().val > timeout.val) - return EC_ERROR_TIMEOUT; - - /* Disable RX DMA */ - dma_disable(dma_rx_option[port].channel); - } - - spi->cr1 &= ~STM32_SPI_CR1_SPE; - spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN); - - return rv; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - int full_readback = 0; - - char *buf = NULL; - -#ifndef CONFIG_SPI_HALFDUPLEX - if (rxlen == SPI_READBACK_ALL) { - buf = rxdata; - full_readback = 1; - } else { - rv = shared_mem_acquire(MAX(txlen, rxlen), &buf); - if (rv != EC_SUCCESS) - return rv; - } -#endif - - /* Drive SS low */ - gpio_set_level(spi_device->gpio_cs, 0); - - rv = spi_dma_start(port, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - - if (full_readback) - return EC_SUCCESS; - - if (rxlen) { - rv = spi_dma_wait(port); - if (rv != EC_SUCCESS) - goto err_free; - - rv = spi_dma_start(port, buf, rxdata, rxlen); - if (rv != EC_SUCCESS) - goto err_free; - } - -err_free: - if (!full_readback) - shared_mem_release(buf); - return rv; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int rv = spi_dma_wait(spi_device->port); - - /* Drive SS high */ - gpio_set_level(spi_device->gpio_cs, 1); - - return rv; -} - -int spi_transaction_wait(const struct spi_device_t *spi_device) -{ - return spi_dma_wait(spi_device->port); -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv; - int port = spi_device->port; - - mutex_lock(spi_mutex + port); - rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - rv |= spi_transaction_flush(spi_device); - mutex_unlock(spi_mutex + port); - - return rv; -} diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c deleted file mode 100644 index 47c5be3979..0000000000 --- a/chip/stm32/spi_master.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI master driver. - */ - -#include "common.h" -#include "dma.h" -#include "gpio.h" -#include "hwtimer.h" -#include "shared_mem.h" -#include "spi.h" -#include "stm32-dma.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#if defined(CHIP_VARIANT_STM32F373) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_VARIANT_STM32F76X) -#define HAS_SPI3 -#else -#undef HAS_SPI3 -#endif - -/* The second (and third if available) SPI port are used as master */ -static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - STM32_SPI1_REGS, -#endif - STM32_SPI2_REGS, -#ifdef HAS_SPI3 - STM32_SPI3_REGS, -#endif -}; - -#ifdef CHIP_FAMILY_STM32L4 -/* DMA request mapping on channels */ -static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER - /* SPI1 */ 1, -#endif - /* SPI2 */ 1, - /* SPI3 */ 3, -}; -#endif - -static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; - -#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) - -/* Default DMA channel options */ -#ifdef CHIP_FAMILY_STM32F4 -#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) -#else -#define F4_CHANNEL(ch) 0 -#endif - -static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_TX_REQ_CH) - }, -#endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_TX_REQ_CH) - }, -#ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_TX_REQ_CH) - }, -#endif -}; - -static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_RX_REQ_CH) - }, -#endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_RX_REQ_CH) - }, -#ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_RX_REQ_CH) - }, -#endif -}; - -static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; - -static int spi_tx_done(stm32_spi_regs_t *spi) -{ - return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY)); -} - -static int spi_rx_done(stm32_spi_regs_t *spi) -{ - return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE)); -} - -/* Read until RX FIFO is empty (i.e. RX done) */ -static int spi_clear_rx_fifo(stm32_spi_regs_t *spi) -{ - uint8_t dummy __attribute__((unused)); - uint32_t start = __hw_clock_source_read(), delta; - - while (!spi_rx_done(spi)) { - dummy = spi->dr; /* Read one byte from FIFO */ - delta = __hw_clock_source_read() - start; - if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) - return EC_ERROR_TIMEOUT; - } - return EC_SUCCESS; -} - -/* Wait until TX FIFO is empty (i.e. TX done) */ -static int spi_clear_tx_fifo(stm32_spi_regs_t *spi) -{ - uint32_t start = __hw_clock_source_read(), delta; - - while (!spi_tx_done(spi)) { - /* wait for TX complete */ - delta = __hw_clock_source_read() - start; - if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) - return EC_ERROR_TIMEOUT; - } - return EC_SUCCESS; -} - -/** - * Initialize SPI module, registers, and clocks - * - * - port: which port to initialize. - */ -static int spi_master_initialize(int port) -{ - int i, div = 0; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Set SPI master, baud rate, and software slave control. - * */ - for (i = 0; i < spi_devices_used; i++) - if ((spi_devices[i].port == port) && - (div < spi_devices[i].div)) - div = spi_devices[i].div; - - /* - * STM32F412 - * Section 26.3.5 Slave select (NSS) pin management and Figure 276 - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817 - * - * The documentation in this section is a bit confusing, so here's a - * summary based on discussion with ST: - * - * Software NSS management (SSM = 1): - * - In master mode, the NSS output is deactivated. You need to use a - * GPIO in output mode for slave select. This is generally used for - * multi-slave operation, but you can also use it for single slave - * operation. In this case, you should make sure to configure a GPIO - * for NSS, but *not* activate the SPI alternate function on that - * same pin since that will enable hardware NSS management (see - * below). - * - In slave mode, the NSS input level is equal to the SSI bit value. - * - * Hardware NSS management (SSM = 0): - * - In slave mode, when NSS pin is detected low the slave (MCU) is - * selected. - * - In master mode, there are two configurations, depending on the - * SSOE bit in register SPIx_CR1. - * - NSS output enable (SSM=0, SSOE=1): - * The MCU (master) drives NSS low as soon as SPI is enabled - * (SPE=1) and releases it when SPI is disabled (SPE=0). - * - * - NSS output disable (SSM=0, SSOE=0): - * Allows multimaster capability. The MCU (master) drives NSS - * low. If another master tries to takes control of the bus and - * NSS is pulled low, a mode fault is generated and the MCU - * changes to slave mode. - * - * - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as - * master on the bus, this config allows multimaster capability. If - * the NSS pin is pulled low in this mode, the SPI enters master - * mode fault state and the device is automatically reconfigured in - * slave mode. In slave mode, the NSS pin works as a standard "chip - * select" input and the slave is selected while NSS lin is at low - * level. - */ - spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI | - (div << 3); - -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(dma_tx_option[port].channel, dma_req[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req[port]); -#endif - /* - * Configure 8-bit datasize, set FRXTH, enable DMA, - * and set data size (applies to STM32F0 only). - * - * STM32F412: - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852 - * - * - * STM32F0: - * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803 - */ - spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); - -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE; -#endif - - for (i = 0; i < spi_devices_used; i++) { - if (spi_devices[i].port != port) - continue; - /* Drive SS high */ - gpio_set_level(spi_devices[i].gpio_cs, 1); - } - - /* Set flag */ - spi_enabled[port] = 1; - - return EC_SUCCESS; -} - -/** - * Shutdown SPI module - */ -static int spi_master_shutdown(int port) -{ - int rv = EC_SUCCESS; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* Set flag */ - spi_enabled[port] = 0; - - /* Disable DMA streams */ - dma_disable(dma_tx_option[port].channel); - dma_disable(dma_rx_option[port].channel); - - /* Disable SPI */ - spi->cr1 &= ~STM32_SPI_CR1_SPE; - - spi_clear_rx_fifo(spi); - - /* Disable DMA buffers */ - spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN); - - return rv; -} - -int spi_enable(int port, int enable) -{ - if (enable == spi_enabled[port]) - return EC_SUCCESS; - if (enable) - return spi_master_initialize(port); - else - return spi_master_shutdown(port); -} - -static int spi_dma_start(int port, const uint8_t *txdata, - uint8_t *rxdata, int len) -{ - dma_chan_t *txdma; - - /* Set up RX DMA */ - if (rxdata) - dma_start_rx(&dma_rx_option[port], len, rxdata); - - /* Set up TX DMA */ - if (txdata) { - txdma = dma_get_channel(dma_tx_option[port].channel); - dma_prepare_tx(&dma_tx_option[port], len, txdata); - dma_go(txdma); - } - - return EC_SUCCESS; -} - -static bool dma_is_enabled_(const struct dma_option *option) -{ - return dma_is_enabled(dma_get_channel(option->channel)); -} - -static int spi_dma_wait(int port) -{ - int rv = EC_SUCCESS; - - /* Wait for DMA transmission to complete */ - if (dma_is_enabled_(&dma_tx_option[port])) { - /* - * In TX mode, SPI only generates clock when we write to FIFO. - * Therefore, even though `dma_wait` polls with interval 0.1ms, - * we won't send extra bytes. - */ - rv = dma_wait(dma_tx_option[port].channel); - if (rv) - return rv; - /* Disable TX DMA */ - dma_disable(dma_tx_option[port].channel); - } - - /* Wait for DMA reception to complete */ - if (dma_is_enabled_(&dma_rx_option[port])) { - /* - * Because `dma_wait` polls with interval 0.1ms, we will read at - * least ~100 bytes (with 8MHz clock). If you don't want this - * overhead, you can use interrupt handler - * (`dma_enable_tc_interrupt_callback`) and disable SPI - * interface in callback function. - */ - rv = dma_wait(dma_rx_option[port].channel); - if (rv) - return rv; - /* Disable RX DMA */ - dma_disable(dma_rx_option[port].channel); - } - return rv; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - int full_readback = 0; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - char *buf = NULL; - -#ifndef CONFIG_SPI_HALFDUPLEX - if (rxlen == SPI_READBACK_ALL) { - buf = rxdata; - full_readback = 1; - } else { - rv = shared_mem_acquire(MAX(txlen, rxlen), &buf); - if (rv != EC_SUCCESS) - return rv; - } -#endif - - /* Drive SS low */ - gpio_set_level(spi_device->gpio_cs, 0); - - spi_clear_rx_fifo(spi); - - rv = spi_dma_start(port, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIOE; -#endif - spi->cr1 |= STM32_SPI_CR1_SPE; - - if (full_readback) - return EC_SUCCESS; - - rv = spi_dma_wait(port); - if (rv != EC_SUCCESS) - goto err_free; - - spi_clear_tx_fifo(spi); - - spi->cr1 &= ~STM32_SPI_CR1_SPE; - - if (rxlen) { - rv = spi_dma_start(port, buf, rxdata, rxlen); - if (rv != EC_SUCCESS) - goto err_free; -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 &= ~STM32_SPI_CR1_BIDIOE; -#endif - spi->cr1 |= STM32_SPI_CR1_SPE; - } - -err_free: -#ifndef CONFIG_SPI_HALFDUPLEX - if (!full_readback) - shared_mem_release(buf); -#endif - return rv; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int rv = spi_dma_wait(spi_device->port); - stm32_spi_regs_t *spi = SPI_REGS[spi_device->port]; - - spi->cr1 &= ~STM32_SPI_CR1_SPE; - /* Drive SS high */ - gpio_set_level(spi_device->gpio_cs, 1); - - return rv; -} - -int spi_transaction_wait(const struct spi_device_t *spi_device) -{ - return spi_dma_wait(spi_device->port); -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv; - int port = spi_device->port; - - mutex_lock(spi_mutex + port); - rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - rv |= spi_transaction_flush(spi_device); - mutex_unlock(spi_mutex + port); - - return rv; -} diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h deleted file mode 100644 index 06233b9c93..0000000000 --- a/chip/stm32/stm32-dma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * Select DMA stream-channel mapping - * - * This selects which stream (peripheral) to be used on a specific channel. - * Some STM32 chips simply logically OR requests, thus do not require this - * selection. - * - * @param channel: (Global) channel # base 0 (Note some STM32s use base 1) - * @param peripheral: Refer to the TRM for 'peripheral request signals' - */ -void dma_select_channel(enum dma_channel channel, unsigned char stream); diff --git a/chip/stm32/system.c b/chip/stm32/system.c deleted file mode 100644 index 4b0dada71d..0000000000 --- a/chip/stm32/system.c +++ /dev/null @@ -1,596 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : hardware specific implementation */ - -#include "clock.h" -#include "console.h" -#include "cpu.h" -#include "flash.h" -#include "gpio_chip.h" -#include "host_command.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "version.h" -#include "watchdog.h" - -#ifdef CONFIG_STM32_CLOCK_LSE -#define BDCR_SRC BDCR_SRC_LSE -#define BDCR_RDY STM32_RCC_BDCR_LSERDY -#else -#define BDCR_SRC BDCR_SRC_LSI -#define BDCR_RDY 0 -#endif -#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \ - BDCR_RDY) -#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \ - STM32_RCC_BDCR_BDRST) - -/* We use 16-bit BKP / BBRAM entries. */ -#define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2) - -/* - * Use 32-bit for reset flags, if we have space for it: - * - 2 indexes are used unconditionally (SCRATCHPAD and SAVED_RESET_FLAGS) - * - VBNV_CONTEXT requires 8 indexes, so a total of 10 (which is the total - * number of entries on some STM32 variants). - * - Other config options are not a problem (they only take a few entries) - * - * Given this, we can only add an extra entry for the top 16-bit of reset flags - * if VBNV_CONTEXT is not enabled, or if we have more than 10 entries. - */ -#if !defined(CONFIG_HOSTCMD_VBNV_CONTEXT) || STM32_BKP_ENTRIES > 10 -#define CONFIG_STM32_RESET_FLAGS_EXTENDED -#endif - -enum bkpdata_index { - BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ - BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ -#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED - BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ -#endif -#ifdef CONFIG_HOSTCMD_VBNV_CONTEXT - BKPDATA_INDEX_VBNV_CONTEXT0, - BKPDATA_INDEX_VBNV_CONTEXT1, - BKPDATA_INDEX_VBNV_CONTEXT2, - BKPDATA_INDEX_VBNV_CONTEXT3, - BKPDATA_INDEX_VBNV_CONTEXT4, - BKPDATA_INDEX_VBNV_CONTEXT5, - BKPDATA_INDEX_VBNV_CONTEXT6, - BKPDATA_INDEX_VBNV_CONTEXT7, -#endif -#ifdef CONFIG_SOFTWARE_PANIC - BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ - BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ - BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */ -#endif -#ifdef CONFIG_USB_PD_DUAL_ROLE - BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ - BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ - BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ -#endif - BKPDATA_COUNT -}; -BUILD_ASSERT(STM32_BKP_ENTRIES >= BKPDATA_COUNT); - -#ifdef CONFIG_USB_PD_DUAL_ROLE -BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3); -#endif - -/** - * Read backup register at specified index. - * - * @return The value of the register or 0 if invalid index. - */ -static uint16_t bkpdata_read(enum bkpdata_index index) -{ - if (index < 0 || index >= STM32_BKP_ENTRIES) - return 0; - - if (index & 1) - return STM32_BKP_DATA(index >> 1) >> 16; - else - return STM32_BKP_DATA(index >> 1) & 0xFFFF; -} - -/** - * Write hibernate register at specified index. - * - * @return nonzero if error. - */ -static int bkpdata_write(enum bkpdata_index index, uint16_t value) -{ - static struct mutex bkpdata_write_mutex; - - if (index < 0 || index >= STM32_BKP_ENTRIES) - return EC_ERROR_INVAL; - - /* - * Two entries share a single 32-bit register, lock mutex to prevent - * read/mask/write races. - */ - mutex_lock(&bkpdata_write_mutex); - if (index & 1) { - uint32_t val = STM32_BKP_DATA(index >> 1); - val = (val & 0x0000FFFF) | (value << 16); - STM32_BKP_DATA(index >> 1) = val; - } else { - uint32_t val = STM32_BKP_DATA(index >> 1); - val = (val & 0xFFFF0000) | value; - STM32_BKP_DATA(index >> 1) = val; - } - mutex_unlock(&bkpdata_write_mutex); - - return EC_SUCCESS; -} - -void __no_hibernate(uint32_t seconds, uint32_t microseconds) -{ -#ifdef CONFIG_COMMON_RUNTIME - /* - * Hibernate not implemented on this platform. - * - * Until then, treat this as a request to hard-reboot. - */ - cprints(CC_SYSTEM, "hibernate not supported, so rebooting"); - cflush(); - system_reset(SYSTEM_RESET_HARD); -#endif -} - -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) - __attribute__((weak, alias("__no_hibernate"))); - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - /* Flush console before hibernating */ - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* chip specific standby mode */ - __enter_hibernate(seconds, microseconds); -} - -static void check_reset_cause(void) -{ - uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS); - uint32_t raw_cause = STM32_RCC_RESET_CAUSE; - uint32_t pwr_status = STM32_PWR_RESET_CAUSE; - -#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED - flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16; -#endif - - /* Clear the hardware reset cause by setting the RMVF bit */ - STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF; - /* Clear SBF in PWR_CSR */ - STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR; - /* Clear saved reset flags */ - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, 0); -#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, 0); -#endif - - if (raw_cause & RESET_CAUSE_WDG) { - /* - * IWDG or WWDG, if the watchdog was not used as an hard reset - * mechanism - */ - if (!(flags & EC_RESET_FLAG_HARD)) - flags |= EC_RESET_FLAG_WATCHDOG; - } - - if (raw_cause & RESET_CAUSE_SFT) - flags |= EC_RESET_FLAG_SOFT; - - if (raw_cause & RESET_CAUSE_POR) - flags |= EC_RESET_FLAG_POWER_ON; - - if (raw_cause & RESET_CAUSE_PIN) - flags |= EC_RESET_FLAG_RESET_PIN; - - if (pwr_status & RESET_CAUSE_SBF) - /* Hibernated and subsequently awakened */ - flags |= EC_RESET_FLAG_HIBERNATE; - - if (!flags && (raw_cause & RESET_CAUSE_OTHER)) - flags |= EC_RESET_FLAG_OTHER; - - /* - * WORKAROUND: as we cannot de-activate the watchdog during - * long hibernation, we are woken-up once by the watchdog and - * go back to hibernate if we detect that condition, without - * watchdog initialized this time. - * The RTC deadline (if any) is already set. - */ - if ((flags & EC_RESET_FLAG_HIBERNATE) && - (flags & EC_RESET_FLAG_WATCHDOG)) { - __enter_hibernate(0, 0); - } - - system_set_reset_flags(flags); -} - -/* Stop all timers and WDGs we might use when JTAG stops the CPU. */ -void chip_pre_init(void) -{ - uint32_t apb1fz_reg = 0; - uint32_t apb2fz_reg = 0; - -#if defined(CHIP_FAMILY_STM32F0) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | - STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; - - /* enable clock to debug module before writing */ - STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN; -#elif defined(CHIP_FAMILY_STM32F3) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; -#elif defined(CHIP_FAMILY_STM32F4) - /* TODO(nsanders): Implement this if someone needs jtag. */ -#elif defined(CHIP_FAMILY_STM32L4) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; -#elif defined(CHIP_FAMILY_STM32L) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | - STM32_RCC_PB2_TIM11; -#elif defined(CHIP_FAMILY_STM32H7) - /* TODO(b/67081508) */ -#endif - - if (apb1fz_reg) - STM32_DBGMCU_APB1FZ |= apb1fz_reg; - if (apb2fz_reg) - STM32_DBGMCU_APB2FZ |= apb2fz_reg; -} - -void system_pre_init(void) -{ -#ifdef CONFIG_SOFTWARE_PANIC - uint16_t reason, info; - uint8_t exception; -#endif - - /* enable clock on Power module */ -#ifndef CHIP_FAMILY_STM32H7 - STM32_RCC_APB1ENR |= STM32_RCC_PWREN; -#endif -#if defined(CHIP_FAMILY_STM32F4) - /* enable backup registers */ - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; -#elif defined(CHIP_FAMILY_STM32H7) - /* enable backup registers */ - STM32_RCC_AHB4ENR |= BIT(28); -#else - /* enable backup registers */ - STM32_RCC_APB1ENR |= BIT(27); -#endif - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= BIT(8); -#ifdef CHIP_VARIANT_STM32L476 - /* Enable Vddio2 */ - STM32_PWR_CR2 |= BIT(9); -#endif - - /* switch on LSI */ - STM32_RCC_CSR |= BIT(0); - /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & BIT(1))) - ; - /* re-configure RTC if needed */ -#ifdef CHIP_FAMILY_STM32L - if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) { - /* The RTC settings are bad, we need to reset it */ - STM32_RCC_CSR |= 0x00800000; - /* Enable RTC and use LSI as clock source */ - STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; - } -#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32F4) || \ - defined(CHIP_FAMILY_STM32H7) - if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { - /* The RTC settings are bad, we need to reset it */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; - STM32_RCC_BDCR = STM32_RCC_BDCR & ~BDCR_ENABLE_MASK; -#ifdef CONFIG_STM32_CLOCK_LSE - /* Turn on LSE */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_LSEON; - /* Wait for LSE to be ready */ - while (!(STM32_RCC_BDCR & STM32_RCC_BDCR_LSERDY)) - ; -#endif - /* Select clock source and enable RTC */ - STM32_RCC_BDCR |= BDCR_RTCSEL(BDCR_SRC) | STM32_RCC_BDCR_RTCEN; - } -#else -#error "Unsupported chip family" -#endif - - check_reset_cause(); - -#ifdef CONFIG_SOFTWARE_PANIC - /* Restore then clear saved panic reason */ - reason = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_REASON); - info = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_INFO); - exception = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION); - if (reason || info || exception) { - panic_set_reason(reason, info, exception); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, 0); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, 0); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, 0); - } -#endif -} - -void system_reset(int flags) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - /* Remember that the software asked us to hard reboot */ - if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - -#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED - if (flags & SYSTEM_RESET_AP_WATCHDOG) - save_flags |= EC_RESET_FLAG_AP_WATCHDOG; - - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff); - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16); -#else - /* Reset flags are 32-bits, but BBRAM entry is only 16 bits. */ - ASSERT(!(save_flags >> 16)); - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags); -#endif - - if (flags & SYSTEM_RESET_HARD) { -#ifdef CONFIG_SOFTWARE_PANIC - uint32_t reason, info; - uint8_t exception; - - /* Panic data will be wiped by hard reset, so save it */ - panic_get_reason(&reason, &info, &exception); - /* 16 bits stored - upper 16 bits of reason / info are lost */ - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, exception); -#endif - -#ifdef CHIP_FAMILY_STM32L - /* - * Ask the flash module to reboot, so that we reload the - * option bytes. - */ - flash_physical_force_reload(); - - /* Fall through to watchdog if that fails */ -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* - * On some chips, a reboot doesn't always reload the option - * bytes, and we need to explicitly request for a reload. - * The reload request triggers a chip reset, so let's just - * use this for hard reset. - */ - STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; -#elif defined(CHIP_FAMILY_STM32L4) - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; - STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; -#else - /* - * RM0433 Rev 6 - * Section 44.3.3 - * https://www.st.com/resource/en/reference_manual/dm00314099.pdf#page=1898 - * - * When the window option is not used, the IWDG can be - * configured as follows: - * - * 1. Enable the IWDG by writing 0x0000 CCCC in the Key - * register (IWDG_KR). - * 2. Enable register access by writing 0x0000 5555 in the Key - * register (IWDG_KR). - * 3. Write the prescaler by programming the Prescaler register - * (IWDG_PR) from 0 to 7. - * 4. Write the Reload register (IWDG_RLR). - * 5. Wait for the registers to be updated - * (IWDG_SR = 0x0000 0000). - * 6. Refresh the counter value with IWDG_RLR - * (IWDG_KR = 0x0000 AAAA) - */ - - /* - * Enable IWDG, which shouldn't be necessary since the IWDG - * only needs to be started once, but STM32F412 hangs unless - * this is added. - * - * See http://b/137045370. - */ - STM32_IWDG_KR = STM32_IWDG_KR_START; - - /* Ask the watchdog to trigger a hard reboot */ - STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; - STM32_IWDG_RLR = 0x1; - /* Wait for value to be reloaded. */ - while (STM32_IWDG_SR & STM32_IWDG_SR_RVU) - ; - STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; -#endif - /* wait for the chip to reboot */ - while (1) - ; - } else { - if (flags & SYSTEM_RESET_WAIT_EXT) { - int i; - - /* Wait 10 seconds for external reset */ - for (i = 0; i < 1000; i++) { - watchdog_reload(); - udelay(10000); - } - } - CPU_NVIC_APINT = 0x05fa0004; - } - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -int system_set_scratchpad(uint32_t value) -{ - /* Check if value fits in 16 bits */ - if (value & 0xffff0000) - return EC_ERROR_INVAL; - return bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, (uint16_t)value); -} - -uint32_t system_get_scratchpad(void) -{ - return (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD); -} - -const char *system_get_chip_vendor(void) -{ - return "stm"; -} - -const char *system_get_chip_name(void) -{ - return STRINGIFY(CHIP_VARIANT); -} - -const char *system_get_chip_revision(void) -{ - return ""; -} - -int system_get_chip_unique_id(uint8_t **id) -{ - *id = (uint8_t *)STM32_UNIQUE_ID_ADDRESS; - return STM32_UNIQUE_ID_LENGTH; -} - -static int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb) -{ - *msb = 0; - -#ifdef CONFIG_HOSTCMD_VBNV_CONTEXT - if (idx >= SYSTEM_BBRAM_IDX_VBNVBLOCK0 && - idx <= SYSTEM_BBRAM_IDX_VBNVBLOCK15) { - *msb = (idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0) % 2; - return BKPDATA_INDEX_VBNV_CONTEXT0 + - (idx - SYSTEM_BBRAM_IDX_VBNVBLOCK0) / 2; - } -#endif -#ifdef CONFIG_USB_PD_DUAL_ROLE - if (idx == SYSTEM_BBRAM_IDX_PD0) - return BKPDATA_INDEX_PD0; - if (idx == SYSTEM_BBRAM_IDX_PD1) - return BKPDATA_INDEX_PD1; - if (idx == SYSTEM_BBRAM_IDX_PD2) - return BKPDATA_INDEX_PD2; -#endif - return -1; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int msb = 0; - int bkpdata_index = bkpdata_index_lookup(idx, &msb); - - if (bkpdata_index < 0) - return EC_ERROR_INVAL; - - *value = (bkpdata_read(bkpdata_index) >> (8 * msb)) & 0xff; - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - uint16_t read; - int msb = 0; - int bkpdata_index = bkpdata_index_lookup(idx, &msb); - - if (bkpdata_index < 0) - return EC_ERROR_INVAL; - - read = bkpdata_read(bkpdata_index); - if (msb) - read = (read & 0xff) | (value << 8); - else - read = (read & 0xff00) | value; - - bkpdata_write(bkpdata_index, read); - return EC_SUCCESS; -} - -int system_is_reboot_warm(void) -{ - /* - * Detecting if the system is warm is relevant for a - * few reasons. - * One such reason is that some firmwares transition from - * RO to RW images. When this happens, we may not need to - * restart certain clocks. On the flip side, we may need - * to restart the clocks if the RW requires a different - * set of clocks. Thus, the clock configurations need to - * be checked for a perfect match. - */ - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - return ((STM32_RCC_AHBENR & 0x7e0000) == 0x7e0000); -#elif defined(CHIP_FAMILY_STM32L) - return ((STM32_RCC_AHBENR & 0x3f) == 0x3f); -#elif defined(CHIP_FAMILY_STM32L4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); -#elif defined(CHIP_FAMILY_STM32F4) - return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) - == gpio_required_clocks()); -#elif defined(CHIP_FAMILY_STM32H7) - return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) - == STM32_RCC_AHB4ENR_GPIOMASK); -#endif -} diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c deleted file mode 100644 index eff3ca0181..0000000000 --- a/chip/stm32/trng.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware Random Number Generator */ - -#include "common.h" -#include "console.h" -#include "host_command.h" -#include "panic.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "trng.h" -#include "util.h" - -uint32_t rand(void) -{ - int tries = 300; - /* Wait for a valid random number */ - while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries) - ; - /* we cannot afford to feed the caller with a dummy number */ - if (!tries) - software_panic(PANIC_SW_BAD_RNG, task_get_current()); - /* Finally the 32-bit of entropy */ - return STM32_RNG_DR; -} - -test_mockable void rand_bytes(void *buffer, size_t len) -{ - while (len) { - uint32_t number = rand(); - size_t cnt = 4; - /* deal with the lack of alignment guarantee in the API */ - uintptr_t align = (uintptr_t)buffer & 3; - - if (len < 4 || align) { - cnt = MIN(4 - align, len); - memcpy(buffer, &number, cnt); - } else { - *(uint32_t *)buffer = number; - } - len -= cnt; - buffer += cnt; - } -} - -test_mockable void init_trng(void) -{ -#ifdef CHIP_FAMILY_STM32L4 - /* Enable the 48Mhz internal RC oscillator */ - STM32_RCC_CRRCR |= STM32_RCC_CRRCR_HSI48ON; - /* no timeout: we watchdog if the oscillator doesn't start */ - while (!(STM32_RCC_CRRCR & STM32_RCC_CRRCR_HSI48RDY)) - ; - - /* Clock the TRNG using the HSI48 */ - STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) - | (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); -#elif defined(CHIP_FAMILY_STM32H7) - /* Enable the 48Mhz internal RC oscillator */ - STM32_RCC_CR |= STM32_RCC_CR_HSI48ON; - /* no timeout: we watchdog if the oscillator doesn't start */ - while (!(STM32_RCC_CR & STM32_RCC_CR_HSI48RDY)) - ; - - /* Clock the TRNG using the HSI48 */ - STM32_RCC_D2CCIP2R = - (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) - | STM32_RCC_D2CCIP2_RNGSEL_HSI48; -#elif defined(CHIP_FAMILY_STM32F4) - /* - * The RNG clock is the same as the SDIO/USB OTG clock, already set at - * 48 MHz during clock initialisation. Nothing to do. - */ -#else -#error "Please add support for CONFIG_RNG on this chip family." -#endif - /* Enable the RNG logic */ - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_RNGEN; - /* Start the random number generation */ - STM32_RNG_CR |= STM32_RNG_CR_RNGEN; -} - -test_mockable void exit_trng(void) -{ - STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; - STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; -#ifdef CHIP_FAMILY_STM32L4 - STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON; -#elif defined(CHIP_FAMILY_STM32H7) - STM32_RCC_CR &= ~STM32_RCC_CR_HSI48ON; -#elif defined(CHIP_FAMILY_STM32F4) - /* Nothing to do */ -#endif -} - -#if defined(CONFIG_CMD_RAND) -/* - * We want to avoid accidentally exposing debug commands in RO since we can't - * update RO once in production. - */ -#if defined(SECTION_IS_RW) -static int command_rand(int argc, char **argv) -{ - uint8_t data[32]; - - init_trng(); - rand_bytes(data, sizeof(data)); - exit_trng(); - - ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rand, command_rand, - NULL, "Output random bytes to console."); - -static enum ec_status host_command_rand(struct host_cmd_handler_args *args) -{ - const struct ec_params_rand_num *p = args->params; - struct ec_response_rand_num *r = args->response; - uint16_t num_rand_bytes = p->num_rand_bytes; - - if (system_is_locked()) - return EC_RES_ACCESS_DENIED; - - if (num_rand_bytes > args->response_max) - return EC_RES_OVERFLOW; - - init_trng(); - rand_bytes(r->rand, num_rand_bytes); - exit_trng(); - - args->response_size = num_rand_bytes; - - return EC_SUCCESS; -} - -DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand, - EC_VER_MASK(EC_VER_RAND_NUM)); -#endif /* SECTION_IS_RW */ -#endif /* CONFIG_CMD_RAND */ diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c deleted file mode 100644 index f20805f7e5..0000000000 --- a/chip/stm32/uart.c +++ /dev/null @@ -1,396 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USART driver for Chrome EC */ - -#include "common.h" -#include "clock.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" -#include "stm32-dma.h" - -/* Console USART index */ -#define UARTN CONFIG_UART_CONSOLE -#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) - -#ifdef CONFIG_UART_TX_DMA -#define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE - -#ifndef CONFIG_UART_TX_DMA_CH -#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX -#endif - -/* DMA channel options; assumes UART1 */ -static const struct dma_option dma_tx_option = { - CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) -#endif -}; - -#else -#define UART_TX_INT_ENABLE STM32_USART_CR1_TXEIE -#endif - -#ifdef CONFIG_UART_RX_DMA - -#ifndef CONFIG_UART_RX_DMA_CH -#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART1_RX -#endif -/* DMA channel options; assumes UART1 */ -static const struct dma_option dma_rx_option = { - CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | -#ifdef CHIP_FAMILY_STM32F4 - STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | -#endif - STM32_DMA_CCR_CIRC -}; - -static int dma_rx_len; /* Size of receive DMA circular buffer */ -#endif - -static int init_done; /* Initialization done? */ -static int should_stop; /* Last TX control action */ - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE) - return; - - disable_sleep(SLEEP_MASK_UART); - should_stop = 0; - STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE | - STM32_USART_CR1_TCIE; - task_trigger_irq(STM32_IRQ_USART(UARTN)); -} - -void uart_tx_stop(void) -{ - STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE; - should_stop = 1; -#ifdef CONFIG_UART_TX_DMA - enable_sleep(SLEEP_MASK_UART); -#endif -} - -void uart_tx_flush(void) -{ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; -} - -int uart_tx_ready(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE; -} - -#ifdef CONFIG_UART_TX_DMA - -int uart_tx_dma_ready(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC; -} - -void uart_tx_dma_start(const char *src, int len) -{ - /* Prepare DMA */ - dma_prepare_tx(&dma_tx_option, len, src); - - /* Force clear TC so we don't re-interrupt */ - STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC; - - /* Enable TCIE (chrome-os-partner:28837) */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE; - - /* Start DMA */ - dma_go(dma_get_channel(dma_tx_option.channel)); -} - -#endif /* CONFIG_UART_TX_DMA */ - -int uart_rx_available(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE; -} - -#ifdef CONFIG_UART_RX_DMA - -void uart_rx_dma_start(char *dest, int len) -{ - /* Start receiving */ - dma_rx_len = len; - dma_start_rx(&dma_rx_option, len, dest); -} - -int uart_rx_dma_head(void) -{ - return dma_bytes_done(dma_get_channel(CONFIG_UART_RX_DMA_CH), - dma_rx_len); -} - -#endif - -void uart_write_char(char c) -{ - /* Wait for space */ - while (!uart_tx_ready()) - ; - - STM32_USART_TDR(UARTN_BASE) = c; -} - -int uart_read_char(void) -{ - return STM32_USART_RDR(UARTN_BASE); -} - -/* Interrupt handler for console USART */ -void uart_interrupt(void) -{ -#ifndef CONFIG_UART_TX_DMA - /* - * When transmission completes, enable sleep if we are done with Tx. - * After that, proceed if there is other interrupt to handle. - */ - if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) { - if (should_stop) { - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE; - enable_sleep(SLEEP_MASK_UART); - } -#if defined(CHIP_FAMILY_STM32F4) - STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC; -#else - STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC; -#endif - if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC)) - return; - } -#endif - -#ifdef CONFIG_UART_TX_DMA - /* Disable transmission complete interrupt if DMA done */ - if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE; -#else - /* - * Disable the TX empty interrupt before filling the TX buffer since it - * needs an actual write to DR to be cleared. - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE; -#endif - -#ifndef CONFIG_UART_RX_DMA - /* - * Read input FIFO until empty. DMA-based receive does this from a - * hook in the UART buffering module. - */ - uart_process_input(); -#endif - - /* Fill output FIFO */ - uart_process_output(); - -#ifndef CONFIG_UART_TX_DMA - /* - * Re-enable TX empty interrupt only if it was not disabled by - * uart_process_output(). - */ - if (!should_stop) - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE; -#endif -} -DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2); - -/** - * Handle clock frequency changes - */ -static void uart_freq_change(void) -{ - int freq; - int div; - -#if (defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) && \ - (UARTN <= 2) - /* - * UART is clocked from HSI (8MHz) to allow it to work when waking - * up from sleep - */ - freq = 8000000; -#elif defined(CHIP_FAMILY_STM32H7) - freq = 64000000; /* from 64 Mhz HSI */ -#else - /* UART clocked from the main clock */ - freq = clock_get_freq(); -#endif - -#if (UARTN == 9) /* LPUART */ - div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256; -#else - div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE); -#endif - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ - defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32F4) - if (div / 16 > 0) { - /* - * CPU clock is high enough to support x16 oversampling. - * BRR = (div mantissa)<<4 | (4-bit div fraction) - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8; - STM32_USART_BRR(UARTN_BASE) = div; - } else { - /* - * CPU clock is low; use x8 oversampling. - * BRR = (div mantissa)<<4 | (3-bit div fraction) - */ - STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7); - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8; - } -#else - /* STM32F only supports x16 oversampling */ - STM32_USART_BRR(UARTN_BASE) = div; -#endif - -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT); - -void uart_init(void) -{ - /* Select clock source */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) -#if (UARTN == 1) - STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ -#elif (UARTN == 2) - STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ -#endif /* UARTN */ -#elif defined(CHIP_FAMILY_STM32H7) /* Clocked from 64 Mhz HSI */ -#if ((UARTN == 1) || (UARTN == 6)) - STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART16SEL_HSI; -#else - STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART234578SEL_HSI; -#endif /* UARTN */ -#elif defined(CHIP_FAMILY_STM32L4) - /* USART1 clock source from SYSCLK */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK; - STM32_RCC_CCIPR |= - (STM32_RCC_CCIPR_UART_SYSCLK << STM32_RCC_CCIPR_USART1SEL_SHIFT); - /* LPUART1 clock source from SYSCLK */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK; - STM32_RCC_CCIPR |= - (STM32_RCC_CCIPR_UART_SYSCLK << STM32_RCC_CCIPR_LPUART1SEL_SHIFT); -#endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */ - - /* Enable USART clock */ -#if (UARTN == 1) - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; -#elif (UARTN == 6) - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART6; -#elif (UARTN == 9) - STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_LPUART1EN; -#else - STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN); -#endif - - /* - * For STM32F3, A delay of 1 APB clock cycles is needed before we - * can access any USART register. Fortunately, we have - * gpio_config_module() below and thus don't need to add the delay. - */ - - /* Configure GPIOs */ - gpio_config_module(MODULE_UART, 1); - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ -|| defined(CHIP_FAMILY_STM32H7) - /* - * Wake up on start bit detection. WUS can only be written when UE=0, - * so clear UE first. - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE; - - /* - * Also disable the RX overrun interrupt, since we don't care about it - * and we don't want to clear an extra flag in the interrupt - */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT | - STM32_USART_CR3_OVRDIS; -#endif - - /* - * UART enabled, 8 Data bits, oversampling x16, no parity, - * TX and RX enabled. - */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; - - /* 1 stop bit, no fancy stuff */ - STM32_USART_CR2(UARTN_BASE) = 0x0000; - -#ifdef CONFIG_UART_TX_DMA - /* Enable DMA transmitter */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT; -#ifdef CONFIG_UART_TX_DMA_PH - dma_select_channel(CONFIG_UART_TX_DMA_CH, CONFIG_UART_TX_DMA_PH); -#endif -#else - /* DMA disabled, special modes disabled, error interrupt disabled */ - STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR & - ~STM32_USART_CR3_DMAT & - ~STM32_USART_CR3_EIE; -#endif - -#ifdef CONFIG_UART_RX_DMA - /* Enable DMA receiver */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR; -#else - /* Enable receive-not-empty interrupt */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE; -#endif - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - /* Use single-bit sampling */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT; -#endif - - /* Set initial baud rate */ - uart_freq_change(); - - /* Enable interrupts */ - task_enable_irq(STM32_IRQ_USART(UARTN)); - - init_done = 1; -} - -#ifdef CONFIG_FORCE_CONSOLE_RESUME -void uart_enable_wakeup(int enable) -{ - if (enable) { - /* - * Allow UART wake up from STOP mode. Note, UART clock must - * be HSI(8MHz) for wakeup to work. - */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM; - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE; - } else { - /* Disable wake up from STOP mode. */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM; - } -} -#endif diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c deleted file mode 100644 index 908542146f..0000000000 --- a/chip/stm32/usart-stm32f0.c +++ /dev/null @@ -1,166 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32f0.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 4 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - /* - * Make sure we register this config before enabling the HW. - * If we did it the other way around the FREQ_CHANGE hook could be - * called before we update the configs array and we would miss the - * clock frequency change event, leaving our baud rate divisor wrong. - */ - configs[config->hw->index] = config; - - usart_set_baud(config, config->baud); - - task_enable_irq(config->hw->irq); -} - -void usart_set_baud(struct usart_config const *config, int baud) -{ - usart_set_baud_f0_l(config, baud, clock_get_freq()); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - int index = config->hw->index; - - /* - * Only disable the shared interrupt for USART3/4 if both USARTs are - * now disabled. - */ - if ((index == 0) || - (index == 1) || - (index == 2 && configs[3] == NULL) || - (index == 3 && configs[2] == NULL)) - task_disable_irq(config->hw->irq); - - configs[index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -static void freq_change(void) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(configs); ++i) - if (configs[i]) - usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); -} - -DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3_4, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART4) -struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART3_4, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART3) || defined(CONFIG_STREAM_USART4) -void usart3_4_interrupt(void) -{ - /* - * This interrupt handler could be called with one of these configs - * not initialized, so we need to check here and only call the generic - * USART interrupt handler for initialized configs. - */ - if (configs[2]) - usart_interrupt(configs[2]); - - if (configs[3]) - usart_interrupt(configs[3]); -} - -DECLARE_IRQ(STM32_IRQ_USART3_4, usart3_4_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h deleted file mode 100644 index 1b7eee95a7..0000000000 --- a/chip/stm32/usart-stm32f0.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32F0_H -#define __CROS_EC_USART_STM32F0_H - -#include "usart.h" - -/* - * The STM32F0 series can have as many as four UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; -extern struct usart_hw_config const usart4_hw; - -#endif /* __CROS_EC_USART_STM32F0_H */ diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c deleted file mode 100644 index 42a0cf310e..0000000000 --- a/chip/stm32/usart-stm32f3.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32f3.h" - -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 3 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - configs[config->hw->index] = config; - - /* - * All three USARTS are clocked from the HSI(8MHz) source. This is - * done because the clock sources elsewhere are setup so that the result - * of clock_get_freq() is not the input clock frequency to the USARTs - * baud rate divisors. - */ - STM32_RCC_CFGR3 |= 0x000f0003; - - usart_set_baud_f0_l(config, config->baud, 8000000); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART3) -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h deleted file mode 100644 index 09f1ba608c..0000000000 --- a/chip/stm32/usart-stm32f3.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32F3_H -#define __CROS_EC_USART_STM32F3_H - -#include "usart.h" - -/* - * The STM32F3 series can have as many as three UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; - -#endif /* __CROS_EC_USART_STM32F3_H */ diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c deleted file mode 100644 index 2b7406a0a4..0000000000 --- a/chip/stm32/usart-stm32l.c +++ /dev/null @@ -1,132 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32l.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 3 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - /* Use single-bit sampling */ - STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; - - /* - * Make sure we register this config before enabling the HW. - * If we did it the other way around the FREQ_CHANGE hook could be - * called before we update the configs array and we would miss the - * clock frequency change event, leaving our baud rate divisor wrong. - */ - configs[config->hw->index] = config; - - usart_set_baud_f0_l(config, config->baud, clock_get_freq()); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -static void freq_change(void) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(configs); ++i) - if (configs[i]) - usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); -} - -DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; - -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h deleted file mode 100644 index eb1ae9db1d..0000000000 --- a/chip/stm32/usart-stm32l.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32L_H -#define __CROS_EC_USART_STM32L_H - -#include "usart.h" - -/* - * The STM32L series can have as many as three UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; - -#endif /* __CROS_EC_USART_STM32L_H */ diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c deleted file mode 100644 index 7f8c55aaa6..0000000000 --- a/chip/stm32/usart.c +++ /dev/null @@ -1,172 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USART driver for Chrome EC */ - -#include "atomic.h" -#include "common.h" -#include "gpio.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "usart.h" -#include "util.h" - -void usart_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - uint32_t cr2, cr3; - - /* - * Enable clock to USART, this must be done first, before attempting - * to configure the USART. - */ - *(config->hw->clock_register) |= config->hw->clock_enable; - - /* - * For STM32F3, A delay of 1 APB clock cycles is needed before we - * can access any USART register. Fortunately, we have - * gpio_config_module() below and thus don't need to add the delay. - */ - - /* - * Switch all GPIOs assigned to the USART module over to their USART - * alternate functions. - */ - gpio_config_module(MODULE_USART, 1); - - /* - * 8N1, 16 samples per bit. error interrupts, and special modes - * disabled. - */ - - cr2 = 0x0000; - cr3 = 0x0000; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) - if (config->flags & USART_CONFIG_FLAG_RX_INV) - cr2 |= BIT(16); - if (config->flags & USART_CONFIG_FLAG_TX_INV) - cr2 |= BIT(17); -#endif - if (config->flags & USART_CONFIG_FLAG_HDSEL) - cr3 |= BIT(3); - - STM32_USART_CR1(base) = 0x0000; - STM32_USART_CR2(base) = cr2; - STM32_USART_CR3(base) = cr3; - - /* - * Enable the RX, TX, and variant specific HW. - */ - config->rx->init(config); - config->tx->init(config); - config->hw->ops->enable(config); - - /* - * Clear error counts. - */ - config->state->rx_overrun = 0; - config->state->rx_dropped = 0; - - /* - * Enable the USART, this must be done last since most of the - * configuration bits require that the USART be disabled for writes to - * succeed. - */ - STM32_USART_CR1(base) |= STM32_USART_CR1_UE; -} - -void usart_shutdown(struct usart_config const *config) -{ - STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE; - - config->hw->ops->disable(config); -} - -void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz) -{ - int div = DIV_ROUND_NEAREST(frequency_hz, baud); - intptr_t base = config->hw->base; - - if (div / 16 > 0) { - /* - * CPU clock is high enough to support x16 oversampling. - * BRR = (div mantissa)<<4 | (4-bit div fraction) - */ - STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8; - STM32_USART_BRR(base) = div; - } else { - /* - * CPU clock is low; use x8 oversampling. - * BRR = (div mantissa)<<4 | (3-bit div fraction) - */ - STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7); - STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8; - } -} - -void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz) -{ - int div = DIV_ROUND_NEAREST(frequency_hz, baud); - - /* STM32F only supports x16 oversampling */ - STM32_USART_BRR(config->hw->base) = div; -} - -int usart_get_parity(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - if (!(STM32_USART_CR1(base) & STM32_USART_CR1_PCE)) - return 0; - if (STM32_USART_CR1(base) & STM32_USART_CR1_PS) - return 1; - return 2; -} - -/* - * We only allow 8 bit word. CR1_PCE modifies parity enable, - * CR1_PS modifies even/odd, CR1_M modifies total word length - * to make room for parity. - */ -void usart_set_parity(struct usart_config const *config, int parity) -{ - uint32_t ue; - intptr_t base = config->hw->base; - - if ((parity < 0) || (parity > 2)) - return; - - /* Record active state and disable the UART. */ - ue = STM32_USART_CR1(base) & STM32_USART_CR1_UE; - STM32_USART_CR1(base) &= ~STM32_USART_CR1_UE; - - if (parity) { - /* Set parity control enable. */ - STM32_USART_CR1(base) |= - (STM32_USART_CR1_PCE | STM32_USART_CR1_M); - /* Set parity select even/odd bit. */ - if (parity == 2) - STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS; - else - STM32_USART_CR1(base) |= STM32_USART_CR1_PS; - } else { - STM32_USART_CR1(base) &= - ~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS | - STM32_USART_CR1_M); - } - - /* Restore active state. */ - STM32_USART_CR1(base) |= ue; -} - -void usart_interrupt(struct usart_config const *config) -{ - config->tx->interrupt(config); - config->rx->interrupt(config); -} diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h deleted file mode 100644 index 3e6f658e26..0000000000 --- a/chip/stm32/usart.h +++ /dev/null @@ -1,258 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_H -#define __CROS_EC_USART_H - -/* STM32 USART driver for Chrome EC */ - -#include "common.h" -#include "consumer.h" -#include "producer.h" -#include "queue.h" - -#include <stdint.h> - -/* - * Per-USART state stored in RAM. This structure will be zero initialized by - * BSS init. - */ -struct usart_state { - /* - * Counter of bytes received and then dropped because of lack of space - * in the RX queue. - */ - uint32_t rx_dropped; - - /* - * Counter of the number of times an receive overrun condition is - * detected. This will not usually be a count of the number of bytes - * that were lost due to overrun conditions. - */ - uint32_t rx_overrun; -}; - -struct usart_config; - -struct usart_hw_ops { - /* - * The generic USART initialization code calls this function to allow - * the variant HW specific code to perform any initialization. This - * function is called before the USART is enabled, and should among - * other things enable the USARTs interrupt. - */ - void (*enable)(struct usart_config const *config); - - /* - * The generic USART shutdown code calls this function, allowing the - * variant specific code an opportunity to do any variant specific - * shutdown tasks. - */ - void (*disable)(struct usart_config const *config); -}; - -/* - * The usart_rx/usart_tx structures contain functions pointers for the - * interrupt handler and producer/consumer operations required to implement a - * particular RX/TX strategy. - * - * These structures are defined by the various RX/TX implementations, and are - * used to initialize the usart_config structure to configure the USART driver - * for interrupt or DMA based transfer. - */ -struct usart_rx { - void (*init)(struct usart_config const *config); - void (*interrupt)(struct usart_config const *config); - - /* - * Print to the console any per-strategy diagnostic information, this - * is used by the usart_info command. This can be NULL if there is - * nothing interesting to display. - */ - void (*info)(struct usart_config const *config); - - struct producer_ops producer_ops; -}; - -struct usart_tx { - void (*init)(struct usart_config const *config); - void (*interrupt)(struct usart_config const *config); - - /* - * Print to the console any per-strategy diagnostic information, this - * is used by the usart_info command. This can be NULL if there is - * nothing interesting to display. - */ - void (*info)(struct usart_config const *config); - - struct consumer_ops consumer_ops; -}; - -extern struct usart_rx const usart_rx_interrupt; -extern struct usart_tx const usart_tx_interrupt; - -/* - * Per-USART hardware configuration stored in flash. Instances of this - * structure are provided by each variants driver, one per physical USART. - */ -struct usart_hw_config { - int index; - intptr_t base; - int irq; - - uint32_t volatile *clock_register; - uint32_t clock_enable; - - struct usart_hw_ops const *ops; -}; - -/* - * Compile time Per-USART configuration stored in flash. Instances of this - * structure are provided by the user of the USART. This structure binds - * together all information required to operate a USART. - */ -struct usart_config { - /* - * Pointer to USART HW configuration. There is one HW configuration - * per physical USART. - */ - struct usart_hw_config const *hw; - - struct usart_rx const *rx; - struct usart_tx const *tx; - - /* - * Pointer to USART state structure. The state structure maintains per - * USART information. - */ - struct usart_state volatile *state; - - /* - * Baud rate for USART. - */ - int baud; - - /* Other flags (rx/tx inversion, half-duplex). */ -#define USART_CONFIG_FLAG_RX_INV BIT(0) -#define USART_CONFIG_FLAG_TX_INV BIT(1) -#define USART_CONFIG_FLAG_HDSEL BIT(2) - unsigned int flags; - - struct consumer consumer; - struct producer producer; -}; - -/* - * Convenience macro for defining USARTs and their associated state and buffers. - * NAME is used to construct the names of the usart_state struct, and - * usart_config struct, the latter is just called NAME. - * - * HW is the name of the usart_hw_config provided by the variant specific code. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this USART - * should write to and read from respectively. - */ -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ - ((struct usart_config const) { \ - .hw = &HW, \ - .rx = &RX, \ - .tx = &TX, \ - .state = &((struct usart_state){}), \ - .baud = BAUD, \ - .flags = FLAGS, \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &TX.consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &RX.producer_ops, \ - }, \ - }) - -/* - * Initialize the given USART. Once init is finished the USART streams are - * available for operating on. - */ -void usart_init(struct usart_config const *config); - -/* - * Shutdown the given USART. - */ -void usart_shutdown(struct usart_config const *config); - -/* - * Handle a USART interrupt. The per-variant USART code creates bindings - * for the variants interrupts to call this generic USART interrupt handler - * with the appropriate usart_config. - */ -void usart_interrupt(struct usart_config const *config); - -/* - * These are HW specific baud rate calculation and setting functions that the - * peripheral variant code uses during initialization and clock frequency - * change. The baud rate divisor input frequency is passed in Hertz. - */ -void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz); -void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz); - -/* - * Allow specification of parity for this usart. - * parity is 0: none, 1: odd, 2: even. - */ -void usart_set_parity(struct usart_config const *config, int parity); - -/* - * Check parity for this usart. - * parity is 0: none, 1: odd, 2: even. - */ -int usart_get_parity(struct usart_config const *config); - -/* - * Set baud rate for this usart. Note that baud rate will get reset on - * core frequency change, so this only makes sense if the board never - * goes to deep idle. - */ -void usart_set_baud(struct usart_config const *config, int baud); - -/* - * Different families provide different ways of clearing the transmit complete - * flag. This function will be provided by the family specific implementation. - */ -void usart_clear_tc(struct usart_config const *config); - -/* - * Each family implementation provides the usart_get_configs function to access - * a read only list of the configs that are currently enabled. - */ -struct usart_configs { - /* - * The family's usart_config array, entries in the array for disabled - * configs will be NULL, enabled configs will point to the usart_config - * that was enabled. And the following will be true: - * - * configs[i]->hw->index == i; - */ - struct usart_config const * const *configs; - - /* - * The total possible number of configs that this family supports. - * This will be the same as the number of usart_hw structs that the - * family provides in its family specific usart header. - */ - size_t count; -}; - -struct usart_configs usart_get_configs(void); - -#endif /* __CROS_EC_USART_H */ diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c deleted file mode 100644 index f6a76d99f3..0000000000 --- a/chip/stm32/usart_info_command.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Console command to query USART state - */ -#include "atomic.h" -#include "common.h" -#include "console.h" -#include "usart.h" - -static int command_usart_info(int argc, char **argv) -{ - struct usart_configs configs = usart_get_configs(); - size_t i; - - for (i = 0; i < configs.count; i++) { - struct usart_config const *config = configs.configs[i]; - - if (config == NULL) - continue; - - ccprintf("USART%d\n" - " dropped %d bytes\n" - " overran %d times\n", - config->hw->index + 1, - atomic_read_clear(&(config->state->rx_dropped)), - atomic_read_clear(&(config->state->rx_overrun))); - - if (config->rx->info) - config->rx->info(config); - - if (config->tx->info) - config->tx->info(config); - } - - return EC_SUCCESS; -} - -DECLARE_CONSOLE_COMMAND(usart_info, - command_usart_info, - NULL, - "Display USART info"); diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c deleted file mode 100644 index 0e26763de6..0000000000 --- a/chip/stm32/usart_rx_dma.c +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "usart_rx_dma.h" - -#include "atomic.h" -#include "common.h" -#include "console.h" -#include "registers.h" -#include "system.h" -#include "util.h" - -void usart_rx_dma_init(struct usart_config const *config) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - intptr_t base = config->hw->base; - - struct dma_option options = { - .channel = dma_config->channel, - .periph = (void *)&STM32_USART_RDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC), - }; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; - STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR; - - dma_config->state->index = 0; - dma_config->state->max_bytes = 0; - - dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer); -} - -void usart_rx_dma_interrupt(struct usart_config const *config) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - dma_chan_t *channel = dma_get_channel(dma_config->channel); - size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); - size_t old_index = dma_config->state->index; - size_t new_bytes = 0; - size_t added = 0; - - if (new_index > old_index) { - new_bytes = new_index - old_index; - - added = queue_add_units(config->producer.queue, - dma_config->fifo_buffer + old_index, - new_bytes); - } else if (new_index < old_index) { - /* - * Handle the case where the received bytes are not contiguous - * in the circular DMA buffer. This is done with two queue - * adds. - */ - new_bytes = dma_config->fifo_size - (old_index - new_index); - - added = queue_add_units(config->producer.queue, - dma_config->fifo_buffer + old_index, - dma_config->fifo_size - old_index) + - queue_add_units(config->producer.queue, - dma_config->fifo_buffer, - new_index); - } else { - /* (new_index == old_index): nothing to add to the queue. */ - } - - atomic_add(&config->state->rx_dropped, new_bytes - added); - - if (dma_config->state->max_bytes < new_bytes) - dma_config->state->max_bytes = new_bytes; - - dma_config->state->index = new_index; -} - -void usart_rx_dma_info(struct usart_config const *config) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - ccprintf(" DMA RX max_bytes %d\n", - atomic_read_clear(&dma_config->state->max_bytes)); -} diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h deleted file mode 100644 index a5a04e2829..0000000000 --- a/chip/stm32/usart_rx_dma.h +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Hybrid DMA/Interrupt based USART RX driver for STM32 - */ -#ifndef __CROS_EC_USART_RX_DMA_H -#define __CROS_EC_USART_RX_DMA_H - -#include "producer.h" -#include "dma.h" -#include "queue.h" -#include "usart.h" - -/* - * Only reference the usart_rx_dma_info function if CONFIG_CMD_USART_INFO - * is defined. This allows the compiler to remove this function as dead code - * when CONFIG_CMD_USART_INFO is not defined. - */ -#ifdef CONFIG_CMD_USART_INFO -#define USART_RX_DMA_INFO usart_rx_dma_info -#else -#define USART_RX_DMA_INFO NULL -#endif - -/* - * Construct a USART RX instance for DMA using the given DMA channel. - * - * This macro creates a new usart_rx_dma struct, complete with in RAM state, - * the contained usart_rx struct can be used in initializing a usart_config - * struct. - * - * CHANNEL is the DMA channel to be used for reception. This must be a valid - * DMA channel for the USART peripheral and any alternate channel mappings must - * be handled by the board specific code. - * - * FIFO_SIZE is the number of bytes (which does not need to be a power of two) - * to use for the DMA circular buffer. This buffer must be large enough to - * hide the worst case interrupt latency the system will encounter. The DMA - * RX driver adds to the output of the usart_info command a high water mark - * of how many bytes were transferred out of this FIFO on any one interrupt. - * This value can be used to correctly size the FIFO by setting the FIFO_SIZE - * to something large, stress test the USART, and run usart_info. After a - * reasonable stress test the "DMA RX max_bytes" value will be a reasonable - * size for the FIFO (perhaps +10% for safety). - */ -#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ - ((struct usart_rx_dma const) { \ - .usart_rx = { \ - .producer_ops = { \ - .read = NULL, \ - }, \ - \ - .init = usart_rx_dma_init, \ - .interrupt = usart_rx_dma_interrupt, \ - .info = USART_RX_DMA_INFO, \ - }, \ - \ - .state = &((struct usart_rx_dma_state) {}), \ - .fifo_buffer = ((uint8_t[FIFO_SIZE]) {}), \ - .fifo_size = FIFO_SIZE, \ - .channel = CHANNEL, \ - }) - -/* - * In RAM state required to manage DMA based transmission. - */ -struct usart_rx_dma_state { - /* - * Previous value of dma_bytes_done. This will wrap when the DMA fills - * the queue. - */ - size_t index; - - /* - * Maximum number of bytes transferred in any one RX interrupt. - */ - uint32_t max_bytes; -}; - -/* - * Extension of the usart_rx struct to include required configuration for - * DMA based transmission. - */ -struct usart_rx_dma { - struct usart_rx usart_rx; - - struct usart_rx_dma_state volatile *state; - - uint8_t *fifo_buffer; - size_t fifo_size; - - enum dma_channel channel; -}; - -/* - * Function pointers needed to initialize a usart_rx struct. These shouldn't - * be called in any other context as they assume that the producer or config - * that they are passed was initialized with a complete usart_rx_dma struct. - */ -void usart_rx_dma_init(struct usart_config const *config); -void usart_rx_dma_interrupt(struct usart_config const *config); - -/* - * Debug function, used to print DMA RX statistics to the console. - */ -void usart_rx_dma_info(struct usart_config const *config); - -#endif /* __CROS_EC_USART_RX_DMA_H */ diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f0.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c
\ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c
\ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c deleted file mode 100644 index 061689edf1..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32l.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART RX driver for STM32L */ - -#include "usart.h" - -#include "atomic.h" -#include "common.h" -#include "queue.h" -#include "registers.h" - -static void usart_rx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; -} - -static void usart_rx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); - - /* - * We have to check and clear the overrun error flag on STM32L because - * we can't disable it. - */ - if (status & STM32_USART_SR_ORE) { - /* - * In the unlikely event that the overrun error bit was set but - * the RXNE bit was not (possibly because a read was done from - * RDR without first reading the status register) we do a read - * here to clear the overrun error bit. - */ - if (!(status & STM32_USART_SR_RXNE)) - (void)STM32_USART_RDR(config->hw->base); - - atomic_add(&config->state->rx_overrun, 1); - } - - if (status & STM32_USART_SR_RXNE) { - uint8_t byte = STM32_USART_RDR(base); - - if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add(&config->state->rx_dropped, 1); - } -} - -struct usart_rx const usart_rx_interrupt = { - .producer_ops = { - /* - * Nothing to do here, we either had enough space in the queue - * when a character came in or we dropped it already. - */ - .read = NULL, - }, - - .init = usart_rx_init, - .interrupt = usart_rx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c deleted file mode 100644 index 007cc63467..0000000000 --- a/chip/stm32/usart_rx_interrupt.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ - -#include "usart.h" - -#include "atomic.h" -#include "common.h" -#include "queue.h" -#include "registers.h" - -static void usart_rx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; - STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; -} - -static void usart_rx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); - - if (status & STM32_USART_SR_RXNE) { - uint8_t byte = STM32_USART_RDR(base); - - if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add(&config->state->rx_dropped, 1); - } -} - -struct usart_rx const usart_rx_interrupt = { - .producer_ops = { - /* - * Nothing to do here, we either had enough space in the queue - * when a character came in or we dropped it already. - */ - .read = NULL, - }, - - .init = usart_rx_init, - .interrupt = usart_rx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c deleted file mode 100644 index 0c8e2c73d6..0000000000 --- a/chip/stm32/usart_tx_dma.c +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart_tx_dma.h" - -#include "usart.h" -#include "common.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -void usart_tx_dma_written(struct consumer const *consumer, size_t count) -{ - struct usart_config const *config = - DOWNCAST(consumer, struct usart_config, consumer); - - task_trigger_irq(config->hw->irq); -} - -void usart_tx_dma_init(struct usart_config const *config) -{ - struct usart_tx_dma const *dma_config = - DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx); - - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_TE; - STM32_USART_CR3(base) |= STM32_USART_CR3_DMAT; - - dma_config->state->dma_active = 0; -} - -static void usart_tx_dma_start(struct usart_config const *config, - struct usart_tx_dma const *dma_config) -{ - struct usart_tx_dma_state volatile *state = dma_config->state; - intptr_t base = config->hw->base; - - struct dma_option options = { - .channel = dma_config->channel, - .periph = (void *)&STM32_USART_TDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT), - }; - - /* - * Limit our DMA transfer. If we didn't do this then it would be - * possible to start a large DMA transfer of an entirely full buffer - * that would hold up any additional writes to the TX queue - * unnecessarily. - */ - state->chunk.count = MIN(state->chunk.count, dma_config->max_bytes); - - dma_prepare_tx(&options, state->chunk.count, state->chunk.buffer); - - state->dma_active = 1; - - usart_clear_tc(config); - STM32_USART_CR1(base) |= STM32_USART_CR1_TCIE; - - dma_go(dma_get_channel(options.channel)); -} - -static void usart_tx_dma_stop(struct usart_config const *config, - struct usart_tx_dma const *dma_config) -{ - dma_config->state->dma_active = 0; - - STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_TCIE; -} - -void usart_tx_dma_interrupt(struct usart_config const *config) -{ - struct usart_tx_dma const *dma_config = - DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx); - struct usart_tx_dma_state volatile *state = dma_config->state; - - /* - * If we have completed a DMA transaction, or if we haven't yet started - * one then we clean up and start one now. - */ - if ((STM32_USART_SR(config->hw->base) & STM32_USART_SR_TC) || - !state->dma_active) { - struct queue const *queue = config->consumer.queue; - - /* - * Only advance the queue head (indicating that we have read - * units from the queue if we had an active DMA transfer. - */ - if (state->dma_active) - queue_advance_head(queue, state->chunk.count); - - state->chunk = queue_get_read_chunk(queue); - - if (state->chunk.count) - usart_tx_dma_start(config, dma_config); - else - usart_tx_dma_stop(config, dma_config); - } -} diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h deleted file mode 100644 index c17164e04a..0000000000 --- a/chip/stm32/usart_tx_dma.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * DMA based USART TX driver for STM32 - */ -#ifndef __CROS_EC_USART_TX_DMA_H -#define __CROS_EC_USART_TX_DMA_H - -#include "consumer.h" -#include "dma.h" -#include "queue.h" -#include "usart.h" - -/* - * Construct a USART TX instance for DMA using the given DMA channel. - * - * This macro creates a new usart_tx_dma struct, complete with in RAM state, - * the contained usart_tx struct can be used in initializing a usart_config - * struct. - * - * CHANNEL is the DMA channel to be used for transmission. This must be a - * valid DMA channel for the USART peripheral and any alternate channel - * mappings must be handled by the board specific code. - * - * MAX_BYTES is the maximum size in bytes of a single DMA transfer. This - * allows the board to tune how often the TX engine updates the queue state. - * A larger number here could cause the queue to appear full for longer than - * required because the queue isn't notified that it has been read from until - * after the DMA transfer completes. - */ -#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ - ((struct usart_tx_dma const) { \ - .usart_tx = { \ - .consumer_ops = { \ - .written = usart_tx_dma_written,\ - }, \ - \ - .init = usart_tx_dma_init, \ - .interrupt = usart_tx_dma_interrupt, \ - .info = NULL, \ - }, \ - \ - .state = &((struct usart_tx_dma_state){}), \ - .channel = CHANNEL, \ - .max_bytes = MAX_BYTES, \ - }) - -/* - * In RAM state required to manage DMA based transmission. - */ -struct usart_tx_dma_state { - /* - * The current chunk of queue buffer being used for transmission. Once - * the transfer is complete, this is used to update the TX queue head - * pointer as well. - */ - struct queue_chunk chunk; - - /* - * Flag indicating whether a DMA transfer is currently active. - */ - int dma_active; -}; - -/* - * Extension of the usart_tx struct to include required configuration for - * DMA based transmission. - */ -struct usart_tx_dma { - struct usart_tx usart_tx; - - struct usart_tx_dma_state volatile *state; - - enum dma_channel channel; - - size_t max_bytes; -}; - -/* - * Function pointers needed to initialize a usart_tx struct. These shouldn't - * be called in any other context as they assume that the consumer or config - * that they are passed was initialized with a complete usart_tx_dma struct. - */ -void usart_tx_dma_written(struct consumer const *consumer, size_t count); -void usart_tx_dma_flush(struct consumer const *consumer); -void usart_tx_dma_init(struct usart_config const *config); -void usart_tx_dma_interrupt(struct usart_config const *config); - -#endif /* __CROS_EC_USART_TX_DMA_H */ diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c deleted file mode 100644 index 7c7f1f84de..0000000000 --- a/chip/stm32/usart_tx_interrupt.c +++ /dev/null @@ -1,75 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART TX driver for STM32 */ - -#include "usart.h" - -#include "common.h" -#include "registers.h" -#include "system.h" -#include "util.h" - -static void usart_tx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_TE; -} - -static void usart_written(struct consumer const *consumer, size_t count) -{ - struct usart_config const *config = - DOWNCAST(consumer, struct usart_config, consumer); - - /* - * Enable USART interrupt. This causes the USART interrupt handler to - * start fetching from the TX queue if it wasn't already. - */ - if (count) - STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE; -} - -static void usart_tx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - uint8_t byte; - - if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE)) - return; - - if (queue_remove_unit(config->consumer.queue, &byte)) { - STM32_USART_TDR(base) = byte; - - /* - * Make sure the TXE interrupt is enabled and that we won't go - * into deep sleep. This invocation of the USART interrupt - * handler may have been manually triggered to start - * transmission. - */ - disable_sleep(SLEEP_MASK_UART); - - STM32_USART_CR1(base) |= STM32_USART_CR1_TXEIE; - } else { - /* - * The TX queue is empty, disable the TXE interrupt and enable - * deep sleep mode. The TXE interrupt will remain disabled - * until a write call happens. - */ - enable_sleep(SLEEP_MASK_UART); - - STM32_USART_CR1(base) &= ~STM32_USART_CR1_TXEIE; - } -} - -struct usart_tx const usart_tx_interrupt = { - .consumer_ops = { - .written = usart_written, - }, - - .init = usart_tx_init, - .interrupt = usart_tx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c deleted file mode 100644 index 08c0a17455..0000000000 --- a/chip/stm32/usb-stm32f0.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F0 Family specific USB functionality - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_USB_BCDR |= BIT(15) /* DPPU */; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~BIT(15) /* DPPU */; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c deleted file mode 100644 index 2376d00b41..0000000000 --- a/chip/stm32/usb-stm32f3.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F3 Family specific USB functionality - */ - -#include "usb-stm32f3.h" - -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - usb_board_connect(); -} - -void usb_disconnect(void) -{ - usb_board_disconnect(); - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h deleted file mode 100644 index 196c43a53a..0000000000 --- a/chip/stm32/usb-stm32f3.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F3 Family specific USB functionality - */ - -/* - * A device that uses an STM32F3 part will need to define these two functions - * which are used to connect and disconnect the device from the USB bus. This - * is usually accomplished by enabling a pullup on the DP USB line. The pullup - * should be enabled by default so that the STM32 will enumerate correctly in - * DFU mode (which doesn't know how to enable the DP pullup, so it assumes that - * the pullup is always there). - */ -void usb_board_connect(void); -void usb_board_disconnect(void); diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c deleted file mode 100644 index bb9838531b..0000000000 --- a/chip/stm32/usb-stm32l.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32L Family specific USB functionality - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_SYSCFG_PMC |= 1; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_SYSCFG_PMC &= ~1; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c deleted file mode 100644 index 5741201ff1..0000000000 --- a/chip/stm32/usb-stream.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "common.h" -#include "config.h" -#include "link_defs.h" -#include "printf.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usart.h" -#include "usb_hw.h" -#include "usb-stream.h" - -static size_t rx_read(struct usb_stream_config const *config) -{ - uintptr_t address = btable_ep[config->endpoint].rx_addr; - size_t count = btable_ep[config->endpoint].rx_count & 0x3ff; - - /* - * Only read the received USB packet if there is enough space in the - * receive queue. - */ - if (count > queue_space(config->producer.queue)) - return 0; - - return queue_add_memcpy(config->producer.queue, - (void *) address, - count, - memcpy_from_usbram); -} - -static size_t tx_write(struct usb_stream_config const *config) -{ - uintptr_t address = btable_ep[config->endpoint].tx_addr; - size_t count = queue_remove_memcpy(config->consumer.queue, - (void *) address, - config->tx_size, - memcpy_to_usbram); - - btable_ep[config->endpoint].tx_count = count; - - return count; -} - -static int tx_valid(struct usb_stream_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) == EP_TX_VALID; -} - -static int rx_valid(struct usb_stream_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID; -} - -static int rx_disabled(struct usb_stream_config const *config) -{ - return config->state->rx_disabled; -} - -static void usb_read(struct producer const *producer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(producer, struct usb_stream_config, producer); - - hook_call_deferred(config->deferred, 0); -} - -static void usb_written(struct consumer const *consumer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(consumer, struct usb_stream_config, consumer); - - hook_call_deferred(config->deferred, 0); -} - -struct producer_ops const usb_stream_producer_ops = { - .read = usb_read, -}; - -struct consumer_ops const usb_stream_consumer_ops = { - .written = usb_written, -}; - -void usb_stream_deferred(struct usb_stream_config const *config) -{ - if (!tx_valid(config) && tx_write(config)) - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); - - if (!rx_valid(config) && !rx_disabled(config) && rx_read(config)) - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); -} - -void usb_stream_tx(struct usb_stream_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - - hook_call_deferred(config->deferred, 0); -} - -void usb_stream_rx(struct usb_stream_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - - hook_call_deferred(config->deferred, 0); -} - -static usb_uint usb_ep_rx_size(size_t bytes) -{ - if (bytes < 64) - return bytes << 9; - else - return 0x8000 | ((bytes - 32) << 5); -} - -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) -{ - int i; - - if (evt != USB_EVENT_RESET) - return; - - i = config->endpoint; - - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); - btable_ep[i].tx_count = 0; - - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); - btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size); - - config->state->rx_waiting = 0; - - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID)); -} - -int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, - usb_uint *rx_buf, usb_uint *tx_buf) -{ - struct usb_setup_packet req; - - usb_read_setup_packet(rx_buf, &req); - - if (req.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) - return -1; - - if (req.wIndex != interface || - req.wLength != 0) - return -1; - - switch (req.bRequest) { - /* Set parity. */ - case USB_USART_SET_PARITY: - usart_set_parity(usart, req.wValue); - break; - case USB_USART_SET_BAUD: - usart_set_baud(usart, req.wValue * 100); - break; - - /* TODO(nsanders): support reading parity. */ - /* TODO(nsanders): support reading baud. */ - default: - return -1; - } - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT); - return 0; -} diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h deleted file mode 100644 index 915d8905cd..0000000000 --- a/chip/stm32/usb-stream.h +++ /dev/null @@ -1,301 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_STREAM_H -#define __CROS_EC_USB_STREAM_H - -#if defined(CHIP_FAMILY_STM32F4) -#include "usb_dwc_stream.h" -#else - -/* STM32 USB STREAM driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "consumer.h" -#include "hooks.h" -#include "producer.h" -#include "queue.h" -#include "usart.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -#include <stdint.h> - -/* - * Per-USB stream state stored in RAM. Zero initialization of this structure - * by the BSS initialization leaves it in a valid and correctly initialized - * state, so there is no need currently for a usb_stream_init style function. - */ -struct usb_stream_state { - /* - * Flag indicating that there is a full RX buffer in the USB packet RAM - * that we were not able to move into the RX queue because there was - * not enough room when the packet was initially received. The - * producer read operation checks this flag so that once there is - * room in the queue it can copy the RX buffer into the queue and - * restart USB reception by marking the RX buffer as VALID. - */ - int rx_waiting; - /* - * Flag indicating that the incoming data on the USB link are discarded. - */ - int rx_disabled; -}; - -/* - * Compile time Per-USB stream configuration stored in flash. Instances of this - * structure are provided by the user of the USB stream. This structure binds - * together all information required to operate a USB stream. - */ -struct usb_stream_config { - /* - * Pointer to usb_stream_state structure. The state structure - * maintains per USB stream information. - */ - struct usb_stream_state volatile *state; - - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - - /* - * Deferred function to call to handle USB and Queue request. - */ - const struct deferred_data *deferred; - - size_t rx_size; - size_t tx_size; - - usb_uint *rx_ram; - usb_uint *tx_ram; - - struct consumer consumer; - struct producer producer; -}; - -/* - * These function tables are defined by the USB Stream driver and are used to - * initialize the consumer and producer in the usb_stream_config. - */ -extern struct consumer_ops const usb_stream_consumer_ops; -extern struct producer_ops const usb_stream_producer_ops; - -/* - * Convenience macro for defining USB streams and their associated state and - * buffers. - * - * NAME is used to construct the names of the packet RAM buffers, trampoline - * functions, usb_stream_state struct, and usb_stream_config struct, the - * latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * stream. - * - * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the - * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields - * respectively in the USB interface descriptor. - * - * INTERFACE_NAME is the index of the USB string descriptor (iInterface). - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - * - * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate - * for the RX and TX packets respectively. The valid values for these - * parameters are dictated by the USB peripheral. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver - * should write to and read from respectively. - */ -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE); - * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE); - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(RX_SIZE > 0); \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ - (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ - static struct usb_stream_state CONCAT2(NAME, _state); \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_stream_config const NAME = { \ - .state = &CONCAT2(NAME, _state), \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .rx_size = RX_SIZE, \ - .tx_size = TX_SIZE, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &usb_stream_consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &usb_stream_producer_ops, \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_stream_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_stream_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_stream_deferred(&NAME); } - -/* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) - -/* Declare a utility interface for setting parity/baud. */ -#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ - rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)) - -/* This is a medium version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG_USART_IFACE(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE, \ - USART_CFG) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE); \ - USB_USART_IFACE(NAME, INTERFACE, USART_CFG) - -/* - * Handle USB and Queue request in a deferred callback. - */ -void usb_stream_deferred(struct usb_stream_config const *config); - -/* - * Handle control interface requests. - */ -enum usb_usart { - USB_USART_REQ_PARITY = 0, - USB_USART_SET_PARITY = 1, - USB_USART_REQ_BAUD = 2, - USB_USART_SET_BAUD = 3, -}; - -/* - * baud rate is req/set in multiples of 100, to avoid overflowing - * 16-bit integer. - */ -#define USB_USART_BAUD_MULTIPLIER 100 - -int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, usb_uint *rx_buf, usb_uint *tx_buf); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB stream driver. - */ -void usb_stream_tx(struct usb_stream_config const *config); -void usb_stream_rx(struct usb_stream_config const *config); -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); - -#endif /* defined(CHIP_FAMILY_STM32F4) */ -#endif /* __CROS_EC_USB_STREAM_H */ diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c deleted file mode 100644 index c901c293f7..0000000000 --- a/chip/stm32/usb.c +++ /dev/null @@ -1,878 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "flash.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -#ifdef CONFIG_USB_BOS -/* v2.10 (vs 2.00) BOS Descriptor provided */ -#define USB_DEV_BCDUSB 0x0210 -#else -#define USB_DEV_BCDUSB 0x0200 -#endif - -#ifndef USB_DEV_CLASS -#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE -#endif - -#ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ -#endif - -#ifndef CONFIG_USB_SERIALNO -#define USB_STR_SERIALNO 0 -#else -static int usb_load_serial(void); -#endif - -#define USB_RESUME_TIMEOUT_MS 3000 - -/* USB Standard Device Descriptor */ -static const struct usb_device_descriptor dev_desc = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = USB_DEV_BCDUSB, - .bDeviceClass = USB_DEV_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = USB_MAX_PACKET_SIZE, - .idVendor = USB_VID_GOOGLE, - .idProduct = CONFIG_USB_PID, - .bcdDevice = CONFIG_USB_BCD_DEV, - .iManufacturer = USB_STR_VENDOR, - .iProduct = USB_STR_PRODUCT, - .iSerialNumber = USB_STR_SERIALNO, - .bNumConfigurations = 1 -}; - -/* USB Configuration Descriptor */ -const struct usb_config_descriptor USB_CONF_DESC(conf) = { - .bLength = USB_DT_CONFIG_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* no of returned bytes, set at runtime */ - .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, - .iConfiguration = USB_STR_VERSION, - .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 -#endif - , - .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), -}; - -const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ -}; - -/* Endpoint table in USB controller RAM */ -struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable; -/* Control endpoint (EP0) buffers */ -static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; - -#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx)) - -static int set_addr; -/* remaining size of descriptor data to transfer */ -static int desc_left; -/* pointer to descriptor data if any */ -static const uint8_t *desc_ptr; -/* interface that should handle the next tx transaction */ -static uint8_t iface_next = USB_IFACE_COUNT; -#ifdef CONFIG_USB_REMOTE_WAKEUP -/* remote wake up feature enabled */ -static int remote_wakeup_enabled; -#endif - -void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet) -{ - packet->bmRequestType = buffer[0] & 0xff; - packet->bRequest = buffer[0] >> 8; - packet->wValue = buffer[1]; - packet->wIndex = buffer[2]; - packet->wLength = buffer[3]; -} - -struct usb_descriptor_patch { - const void *address; - uint16_t data; -}; - -static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT]; - -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data) -{ - desc_patches[type].address = address; - desc_patches[type].data = data; -} - -void *memcpy_to_usbram_ep0_patch(const void *src, size_t n) -{ - int i; - void *ret; - - ret = memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), src, n); - - for (i = 0; i < USB_DESC_PATCH_COUNT; i++) { - unsigned int offset = desc_patches[i].address - src; - - if (offset >= n) - continue; - - memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset), - &desc_patches[i].data, sizeof(desc_patches[i].data)); - } - - return ret; -} - -static void ep0_send_descriptor(const uint8_t *desc, int len, - uint16_t fixup_size) -{ - /* do not send more than what the host asked for */ - len = MIN(ep0_buf_rx[3], len); - /* - * if we cannot transmit everything at once, - * keep the remainder for the next IN packet - */ - if (len >= USB_MAX_PACKET_SIZE) { - desc_left = len - USB_MAX_PACKET_SIZE; - desc_ptr = desc + USB_MAX_PACKET_SIZE; - len = USB_MAX_PACKET_SIZE; - } - memcpy_to_usbram_ep0_patch(desc, len); - if (fixup_size) /* set the real descriptor size */ - ep0_buf_tx[1] = fixup_size; - btable_ep[0].tx_count = len; - /* send the null OUT transaction if the transfer is complete */ - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - desc_left ? 0 : EP_STATUS_OUT); -} - -/* Requests on the control endpoint (aka EP0) */ -static void ep0_rx(void) -{ - uint16_t req = ep0_buf_rx[0]; /* bRequestType | bRequest */ - - /* reset any incomplete descriptor transfer */ - desc_ptr = NULL; - iface_next = USB_IFACE_COUNT; - - /* interface specific requests */ - if ((req & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { - uint8_t iface = ep0_buf_rx[2] & 0xff; - if (iface < USB_IFACE_COUNT) { - int ret; - - ret = usb_iface_request[iface](ep0_buf_rx, ep0_buf_tx); - if (ret < 0) - goto unknown_req; - if (ret == 1) - iface_next = iface; - return; - } - } - /* vendor specific request */ - if ((req & USB_TYPE_MASK) == USB_TYPE_VENDOR) { -#ifdef CONFIG_WEBUSB_URL - uint8_t b_req = req >> 8; /* bRequest in the transfer */ - uint16_t idx = ep0_buf_rx[2]; /* wIndex in the transfer */ - - if (b_req == 0x01 && idx == WEBUSB_REQ_GET_URL) { - int len = *(uint8_t *)webusb_url; - - ep0_send_descriptor(webusb_url, len, 0); - return; - } -#endif - goto unknown_req; - } - - /* TODO check setup bit ? */ - if (req == (USB_DIR_IN | (USB_REQ_GET_DESCRIPTOR << 8))) { - uint8_t type = ep0_buf_rx[1] >> 8; - uint8_t idx = ep0_buf_rx[1] & 0xff; - const uint8_t *desc; - int len; - - switch (type) { - case USB_DT_DEVICE: /* Setup : Get device descriptor */ - desc = (void *)&dev_desc; - len = sizeof(dev_desc); - break; - case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */ - desc = __usb_desc; - len = USB_DESC_SIZE; - break; -#ifdef CONFIG_USB_BOS - case USB_DT_BOS: /* Setup : Get BOS descriptor */ - desc = bos_ctx.descp; - len = bos_ctx.size; - break; -#endif - case USB_DT_STRING: /* Setup : Get string descriptor */ - if (idx >= USB_STR_COUNT) - /* The string does not exist : STALL */ - goto unknown_req; -#ifdef CONFIG_USB_SERIALNO - if (idx == USB_STR_SERIALNO) - desc = (uint8_t *)usb_serialno_desc; - else -#endif - desc = usb_strings[idx]; - len = desc[0]; - break; - case USB_DT_DEVICE_QUALIFIER: /* Get device qualifier desc */ - /* Not high speed : STALL next IN used as handshake */ - goto unknown_req; - default: /* unhandled descriptor */ - goto unknown_req; - } - ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ? - USB_DESC_SIZE : 0); - } else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) { - uint16_t data = 0; - /* Get status */ -#ifdef CONFIG_USB_SELF_POWERED - data |= USB_REQ_GET_STATUS_SELF_POWERED; -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (remote_wakeup_enabled) - data |= USB_REQ_GET_STATUS_REMOTE_WAKEUP; -#endif - memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2); - btable_ep[0].tx_count = 2; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT /*null OUT transaction */); - } else if ((req & 0xff) == USB_DIR_OUT) { - switch (req >> 8) { - case USB_REQ_SET_FEATURE: - case USB_REQ_CLEAR_FEATURE: -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (ep0_buf_rx[1] == - USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { - remote_wakeup_enabled = - ((req >> 8) == USB_REQ_SET_FEATURE); - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, - EP_TX_RX_VALID, 0); - break; - } -#endif - goto unknown_req; - case USB_REQ_SET_ADDRESS: - /* set the address after we got IN packet handshake */ - set_addr = ep0_buf_rx[1] & 0xff; - /* need null IN transaction -> TX Valid */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - break; - case USB_REQ_SET_CONFIGURATION: - /* uint8_t cfg = ep0_buf_rx[1] & 0xff; */ - /* null IN for handshake */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - break; - default: /* unhandled request */ - goto unknown_req; - } - - } else { - goto unknown_req; - } - - return; -unknown_req: - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_RX_VALID | EP_TX_STALL, 0); -} - -static void ep0_tx(void) -{ - if (set_addr) { - STM32_USB_DADDR = set_addr | 0x80; - set_addr = 0; - CPRINTF("SETAD %02x\n", STM32_USB_DADDR); - } - if (desc_ptr) { - /* we have an on-going descriptor transfer */ - int len = MIN(desc_left, USB_MAX_PACKET_SIZE); - memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, desc_ptr, len); - btable_ep[0].tx_count = len; - desc_left -= len; - desc_ptr += len; - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, - desc_left ? 0 : EP_STATUS_OUT); - /* send the null OUT transaction if the transfer is complete */ - return; - } - if (iface_next < USB_IFACE_COUNT) { - int ret; - - ret = usb_iface_request[iface_next](NULL, ep0_buf_tx); - if (ret < 0) - goto error; - if (ret == 0) - iface_next = USB_IFACE_COUNT; - return; - } - -error: - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, 0); -} - -static void ep0_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - STM32_USB_EP(0) = BIT(9) /* control EP */ | - (2 << 4) /* TX NAK */ | - (3 << 12) /* RX VALID */; - - btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx); - btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx); - btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10); - btable_ep[0].tx_count = 0; -} -USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event); - -static void usb_reset(void) -{ - int ep; - - for (ep = 0; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_RESET); - - /* - * set the default address : 0 - * as we are not configured yet - */ - STM32_USB_DADDR = 0 | 0x80; - CPRINTF("RST EP0 %04x\n", STM32_USB_EP(0)); -} - -#ifdef CONFIG_USB_SUSPEND -static void usb_pm_change_notify_hooks(void) -{ - hook_notify(HOOK_USB_PM_CHANGE); -} -DECLARE_DEFERRED(usb_pm_change_notify_hooks); - -/* See RM0091 Reference Manual 30.5.5 Suspend/Resume events */ -static void usb_suspend(void) -{ - CPRINTF("SUS%d\n", remote_wakeup_enabled); - - /* - * usb_suspend can be called from hook task, make sure no interrupt is - * modifying CNTR at the same time. - */ - interrupt_disable(); - /* Set FSUSP bit to activate suspend mode */ - STM32_USB_CNTR |= STM32_USB_CNTR_FSUSP; - - /* Set USB low power mode */ - STM32_USB_CNTR |= STM32_USB_CNTR_LP_MODE; - interrupt_enable(); - - clock_enable_module(MODULE_USB, 0); - - /* USB is not in use anymore, we can (hopefully) sleep now. */ - enable_sleep(SLEEP_MASK_USB_DEVICE); - - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); -} - -static void usb_resume_deferred(void) -{ - uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - CPRINTF("RSMd %d %04x\n", state, STM32_USB_CNTR); - if (state == 2 || state == 3) - usb_suspend(); - else - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); -} -DECLARE_DEFERRED(usb_resume_deferred); - -static void usb_resume(void) -{ - uint32_t state; - - clock_enable_module(MODULE_USB, 1); - - /* Clear FSUSP bit to exit suspend mode */ - STM32_USB_CNTR &= ~STM32_USB_CNTR_FSUSP; - - /* USB is in use again */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR); - - /* - * Reference manual tells we should go back to sleep if state is 10 or - * 11. However, setting FSUSP and LP_MODE in this interrupt routine - * seems to lock the USB controller (see b/35775088 and b/71688150). - * Instead, we do it in a deferred routine. The host must assert the - * reset condition for 20ms, so reading D+/D- after ~3ms should be safe - * (there is no chance we end up sampling during a bus transaction). - */ - if (state == 2 || state == 3) - hook_call_deferred(&usb_resume_deferred_data, 3 * MSEC); - else - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); -} - -#ifdef CONFIG_USB_REMOTE_WAKEUP -/* - * Makes sure usb_wake is only run once. When 0, wake is in progress. - */ -static volatile int usb_wake_done = 1; - -/* - * ESOF counter (incremented in interrupt), RESUME bit is cleared when - * this reaches 0. Also used to detect resume timeout. - */ -static volatile int esof_count; - -__attribute__((weak)) -void board_usb_wake(void) -{ - /* Side-band USB wake, do nothing by default. */ -} - -/* Called 10ms after usb_wake started. */ -static void usb_wake_deferred(void) -{ - if (esof_count == 3) { - /* - * If we reach here, it means that we are not counting ESOF/SOF - * properly (either of these interrupts should occur every 1ms). - * This should never happen if we implemented the resume logic - * correctly. - * - * We reset the controller in that case, which recovers the - * interface. - */ - CPRINTF("USB stuck\n"); - STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB; - STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB; - usb_init(); - } -} -DECLARE_DEFERRED(usb_wake_deferred); - -void usb_wake(void) -{ - if (!remote_wakeup_enabled || - !(STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)) { - /* - * USB wake not enabled, or already woken up, or already waking - * up, nothing to do. - */ - return; - } - - /* Only allow one caller at a time. */ - if (!atomic_read_clear(&usb_wake_done)) - return; - - CPRINTF("WAKE\n"); - - /* - * Sometimes the USB controller gets stuck, and does not count SOF/ESOF - * frames anymore, detect that. - */ - hook_call_deferred(&usb_wake_deferred_data, 10 * MSEC); - - /* - * Set RESUME bit for 1 to 15 ms, then clear it. We ask the interrupt - * routine to count 3 ESOF interrupts, which should take between - * 2 and 3 ms. - */ - esof_count = 3; - - /* STM32_USB_CNTR can also be updated from interrupt context. */ - interrupt_disable(); - STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | - STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM; - interrupt_enable(); - - /* Try side-band wake as well. */ - board_usb_wake(); -} -#endif - -int usb_is_suspended(void) -{ - /* Either hardware block is suspended... */ - if (STM32_USB_CNTR & STM32_USB_CNTR_FSUSP) - return 1; - -#ifdef CONFIG_USB_REMOTE_WAKEUP - /* ... or we are currently waking up. */ - if (!usb_wake_done) - return 1; -#endif - - return 0; -} - -int usb_is_remote_wakeup_enabled(void) -{ -#ifdef CONFIG_USB_REMOTE_WAKEUP - return remote_wakeup_enabled; -#else - return 0; -#endif -} -#endif /* CONFIG_USB_SUSPEND */ - -#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_USB_REMOTE_WAKEUP) -/* - * Called by usb_interrupt when usb_wake is asking us to count esof_count ESOF - * interrupts (one per millisecond), then disable RESUME, then wait for resume - * to complete. - */ -static void usb_interrupt_handle_wake(uint16_t status) -{ - int state; - int good; - - esof_count--; - - /* Keep counting. */ - if (esof_count > 0) - return; - - /* Clear RESUME bit. */ - if (esof_count == 0) - STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME; - - /* Then count down until state is resumed. */ - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - /* - * state 2, or receiving an SOF, means resume - * completed successfully. - */ - good = (status & STM32_USB_ISTR_SOF) || (state == 2); - - /* Either: state is ready, or we timed out. */ - if (good || state == 3 || esof_count <= -USB_RESUME_TIMEOUT_MS) { - int ep; - - STM32_USB_CNTR &= ~(STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM); - usb_wake_done = 1; - if (!good) { - CPRINTF("wake error: cnt=%d state=%d\n", - esof_count, state); - usb_suspend(); - return; - } - - CPRINTF("RSMOK%d %d\n", -esof_count, state); - - for (ep = 1; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_DEVICE_RESUME); - } -} -#endif /* CONFIG_USB_SUSPEND && CONFIG_USB_REMOTE_WAKEUP */ - -void usb_interrupt(void) -{ - uint16_t status = STM32_USB_ISTR; - - if (status & STM32_USB_ISTR_RESET) - usb_reset(); - -#ifdef CONFIG_USB_SUSPEND -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) && - !usb_wake_done) - usb_interrupt_handle_wake(status); -#endif - - if (status & STM32_USB_ISTR_SUSP) - usb_suspend(); - - if (status & STM32_USB_ISTR_WKUP) - usb_resume(); -#endif - - if (status & STM32_USB_ISTR_CTR) { - int ep = status & STM32_USB_ISTR_EP_ID_MASK; - if (ep < USB_EP_COUNT) { - if (status & STM32_USB_ISTR_DIR) - usb_ep_rx[ep](); - else - usb_ep_tx[ep](); - } - /* TODO: do it in a USB task */ - /* task_set_event(, 1 << ep_task); */ - } - - /* ack only interrupts that we handled */ - STM32_USB_ISTR = ~status; -} -DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1); - -void usb_init(void) -{ - /* Enable USB device clock. */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; - - /* we need a proper 48MHz clock */ - clock_enable_module(MODULE_USB, 1); - - /* configure the pinmux */ - gpio_config_module(MODULE_USB, 1); - - /* power on sequence */ - - /* keep FRES (USB reset) and remove PDWN (power down) */ - STM32_USB_CNTR = STM32_USB_CNTR_FRES; - udelay(1); /* startup time */ - /* reset FRES and keep interrupts masked */ - STM32_USB_CNTR = 0x00; - /* clear pending interrupts */ - STM32_USB_ISTR = 0; - - /* set descriptors table offset in dedicated SRAM */ - STM32_USB_BTABLE = 0; - - /* EXTI18 is USB wake up interrupt */ - /* STM32_EXTI_RTSR |= BIT(18); */ - /* STM32_EXTI_IMR |= BIT(18); */ - - /* Enable interrupt handlers */ - task_enable_irq(STM32_IRQ_USB_LP); - /* set interrupts mask : reset/correct transfer/errors */ - STM32_USB_CNTR = STM32_USB_CNTR_CTRM | - STM32_USB_CNTR_PMAOVRM | - STM32_USB_CNTR_ERRM | -#ifdef CONFIG_USB_SUSPEND - STM32_USB_CNTR_WKUPM | - STM32_USB_CNTR_SUSPM | -#endif - STM32_USB_CNTR_RESETM; - -#ifdef CONFIG_USB_SERIALNO - usb_load_serial(); -#endif -#ifndef CONFIG_USB_INHIBIT_CONNECT - usb_connect(); -#endif - - CPRINTF("USB init done\n"); -} - -#ifndef CONFIG_USB_INHIBIT_INIT -DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT); -#endif - -void usb_release(void) -{ - /* signal disconnect to host */ - usb_disconnect(); - - /* power down USB */ - STM32_USB_CNTR = 0; - - /* disable interrupt handlers */ - task_disable_irq(STM32_IRQ_USB_LP); - - /* unset pinmux */ - gpio_config_module(MODULE_USB, 0); - - /* disable 48MHz clock */ - clock_enable_module(MODULE_USB, 0); - - /* disable USB device clock */ - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; -} -/* ensure the host disconnects and reconnects over a sysjump */ -DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT); - -int usb_is_enabled(void) -{ - return (STM32_RCC_APB1ENR & STM32_RCC_PB1_USB) ? 1 : 0; -} - -void *memcpy_to_usbram(void *dest, const void *src, size_t n) -{ - int unaligned = (((uintptr_t) dest) & 1); - usb_uint *d = &__usb_ram_start[((uintptr_t) dest) / 2]; - uint8_t *s = (uint8_t *) src; - int i; - - /* - * Handle unaligned leading byte via read/modify/write. - */ - if (unaligned && n) { - *d = (*d & ~0xff00) | (*s << 8); - n--; - s++; - d++; - } - - for (i = 0; i < n / 2; i++, s += 2) - *d++ = (s[1] << 8) | s[0]; - - /* - * There is a trailing byte to write into a final USB packet memory - * location, use a read/modify/write to be safe. - */ - if (n & 1) - *d = (*d & ~0x00ff) | *s; - - return dest; -} - -void *memcpy_from_usbram(void *dest, const void *src, size_t n) -{ - int unaligned = (((uintptr_t) src) & 1); - usb_uint const *s = &__usb_ram_start[((uintptr_t) src) / 2]; - uint8_t *d = (uint8_t *) dest; - int i; - - if (unaligned && n) { - *d = *s >> 8; - n--; - s++; - d++; - } - - for (i = 0; i < n / 2; i++) { - usb_uint value = *s++; - - *d++ = (value >> 0) & 0xff; - *d++ = (value >> 8) & 0xff; - } - - if (n & 1) - *d = *s; - - return dest; -} - -#ifdef CONFIG_USB_SERIALNO -/* This will be subbed into USB_STR_SERIALNO. */ -struct usb_string_desc *usb_serialno_desc = - USB_WR_STRING_DESC(DEFAULT_SERIALNO); - -/* Update serial number */ -static int usb_set_serial(const char *serialno) -{ - struct usb_string_desc *sd = usb_serialno_desc; - int i; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Convert into unicode usb string desc. */ - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) { - sd->_data[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - /* Count wchars (w/o null terminator) plus size & type bytes. */ - sd->_len = (i * 2) + 2; - sd->_type = USB_DT_STRING; - - return EC_SUCCESS; -} - -/* Retrieve serial number from pstate flash. */ -static int usb_load_serial(void) -{ - const char *serialno; - int rv; - - serialno = board_read_serial(); - if (!serialno) - return EC_ERROR_ACCESS_DENIED; - - rv = usb_set_serial(serialno); - return rv; -} - -/* Save serial number into pstate region. */ -static int usb_save_serial(const char *serialno) -{ - int rv; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Save this new serial number to flash. */ - rv = board_write_serial(serialno); - if (rv) - return rv; - - /* Load this new serial number to memory. */ - rv = usb_load_serial(); - return rv; -} - -static int command_serialno(int argc, char **argv) -{ - struct usb_string_desc *sd = usb_serialno_desc; - char buf[CONFIG_SERIALNO_LEN]; - int rv = EC_SUCCESS; - int i; - - if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { - ccprintf("Saving serial number\n"); - rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { - ccprintf("Loading serial number\n"); - rv = usb_load_serial(); - } else - return EC_ERROR_INVAL; - } - - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) - buf[i] = sd->_data[i]; - ccprintf("Serial number: %s\n", buf); - return rv; -} - -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c deleted file mode 100644 index 587609ba5d..0000000000 --- a/chip/stm32/usb_console.c +++ /dev/null @@ -1,273 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "config.h" -#include "console.h" -#include "link_defs.h" -#include "printf.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define USB_CONSOLE_TIMEOUT_US (30 * MSEC) - -static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, - uint8_t); -static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - -static int last_tx_ok = 1; - -static int is_reset; -static int is_enabled = 1; -static int is_readonly; - -/* USB-Serial descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10 -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 -}; - -static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -static usb_uint ep_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; - -/* Forward declaration */ -static void handle_output(void); - -static void con_ep_tx(void) -{ - /* clear IT */ - STM32_TOGGLE_EP(USB_EP_CONSOLE, 0, 0, 0); - - /* Check bytes in the FIFO needed to transmitted */ - handle_output(); -} - -static void con_ep_rx(void) -{ - int i; - - for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & 0x3ff); i++) { - int val = ((i & 1) ? - (ep_buf_rx[i >> 1] >> 8) : - (ep_buf_rx[i >> 1] & 0xff)); - - QUEUE_ADD_UNITS(&rx_q, &val, 1); - } - - /* clear IT */ - STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_RX_MASK, EP_RX_VALID, 0); - - /* wake-up the console task */ - console_has_input(); -} - -static void ep_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); - btable_ep[USB_EP_CONSOLE].tx_count = 0; - - btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); - btable_ep[USB_EP_CONSOLE].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - - STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (is_readonly ? EP_RX_NAK - : EP_RX_VALID)); - - is_reset = 1; -} - -USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); - -static int __tx_char(void *context, int c) -{ - /* Do newline to CRLF translation */ - if (c == '\n' && __tx_char(context, '\r')) - return 1; - - /* Return 0 on success */ - return !QUEUE_ADD_UNITS(&tx_q, &c, 1); -} - -static void usb_enable_tx(int len) -{ - if (!is_enabled) - return; - - btable_ep[USB_EP_CONSOLE].tx_count = len; - STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_TX_MASK, EP_TX_VALID, 0); -} - -static inline int usb_console_tx_valid(void) -{ - return (STM32_USB_EP(USB_EP_CONSOLE) & EP_TX_MASK) == EP_TX_VALID; -} - -static int usb_wait_console(void) -{ - timestamp_t deadline = get_time(); - int wait_time_us = 1; - - if (!is_enabled || !usb_is_enabled()) - return EC_SUCCESS; - - deadline.val += USB_CONSOLE_TIMEOUT_US; - - /* - * If the USB console is not used, Tx buffer would never free up. - * In this case, let's drop characters immediately instead of sitting - * for some time just to time out. On the other hand, if the last - * Tx is good, it's likely the host is there to receive data, and - * we should wait so that we don't clobber the buffer. - */ - if (last_tx_ok) { - while (usb_console_tx_valid() || !is_reset) { - if (timestamp_expired(deadline, NULL)) { - last_tx_ok = 0; - return EC_ERROR_TIMEOUT; - } - if (wait_time_us < MSEC) - udelay(wait_time_us); - else - usleep(wait_time_us); - wait_time_us *= 2; - } - - return EC_SUCCESS; - } else { - last_tx_ok = !usb_console_tx_valid(); - return EC_SUCCESS; - } -} - -/* Try to send some bytes from the Tx FIFO to the host */ -static void tx_fifo_handler(void) -{ - int ret; - size_t count; - usb_uint *buf = (usb_uint *)ep_buf_tx; - - if (!is_reset) - return; - - ret = usb_wait_console(); - if (ret) - return; - - count = 0; - while (count < USB_MAX_PACKET_SIZE) { - int val = 0; - - if (!QUEUE_REMOVE_UNITS(&tx_q, &val, 1)) - break; - - if (!(count & 1)) - buf[count/2] = val; - else - buf[count/2] |= val << 8; - count++; - } - - if (count) - usb_enable_tx(count); -} -DECLARE_DEFERRED(tx_fifo_handler); - -static void handle_output(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); -} - -/* - * Public USB console implementation below. - */ -int usb_getc(void) -{ - int c = 0; - - if (!is_enabled) - return -1; - - if (!QUEUE_REMOVE_UNITS(&rx_q, &c, 1)) - return -1; - - return c; -} - -int usb_putc(int c) -{ - int ret; - - ret = __tx_char(NULL, c); - handle_output(); - - return ret; -} - -int usb_puts(const char *outstr) -{ - /* Put all characters in the output buffer */ - while (*outstr) { - if (__tx_char(NULL, *outstr++) != 0) - break; - } - handle_output(); - - /* Successful if we consumed all output */ - return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS; -} - -int usb_vprintf(const char *format, va_list args) -{ - int ret; - - ret = vfnprintf(__tx_char, NULL, format, args); - handle_output(); - - return ret; -} - -void usb_console_enable(int enabled, int readonly) -{ - is_enabled = enabled; - is_readonly = readonly; -} diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c deleted file mode 100644 index f4ee89f1f0..0000000000 --- a/chip/stm32/usb_dwc.c +++ /dev/null @@ -1,1423 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "flash.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "usb_hw.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "watchdog.h" - - -/****************************************************************************/ -/* Debug output */ - -/* Console output macro */ -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -/* TODO: Something unexpected happened. Figure out how to report & fix it. */ -#define report_error(val) \ - CPRINTS("Unhandled USB event at %s line %d: 0x%x", \ - __FILE__, __LINE__, val) - - -/****************************************************************************/ -/* Standard USB stuff */ - -#ifdef CONFIG_USB_BOS -/* v2.10 (vs 2.00) BOS Descriptor provided */ -#define USB_DEV_BCDUSB 0x0210 -#else -#define USB_DEV_BCDUSB 0x0200 -#endif - -#ifndef USB_DEV_CLASS -#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE -#endif - -#ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ -#endif - -#ifndef CONFIG_USB_SERIALNO -#define USB_STR_SERIALNO 0 -#else -static int usb_load_serial(void); -#endif - - -/* USB Standard Device Descriptor */ -static const struct usb_device_descriptor dev_desc = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = USB_DEV_BCDUSB, - .bDeviceClass = USB_DEV_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = USB_MAX_PACKET_SIZE, - .idVendor = USB_VID_GOOGLE, - .idProduct = CONFIG_USB_PID, - .bcdDevice = CONFIG_USB_BCD_DEV, - .iManufacturer = USB_STR_VENDOR, - .iProduct = USB_STR_PRODUCT, - .iSerialNumber = USB_STR_SERIALNO, - .bNumConfigurations = 1 -}; - -/* USB Configuration Descriptor */ -const struct usb_config_descriptor USB_CONF_DESC(conf) = { - .bLength = USB_DT_CONFIG_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ - .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, /* Caution: hard-coded value */ - .iConfiguration = USB_STR_VERSION, - .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 -#endif - , - .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), -}; - -const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ -}; - -/****************************************************************************/ -/* Packet-handling stuff, specific to this SoC */ - -/* Some internal state to keep track of what's going on */ -static enum { - WAITING_FOR_SETUP_PACKET, - DATA_STAGE_IN, - NO_DATA_STAGE, -} what_am_i_doing; - -#ifdef DEBUG_ME -static const char * const wat[3] = { - [WAITING_FOR_SETUP_PACKET] = "wait_for_setup", - [DATA_STAGE_IN] = "data_in", - [NO_DATA_STAGE] = "no_data", -}; -#endif - -/* Programmer's Guide, Table 10-7 */ -enum table_case { - BAD_0, - TABLE_CASE_COMPLETE, - TABLE_CASE_SETUP, - TABLE_CASE_WTF, - TABLE_CASE_D, - TABLE_CASE_E, - BAD_6, - BAD_7, -}; - -static enum table_case decode_table_10_7(uint32_t doepint) -{ - enum table_case val = BAD_0; - - /* Bits: SI, SPD, IOC */ - if (doepint & DOEPINT_XFERCOMPL) - val += 1; - if (doepint & DOEPINT_SETUP) - val += 2; - return val; -} - -/* For STATUS/OUT: Use two DMA descriptors, each with one-packet buffers */ -#define NUM_OUT_BUFFERS 2 -static uint8_t __aligned(4) ep0_setup_buf[USB_MAX_PACKET_SIZE]; - -/* For IN: Several DMA descriptors, all pointing into one large buffer, so that - * we can return the configuration descriptor as one big blob. - */ -#define NUM_IN_PACKETS_AT_ONCE 4 -#define IN_BUF_SIZE (NUM_IN_PACKETS_AT_ONCE * USB_MAX_PACKET_SIZE) -static uint8_t __aligned(4) ep0_in_buf[IN_BUF_SIZE]; - -struct dwc_usb_ep ep0_ctl = { - .max_packet = USB_MAX_PACKET_SIZE, - .tx_fifo = 0, - .out_pending = 0, - .out_expected = 0, - .out_data = 0, - .out_databuffer = ep0_setup_buf, - .out_databuffer_max = sizeof(ep0_setup_buf), - .rx_deferred = 0, - .in_packets = 0, - .in_pending = 0, - .in_data = 0, - .in_databuffer = ep0_in_buf, - .in_databuffer_max = sizeof(ep0_in_buf), - .tx_deferred = 0, -}; - -/* Overall device state (USB 2.0 spec, section 9.1.1). - * We only need a few, though. - */ -static enum { - DS_DEFAULT, - DS_ADDRESS, - DS_CONFIGURED, -} device_state; -static uint8_t configuration_value; - - -/* True if the HW Rx/OUT FIFO is currently listening. */ -int rx_ep_is_active(uint32_t ep_num) -{ - return (GR_USB_DOEPCTL(ep_num) & DXEPCTL_EPENA) ? 1 : 0; -} - -/* Number of bytes the HW Rx/OUT FIFO has for us. - * - * @param ep_num USB endpoint - * - * @returns number of bytes ready, zero if none. - */ -int rx_ep_pending(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - return ep->out_pending; -} - -/* True if the Tx/IN FIFO can take some bytes from us. */ -int tx_ep_is_ready(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - int ready; - - /* Is the tx hw idle? */ - ready = !(GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA); - - /* Is there no pending data? */ - ready &= (ep->in_pending == 0); - return ready; -} - -/* Write packets of data IN to the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the write completion event. - * - * @param ep_num USB endpoint to write - * @param len number of bytes to write - * @param data pointer of data to write - * - * @return bytes written - */ -int usb_write_ep(uint32_t ep_num, int len, void *data) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) { - CPRINTS("usb_write_ep ep%d: FAIL: tx already in progress!", - ep_num); - return 0; - } - - /* We will send as many packets as necessary, including a final - * packet of < USB_MAX_PACKET_SIZE (maybe zero length) - */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE; - ep->in_pending = len; - ep->in_data = data; - - GR_USB_DIEPTSIZ(ep_num) = 0; - - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(ep->in_packets); - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(ep_num) = (uint32_t)(ep->in_data); - - /* We could support longer multi-dma transfers here. */ - ep->in_pending -= len; - ep->in_packets -= ep->in_packets; - ep->in_data += len; - - /* We are ready to enable this endpoint to start transferring data. */ - GR_USB_DIEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - return len; -} - -/* Tx/IN interrupt handler */ -void usb_epN_tx(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - uint32_t dieptsiz = GR_USB_DIEPTSIZ(ep_num); - - if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) { - CPRINTS("usb_epN_tx ep%d: tx still active.", ep_num); - return; - } - - /* clear the Tx/IN interrupts */ - GR_USB_DIEPINT(ep_num) = 0xffffffff; - - /* - * Let's assume this is actually true. - * We could support multi-dma transfers here. - */ - ep->in_packets = 0; - ep->in_pending = dieptsiz & GC_USB_DIEPTSIZ1_XFERSIZE_MASK; - - if (ep->tx_deferred) - hook_call_deferred(ep->tx_deferred, 0); -} - -/* Read a packet of data OUT from the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the read completion event. - * - * @param ep_num USB endpoint to read - * @param len number of bytes to read - * @param data pointer of data to read - * - * @return EC_SUCCESS on success - */ -int usb_read_ep(uint32_t ep_num, int len, void *data) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - int packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE; - - ep->out_data = data; - ep->out_pending = 0; - ep->out_expected = len; - - GR_USB_DOEPTSIZ(ep_num) = 0; - GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(packets); - GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DOEPDMA(ep_num) = (uint32_t)ep->out_data; - - GR_USB_DOEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - return EC_SUCCESS; -} - -/* Rx/OUT endpoint interrupt handler */ -void usb_epN_rx(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - /* Still receiving data. Let's wait. */ - if (rx_ep_is_active(ep_num)) - return; - - /* Bytes received decrement DOEPTSIZ XFERSIZE */ - if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) { - if (ep->out_expected > 0) { - ep->out_pending = - ep->out_expected - - (GR_USB_DOEPTSIZ(ep_num) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); - } else { - CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n", - ep_num, GR_USB_DOEPTSIZ(ep_num)); - ep->out_pending = 0; - } - ep->out_expected = 0; - GR_USB_DOEPTSIZ(ep_num) = 0; - } - - /* clear the RX/OUT interrupts */ - GR_USB_DOEPINT(ep_num) = 0xffffffff; - - if (ep->rx_deferred) - hook_call_deferred(ep->rx_deferred, 0); -} - -/* Reset endpoint HW block. */ -void epN_reset(uint32_t ep_num) -{ - GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; - GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | - DXEPCTL_TXFNUM(ep_num); - GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | - DAINT_OUTEP(ep_num); -} - - -/****************************************************************************** - * Internal and EP0 functions. - */ - - -static void flush_all_fifos(void) -{ - /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; - while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; -} - -int send_in_packet(uint32_t ep_num) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[ep_num]; - int len = MIN(USB_MAX_PACKET_SIZE, ep->in_pending); - - if (ep->in_packets == 0) { - report_error(ep_num); - return -1; - } - - GR_USB_DIEPTSIZ(ep_num) = 0; - - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data; - - - /* We're sending this much. */ - ep->in_pending -= len; - ep->in_packets -= 1; - ep->in_data += len; - - /* We are ready to enable this endpoint to start transferring data. */ - return len; -} - - -/* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns - * len, or negative on error. - */ -int initialize_in_transfer(const void *source, uint32_t len) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - -#ifdef CONFIG_USB_DWC_FS - /* FS OTG port does not support DMA or external phy */ - ASSERT(!(usb->dma_en)); - ASSERT(usb->phy_type == USB_PHY_INTERNAL); - ASSERT(usb->speed == USB_SPEED_FS); - ASSERT(usb->irq == STM32_IRQ_OTG_FS); -#else - /* HS OTG port requires an external phy to support HS */ - ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) && - (usb->speed == USB_SPEED_HS))); - ASSERT(usb->irq == STM32_IRQ_OTG_HS); -#endif - - /* Copy the data into our FIFO buffer */ - if (len >= IN_BUF_SIZE) { - report_error(len); - return -1; - } - - /* Stage data in DMA buffer. */ - memcpy(ep->in_databuffer, source, len); - ep->in_data = ep->in_databuffer; - - /* We will send as many packets as necessary, including a final - * packet of < USB_MAX_PACKET_SIZE (maybe zero length) - */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE; - ep->in_pending = len; - - send_in_packet(0); - return len; -} - -/* Prepare the EP0 OUT FIFO buffer to accept some data. Returns len, or - * negative on error. - */ -int accept_out_fifo(uint32_t len) -{ - /* TODO: This is not yet implemented */ - report_error(len); - return -1; -} - -/* The next packet from the host should be a Setup packet. Get ready for it. */ -static void expect_setup_packet(void) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - - what_am_i_doing = WAITING_FOR_SETUP_PACKET; - ep->out_data = ep->out_databuffer; - - /* We don't care about IN packets right now, only OUT. */ - GR_USB_DAINTMSK |= DAINT_OUTEP(0); - GR_USB_DAINTMSK &= ~DAINT_INEP(0); - - GR_USB_DOEPTSIZ(0) = 0; - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(0x18); - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_SUPCNT(1); - GR_USB_DOEPCTL(0) = DXEPCTL_USBACTEP | DXEPCTL_EPENA; - GR_USB_DOEPDMA(0) = (uint32_t)ep->out_data; -} - -/* We're complaining about something by stalling both IN and OUT packets, - * but a SETUP packet will get through anyway, so prepare for it. - */ -static void stall_both_fifos(void) -{ - what_am_i_doing = WAITING_FOR_SETUP_PACKET; - /* We don't care about IN packets right now, only OUT. */ - GR_USB_DAINTMSK |= DAINT_OUTEP(0); - GR_USB_DAINTMSK &= ~DAINT_INEP(0); - - GR_USB_DOEPCTL(0) |= DXEPCTL_STALL; - GR_USB_DIEPCTL(0) |= DXEPCTL_STALL; - expect_setup_packet(); -} - -/* The TX FIFO buffer is loaded. Start the Data phase. */ -static void expect_data_phase_in(enum table_case tc) -{ - what_am_i_doing = DATA_STAGE_IN; - - /* Send the reply (data phase in) */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | - DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; - - /* We'll receive an empty packet back as a ack, I guess. */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DOEPCTL(0) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DOEPCTL(0) |= DXEPCTL_EPENA; - - /* Get an interrupt when either IN or OUT arrives */ - GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); - -} - -static void expect_data_phase_out(enum table_case tc) -{ - /* TODO: This is not yet supported */ - report_error(tc); - expect_setup_packet(); -} - -/* No Data phase, just Status phase (which is IN, since Setup is OUT) */ -static void expect_status_phase_in(enum table_case tc) -{ - what_am_i_doing = NO_DATA_STAGE; - - /* Expect a zero-length IN for the Status phase */ - (void) initialize_in_transfer(0, 0); - - /* Blindly following instructions here, too. */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP - | DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; - - /* Get an interrupt when either IN or OUT arrives */ - GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); -} - -/* Handle a Setup packet that expects us to send back data in reply. Return the - * length of the data we're returning, or negative to indicate an error. - */ -static int handle_setup_with_in_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - - const void *data = 0; - uint32_t len = 0; - int ugly_hack = 0; - static const uint16_t zero; /* == 0 */ - - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: { - uint8_t type = req->wValue >> 8; - uint8_t idx = req->wValue & 0xff; - - switch (type) { - case USB_DT_DEVICE: - data = &dev_desc; - len = sizeof(dev_desc); - break; - case USB_DT_CONFIGURATION: - data = __usb_desc; - len = USB_DESC_SIZE; - ugly_hack = 1; /* see below */ - break; -#ifdef CONFIG_USB_BOS - case USB_DT_BOS: - data = bos_ctx.descp; - len = bos_ctx.size; - break; -#endif - case USB_DT_STRING: - if (idx >= USB_STR_COUNT) - return -1; -#ifdef CONFIG_USB_SERIALNO - if (idx == USB_STR_SERIALNO) - data = (uint8_t *)usb_serialno_desc; - else -#endif - data = usb_strings[idx]; - len = *(uint8_t *)data; - break; - case USB_DT_DEVICE_QUALIFIER: - /* We're not high speed */ - return -1; - case USB_DT_DEBUG: - /* Not supported */ - return -1; - default: - report_error(type); - return -1; - } - break; - } - case USB_REQ_GET_STATUS: { - /* TODO: Device Status: Remote Wakeup? Self Powered? */ - data = &zero; - len = sizeof(zero); - break; - } - case USB_REQ_GET_CONFIGURATION: - data = &configuration_value; - len = sizeof(configuration_value); - break; - - case USB_REQ_SYNCH_FRAME: - /* Unimplemented */ - return -1; - - default: - report_error(req->bRequest); - return -1; - } - - /* Don't send back more than we were asked for. */ - len = MIN(req->wLength, len); - - /* Prepare the TX FIFO. If we haven't preallocated enough room in the - * TX FIFO for the largest reply, we'll have to stall. This is a bug in - * our code, but detecting it easily at compile time is related to the - * ugly_hack directly below. - */ - if (initialize_in_transfer(data, len) < 0) - return -1; - - if (ugly_hack) { - /* - * TODO: Somebody figure out how to fix this, please. - * - * The USB configuration descriptor request is unique in that - * it not only returns the configuration descriptor, but also - * all the interface descriptors and all their endpoint - * descriptors as one enormous blob. We've set up some macros - * so we can declare and implement separate interfaces in - * separate files just by compiling them, and all the relevant - * descriptors are sorted and bundled up by the linker. But the - * total length of the entire blob needs to appear in the first - * configuration descriptor struct and because we don't know - * that value until after linking, it can't be initialized as a - * constant. So we have to compute it at run-time and shove it - * in here, which also means that we have to copy the whole - * blob into our TX FIFO buffer so that it's mutable. Otherwise - * we could just point at it (or pretty much any other constant - * struct that we wanted to send to the host). Bah. - */ - struct usb_config_descriptor *cfg = - (struct usb_config_descriptor *)ep->in_databuffer; - /* set the real descriptor size */ - cfg->wTotalLength = USB_DESC_SIZE; - } - - return len; -} - -/* Handle a Setup that comes with additional data for us. */ -static int handle_setup_with_out_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - /* TODO: We don't support any of these. We should. */ - report_error(-1); - return -1; -} - -/* Some Setup packets don't have a data stage at all. */ -static int handle_setup_with_no_data_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - uint8_t set_addr; - - switch (req->bRequest) { - case USB_REQ_SET_ADDRESS: - /* - * Set the address after the IN packet handshake. - * - * From the USB 2.0 spec, section 9.4.6: - * - * As noted elsewhere, requests actually may result in - * up to three stages. In the first stage, the Setup - * packet is sent to the device. In the optional second - * stage, data is transferred between the host and the - * device. In the final stage, status is transferred - * between the host and the device. The direction of - * data and status transfer depends on whether the host - * is sending data to the device or the device is - * sending data to the host. The Status stage transfer - * is always in the opposite direction of the Data - * stage. If there is no Data stage, the Status stage - * is from the device to the host. - * - * Stages after the initial Setup packet assume the - * same device address as the Setup packet. The USB - * device does not change its device address until - * after the Status stage of this request is completed - * successfully. Note that this is a difference between - * this request and all other requests. For all other - * requests, the operation indicated must be completed - * before the Status stage - */ - set_addr = req->wValue & 0xff; - /* - * NOTE: Now that we've said that, we don't do it. The - * hardware for this SoC knows that an IN packet will - * be following the SET ADDRESS, so it waits until it - * sees that happen before the address change takes - * effect. If we wait until after the IN packet to - * change the register, the hardware gets confused and - * doesn't respond to anything. - */ - GWRITE_FIELD(USB, DCFG, DEVADDR, set_addr); - CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr); - device_state = DS_ADDRESS; - break; - - case USB_REQ_SET_CONFIGURATION: - switch (req->wValue) { - case 0: - configuration_value = req->wValue; - device_state = DS_ADDRESS; - break; - case 1: /* Caution: Only one config descriptor TODAY */ - /* TODO: All endpoints set to DATA0 toggle state */ - configuration_value = req->wValue; - device_state = DS_CONFIGURED; - break; - default: - /* Nope. That's a paddlin. */ - report_error(-1); - return -1; - } - break; - - case USB_REQ_CLEAR_FEATURE: - case USB_REQ_SET_FEATURE: - /* TODO: Handle DEVICE_REMOTE_WAKEUP, ENDPOINT_HALT? */ - break; - - default: - /* Anything else is unsupported */ - report_error(-1); - return -1; - } - - /* No data to transfer, go straight to the Status phase. */ - return 0; -} - -/* Dispatch an incoming Setup packet according to its type */ -static void handle_setup(enum table_case tc) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - struct usb_setup_packet *req = - (struct usb_setup_packet *)ep->out_databuffer; - int data_phase_in = req->bmRequestType & USB_DIR_IN; - int data_phase_out = !data_phase_in && req->wLength; - int bytes = -1; /* default is to stall */ - - if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) { - /* Standard Device requests */ - if (data_phase_in) - bytes = handle_setup_with_in_stage(tc, req); - else if (data_phase_out) - bytes = handle_setup_with_out_stage(tc, req); - else - bytes = handle_setup_with_no_data_stage(tc, req); - } else if (USB_RECIP_INTERFACE == - (req->bmRequestType & USB_RECIP_MASK)) { - /* Interface-specific requests */ - uint8_t iface = req->wIndex & 0xff; - - if (iface < USB_IFACE_COUNT) - bytes = usb_iface_request[iface](req); - } else { - /* Something we need to add support for? */ - report_error(-1); - } - - /* We say "no" to unsupported and intentionally unhandled requests by - * stalling the Data and/or Status stage. - */ - if (bytes < 0) { - /* Stall both IN and OUT. SETUP will come through anyway. */ - stall_both_fifos(); - } else { - if (data_phase_in) - expect_data_phase_in(tc); - else if (data_phase_out) - expect_data_phase_out(tc); - else - expect_status_phase_in(tc); - } -} - -/* This handles both IN and OUT interrupts for EP0 */ -static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - uint32_t doepint, diepint; - enum table_case tc; - int out_complete, out_setup, in_complete; - - /* Determine the interrupt cause and clear the bits quickly, but only - * if they really apply. I don't think they're trustworthy if we didn't - * actually get an interrupt. - */ - doepint = GR_USB_DOEPINT(0) & GR_USB_DOEPMSK; - if (intr_on_out) - GR_USB_DOEPINT(0) = doepint; - diepint = GR_USB_DIEPINT(0) & GR_USB_DIEPMSK; - if (intr_on_in) - GR_USB_DIEPINT(0) = diepint; - - out_complete = doepint & DOEPINT_XFERCOMPL; - out_setup = doepint & DOEPINT_SETUP; - in_complete = diepint & DIEPINT_XFERCOMPL; - - /* Decode the situation according to Table 10-7 */ - tc = decode_table_10_7(doepint); - - switch (what_am_i_doing) { - case WAITING_FOR_SETUP_PACKET: - if (out_setup) - handle_setup(tc); - else - report_error(-1); - break; - - case DATA_STAGE_IN: - if (intr_on_in && in_complete) { - /* A packet is sent. Should we send another? */ - if (ep->in_packets > 0) { - /* Send another packet. */ - send_in_packet(0); - expect_data_phase_in(tc); - } - } - - /* But we should ignore the OUT endpoint if we didn't actually - * get an OUT interrupt. - */ - if (!intr_on_out) - break; - - if (out_setup) { - /* The first IN packet has been seen. Keep going. */ - break; - } - if (out_complete) { - /* We've handled the Status phase. All done. */ - expect_setup_packet(); - break; - } - - /* Anything else should be ignorable. Right? */ - break; - - case NO_DATA_STAGE: - if (intr_on_in && in_complete) { - /* We are not expecting an empty packet in - * return for our empty packet. - */ - expect_setup_packet(); - } - - /* Done unless we got an OUT interrupt */ - if (!intr_on_out) - break; - - if (out_setup) { - report_error(-1); - break; - } - - /* Anything else means get ready for a Setup packet */ - report_error(-1); - expect_setup_packet(); - break; - } -} - -/****************************************************************************/ -/* USB device initialization and shutdown routines */ - -/* - * DATA FIFO Setup. There is an internal SPRAM used to buffer the IN/OUT - * packets and track related state without hammering the AHB and system RAM - * during USB transactions. We have to specify where and how much of that SPRAM - * to use for what. - * - * See Programmer's Guide chapter 2, "Calculating FIFO Size". - * We're using Dedicated TxFIFO Operation, without enabling thresholding. - * - * Section 2.1.1.2, page 30: RXFIFO size is the same as for Shared FIFO, which - * is Section 2.1.1.1, page 28. This is also the same as Method 2 on page 45. - * - * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max - * data packet size is 64 bytes. Total SPRAM available is 1024 slots. - */ -#define MAX_CONTROL_EPS 3 -#define MAX_NORMAL_EPS 16 -#define FIFO_RAM_DEPTH 1024 -/* - * Device RX FIFO size is thus: - * (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85 - */ -#define RXFIFO_SIZE ((4 * MAX_CONTROL_EPS + 6) + \ - 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ - (2 * MAX_NORMAL_EPS) + 1) -/* - * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46). - */ -#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) -/* - * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1, - * unconfigurable). - */ -#define EP_STATUS_SIZE (4 * MAX_NORMAL_EPS * 2) -/* - * Make sure all that fits. - */ -BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE < - FIFO_RAM_DEPTH); - - -/* Now put those constants into the correct registers */ -static void setup_data_fifos(void) -{ - int i; - - /* Programmer's Guide, p31 */ - GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ - GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */ - - /* TXFIFO 1..15 */ - for (i = 1; i < MAX_NORMAL_EPS; i++) - GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) | - (RXFIFO_SIZE + i * TXFIFO_SIZE)); - - /* - * TODO: The Programmer's Guide is confusing about when or whether to - * flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section - * 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section - * 7.5.4 (p162) says that flushing the RXFIFO at reset is not - * recommended at all. - * - * I'm also unclear on whether or not the individual EPs are expected - * to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so, - * whether by firmware or hardware. - */ - - /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; - while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; /* TODO: timeout 100ms */ -} - -static void usb_init_endpoints(void) -{ - int ep; - - /* Prepare to receive packets on EP0 */ - expect_setup_packet(); - - /* Reset the other endpoints */ - for (ep = 1; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_RESET); -} - -static void usb_reset(void) -{ - /* Clear our internal state */ - device_state = DS_DEFAULT; - configuration_value = 0; - - /* Clear the device address */ - GWRITE_FIELD(USB, DCFG, DEVADDR, 0); - - /* Reinitialize all the endpoints */ - usb_init_endpoints(); -} - -static void usb_resetdet(void) -{ - /* TODO: Same as normal reset, right? I think we only get this if we're - * suspended (sleeping) and the host resets us. Try it and see. - */ - usb_reset(); -} - -static void usb_enumdone(void) -{ - /* We can change to HS here. We will not go to HS today */ - GR_USB_DCTL |= DCTL_CGOUTNAK; -} - - -void usb_interrupt(void) -{ - uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK; - uint32_t oepint = status & GINTSTS(OEPINT); - uint32_t iepint = status & GINTSTS(IEPINT); - int ep; - - if (status & GINTSTS(ENUMDONE)) - usb_enumdone(); - - if (status & GINTSTS(RESETDET)) - usb_resetdet(); - - if (status & GINTSTS(USBRST)) - usb_reset(); - - /* Endpoint interrupts */ - if (oepint || iepint) { - /* Note: It seems that the DAINT bits are only trustworthy for - * identifying interrupts when selected by the corresponding - * OEPINT and IEPINT bits from GINTSTS. - */ - uint32_t daint = GR_USB_DAINT; - - /* EP0 has a combined IN/OUT handler. Only call it once, but - * let it know which direction(s) had an interrupt. - */ - if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) { - uint32_t intr_on_out = (oepint && - (daint & DAINT_OUTEP(0))); - uint32_t intr_on_in = (iepint && - (daint & DAINT_INEP(0))); - ep0_interrupt(intr_on_out, intr_on_in); - } - - /* Invoke the unidirectional IN and OUT functions for the other - * endpoints. Each handler must clear their own bits in - * DIEPINTn/DOEPINTn. - */ - for (ep = 1; ep < USB_EP_COUNT; ep++) { - if (oepint && (daint & DAINT_OUTEP(ep))) - usb_ep_rx[ep](); - if (iepint && (daint & DAINT_INEP(ep))) - usb_ep_tx[ep](); - } - } - - GR_USB_GINTSTS = status; -} -DECLARE_IRQ(STM32_IRQ_OTG_FS, usb_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_OTG_HS, usb_interrupt, 1); - -static void usb_softreset(void) -{ - int timeout; - - CPRINTS("%s", __func__); - - /* Wait for bus idle */ - timeout = 10000; - while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0) - ; - - /* Reset and wait for clear */ - GR_USB_GRSTCTL = GRSTCTL_CSFTRST; - timeout = 10000; - while ((GR_USB_GRSTCTL & GRSTCTL_CSFTRST) && timeout-- > 0) - ; - if (GR_USB_GRSTCTL & GRSTCTL_CSFTRST) { - CPRINTF("USB: reset failed\n"); - return; - } - - /* Some more idle? */ - timeout = 10000; - while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0) - ; - - if (!timeout) { - CPRINTF("USB: reset timeout\n"); - return; - } - /* TODO: Wait 3 PHY clocks before returning */ -} - -void usb_connect(void) -{ - GR_USB_DCTL &= ~DCTL_SFTDISCON; -} - -void usb_disconnect(void) -{ - GR_USB_DCTL |= DCTL_SFTDISCON; - - device_state = DS_DEFAULT; - configuration_value = 0; -} - -void usb_reset_init_phy(void) -{ - struct dwc_usb *usb = &usb_ctl; - - if (usb->phy_type == USB_PHY_ULPI) { - GR_USB_GCCFG &= ~GCCFG_PWRDWN; - GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS | - GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); - GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); - /* No suspend */ - GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR; - - usb_softreset(); - } else { - GR_USB_GUSBCFG |= GUSBCFG_PHYSEL; - usb_softreset(); - GR_USB_GCCFG |= GCCFG_PWRDWN; - } -} - -void usb_init(void) -{ - int i; - struct dwc_usb *usb = &usb_ctl; - - CPRINTS("%s", __func__); - -#ifdef CONFIG_USB_SERIALNO - usb_load_serial(); -#endif - - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - /* Enable clocks */ - clock_enable_module(MODULE_USB, 0); - clock_enable_module(MODULE_USB, 1); - - /* TODO(crbug.com/496888): set up pinmux */ - gpio_config_module(MODULE_USB, 1); - - /* Make sure interrupts are disabled */ - GR_USB_GINTMSK = 0; - GR_USB_DAINTMSK = 0; - GR_USB_DIEPMSK = 0; - GR_USB_DOEPMSK = 0; - - /* Full-Speed Serial PHY */ - usb_reset_init_phy(); - - /* Global + DMA configuration */ - GR_USB_GAHBCFG = GAHBCFG_GLB_INTR_EN; - GR_USB_GAHBCFG |= GAHBCFG_HBSTLEN_INCR4; - if (usb->dma_en) - GR_USB_GAHBCFG |= GAHBCFG_DMA_EN; - - /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD; - GR_USB_GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; - - GR_USB_GCCFG &= ~GCCFG_VBDEN; - GR_USB_GOTGCTL |= GOTGCTL_BVALOEN; - GR_USB_GOTGCTL |= GOTGCTL_BVALOVAL; - - GR_USB_PCGCCTL = 0; - - if (usb->phy_type == USB_PHY_ULPI) { - /* TODO(nsanders): add HS support like so. - * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - * | DCFG_DEVSPD_HSULPI; - */ - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FSULPI; - } else { - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FS48; - } - - GR_USB_DCFG |= DCFG_NZLSOHSK; - - flush_all_fifos(); - - /* Clear pending interrupts again */ - GR_USB_GINTMSK = 0; - GR_USB_DIEPMSK = 0; - GR_USB_DOEPMSK = 0; - GR_USB_DAINT = 0xffffffff; - GR_USB_DAINTMSK = 0; - - /* TODO: What about the AHB Burst Length Field? It's 0 now. */ - GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL; - - /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD - | GUSBCFG_TOUTCAL(7) - /* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */ - | GUSBCFG_USBTRDTIM(14); - - /* Be in disconnected state until we are ready */ - usb_disconnect(); - - /* If we've restored a nonzero device address, update our state. */ - if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) { - /* Caution: We only have one config TODAY, so there's no real - * difference between DS_CONFIGURED and DS_ADDRESS. - */ - device_state = DS_CONFIGURED; - configuration_value = 1; - } else { - device_state = DS_DEFAULT; - configuration_value = 0; - } - - /* Now that DCFG.DesDMA is accurate, prepare the FIFOs */ - setup_data_fifos(); - - usb_init_endpoints(); - - /* Clear any pending interrupts */ - for (i = 0; i < 16; i++) { - GR_USB_DIEPINT(i) = 0xffffffff; - GR_USB_DIEPTSIZ(i) = 0; - GR_USB_DOEPINT(i) = 0xffffffff; - GR_USB_DOEPTSIZ(i) = 0; - } - - if (usb->dma_en) { - GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6; - GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN - | DTHRCTL_NONISOTHREN; - i = GR_USB_DTHRCTL; - } - - GR_USB_GINTSTS = 0xFFFFFFFF; - - GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL - | GAHBCFG_PTXFELVL; - - if (!(usb->dma_en)) - GR_USB_GINTMSK |= GINTMSK(RXFLVL); - - /* Unmask some endpoint interrupt causes */ - GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK; - GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK | - DOEPMSK_SETUPMSK; - - /* Enable interrupt handlers */ - task_enable_irq(usb->irq); - - /* Allow USB interrupts to come in */ - GR_USB_GINTMSK |= - /* NAK bits that must be cleared by the DCTL register */ - GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) | - /* Initialization events */ - GINTMSK(USBRST) | GINTMSK(ENUMDONE) | - /* Reset detected while suspended. Need to wake up. */ - GINTMSK(RESETDET) | /* TODO: Do we need this? */ - /* Idle, Suspend detected. Should go to sleep. */ - GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP); - - GR_USB_GINTMSK |= - /* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */ - GINTMSK(OEPINT) | GINTMSK(IEPINT); - - /* Device registers have been setup */ - GR_USB_DCTL |= DCTL_PWRONPRGDONE; - udelay(10); - GR_USB_DCTL &= ~DCTL_PWRONPRGDONE; - - /* Clear global NAKs */ - GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK; - -#ifndef CONFIG_USB_INHIBIT_CONNECT - /* Indicate our presence to the USB host */ - usb_connect(); -#endif -} -#ifndef CONFIG_USB_INHIBIT_INIT -DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT); -#endif - -void usb_release(void) -{ - struct dwc_usb *usb = &usb_ctl; - - /* signal disconnect to host */ - usb_disconnect(); - - /* disable interrupt handlers */ - task_disable_irq(usb->irq); - - /* disable clocks */ - clock_enable_module(MODULE_USB, 0); - /* TODO: pin-mux */ - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} - -/* Print USB info and stats */ -static void usb_info(void) -{ - struct dwc_usb *usb = &usb_ctl; - int i; - - CPRINTF("USB settings: %s%s%s\n", - usb->speed == USB_SPEED_FS ? "FS " : "HS ", - usb->phy_type == USB_PHY_INTERNAL ? "Internal Phy " : "ULPI ", - usb->dma_en ? "DMA " : ""); - - for (i = 0; i < USB_EP_COUNT; i++) { - CPRINTF("Endpoint %d activity: %s%s\n", i, - rx_ep_is_active(i) ? "RX " : "", - tx_ep_is_ready(i) ? "" : "TX "); - } -} - -static int command_usb(int argc, char **argv) -{ - if (argc > 1) { - if (!strcasecmp("on", argv[1])) - usb_init(); - else if (!strcasecmp("off", argv[1])) - usb_release(); - else if (!strcasecmp("info", argv[1])) - usb_info(); - return EC_SUCCESS; - } - - return EC_ERROR_PARAM1; -} -DECLARE_CONSOLE_COMMAND(usb, command_usb, - "[on|off|info]", - "Get/set the USB connection state and PHY selection"); - -#ifdef CONFIG_USB_SERIALNO -/* This will be subbed into USB_STR_SERIALNO. */ -struct usb_string_desc *usb_serialno_desc = - USB_WR_STRING_DESC(DEFAULT_SERIALNO); - -/* Update serial number */ -static int usb_set_serial(const char *serialno) -{ - struct usb_string_desc *sd = usb_serialno_desc; - int i; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Convert into unicode usb string desc. */ - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) { - sd->_data[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - /* Count wchars (w/o null terminator) plus size & type bytes. */ - sd->_len = (i * 2) + 2; - sd->_type = USB_DT_STRING; - - return EC_SUCCESS; -} - -/* Retrieve serial number from pstate flash. */ -static int usb_load_serial(void) -{ - const char *serialno; - int rv; - - serialno = board_read_serial(); - if (!serialno) - return EC_ERROR_ACCESS_DENIED; - - rv = usb_set_serial(serialno); - return rv; -} - -/* Save serial number into pstate region. */ -static int usb_save_serial(const char *serialno) -{ - int rv; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Save this new serial number to flash. */ - rv = board_write_serial(serialno); - if (rv) - return rv; - - /* Load this new serial number to memory. */ - rv = usb_load_serial(); - return rv; -} - -static int command_serialno(int argc, char **argv) -{ - struct usb_string_desc *sd = usb_serialno_desc; - char buf[CONFIG_SERIALNO_LEN]; - int rv = EC_SUCCESS; - int i; - - if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { - ccprintf("Saving serial number\n"); - rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { - ccprintf("Loading serial number\n"); - rv = usb_load_serial(); - } else - return EC_ERROR_INVAL; - } - - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) - buf[i] = sd->_data[i]; - ccprintf("Serial number: %s\n", buf); - return rv; -} - -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c deleted file mode 100644 index 0d1340fb83..0000000000 --- a/chip/stm32/usb_dwc_console.c +++ /dev/null @@ -1,360 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "config.h" -#include "console.h" -#include "link_defs.h" -#include "printf.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define USB_CONSOLE_TIMEOUT_US (30 * MSEC) - -static int last_tx_ok = 1; - -static int is_reset; -static int is_enabled = 1; -static int is_readonly; - -/* USB-Serial descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 -}; - -static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE]; -static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE]; - -static struct queue const tx_q = QUEUE_NULL(256, uint8_t); -static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - - -struct dwc_usb_ep ep_console_ctl = { - .max_packet = USB_MAX_PACKET_SIZE, - .tx_fifo = USB_EP_CONSOLE, - .out_pending = 0, - .out_data = 0, - .out_databuffer = ep_buf_tx, - .out_databuffer_max = sizeof(ep_buf_tx), - .in_packets = 0, - .in_pending = 0, - .in_data = 0, - .in_databuffer = ep_buf_rx, - .in_databuffer_max = sizeof(ep_buf_rx), -}; - - - -/* Let the USB HW IN-to-host FIFO transmit some bytes */ -static void usb_enable_tx(int len) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - ep->in_data = ep->in_databuffer; - ep->in_packets = 1; - ep->in_pending = len; - - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) = 0; - - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->in_data; - - GR_USB_DIEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA; -} - -/* Let the USB HW OUT-from-host FIFO receive some bytes */ -static void usb_enable_rx(int len) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - ep->out_data = ep->out_databuffer; - ep->out_pending = 0; - - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) = 0; - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->out_data; - - GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA; -} - -/* True if the HW Rx/OUT FIFO has bytes for us. */ -static inline int rx_fifo_is_ready(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - return ep->out_pending; -} - -/* - * This function tries to shove new bytes from the USB host into the queue for - * consumption elsewhere. It is invoked either by a HW interrupt (telling us we - * have new bytes from the USB host), or by whoever is reading bytes out of the - * other end of the queue (telling us that there's now more room in the queue - * if we still have bytes to shove in there). - */ -char buffer[65]; -static void rx_fifo_handler(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - int rx_in_fifo; - size_t added; - - if (!rx_fifo_is_ready()) - return; - - rx_in_fifo = ep->out_pending; - added = QUEUE_ADD_UNITS(&rx_q, ep->out_databuffer, rx_in_fifo); - - if (added != rx_in_fifo) - CPRINTF("DROP CONSOLE: %d/%d process\n", added, rx_in_fifo); - - /* wake-up the console task */ - console_has_input(); - - usb_enable_rx(USB_MAX_PACKET_SIZE); -} -DECLARE_DEFERRED(rx_fifo_handler); - -/* Rx/OUT interrupt handler */ -static void con_ep_rx(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - if (GR_USB_DOEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA) - return; - - /* Bytes received decrement DOEPTSIZ XFERSIZE */ - if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) { - ep->out_pending = - ep->max_packet - - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); - } - - /* Wake up the Rx FIFO handler */ - hook_call_deferred(&rx_fifo_handler_data, 0); - - /* clear the RX/OUT interrupts */ - GR_USB_DOEPINT(USB_EP_CONSOLE) = 0xffffffff; -} - -/* True if the Tx/IN FIFO can take some bytes from us. */ -static inline int tx_fifo_is_ready(void) -{ - return !(GR_USB_DIEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA); -} - -/* Try to send some bytes to the host */ -static void tx_fifo_handler(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - size_t count; - - if (!is_reset) - return; - - /* If the HW FIFO isn't ready, then we can't do anything right now. */ - if (!tx_fifo_is_ready()) - return; - - count = QUEUE_REMOVE_UNITS(&tx_q, - ep->in_databuffer, USB_MAX_PACKET_SIZE); - if (count) - usb_enable_tx(count); -} -DECLARE_DEFERRED(tx_fifo_handler); - -static void handle_output(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); -} - -/* Tx/IN interrupt handler */ -static void con_ep_tx(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); - - /* clear the Tx/IN interrupts */ - GR_USB_DIEPINT(USB_EP_CONSOLE) = 0xffffffff; -} - -static void ep_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - epN_reset(USB_EP_CONSOLE); - - is_reset = 1; - - /* Flush any queued data */ - hook_call_deferred(&tx_fifo_handler_data, 0); - hook_call_deferred(&rx_fifo_handler_data, 0); - - usb_enable_rx(USB_MAX_PACKET_SIZE); -} - - -USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); - -static int usb_wait_console(void) -{ - timestamp_t deadline = get_time(); - int wait_time_us = 1; - - if (!is_enabled || !tx_fifo_is_ready()) - return EC_SUCCESS; - - deadline.val += USB_CONSOLE_TIMEOUT_US; - - /* - * If the USB console is not used, Tx buffer would never free up. - * In this case, let's drop characters immediately instead of sitting - * for some time just to time out. On the other hand, if the last - * Tx is good, it's likely the host is there to receive data, and - * we should wait so that we don't clobber the buffer. - */ - if (last_tx_ok) { - while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE || !is_reset) { - if (timestamp_expired(deadline, NULL) || - in_interrupt_context()) { - last_tx_ok = 0; - return EC_ERROR_TIMEOUT; - } - if (wait_time_us < MSEC) - udelay(wait_time_us); - else - usleep(wait_time_us); - wait_time_us *= 2; - } - - return EC_SUCCESS; - } - - last_tx_ok = queue_space(&tx_q); - return EC_SUCCESS; -} -static int __tx_char(void *context, int c) -{ - struct queue *state = - (struct queue *) context; - - if (c == '\n' && __tx_char(state, '\r')) - return 1; - - QUEUE_ADD_UNITS(state, &c, 1); - return 0; -} - -/* - * Public USB console implementation below. - */ -int usb_getc(void) -{ - int c; - - if (!is_enabled) - return -1; - - if (QUEUE_REMOVE_UNITS(&rx_q, &c, 1)) - return c; - - return -1; -} - -int usb_puts(const char *outstr) -{ - int ret; - struct queue state; - - if (is_readonly) - return EC_SUCCESS; - - ret = usb_wait_console(); - if (ret) - return ret; - - state = tx_q; - while (*outstr) - if (__tx_char(&state, *outstr++)) - break; - - if (queue_count(&state)) - handle_output(); - - return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS; -} - -int usb_putc(int c) -{ - char string[2]; - - string[0] = c; - string[1] = '\0'; - return usb_puts(string); -} - -int usb_vprintf(const char *format, va_list args) -{ - int ret; - struct queue state; - - if (is_readonly) - return EC_SUCCESS; - - ret = usb_wait_console(); - if (ret) - return ret; - - state = tx_q; - ret = vfnprintf(__tx_char, &state, format, args); - - if (queue_count(&state)) - handle_output(); - - return ret; -} - -void usb_console_enable(int enabled, int readonly) -{ - is_enabled = enabled; - is_readonly = readonly; -} diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h deleted file mode 100644 index ab2206d359..0000000000 --- a/chip/stm32/usb_dwc_console.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CHIP_STM32_USB_DWC_CONSOLE_H -#define __CHIP_STM32_USB_DWC_CONSOLE_H - -#include "usb_hw.h" - -extern struct dwc_usb_ep ep_console_ctl; - -#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h deleted file mode 100644 index d1fe07cb87..0000000000 --- a/chip/stm32/usb_dwc_hw.h +++ /dev/null @@ -1,106 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_DWC_HW_H -#define __CROS_EC_USB_DWC_HW_H - -#include "usb_dwc_registers.h" - -/* Helpers for endpoint declaration */ -#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix) -#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx) -#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx) -#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt) -/* Used to check function types are correct (attribute alias does not do it) */ -#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck) -#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) -#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) - -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler - -/* Endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); -struct usb_setup_packet; -/* EP0 Interface handler callbacks */ -extern int (*usb_iface_request[]) (struct usb_setup_packet *req); - - -/* True if the HW Rx/OUT FIFO is currently listening. */ -int rx_ep_is_active(uint32_t ep_num); - -/* Number of bytes the HW Rx/OUT FIFO has for us. - * - * @param ep_num USB endpoint - * - * @returns number of bytes ready, zero if none. - */ -int rx_ep_pending(uint32_t ep_num); - -/* True if the Tx/IN FIFO can take some bytes from us. */ -int tx_ep_is_ready(uint32_t ep_num); - -/* Write packets of data IN to the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the write completion event. - * - * @param ep_num USB endpoint to write - * @param len number of bytes to write - * @param data pointer of data to write - * - * @return bytes written - */ -int usb_write_ep(uint32_t ep_num, int len, void *data); - -/* Read a packet of data OUT from the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the read completion event. - * - * @param ep_num USB endpoint to read - * @param len number of bytes to read - * @param data pointer of data to read - * - * @return EC_SUCCESS on success - */ -int usb_read_ep(uint32_t ep_num, int len, void *data); - -/* Tx/IN interrupt handler */ -void usb_epN_tx(uint32_t ep_num); - -/* Rx/OUT endpoint interrupt handler */ -void usb_epN_rx(uint32_t ep_num); - -/* Reset endpoint HW block. */ -void epN_reset(uint32_t ep_num); - -/* - * Declare any interface-specific control request handlers. These Setup packets - * arrive on the control endpoint (EP0), but are handled by the interface code. - * The callback must prepare the EP0 IN or OUT FIFOs and return the number of - * bytes placed in the IN FIFO. A negative return value will STALL the response - * (and thus indicate error to the host). - */ -#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(struct usb_setup_packet *req) \ - __attribute__ ((alias(STRINGIFY(handler)))) - -#endif /* __CROS_EC_USB_DWC_HW_H */ diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h deleted file mode 100644 index e44002268a..0000000000 --- a/chip/stm32/usb_dwc_i2c.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_DWC_I2C_H -#define __CROS_EC_USB_DWC_I2C_H -#include "usb_i2c.h" - -/* I2C over USB interface. This gets declared in usb_i2c.c */ -extern struct dwc_usb_ep i2c_usb__ep_ctl; - -#endif /* __CROS_EC_USB_DWC_I2C_H */ diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h deleted file mode 100644 index faac9ca775..0000000000 --- a/chip/stm32/usb_dwc_registers.h +++ /dev/null @@ -1,7533 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for STM32F446 USB - */ - -#ifndef __CHIP_STM32_USB_DWC_REGISTERS_H -#define __CHIP_STM32_USB_DWC_REGISTERS_H - -/* Endpoint state */ -struct dwc_usb_ep { - int max_packet; - int tx_fifo; - - int out_pending; - int out_expected; - uint8_t *out_data; - uint8_t *out_databuffer; - int out_databuffer_max; - const struct deferred_data *rx_deferred; - - int in_packets; - int in_pending; - uint8_t *in_data; - uint8_t *in_databuffer; - int in_databuffer_max; - const struct deferred_data *tx_deferred; -}; - -/* USB state */ -enum dwc_usb_speed { - USB_SPEED_FS = 0, - USB_SPEED_HS, -}; - -enum dwc_usb_phy { - USB_PHY_INTERNAL = 0, - USB_PHY_ULPI, -}; - -struct dwc_usb { - struct dwc_usb_ep *ep[USB_EP_COUNT]; - enum dwc_usb_speed speed; - enum dwc_usb_phy phy_type; - int dma_en; - /* IRQ must be STM32_IRQ_OTG_FS / STM32_IRQ_OTG_HS */ - int irq; -}; - -extern struct dwc_usb_ep ep0_ctl; -extern struct dwc_usb usb_ctl; - -/* - * Added Alias Module Family Base Address to 0-instance Module Base Address - * Simplify GBASE(mname) macro - */ -#define GC_MODULE_OFFSET 0x10000 - -#define GBASE(mname) \ - GC_ ## mname ## _BASE_ADDR -#define GOFFSET(mname, rname) \ - GC_ ## mname ## _ ## rname ## _OFFSET - -#define GREG8(mname, rname) \ - REG8(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32(mname, rname) \ - REG32(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32_ADDR(mname, rname) \ - REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname)) -#define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value)) -#define GREAD(mname, rname) GREG32(mname, rname) - -#define GFIELD_MASK(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK - -#define GFIELD_LSB(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB - -#define GREAD_FIELD(mname, rname, fname) \ - ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) - -#define GWRITE_FIELD(mname, rname, fname, fval) \ - (GREG32(mname, rname) = \ - ((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) - - -#define GBASE_I(mname, i) (GBASE(mname) + i*GC_MODULE_OFFSET) - -#define GREG32_I(mname, i, rname) \ - REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) - -#define GREG32_ADDR_I(mname, i, rname) \ - REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) - -#define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value)) -#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) - -#define GREAD_FIELD_I(mname, i, rname, fname) \ - ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) - -#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ - (GREG32_I(mname, i, rname) = \ - ((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) - -/* Replace masked bits with val << lsb */ -#define REG_WRITE_MLV(reg, mask, lsb, val) \ - (reg = ((reg & ~mask) | ((val << lsb) & mask))) - - -/* USB device controller */ -#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) -#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) -#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) -#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) -#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) -#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) -#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) -#define GINTSTS(bit) (1 << GC_USB_GINTSTS_ ## bit ## _LSB) -#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) -#define GINTMSK(bit) (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB) -#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) -#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) -#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) -#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) -/*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ -#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN BIT(21) -#define GCCFG_PWRDWN BIT(16) -#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) - -#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) -#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) -#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) -#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) -#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) -#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) -#define GR_USB_DIEPTXF(n) \ - GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) -#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) -#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) -#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) -#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) -#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) -#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) -#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) -#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) -#define DAINT_OUTEP(ep) \ - (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) -#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) -#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) -#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN BIT(16) -#define DTHRCTL_ISOTHREN BIT(1) -#define DTHRCTL_NONISOTHREN BIT(0) -#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) - -#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) -#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n) * 0x20 + (off)) -#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) -#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) -#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) -#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) -#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) -#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) -#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) -#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) -#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) -#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) -#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) - -#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL BIT(7) - -/* Bit 5 */ -#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) -/* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) -/* HS Burst Len */ -#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) -/* Bit 7 */ -#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) -#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL BIT(8) - -#define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ - & GC_USB_GUSBCFG_TOUTCAL_MASK) -#define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ - & GC_USB_GUSBCFG_USBTRDTIM_MASK) -/* Force device mode */ -#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL BIT(6) -#define GUSBCFG_SRPCAP BIT(8) -#define GUSBCFG_HNPCAP BIT(9) -#define GUSBCFG_ULPIFSLS BIT(17) -#define GUSBCFG_ULPIAR BIT(18) -#define GUSBCFG_ULPICSM BIT(19) -#define GUSBCFG_ULPIEVBUSD BIT(20) -#define GUSBCFG_ULPIEVBUSI BIT(21) -#define GUSBCFG_TSDPS BIT(22) -#define GUSBCFG_PCCI BIT(23) -#define GUSBCFG_PTCI BIT(24) -#define GUSBCFG_ULPIIPD BIT(25) -#define GUSBCFG_TSDPS BIT(22) - - -#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) -#define GRSTCTL_TXFNUM(n) \ - (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) - -#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVADDR(a) \ - (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) - -#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) - -/* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) - -/* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) - -/* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) - -/* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) - -#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK -#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) -#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) -#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) - -#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) -#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) -#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) - -#define DOEPDMA_BS_HOST_RDY (0 << 30) -#define DOEPDMA_BS_DMA_BSY (1 << 30) -#define DOEPDMA_BS_DMA_DONE (2 << 30) -#define DOEPDMA_BS_HOST_BSY (3 << 30) -#define DOEPDMA_BS_MASK (3 << 30) -#define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST BIT(27) -#define DOEPDMA_SP BIT(26) -#define DOEPDMA_IOC BIT(25) -#define DOEPDMA_SR BIT(24) -#define DOEPDMA_MTRF BIT(23) -#define DOEPDMA_NAK BIT(16) -#define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) -#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) - -#define DIEPDMA_BS_HOST_RDY (0 << 30) -#define DIEPDMA_BS_DMA_BSY (1 << 30) -#define DIEPDMA_BS_DMA_DONE (2 << 30) -#define DIEPDMA_BS_HOST_BSY (3 << 30) -#define DIEPDMA_BS_MASK (3 << 30) -#define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST BIT(27) -#define DIEPDMA_SP BIT(26) -#define DIEPDMA_IOC BIT(25) -#define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) -#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) - - - -/* Register defs referenced from DWC block in CR50. This is not a native - * ST block, so we'll use this modified regdefs list. - */ - -#define GC_USB_FS_BASE_ADDR 0x50000000 -#define GC_USB_HS_BASE_ADDR 0x40040000 -#ifdef CONFIG_USB_DWC_FS -#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR -#else -#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR -#endif - -#define GC_USB_GOTGCTL_OFFSET 0x0 -#define GC_USB_GOTGCTL_DEFAULT 0x0 -#define GC_USB_GOTGINT_OFFSET 0x4 -#define GC_USB_GOTGINT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_OFFSET 0x8 -#define GC_USB_GAHBCFG_DEFAULT 0x0 -#define GC_USB_GUSBCFG_OFFSET 0xc -#define GC_USB_GUSBCFG_DEFAULT 0x0 -#define GC_USB_GRSTCTL_OFFSET 0x10 -#define GC_USB_GRSTCTL_DEFAULT 0x0 -#define GC_USB_GINTSTS_OFFSET 0x14 -#define GC_USB_GINTSTS_DEFAULT 0x0 -#define GC_USB_GINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DEFAULT 0x0 -#define GC_USB_GRXSTSR_OFFSET 0x1c -#define GC_USB_GRXSTSR_DEFAULT 0x0 -#define GC_USB_GRXSTSP_OFFSET 0x20 -#define GC_USB_GRXSTSP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_OFFSET 0x24 -#define GC_USB_GRXFSIZ_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 - -#define GC_USB_GCCFG_OFFSET 0x38 -#define GC_USB_GCCFG_DEFAULT 0x0 -#define GC_USB_GUID_OFFSET 0x3c -#define GC_USB_GUID_DEFAULT 0x0 -#define GC_USB_GSNPSID_OFFSET 0x40 -#define GC_USB_GSNPSID_DEFAULT 0x0 -#define GC_USB_GHWCFG1_OFFSET 0x44 -#define GC_USB_GHWCFG1_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OFFSET 0x48 -#define GC_USB_GHWCFG2_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OFFSET 0x4c -#define GC_USB_GHWCFG3_DEFAULT 0x0 -#define GC_USB_GHWCFG4_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_OFFSET 0x104 -#define GC_USB_DIEPTXF1_DEFAULT 0x1000 -#define GC_USB_DIEPTXF2_OFFSET 0x108 -#define GC_USB_DIEPTXF2_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_OFFSET 0x10c -#define GC_USB_DIEPTXF3_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_OFFSET 0x110 -#define GC_USB_DIEPTXF4_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_OFFSET 0x114 -#define GC_USB_DIEPTXF5_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_OFFSET 0x118 -#define GC_USB_DIEPTXF6_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_OFFSET 0x11c -#define GC_USB_DIEPTXF7_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_OFFSET 0x120 -#define GC_USB_DIEPTXF8_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_OFFSET 0x124 -#define GC_USB_DIEPTXF9_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_OFFSET 0x128 -#define GC_USB_DIEPTXF10_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_OFFSET 0x12c -#define GC_USB_DIEPTXF11_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_OFFSET 0x130 -#define GC_USB_DIEPTXF12_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_OFFSET 0x134 -#define GC_USB_DIEPTXF13_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_OFFSET 0x138 -#define GC_USB_DIEPTXF14_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_OFFSET 0x13c -#define GC_USB_DIEPTXF15_DEFAULT 0x0 -#define GC_USB_DCFG_OFFSET 0x800 -#define GC_USB_DCFG_DEFAULT 0x8000000 -#define GC_USB_DCTL_OFFSET 0x804 -#define GC_USB_DCTL_DEFAULT 0x0 -#define GC_USB_DSTS_OFFSET 0x808 -#define GC_USB_DSTS_DEFAULT 0x0 -#define GC_USB_DIEPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_DEFAULT 0x80 -#define GC_USB_DOEPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_DEFAULT 0x0 -#define GC_USB_DAINT_OFFSET 0x818 -#define GC_USB_DAINT_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OFFSET 0x81c -#define GC_USB_DAINTMSK_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DTHRCTL_OFFSET 0x830 -#define GC_USB_DTHRCTL_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_OFFSET 0x900 -#define GC_USB_DIEPCTL0_DEFAULT 0x0 -#define GC_USB_DIEPINT0_OFFSET 0x908 -#define GC_USB_DIEPINT0_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_OFFSET 0x914 -#define GC_USB_DIEPDMA0_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_OFFSET 0x918 -#define GC_USB_DTXFSTS0_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_OFFSET 0x91c -#define GC_USB_DIEPDMAB0_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DEFAULT 0x0 -#define GC_USB_DIEPINT1_OFFSET 0x928 -#define GC_USB_DIEPINT1_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_OFFSET 0x934 -#define GC_USB_DIEPDMA1_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_OFFSET 0x938 -#define GC_USB_DTXFSTS1_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_OFFSET 0x93c -#define GC_USB_DIEPDMAB1_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DEFAULT 0x0 -#define GC_USB_DIEPINT2_OFFSET 0x948 -#define GC_USB_DIEPINT2_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_OFFSET 0x954 -#define GC_USB_DIEPDMA2_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_OFFSET 0x958 -#define GC_USB_DTXFSTS2_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_OFFSET 0x95c -#define GC_USB_DIEPDMAB2_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DEFAULT 0x0 -#define GC_USB_DIEPINT3_OFFSET 0x968 -#define GC_USB_DIEPINT3_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_OFFSET 0x974 -#define GC_USB_DIEPDMA3_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_OFFSET 0x978 -#define GC_USB_DTXFSTS3_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_OFFSET 0x97c -#define GC_USB_DIEPDMAB3_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DEFAULT 0x0 -#define GC_USB_DIEPINT4_OFFSET 0x988 -#define GC_USB_DIEPINT4_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_OFFSET 0x994 -#define GC_USB_DIEPDMA4_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_OFFSET 0x998 -#define GC_USB_DTXFSTS4_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_OFFSET 0x99c -#define GC_USB_DIEPDMAB4_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DEFAULT 0x0 -#define GC_USB_DIEPINT5_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_OFFSET 0x9b4 -#define GC_USB_DIEPDMA5_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_OFFSET 0x9b8 -#define GC_USB_DTXFSTS5_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_OFFSET 0x9bc -#define GC_USB_DIEPDMAB5_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DEFAULT 0x0 -#define GC_USB_DIEPINT6_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_OFFSET 0x9d4 -#define GC_USB_DIEPDMA6_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_OFFSET 0x9d8 -#define GC_USB_DTXFSTS6_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_OFFSET 0x9dc -#define GC_USB_DIEPDMAB6_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DEFAULT 0x0 -#define GC_USB_DIEPINT7_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_OFFSET 0x9f4 -#define GC_USB_DIEPDMA7_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_OFFSET 0x9f8 -#define GC_USB_DTXFSTS7_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_OFFSET 0x9fc -#define GC_USB_DIEPDMAB7_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DEFAULT 0x0 -#define GC_USB_DIEPINT8_OFFSET 0xa08 -#define GC_USB_DIEPINT8_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_OFFSET 0xa14 -#define GC_USB_DIEPDMA8_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_OFFSET 0xa18 -#define GC_USB_DTXFSTS8_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_OFFSET 0xa1c -#define GC_USB_DIEPDMAB8_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DEFAULT 0x0 -#define GC_USB_DIEPINT9_OFFSET 0xa28 -#define GC_USB_DIEPINT9_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_OFFSET 0xa34 -#define GC_USB_DIEPDMA9_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_OFFSET 0xa38 -#define GC_USB_DTXFSTS9_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_OFFSET 0xa3c -#define GC_USB_DIEPDMAB9_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DEFAULT 0x0 -#define GC_USB_DIEPINT10_OFFSET 0xa48 -#define GC_USB_DIEPINT10_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_OFFSET 0xa54 -#define GC_USB_DIEPDMA10_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_OFFSET 0xa58 -#define GC_USB_DTXFSTS10_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_OFFSET 0xa5c -#define GC_USB_DIEPDMAB10_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DEFAULT 0x0 -#define GC_USB_DIEPINT11_OFFSET 0xa68 -#define GC_USB_DIEPINT11_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_OFFSET 0xa74 -#define GC_USB_DIEPDMA11_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_OFFSET 0xa78 -#define GC_USB_DTXFSTS11_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_OFFSET 0xa7c -#define GC_USB_DIEPDMAB11_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DEFAULT 0x0 -#define GC_USB_DIEPINT12_OFFSET 0xa88 -#define GC_USB_DIEPINT12_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_OFFSET 0xa94 -#define GC_USB_DIEPDMA12_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_OFFSET 0xa98 -#define GC_USB_DTXFSTS12_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_OFFSET 0xa9c -#define GC_USB_DIEPDMAB12_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DEFAULT 0x0 -#define GC_USB_DIEPINT13_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_OFFSET 0xab4 -#define GC_USB_DIEPDMA13_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_OFFSET 0xab8 -#define GC_USB_DTXFSTS13_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_OFFSET 0xabc -#define GC_USB_DIEPDMAB13_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DEFAULT 0x0 -#define GC_USB_DIEPINT14_OFFSET 0xac8 -#define GC_USB_DIEPINT14_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_OFFSET 0xad4 -#define GC_USB_DIEPDMA14_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_OFFSET 0xad8 -#define GC_USB_DTXFSTS14_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_OFFSET 0xadc -#define GC_USB_DIEPDMAB14_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DEFAULT 0x0 -#define GC_USB_DIEPINT15_OFFSET 0xae8 -#define GC_USB_DIEPINT15_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_OFFSET 0xaf4 -#define GC_USB_DIEPDMA15_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_OFFSET 0xaf8 -#define GC_USB_DTXFSTS15_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_OFFSET 0xafc -#define GC_USB_DIEPDMAB15_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OFFSET 0xb08 -#define GC_USB_DOEPINT0_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_OFFSET 0xb14 -#define GC_USB_DOEPDMA0_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_OFFSET 0xb1c -#define GC_USB_DOEPDMAB0_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OFFSET 0xb28 -#define GC_USB_DOEPINT1_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_OFFSET 0xb34 -#define GC_USB_DOEPDMA1_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_OFFSET 0xb3c -#define GC_USB_DOEPDMAB1_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OFFSET 0xb48 -#define GC_USB_DOEPINT2_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_OFFSET 0xb54 -#define GC_USB_DOEPDMA2_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_OFFSET 0xb5c -#define GC_USB_DOEPDMAB2_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OFFSET 0xb68 -#define GC_USB_DOEPINT3_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_OFFSET 0xb74 -#define GC_USB_DOEPDMA3_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_OFFSET 0xb7c -#define GC_USB_DOEPDMAB3_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OFFSET 0xb88 -#define GC_USB_DOEPINT4_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_OFFSET 0xb94 -#define GC_USB_DOEPDMA4_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_OFFSET 0xb9c -#define GC_USB_DOEPDMAB4_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OFFSET 0xba8 -#define GC_USB_DOEPINT5_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_OFFSET 0xbb4 -#define GC_USB_DOEPDMA5_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_OFFSET 0xbbc -#define GC_USB_DOEPDMAB5_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_OFFSET 0xbd4 -#define GC_USB_DOEPDMA6_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_OFFSET 0xbdc -#define GC_USB_DOEPDMAB6_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_OFFSET 0xbf4 -#define GC_USB_DOEPDMA7_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_OFFSET 0xbfc -#define GC_USB_DOEPDMAB7_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OFFSET 0xc08 -#define GC_USB_DOEPINT8_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_OFFSET 0xc14 -#define GC_USB_DOEPDMA8_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_OFFSET 0xc1c -#define GC_USB_DOEPDMAB8_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OFFSET 0xc28 -#define GC_USB_DOEPINT9_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_OFFSET 0xc34 -#define GC_USB_DOEPDMA9_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_OFFSET 0xc3c -#define GC_USB_DOEPDMAB9_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OFFSET 0xc48 -#define GC_USB_DOEPINT10_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_OFFSET 0xc54 -#define GC_USB_DOEPDMA10_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_OFFSET 0xc5c -#define GC_USB_DOEPDMAB10_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OFFSET 0xc68 -#define GC_USB_DOEPINT11_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_OFFSET 0xc74 -#define GC_USB_DOEPDMA11_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_OFFSET 0xc7c -#define GC_USB_DOEPDMAB11_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OFFSET 0xc88 -#define GC_USB_DOEPINT12_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_OFFSET 0xc94 -#define GC_USB_DOEPDMA12_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_OFFSET 0xc9c -#define GC_USB_DOEPDMAB12_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OFFSET 0xca8 -#define GC_USB_DOEPINT13_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_OFFSET 0xcb4 -#define GC_USB_DOEPDMA13_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_OFFSET 0xcbc -#define GC_USB_DOEPDMAB13_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_OFFSET 0xcd4 -#define GC_USB_DOEPDMA14_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_OFFSET 0xcdc -#define GC_USB_DOEPDMAB14_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OFFSET 0xce8 -#define GC_USB_DOEPINT15_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_OFFSET 0xcf4 -#define GC_USB_DOEPDMA15_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_OFFSET 0xcfc -#define GC_USB_DOEPDMAB15_DEFAULT 0x0 -#define GC_USB_PCGCCTL_OFFSET 0xe00 -#define GC_USB_PCGCCTL_DEFAULT 0x0 -#define GC_USB_DFIFO_OFFSET 0x20000 -#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 -#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 -#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 -#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 -#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 -#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 -#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 -#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 -#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 -#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 -#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 -#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 -#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 -#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 -#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 -#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 -#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 -#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 -#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 -#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 -#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 -#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 -#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 -#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 -#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 -#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 -#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 -#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 -#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 -#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 -#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 -#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 -#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 -#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 -#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e -#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 -#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 -#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 -#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 -#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 - -#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 - -#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 -#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 -#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 -#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 -#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 -#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 -#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 -#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 -#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 -#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 -#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 -#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 -#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc - -#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa -#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 -#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 -#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 -#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 -#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 -#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 -#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 -#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 -#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 -#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 -#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 -#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 -#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc - -#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc - -#define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) -#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc - -#define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) -#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) -#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc - -#define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) -#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc - -#define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) -#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc - -#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 -#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 -#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 -#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 -#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 -#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 -#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 -#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 -#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 -#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 -#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e -#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 -#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 -#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 -#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 -#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f -#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 -#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 -#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 -#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 -#define GC_USB_GINTSTS_CURMOD_LSB 0x0 -#define GC_USB_GINTSTS_CURMOD_MASK 0x1 -#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 -#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 -#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 -#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 -#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 -#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 -#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_OTGINT_LSB 0x2 -#define GC_USB_GINTSTS_OTGINT_MASK 0x4 -#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 -#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 -#define GC_USB_GINTSTS_SOF_LSB 0x3 -#define GC_USB_GINTSTS_SOF_MASK 0x8 -#define GC_USB_GINTSTS_SOF_SIZE 0x1 -#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 -#define GC_USB_GINTSTS_SOF_OFFSET 0x14 -#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 -#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 -#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 -#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 -#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 -#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 -#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 -#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 -#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 -#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa -#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 -#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBSUSP_LSB 0xb -#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 -#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBRST_LSB 0xc -#define GC_USB_GINTSTS_USBRST_MASK 0x1000 -#define GC_USB_GINTSTS_USBRST_SIZE 0x1 -#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 -#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd -#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 -#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 -#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 -#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 -#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe -#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 -#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 -#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 -#define GC_USB_GINTSTS_EOPF_LSB 0xf -#define GC_USB_GINTSTS_EOPF_MASK 0x8000 -#define GC_USB_GINTSTS_EOPF_SIZE 0x1 -#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 -#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 -#define GC_USB_GINTSTS_EPMIS_LSB 0x11 -#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 -#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 -#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_IEPINT_LSB 0x12 -#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 -#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_OEPINT_LSB 0x13 -#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 -#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 -#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 -#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 -#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 -#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 -#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 -#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_RESETDET_LSB 0x17 -#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 -#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 -#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 -#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 -#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c -#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 -#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 -#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 -#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 -#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e -#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 -#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 -#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 -#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f -#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 -#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 -#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 -#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 -#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 -#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 -#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 -#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 -#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 -#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 -#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 -#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 -#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 -#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 -#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 -#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa -#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 -#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb -#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 -#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc -#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 -#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd -#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 -#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe -#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf -#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 -#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 -#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 -#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 -#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 -#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 -#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 -#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 -#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 -#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 -#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 -#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 -#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 -#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 -#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 -#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 -#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d -#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 -#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e -#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 -#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f -#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 -#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 -#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSR_CHNUM_MASK 0xf -#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c -#define GC_USB_GRXSTSR_BCNT_LSB 0x4 -#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSR_BCNT_SIZE 0xb -#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c -#define GC_USB_GRXSTSR_DPID_LSB 0xf -#define GC_USB_GRXSTSR_DPID_MASK 0x18000 -#define GC_USB_GRXSTSR_DPID_SIZE 0x2 -#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c -#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c -#define GC_USB_GRXSTSR_FN_LSB 0x15 -#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSR_FN_SIZE 0x4 -#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSR_FN_OFFSET 0x1c -#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSP_CHNUM_MASK 0xf -#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 -#define GC_USB_GRXSTSP_BCNT_LSB 0x4 -#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSP_BCNT_SIZE 0xb -#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 -#define GC_USB_GRXSTSP_DPID_LSB 0xf -#define GC_USB_GRXSTSP_DPID_MASK 0x18000 -#define GC_USB_GRXSTSP_DPID_SIZE 0x2 -#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 -#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 -#define GC_USB_GRXSTSP_FN_LSB 0x15 -#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSP_FN_SIZE 0x4 -#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSP_FN_OFFSET 0x20 -#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff -#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb -#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 - -#define GC_USB_GUID_GUID_LSB 0x0 -#define GC_USB_GUID_GUID_MASK 0xffffffff -#define GC_USB_GUID_GUID_SIZE 0x20 -#define GC_USB_GUID_GUID_DEFAULT 0x0 -#define GC_USB_GUID_GUID_OFFSET 0x3c -#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff -#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 -#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 -#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 -#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff -#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 -#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 -#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 -#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 -#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 -#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 -#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 -#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 -#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 -#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 -#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 -#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 -#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 -#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 -#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 -#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 -#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 -#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 -#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 -#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa -#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 -#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe -#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 -#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 -#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 -#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 -#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 -#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 -#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 -#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 -#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 -#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a -#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 -#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 -#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 -#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 -#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 -#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c -#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 -#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 -#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 -#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 -#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c -#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 -#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 -#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 -#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c -#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa -#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 -#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 -#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c -#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb -#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 -#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 -#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c -#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc -#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 -#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd -#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 -#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe -#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 -#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf -#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 -#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 -#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 -#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 -#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 -#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 -#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 -#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 -#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 -#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 -#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 -#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 -#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe -#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 -#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 -#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 -#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 -#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 -#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 -#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 -#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 -#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 -#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 -#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 -#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 -#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 -#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 -#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 -#define GC_USB_GHWCFG4_INEPS_LSB 0x1a -#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 -#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e -#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 -#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f -#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 -#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff -#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 -#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc -#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 -#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c -#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c -#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c -#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c -#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c -#define GC_USB_DCFG_DEVSPD_LSB 0x0 -#define GC_USB_DCFG_DEVSPD_MASK 0x3 -#define GC_USB_DCFG_DEVSPD_SIZE 0x2 -#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 -#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 -#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 -#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 -#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 -#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 -#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 -#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 -#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 -#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 -#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 -#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 -#define GC_USB_DCFG_DEVADDR_LSB 0x4 -#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 -#define GC_USB_DCFG_DEVADDR_SIZE 0x7 -#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 -#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 -#define GC_USB_DCFG_PERFRINT_LSB 0xb -#define GC_USB_DCFG_PERFRINT_MASK 0x1800 -#define GC_USB_DCFG_PERFRINT_SIZE 0x2 -#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 -#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 -#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd -#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 -#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 -#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 -#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 -#define GC_USB_DCFG_XCVRDLY_LSB 0xe -#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 -#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 -#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 -#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 -#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf -#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 -#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 -#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 -#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 -#define GC_USB_DCFG_DESCDMA_LSB 0x17 -#define GC_USB_DCFG_DESCDMA_MASK 0x800000 -#define GC_USB_DCFG_DESCDMA_SIZE 0x1 -#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 -#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 -#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 -#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 -#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 -#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 -#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 -#define GC_USB_DCFG_RESVALID_LSB 0x1a -#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 -#define GC_USB_DCFG_RESVALID_SIZE 0x6 -#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 -#define GC_USB_DCFG_RESVALID_OFFSET 0x800 -#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 -#define GC_USB_DCTL_SFTDISCON_LSB 0x1 -#define GC_USB_DCTL_SFTDISCON_MASK 0x2 -#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 -#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 -#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 -#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 -#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 -#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 -#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 -#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_TSTCTL_LSB 0x4 -#define GC_USB_DCTL_TSTCTL_MASK 0x70 -#define GC_USB_DCTL_TSTCTL_SIZE 0x3 -#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 -#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 -#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 -#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 -#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 -#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 -#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 -#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 -#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGOUTNAK_LSB 0xa -#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 -#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb -#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 -#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 -#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 -#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 -#define GC_USB_DCTL_GMC_LSB 0xd -#define GC_USB_DCTL_GMC_MASK 0x6000 -#define GC_USB_DCTL_GMC_SIZE 0x2 -#define GC_USB_DCTL_GMC_DEFAULT 0x0 -#define GC_USB_DCTL_GMC_OFFSET 0x804 -#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf -#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 -#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 -#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 -#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 -#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 -#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 -#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 -#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 -#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 -#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 -#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 -#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 -#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 -#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 -#define GC_USB_DSTS_SUSPSTS_LSB 0x0 -#define GC_USB_DSTS_SUSPSTS_MASK 0x1 -#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 -#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 -#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 -#define GC_USB_DSTS_ENUMSPD_LSB 0x1 -#define GC_USB_DSTS_ENUMSPD_MASK 0x6 -#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 -#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 -#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 -#define GC_USB_DSTS_ERRTICERR_LSB 0x3 -#define GC_USB_DSTS_ERRTICERR_MASK 0x8 -#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 -#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 -#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 -#define GC_USB_DSTS_SOFFN_LSB 0x8 -#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 -#define GC_USB_DSTS_SOFFN_SIZE 0xe -#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 -#define GC_USB_DSTS_SOFFN_OFFSET 0x808 -#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 -#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 -#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 -#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 -#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 -#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 -#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 -#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 -#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 -#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 -#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 -#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 -#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 -#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 -#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc -#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 -#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe -#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 -#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 -#define GC_USB_DAINT_INEPINT0_LSB 0x0 -#define GC_USB_DAINT_INEPINT0_MASK 0x1 -#define GC_USB_DAINT_INEPINT0_SIZE 0x1 -#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT1_LSB 0x1 -#define GC_USB_DAINT_INEPINT1_MASK 0x2 -#define GC_USB_DAINT_INEPINT1_SIZE 0x1 -#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT2_LSB 0x2 -#define GC_USB_DAINT_INEPINT2_MASK 0x4 -#define GC_USB_DAINT_INEPINT2_SIZE 0x1 -#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT3_LSB 0x3 -#define GC_USB_DAINT_INEPINT3_MASK 0x8 -#define GC_USB_DAINT_INEPINT3_SIZE 0x1 -#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT4_LSB 0x4 -#define GC_USB_DAINT_INEPINT4_MASK 0x10 -#define GC_USB_DAINT_INEPINT4_SIZE 0x1 -#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT5_LSB 0x5 -#define GC_USB_DAINT_INEPINT5_MASK 0x20 -#define GC_USB_DAINT_INEPINT5_SIZE 0x1 -#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT6_LSB 0x6 -#define GC_USB_DAINT_INEPINT6_MASK 0x40 -#define GC_USB_DAINT_INEPINT6_SIZE 0x1 -#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT7_LSB 0x7 -#define GC_USB_DAINT_INEPINT7_MASK 0x80 -#define GC_USB_DAINT_INEPINT7_SIZE 0x1 -#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT8_LSB 0x8 -#define GC_USB_DAINT_INEPINT8_MASK 0x100 -#define GC_USB_DAINT_INEPINT8_SIZE 0x1 -#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT9_LSB 0x9 -#define GC_USB_DAINT_INEPINT9_MASK 0x200 -#define GC_USB_DAINT_INEPINT9_SIZE 0x1 -#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT10_LSB 0xa -#define GC_USB_DAINT_INEPINT10_MASK 0x400 -#define GC_USB_DAINT_INEPINT10_SIZE 0x1 -#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT11_LSB 0xb -#define GC_USB_DAINT_INEPINT11_MASK 0x800 -#define GC_USB_DAINT_INEPINT11_SIZE 0x1 -#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT12_LSB 0xc -#define GC_USB_DAINT_INEPINT12_MASK 0x1000 -#define GC_USB_DAINT_INEPINT12_SIZE 0x1 -#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT13_LSB 0xd -#define GC_USB_DAINT_INEPINT13_MASK 0x2000 -#define GC_USB_DAINT_INEPINT13_SIZE 0x1 -#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT14_LSB 0xe -#define GC_USB_DAINT_INEPINT14_MASK 0x4000 -#define GC_USB_DAINT_INEPINT14_SIZE 0x1 -#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT15_LSB 0xf -#define GC_USB_DAINT_INEPINT15_MASK 0x8000 -#define GC_USB_DAINT_INEPINT15_SIZE 0x1 -#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 -#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 -#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 -#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 -#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 -#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 -#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 -#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 -#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 -#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 -#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 -#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 -#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 -#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 -#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 -#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 -#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 -#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 -#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 -#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 -#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a -#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 -#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b -#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 -#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c -#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 -#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d -#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 -#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e -#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 -#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f -#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 -#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 -#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 -#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 -#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 -#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 -#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 -#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 -#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 -#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 -#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 -#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 -#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 -#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 -#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 -#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 -#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 -#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 -#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 -#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa -#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 -#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb -#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 -#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc -#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 -#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd -#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 -#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe -#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 -#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf -#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 -#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 -#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 -#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 -#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 -#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 -#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 -#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 -#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 -#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 -#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 -#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 -#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 -#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 -#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 -#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 -#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 -#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 -#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 -#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 -#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 -#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a -#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 -#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b -#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 -#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c -#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 -#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d -#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 -#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e -#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 -#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f -#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 -#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c -#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff -#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 -#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff -#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc -#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 -#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 -#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc -#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb -#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 -#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 -#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 -#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 -#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 -#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 -#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 -#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b -#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 -#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 -#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPCTL0_MPS_LSB 0x0 -#define GC_USB_DIEPCTL0_MPS_MASK 0x3 -#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 -#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 -#define GC_USB_DIEPCTL0_STALL_LSB 0x15 -#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 -#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 -#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 -#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 -#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 -#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 -#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 -#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 -#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 -#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 -#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 -#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 -#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 -#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 -#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c -#define GC_USB_DIEPCTL1_MPS_LSB 0x0 -#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL1_MPS_SIZE 0xb -#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DPID_LSB 0x10 -#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 -#define GC_USB_DIEPCTL1_STALL_LSB 0x15 -#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 -#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 -#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 -#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 -#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 -#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 -#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 -#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 -#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 -#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 -#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 -#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 -#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c -#define GC_USB_DIEPCTL2_MPS_LSB 0x0 -#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL2_MPS_SIZE 0xb -#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DPID_LSB 0x10 -#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 -#define GC_USB_DIEPCTL2_STALL_LSB 0x15 -#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 -#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 -#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 -#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 -#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 -#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 -#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 -#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 -#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 -#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 -#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 -#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 -#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c -#define GC_USB_DIEPCTL3_MPS_LSB 0x0 -#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL3_MPS_SIZE 0xb -#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DPID_LSB 0x10 -#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 -#define GC_USB_DIEPCTL3_STALL_LSB 0x15 -#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 -#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 -#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 -#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 -#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 -#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 -#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 -#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 -#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 -#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 -#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 -#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 -#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c -#define GC_USB_DIEPCTL4_MPS_LSB 0x0 -#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL4_MPS_SIZE 0xb -#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DPID_LSB 0x10 -#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 -#define GC_USB_DIEPCTL4_STALL_LSB 0x15 -#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 -#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 -#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 -#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 -#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 -#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 -#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 -#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 -#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 -#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 -#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 -#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 -#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c -#define GC_USB_DIEPCTL5_MPS_LSB 0x0 -#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL5_MPS_SIZE 0xb -#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DPID_LSB 0x10 -#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_STALL_LSB 0x15 -#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 -#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 -#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc -#define GC_USB_DIEPCTL6_MPS_LSB 0x0 -#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL6_MPS_SIZE 0xb -#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DPID_LSB 0x10 -#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_STALL_LSB 0x15 -#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 -#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 -#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc -#define GC_USB_DIEPCTL7_MPS_LSB 0x0 -#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL7_MPS_SIZE 0xb -#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DPID_LSB 0x10 -#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_STALL_LSB 0x15 -#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 -#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 -#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc -#define GC_USB_DIEPCTL8_MPS_LSB 0x0 -#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL8_MPS_SIZE 0xb -#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DPID_LSB 0x10 -#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_STALL_LSB 0x15 -#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 -#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 -#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 -#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 -#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c -#define GC_USB_DIEPCTL9_MPS_LSB 0x0 -#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL9_MPS_SIZE 0xb -#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DPID_LSB 0x10 -#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_STALL_LSB 0x15 -#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 -#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 -#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 -#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 -#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c -#define GC_USB_DIEPCTL10_MPS_LSB 0x0 -#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL10_MPS_SIZE 0xb -#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DPID_LSB 0x10 -#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_STALL_LSB 0x15 -#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 -#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 -#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 -#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 -#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c -#define GC_USB_DIEPCTL11_MPS_LSB 0x0 -#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL11_MPS_SIZE 0xb -#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DPID_LSB 0x10 -#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_STALL_LSB 0x15 -#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 -#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 -#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 -#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 -#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c -#define GC_USB_DIEPCTL12_MPS_LSB 0x0 -#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL12_MPS_SIZE 0xb -#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DPID_LSB 0x10 -#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_STALL_LSB 0x15 -#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 -#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 -#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 -#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 -#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c -#define GC_USB_DIEPCTL13_MPS_LSB 0x0 -#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL13_MPS_SIZE 0xb -#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DPID_LSB 0x10 -#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_STALL_LSB 0x15 -#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 -#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 -#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc -#define GC_USB_DIEPCTL14_MPS_LSB 0x0 -#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL14_MPS_SIZE 0xb -#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DPID_LSB 0x10 -#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_STALL_LSB 0x15 -#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 -#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 -#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 -#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 -#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc -#define GC_USB_DIEPCTL15_MPS_LSB 0x0 -#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL15_MPS_SIZE 0xb -#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DPID_LSB 0x10 -#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_STALL_LSB 0x15 -#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 -#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 -#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 -#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 -#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc -#define GC_USB_DOEPCTL0_MPS_LSB 0x0 -#define GC_USB_DOEPCTL0_MPS_MASK 0x3 -#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNP_LSB 0x14 -#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_STALL_LSB 0x15 -#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 -#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 -#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_SETUP_LSB 0x3 -#define GC_USB_DOEPINT0_SETUP_MASK 0x8 -#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 -#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 -#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 -#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d -#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 -#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 -#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 -#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c -#define GC_USB_DOEPCTL1_MPS_LSB 0x0 -#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL1_MPS_SIZE 0xb -#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DPID_LSB 0x10 -#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNP_LSB 0x14 -#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_STALL_LSB 0x15 -#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 -#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 -#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_SETUP_LSB 0x3 -#define GC_USB_DOEPINT1_SETUP_MASK 0x8 -#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 -#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 -#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c -#define GC_USB_DOEPCTL2_MPS_LSB 0x0 -#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL2_MPS_SIZE 0xb -#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DPID_LSB 0x10 -#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNP_LSB 0x14 -#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_STALL_LSB 0x15 -#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 -#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 -#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_SETUP_LSB 0x3 -#define GC_USB_DOEPINT2_SETUP_MASK 0x8 -#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 -#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 -#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c -#define GC_USB_DOEPCTL3_MPS_LSB 0x0 -#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL3_MPS_SIZE 0xb -#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DPID_LSB 0x10 -#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNP_LSB 0x14 -#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_STALL_LSB 0x15 -#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 -#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 -#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_SETUP_LSB 0x3 -#define GC_USB_DOEPINT3_SETUP_MASK 0x8 -#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 -#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 -#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c -#define GC_USB_DOEPCTL4_MPS_LSB 0x0 -#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL4_MPS_SIZE 0xb -#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DPID_LSB 0x10 -#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNP_LSB 0x14 -#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_STALL_LSB 0x15 -#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 -#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 -#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_SETUP_LSB 0x3 -#define GC_USB_DOEPINT4_SETUP_MASK 0x8 -#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 -#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 -#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c -#define GC_USB_DOEPCTL5_MPS_LSB 0x0 -#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL5_MPS_SIZE 0xb -#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DPID_LSB 0x10 -#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNP_LSB 0x14 -#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_STALL_LSB 0x15 -#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 -#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 -#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_SETUP_LSB 0x3 -#define GC_USB_DOEPINT5_SETUP_MASK 0x8 -#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 -#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 -#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc -#define GC_USB_DOEPCTL6_MPS_LSB 0x0 -#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL6_MPS_SIZE 0xb -#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DPID_LSB 0x10 -#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNP_LSB 0x14 -#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_STALL_LSB 0x15 -#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 -#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_SETUP_LSB 0x3 -#define GC_USB_DOEPINT6_SETUP_MASK 0x8 -#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 -#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 -#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc -#define GC_USB_DOEPCTL7_MPS_LSB 0x0 -#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL7_MPS_SIZE 0xb -#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DPID_LSB 0x10 -#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNP_LSB 0x14 -#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_STALL_LSB 0x15 -#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 -#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_SETUP_LSB 0x3 -#define GC_USB_DOEPINT7_SETUP_MASK 0x8 -#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 -#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 -#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc -#define GC_USB_DOEPCTL8_MPS_LSB 0x0 -#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL8_MPS_SIZE 0xb -#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DPID_LSB 0x10 -#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNP_LSB 0x14 -#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_STALL_LSB 0x15 -#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 -#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 -#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_SETUP_LSB 0x3 -#define GC_USB_DOEPINT8_SETUP_MASK 0x8 -#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 -#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 -#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c -#define GC_USB_DOEPCTL9_MPS_LSB 0x0 -#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL9_MPS_SIZE 0xb -#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DPID_LSB 0x10 -#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNP_LSB 0x14 -#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_STALL_LSB 0x15 -#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 -#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 -#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_SETUP_LSB 0x3 -#define GC_USB_DOEPINT9_SETUP_MASK 0x8 -#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 -#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 -#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c -#define GC_USB_DOEPCTL10_MPS_LSB 0x0 -#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL10_MPS_SIZE 0xb -#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DPID_LSB 0x10 -#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNP_LSB 0x14 -#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_STALL_LSB 0x15 -#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 -#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 -#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_SETUP_LSB 0x3 -#define GC_USB_DOEPINT10_SETUP_MASK 0x8 -#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 -#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 -#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c -#define GC_USB_DOEPCTL11_MPS_LSB 0x0 -#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL11_MPS_SIZE 0xb -#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DPID_LSB 0x10 -#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNP_LSB 0x14 -#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_STALL_LSB 0x15 -#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 -#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 -#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_SETUP_LSB 0x3 -#define GC_USB_DOEPINT11_SETUP_MASK 0x8 -#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 -#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 -#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c -#define GC_USB_DOEPCTL12_MPS_LSB 0x0 -#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL12_MPS_SIZE 0xb -#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DPID_LSB 0x10 -#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNP_LSB 0x14 -#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_STALL_LSB 0x15 -#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 -#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 -#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_SETUP_LSB 0x3 -#define GC_USB_DOEPINT12_SETUP_MASK 0x8 -#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 -#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 -#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c -#define GC_USB_DOEPCTL13_MPS_LSB 0x0 -#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL13_MPS_SIZE 0xb -#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DPID_LSB 0x10 -#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNP_LSB 0x14 -#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_STALL_LSB 0x15 -#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 -#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 -#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_SETUP_LSB 0x3 -#define GC_USB_DOEPINT13_SETUP_MASK 0x8 -#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 -#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 -#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc -#define GC_USB_DOEPCTL14_MPS_LSB 0x0 -#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL14_MPS_SIZE 0xb -#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DPID_LSB 0x10 -#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNP_LSB 0x14 -#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_STALL_LSB 0x15 -#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 -#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_SETUP_LSB 0x3 -#define GC_USB_DOEPINT14_SETUP_MASK 0x8 -#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 -#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 -#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc -#define GC_USB_DOEPCTL15_MPS_LSB 0x0 -#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL15_MPS_SIZE 0xb -#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DPID_LSB 0x10 -#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNP_LSB 0x14 -#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_STALL_LSB 0x15 -#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 -#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 -#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_SETUP_LSB 0x3 -#define GC_USB_DOEPINT15_SETUP_MASK 0x8 -#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 -#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 -#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc -#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 -#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 -#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 -#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 -#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 -#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 -#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 -#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 -#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 -#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 -#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 -#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 -#define GC_USB_DFIFO_SIZE 0x1000 - - -#endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */ diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c deleted file mode 100644 index 2f20d88dda..0000000000 --- a/chip/stm32/usb_dwc_stream.c +++ /dev/null @@ -1,99 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "registers.h" -#include "timer.h" -#include "usb_dwc_stream.h" -#include "util.h" - -#include "console.h" -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -/* - * This function tries to shove new bytes from the USB host into the queue for - * consumption elsewhere. It is invoked either by a HW interrupt (telling us we - * have new bytes from the USB host), or by whoever is reading bytes out of the - * other end of the queue (telling us that there's now more room in the queue - * if we still have bytes to shove in there). - */ -int rx_stream_handler(struct usb_stream_config const *config) -{ - int rx_count = rx_ep_pending(config->endpoint); - - /* If we have some, try to shove them into the queue */ - if (rx_count) { - size_t added = QUEUE_ADD_UNITS( - config->producer.queue, config->rx_ram, - rx_count); - if (added != rx_count) { - CPRINTF("rx_stream_handler: failed ep%d " - "queue %d bytes, accepted %d\n", - config->endpoint, rx_count, added); - } - } - - if (!rx_ep_is_active(config->endpoint)) - usb_read_ep(config->endpoint, config->rx_size, config->rx_ram); - - return rx_count; -} - -/* Try to send some bytes to the host */ -int tx_stream_handler(struct usb_stream_config const *config) -{ - size_t count; - - if (!*(config->is_reset)) - return 0; - if (!tx_ep_is_ready(config->endpoint)) - return 0; - - count = QUEUE_REMOVE_UNITS(config->consumer.queue, config->tx_ram, - config->tx_size); - if (count) - usb_write_ep(config->endpoint, count, config->tx_ram); - - return count; -} - -/* Reset stream */ -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - epN_reset(config->endpoint); - - *(config->is_reset) = 1; - - /* Flush any queued data */ - hook_call_deferred(config->deferred_tx, 0); - hook_call_deferred(config->deferred_rx, 0); -} - -static void usb_read(struct producer const *producer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(producer, struct usb_stream_config, producer); - - hook_call_deferred(config->deferred_rx, 0); -} - -static void usb_written(struct consumer const *consumer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(consumer, struct usb_stream_config, consumer); - - hook_call_deferred(config->deferred_tx, 0); -} - -struct producer_ops const usb_stream_producer_ops = { - .read = usb_read, -}; - -struct consumer_ops const usb_stream_consumer_ops = { - .written = usb_written, -}; diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h deleted file mode 100644 index e46e7a929c..0000000000 --- a/chip/stm32/usb_dwc_stream.h +++ /dev/null @@ -1,237 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_DWC_STREAM_H -#define __CROS_EC_USB_DWC_STREAM_H - -/* USB STREAM driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "consumer.h" -#include "hooks.h" -#include "registers.h" -#include "producer.h" -#include "queue.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * Compile time Per-USB stream configuration stored in flash. Instances of this - * structure are provided by the user of the USB stream. This structure binds - * together all information required to operate a USB stream. - */ -struct usb_stream_config { - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - struct dwc_usb_ep *ep; - - int *is_reset; - int *overflow; - - /* - * Deferred function to call to handle USB and Queue request. - */ - const struct deferred_data *deferred_tx; - const struct deferred_data *deferred_rx; - - int tx_size; - int rx_size; - - uint8_t *tx_ram; - uint8_t *rx_ram; - - struct consumer consumer; - struct producer producer; -}; - -/* - * These function tables are defined by the USB Stream driver and are used to - * initialize the consumer and producer in the usb_stream_config. - */ -extern struct consumer_ops const usb_stream_consumer_ops; -extern struct producer_ops const usb_stream_producer_ops; - - -/* - * Convenience macro for defining USB streams and their associated state and - * buffers. - * - * NAME is used to construct the names of the packet RAM buffers, trampoline - * functions, usb_stream_state struct, and usb_stream_config struct, the - * latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * stream. - * - * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the - * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields - * respectively in the USB interface descriptor. - * - * INTERFACE_NAME is the index of the USB string descriptor (iInterface). - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - * - * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate - * for the RX and TX packets respectively. The valid values for these - * parameters are dictated by the USB peripheral. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver - * should write to and read from respectively. - */ - -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE); - * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE); - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ - static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ - static int CONCAT2(NAME, _is_reset_); \ - static int CONCAT2(NAME, _overflow_); \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - struct usb_stream_config const NAME = { \ - .endpoint = ENDPOINT, \ - .is_reset = &CONCAT2(NAME, _is_reset_), \ - .overflow = &CONCAT2(NAME, _overflow_), \ - .deferred_tx = &CONCAT2(NAME, _deferred_tx__data), \ - .deferred_rx = &CONCAT2(NAME, _deferred_rx__data), \ - .tx_size = TX_SIZE, \ - .rx_size = RX_SIZE, \ - .tx_ram = CONCAT2(NAME, _buf_tx_), \ - .rx_ram = CONCAT2(NAME, _buf_rx_), \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &usb_stream_consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &usb_stream_producer_ops, \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { tx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { rx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_epN_tx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_epN_rx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_expected = 0, \ - .out_data = 0, \ - .out_databuffer = CONCAT2(NAME, _buf_rx_), \ - .out_databuffer_max = RX_SIZE, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = CONCAT2(NAME, _buf_tx_), \ - .in_databuffer_max = TX_SIZE, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); - -/* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) - -/* - * Handle USB and Queue request in a deferred callback. - */ -int rx_stream_handler(struct usb_stream_config const *config); -int tx_stream_handler(struct usb_stream_config const *config); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB stream driver. - */ -void usb_stream_tx(struct usb_stream_config const *config); -void usb_stream_rx(struct usb_stream_config const *config); -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); - -#endif /* __CROS_EC_USB_STREAM_H */ diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h deleted file mode 100644 index 6d79f3aca9..0000000000 --- a/chip/stm32/usb_dwc_update.h +++ /dev/null @@ -1,10 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_STM32_USB_DWC_UPDATE_H -#define __CROS_EC_STM32_USB_DWC_UPDATE_H - -extern struct dwc_usb_ep usb_update_ep_ctl; - -#endif /* __CROS_EC_STM32_USB_DWC_UPDATE_H */ diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c deleted file mode 100644 index 85952a1387..0000000000 --- a/chip/stm32/usb_endpoints.c +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * USB endpoints/interfaces callbacks declaration - */ - -#include <stdint.h> -#include <stddef.h> -#include "config.h" -#include "common.h" -#include "usb_hw.h" - -typedef void (*xfer_func)(void); -typedef void (*evt_func) (enum usb_ep_event evt); - -#if defined(CHIP_FAMILY_STM32F4) -#define iface_arguments struct usb_setup_packet *req -#else -#define iface_arguments usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx -#endif -typedef int (*iface_func)(iface_arguments); - -#ifndef PASS -#define PASS 1 -#endif - -#if PASS == 1 -void ep_undefined(void) -{ - return; -} - -void ep_evt_undefined(enum usb_ep_event evt) -{ - return; -} - -/* Undefined interface callbacks fail by returning non-zero*/ -int iface_undefined(iface_arguments) -{ - return 1; -} - -#define table(type, name, x) x - -#define endpoint_tx(number) \ - extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _tx(void); -#define endpoint_rx(number) \ - extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _rx(void); -#define endpoint_evt(number) \ - extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \ - ep_ ## number ## _evt(enum usb_ep_event evt); -#define interface(number) \ - extern int __attribute__((used, weak, alias("iface_undefined"))) \ - iface_ ## number ## _request(iface_arguments); - -#define null - -#endif /* PASS 1 */ - -#if PASS == 2 -#undef table -#undef endpoint_tx -#undef endpoint_rx -#undef endpoint_evt -#undef interface -#undef null - -/* align function pointers on a 32-bit boundary */ -#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x }; -#define null (void*)0 - -#define ep_(num, suf) CONCAT3(ep_, num, suf) -#define ep(num, suf) ep_(num, suf) - -#define endpoint_tx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx, -#define endpoint_rx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx, -#define endpoint_evt(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt, -#define interface(number) \ - [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request, -#endif /* PASS 2 */ - -/* - * The initializers are listed backwards, but that's so that the items beyond - * the chip's limit are first assigned to the last field, then overwritten by - * its actual value due to the designated initializers in the macros above. - * It all sorts out nicely - */ -table(xfer_func, usb_ep_tx, - endpoint_tx(15) - endpoint_tx(14) - endpoint_tx(13) - endpoint_tx(12) - endpoint_tx(11) - endpoint_tx(10) - endpoint_tx(9) - endpoint_tx(8) - endpoint_tx(7) - endpoint_tx(6) - endpoint_tx(5) - endpoint_tx(4) - endpoint_tx(3) - endpoint_tx(2) - endpoint_tx(1) - endpoint_tx(0) -) - -table(xfer_func, usb_ep_rx, - endpoint_rx(15) - endpoint_rx(14) - endpoint_rx(13) - endpoint_rx(12) - endpoint_rx(11) - endpoint_rx(10) - endpoint_rx(9) - endpoint_rx(8) - endpoint_rx(7) - endpoint_rx(6) - endpoint_rx(5) - endpoint_rx(4) - endpoint_rx(3) - endpoint_rx(2) - endpoint_rx(1) - endpoint_rx(0) -) - -table(evt_func, usb_ep_event, - endpoint_evt(15) - endpoint_evt(14) - endpoint_evt(13) - endpoint_evt(12) - endpoint_evt(11) - endpoint_evt(10) - endpoint_evt(9) - endpoint_evt(8) - endpoint_evt(7) - endpoint_evt(6) - endpoint_evt(5) - endpoint_evt(4) - endpoint_evt(3) - endpoint_evt(2) - endpoint_evt(1) - endpoint_evt(0) -) - -#if USB_IFACE_COUNT > 0 -table(iface_func, usb_iface_request, - interface(7) - interface(6) - interface(5) - interface(4) - interface(3) - interface(2) - interface(1) - interface(0) -) -#endif - -#if PASS == 1 -#undef PASS -#define PASS 2 -#include "usb_endpoints.c" -#endif diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c deleted file mode 100644 index 37eebf5b28..0000000000 --- a/chip/stm32/usb_gpio.c +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "gpio.h" -#include "link_defs.h" -#include "registers.h" -#include "usb_gpio.h" - -void usb_gpio_tx(struct usb_gpio_config const *config) -{ - size_t i; - uint32_t mask = 1; - uint32_t value = 0; - - for (i = 0; i < config->num_gpios; ++i, mask <<= 1) - value |= (gpio_get_level(config->gpios[i])) ? mask : 0; - - config->tx_ram[0] = value; - config->tx_ram[1] = value >> 16; - - btable_ep[config->endpoint].tx_count = USB_GPIO_TX_PACKET_SIZE; - - /* - * TX packet updated, mark the packet as VALID. - */ - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); -} - -void usb_gpio_rx(struct usb_gpio_config const *config) -{ - size_t i; - uint32_t mask = 1; - uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | - (uint32_t)(config->rx_ram[1]) << 16); - uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | - (uint32_t)(config->rx_ram[3]) << 16); - uint32_t ignore_mask = set_mask & clear_mask; - - config->state->set_mask = set_mask; - config->state->clear_mask = clear_mask; - - if ((btable_ep[config->endpoint].rx_count & 0x3ff) == - USB_GPIO_RX_PACKET_SIZE) { - for (i = 0; i < config->num_gpios; ++i, mask <<= 1) { - if (ignore_mask & mask) - ; - else if (set_mask & mask) - gpio_set_level(config->gpios[i], 1); - else if (clear_mask & mask) - gpio_set_level(config->gpios[i], 0); - } - } - - /* - * RX packet consumed, mark the packet as VALID. - */ - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); -} - -void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) -{ - int i; - - if (evt != USB_EVENT_RESET) - return; - - i = config->endpoint; - - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); - btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE; - - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); - btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10); - - /* - * Initialize TX buffer with zero, the first IN transaction will fill - * this in with a valid value. - */ - config->tx_ram[0] = 0; - config->tx_ram[1] = 0; - - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (3 << 4) | /* TX Valid */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ -} diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h deleted file mode 100644 index b27c7f9485..0000000000 --- a/chip/stm32/usb_gpio.h +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_GPIO_H -#define __CROS_EC_USB_GPIO_H - -/* STM32 USB GPIO driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -struct usb_gpio_state { - uint32_t set_mask; - uint32_t clear_mask; -}; - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_gpio_config { - struct usb_gpio_state *state; - - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - - usb_uint *rx_ram; - usb_uint *tx_ram; - - /* - * GPIO list - */ - enum gpio_signal const *gpios; - size_t num_gpios; -}; - -#define USB_GPIO_RX_PACKET_SIZE 8 -#define USB_GPIO_TX_PACKET_SIZE 4 - -/* - * Convenience macro for defining a USB GPIO driver and its associated state. - * - * NAME is used to construct the names of the trampoline functions, - * usb_gpio_state struct, and usb_gpio_config struct, the latter is just - * called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * GPIO driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - */ -#define USB_GPIO_CONFIG(NAME, \ - GPIO_LIST, \ - INTERFACE, \ - ENDPOINT) \ - BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ - struct usb_gpio_config const NAME = { \ - .state = &((struct usb_gpio_state){}), \ - .endpoint = ENDPOINT, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .gpios = GPIO_LIST, \ - .num_gpios = ARRAY_SIZE(GPIO_LIST), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = 0, \ - .bInterfaceProtocol = 0, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_gpio_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_gpio_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_gpio_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)) - - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_gpio_tx(struct usb_gpio_config const *config); -void usb_gpio_rx(struct usb_gpio_config const *config); -void usb_gpio_event(struct usb_gpio_config const *config, - enum usb_ep_event evt); - -#endif /* __CROS_EC_USB_GPIO_H */ diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c deleted file mode 100644 index b8336fa0a0..0000000000 --- a/chip/stm32/usb_hid.c +++ /dev/null @@ -1,156 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -void hid_tx(int ep) -{ - /* clear IT */ - STM32_USB_EP(ep) = (STM32_USB_EP(ep) & EP_MASK); -} - -void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, - usb_uint *hid_ep_rx_buf, int rx_len) -{ - int i; - uint16_t ep_reg; - - btable_ep[ep].tx_addr = usb_sram_addr(hid_ep_tx_buf); - btable_ep[ep].tx_count = tx_len; - - /* STM32 USB SRAM needs to be accessed one U16 at a time */ - for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++) - hid_ep_tx_buf[i] = 0; - - ep_reg = (ep << 0) /* Endpoint Address */ | - EP_TX_VALID | - (3 << 9) /* interrupt EP */ | - EP_RX_DISAB; - - /* Enable RX for output reports */ - if (hid_ep_rx_buf && rx_len > 0) { - btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf); - btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10; - - ep_reg |= EP_RX_VALID; /* RX Valid */ - } - - STM32_USB_EP(ep) = ep_reg; -} - -/* - * Keep track of state in case we need to be called multiple times, - * if the report length is bigger than 64 bytes. - */ -static int report_left; -static const uint8_t *report_ptr; - -/* - * Send report through ep0_buf_tx. - * - * If report size is greater than USB packet size (64 bytes), rest of the - * reports will be saved in `report_ptr` and `report_left`, so we can call this - * function again to send the remain parts. - * - * @return 0 if entire report is sent, 1 if there are remaining data. - */ -static int send_report(usb_uint *ep0_buf_tx, - const uint8_t *report, - int report_size) -{ - int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE); - - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report, packet_size); - btable_ep[0].tx_count = packet_size; - /* report_left != 0 if report doesn't fit in 1 packet. */ - report_left = report_size - packet_size; - report_ptr = report + packet_size; - - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - report_left ? 0 : EP_STATUS_OUT); - - return report_left ? 1 : 0; -} - -int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, - const struct usb_hid_config_t *config) -{ - const uint8_t *report_desc = config->report_desc; - int report_size = config->report_size; - const struct usb_hid_descriptor *hid_desc = config->hid_desc; - - if (!ep0_buf_rx) { - /* - * Continue previous transfer. We ignore report_desc/size here, - * which is fine as only one GET_DESCRIPTOR command comes at a - * time. - */ - if (report_left == 0) - return -1; - report_size = MIN(USB_MAX_PACKET_SIZE, report_left); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report_ptr, report_size); - btable_ep[0].tx_count = report_size; - report_left -= report_size; - report_ptr += report_size; - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, - report_left ? 0 : EP_STATUS_OUT); - return report_left ? 1 : 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE | - (USB_REQ_GET_DESCRIPTOR << 8))) { - if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) { - /* Setup : HID specific : Get Report descriptor */ - return send_report(ep0_buf_tx, report_desc, - MIN(ep0_buf_rx[3], report_size)); - } else if (ep0_buf_rx[1] == (USB_HID_DT_HID << 8)) { - /* Setup : HID specific : Get HID descriptor */ - memcpy_to_usbram_ep0_patch(hid_desc, sizeof(*hid_desc)); - btable_ep[0].tx_count = sizeof(*hid_desc); - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT); - return 0; - } - } else if (ep0_buf_rx[0] == (USB_DIR_IN | - USB_RECIP_INTERFACE | - USB_TYPE_CLASS | - (USB_HID_REQ_GET_REPORT << 8))) { - const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF; - const uint8_t report_id = ep0_buf_rx[1] & 0xFF; - int retval; - - report_left = ep0_buf_rx[3]; - if (!config->get_report) /* not supported */ - return -1; - - retval = config->get_report(report_id, - report_type, - &report_ptr, - &report_left); - if (retval) - return retval; - - return send_report(ep0_buf_tx, report_ptr, report_left); - } - - return -1; -} diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h deleted file mode 100644 index a36a66567e..0000000000 --- a/chip/stm32/usb_hid_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * USB HID HW definitions, to be used by class drivers. - */ - -#ifndef __CROS_EC_USB_HID_HW_H -#define __CROS_EC_USB_HID_HW_H - -#include <common.h> - -struct usb_hid_config_t { - const uint8_t *report_desc; - int report_size; - const struct usb_hid_descriptor *hid_desc; - - /* - * Handle USB HID Get_Report request, can be NULL if not supported. - * - * @param report_id: ID of the report being requested - * @param report_type: 0x1 (INPUT) / 0x2 (OUTPUT) / 0x3 (FEATURE) - * @param buffer_ptr: handler should set it to the pointer of buffer to - * return. - * @param buffer_size: handler should set it to the size of returned - * buffer. - */ - int (*get_report)(uint8_t report_id, - uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size); -}; - -/* internal callbacks for HID class drivers */ -void hid_tx(int ep); -void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, - usb_uint *hid_ep_rx_buf, int rx_len); -int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, - const struct usb_hid_config_t *hid_config); - -#endif diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c deleted file mode 100644 index c6d6fb3292..0000000000 --- a/chip/stm32/usb_hid_keyboard.c +++ /dev/null @@ -1,665 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "keyboard_config.h" -#include "keyboard_protocol.h" -#include "link_defs.h" -#include "pwm.h" -#include "queue.h" -#include "registers.h" -#include "tablet_mode.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -static const int keyboard_debug; - -struct key_event { - uint32_t time; - uint8_t keycode; - uint8_t pressed; -}; - -static struct queue const key_queue = QUEUE_NULL(16, struct key_event); -static struct mutex key_queue_mutex; - -enum hid_protocol { - HID_BOOT_PROTOCOL = 0, - HID_REPORT_PROTOCOL = 1, - HID_PROTOCOL_COUNT = 2, -}; - -/* Current protocol, behaviour is identical in both modes. */ -static enum hid_protocol protocol = HID_REPORT_PROTOCOL; - -#if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \ - defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) -#define HID_KEYBOARD_EXTRA_FIELD -#endif - -/* - * Note: This first 8 bytes of this report format cannot be changed, as that - * would break HID Boot protocol compatibility (see HID 1.11 "Appendix B: Boot - * Interface Descriptors"). - */ -struct usb_hid_keyboard_report { - uint8_t modifiers; /* bitmap of modifiers 224-231 */ - uint8_t reserved; /* 0x0 */ - uint8_t keys[6]; - /* Non-boot protocol fields below */ -#ifdef HID_KEYBOARD_EXTRA_FIELD - /* Assistant/tablet mode switch bitmask */ - uint8_t extra; -#endif -} __packed; - -struct usb_hid_keyboard_output_report { - uint8_t brightness; -} __packed; - -#define HID_KEYBOARD_BOOT_SIZE 8 - -#define HID_KEYBOARD_REPORT_SIZE sizeof(struct usb_hid_keyboard_report) -#define HID_KEYBOARD_OUTPUT_REPORT_SIZE \ - sizeof(struct usb_hid_keyboard_output_report) - -#define HID_KEYBOARD_EP_INTERVAL_MS 16 /* ms */ - -/* - * Coalesce events happening within some interval. The value must be greater - * than EP interval to ensure we cannot have a backlog of keys. - * It must also be short enough to ensure that the intended order of key presses - * is passed to AP, and that we do not coalesce press and release events (which - * would result in lost keys). - */ -#define COALESCE_INTERVAL (18 * MSEC) - -/* - * Discard key events in the FIFO buffer that are older than this amount of - * time. Note that we do not fully drop them, we still update the report, - * but we do not send the events individually anymore (so an old key press - * and release will be dropped altogether, but a single press/release will - * still be reported correctly). - */ -#define KEY_DISCARD_MAX_TIME (1 * SECOND) - -/* Modifiers keycode range */ -#define HID_KEYBOARD_MODIFIER_LOW 0xe0 -#define HID_KEYBOARD_MODIFIER_HIGH 0xe7 - -/* Special keys/switches */ -#define HID_KEYBOARD_EXTRA_LOW 0xf0 -#define HID_KEYBOARD_ASSISTANT_KEY 0xf0 -#define HID_KEYBOARD_TABLET_MODE_SWITCH 0xf1 -#define HID_KEYBOARD_EXTRA_HIGH 0xf1 - -/* The standard Chrome OS keyboard matrix table. See HUT 1.12v2 Table 12 and - * https://www.w3.org/TR/DOM-Level-3-Events-code . - * - * Assistant key is mapped as 0xf0, but this key code is never actually send. - */ -const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00}, - {0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14}, - {0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08}, - {0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15}, - {0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a}, - {0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c}, - {0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18}, - {0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5}, - {0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13}, - {0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12}, - {0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00}, - {0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52}, - {0x00, 0x90, 0x00, 0x91, 0x00, 0x00, 0x4f, 0x50}, -}; - -/* HID descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_KEYBOARD) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_HID_KEYBOARD, - .bAlternateSetting = 0, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - .bNumEndpoints = 2, -#else - .bNumEndpoints = 1, -#endif - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT, - .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, - .iInterface = 0, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 81) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_KEYBOARD_REPORT_SIZE, - .bInterval = HID_KEYBOARD_EP_INTERVAL_MS /* ms polling interval */ -}; - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_HID_KEYBOARD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_KEYBOARD_OUTPUT_REPORT_SIZE, - .bInterval = HID_KEYBOARD_EP_INTERVAL_MS -}; -#endif - -#define KEYBOARD_BASE_DESC \ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ - 0x09, 0x06, /* Usage (Keyboard) */ \ - 0xA1, 0x01, /* Collection (Application) */ \ - \ - /* Modifiers */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ - 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x08, /* Report Count (8) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ - \ - /* Normal keys */ \ - 0x95, 0x06, /* Report Count (6) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0xa4, /* Logical Maximum (164) */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, 0x00, /* Usage Minimum (0) */ \ - 0x29, 0xa4, /* Usage Maximum (164) */ \ - 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ - -/* - * Vendor-defined Usage Page 0xffd1: - * - 0x18: Assistant key - * - 0x19: Tablet mode switch - */ -#ifdef HID_KEYBOARD_EXTRA_FIELD -#ifdef CONFIG_KEYBOARD_ASSISTANT_KEY -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x19, 0x18, /* Usage Minimum */ \ - 0x29, 0x18, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ -#else -/* No assistant key: just pad 1 bit. */ -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ -#endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */ - -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x19, 0x19, /* Usage Minimum */ \ - 0x29, 0x19, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ -#else -/* No tablet mode swtch: just pad 1 bit. */ -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ -#endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */ - -#define KEYBOARD_VENDOR_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ - \ - KEYBOARD_ASSISTANT_KEY_DESC \ - KEYBOARD_TABLET_MODE_SWITCH_DESC \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x06, /* Report Size (6) */ \ - 0x81, 0x01, /* Input (Constant), ;6-bit padding */ -#endif /* HID_KEYBOARD_EXTRA_FIELD */ - -#define KEYBOARD_BACKLIGHT_DESC \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ - 0x09, 0x46, /* Usage (Display Brightness) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x64, /* Logical Maximum (100) */ \ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ - 0xC0, /* End Collection */ - -/* - * To allow dynamic detection of keyboard backlights, we define two descriptors. - * One has keyboard backlight, and the other one does not. - */ - -/* HID : Report Descriptor */ -static const uint8_t report_desc[] = { - - KEYBOARD_BASE_DESC - -#ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC -#endif - - 0xC0 /* End Collection */ -}; - - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - -/* HID : Report Descriptor with keyboard backlight */ -static const uint8_t report_desc_with_backlight[] = { - - KEYBOARD_BASE_DESC - -#ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC -#endif - - KEYBOARD_BACKLIGHT_DESC - - 0xC0 /* End Collection */ -}; - -#endif - -/* HID: HID Descriptor */ -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, - hid, hid_desc_kb) = { - .bLength = 9, - .bDescriptorType = USB_HID_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0x00, /* Hardware target country */ - .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} -}; - -#define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2) - -static usb_uint hid_ep_tx_buf[EP_TX_BUF_SIZE] __usb_ram; -static volatile int hid_current_buf; - -static volatile int hid_ep_data_ready; - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -#define EP_RX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_OUTPUT_REPORT_SIZE, 2) -static usb_uint hid_ep_rx_buf[EP_RX_BUF_SIZE] __usb_ram; -#endif - -static struct usb_hid_keyboard_report report; - -static void keyboard_process_queue(void); -DECLARE_DEFERRED(keyboard_process_queue); - -static void write_keyboard_report(void) -{ - /* Tell the interrupt handler to send the next buffer. */ - hid_ep_data_ready = 1; - if ((STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == EP_TX_VALID) { - /* Endpoint is busy */ - return; - } - - if (atomic_read_clear(&hid_ep_data_ready)) { - /* - * Endpoint is not busy, and interrupt handler did not just - * send the buffer: enable TX. - */ - - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - } - - /* - * Wake the host. This is required to prevent a race between EP getting - * reloaded and host suspending the device, as, ideally, we never want - * to have EP loaded during suspend, to avoid reporting stale data. - */ - usb_wake(); -} - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - -static void hid_keyboard_rx(void) -{ - struct usb_hid_keyboard_output_report report; - memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf), - HID_KEYBOARD_OUTPUT_REPORT_SIZE); - - CPRINTF("Keyboard backlight set to %d%%\n", report.brightness); - - pwm_enable(PWM_CH_KBLIGHT, report.brightness > 0); - pwm_set_duty(PWM_CH_KBLIGHT, report.brightness); - - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); -} - -#endif - -static void hid_keyboard_tx(void) -{ - hid_tx(USB_EP_HID_KEYBOARD); - if (hid_ep_data_ready) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - hid_ep_data_ready = 0; - } - - if (queue_count(&key_queue) > 0) - hook_call_deferred(&keyboard_process_queue_data, 0); -} - -static void hid_keyboard_event(enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) { - protocol = HID_REPORT_PROTOCOL; - - hid_reset(USB_EP_HID_KEYBOARD, - hid_ep_tx_buf, - HID_KEYBOARD_REPORT_SIZE, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_ep_rx_buf, - HID_KEYBOARD_OUTPUT_REPORT_SIZE -#else - NULL, 0 -#endif - ); - - /* - * Reload endpoint on reset, to make sure we report accurate - * state to host (this is especially important for tablet mode - * switch). - */ - write_keyboard_report(); - return; - } - - if (evt == USB_EVENT_DEVICE_RESUME && queue_count(&key_queue) > 0) - hook_call_deferred(&keyboard_process_queue_data, 0); -} - -USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_keyboard_tx, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_keyboard_rx, -#else - hid_keyboard_tx, -#endif - hid_keyboard_event); - -static struct usb_hid_config_t hid_config_kb = { - .report_desc = report_desc, - .report_size = sizeof(report_desc), - .hid_desc = &hid_desc_kb, -}; - -static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - int ret; - - ret = hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_kb); - if (ret >= 0) - return ret; - - if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) { - uint16_t value = ep0_buf_rx[1]; - - if (value >= HID_PROTOCOL_COUNT) - return -1; - - protocol = value; - - /* Reload endpoint with appropriate tx_count. */ - btable_ep[USB_EP_HID_KEYBOARD].tx_count = - (protocol == HID_BOOT_PROTOCOL) ? - HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE; - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - return 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) { - uint8_t value = protocol; - - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &value, sizeof(value)); - btable_ep[0].tx_count = 1; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - return 0; - } - - return -1; -} -USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_keyboard_iface_request) - -void keyboard_clear_buffer(void) -{ - mutex_lock(&key_queue_mutex); - queue_init(&key_queue); - mutex_unlock(&key_queue_mutex); - - memset(&report, 0, sizeof(report)); -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH - if (tablet_get_mode()) - report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - - HID_KEYBOARD_EXTRA_LOW); -#endif - write_keyboard_report(); -} - -static void keyboard_process_queue(void) -{ - int i; - uint8_t mask; - struct key_event ev; - int valid = 0; - int trimming = 0; - uint32_t now = __hw_clock_source_read(); - uint32_t first_key_time; - - if (keyboard_debug) - CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue), - usb_is_suspended(), hid_ep_data_ready, - (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) - == EP_TX_VALID); - mutex_lock(&key_queue_mutex); - - if (queue_count(&key_queue) == 0) { - mutex_unlock(&key_queue_mutex); - return; - } - - if (usb_is_suspended() || hid_ep_data_ready) { - usb_wake(); - - if (!queue_is_full(&key_queue)) { - /* Queue still has space, let's keep gathering keys. */ - mutex_unlock(&key_queue_mutex); - return; - } - - /* - * Queue is full, so we continue, as the code below is - * guaranteed to pop at least one key from the queue, but we do - * not write the report at the end. - */ - CPRINTF("Trimming queue (%d %d %d)\n", queue_count(&key_queue), - usb_is_suspended(), hid_ep_data_ready); - - trimming = 1; - } - - /* There is at least one element in the queue. */ - queue_peek_units(&key_queue, &ev, 0, 1); - first_key_time = ev.time; - - /* - * Pick key events from the queue, coalescing events older than events - * within EP interval time to make sure the queue cannot grow, and - * dropping keys that are too old. - */ - while (queue_count(&key_queue) > 0) { - queue_peek_units(&key_queue, &ev, 0, 1); - if (keyboard_debug) - CPRINTF(" =%02x/%d %d %d\n", ev.keycode, ev.keycode, - ev.pressed, ev.time - now); - - if ((now - ev.time) <= KEY_DISCARD_MAX_TIME && - (ev.time - first_key_time) >= COALESCE_INTERVAL) - break; - - queue_advance_head(&key_queue, 1); - - if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW && - ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { -#ifdef HID_KEYBOARD_EXTRA_FIELD - mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW); - if (ev.pressed) - report.extra |= mask; - else - report.extra &= ~mask; - valid = 1; -#endif - } else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW && - ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { - mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW); - if (ev.pressed) - report.modifiers |= mask; - else - report.modifiers &= ~mask; - valid = 1; - } else if (ev.pressed) { - /* - * Add keycode to the list of keys (does nothing if the - * array is already full). - */ - for (i = 0; i < ARRAY_SIZE(report.keys); i++) { - /* Is key already pressed? */ - if (report.keys[i] == ev.keycode) - break; - if (report.keys[i] == 0) { - report.keys[i] = ev.keycode; - valid = 1; - break; - } - } - } else { - /* - * Remove keycode from the list of keys (does nothing - * if the key is not in the array). - */ - for (i = 0; i < ARRAY_SIZE(report.keys); i++) { - if (report.keys[i] == ev.keycode) { - report.keys[i] = 0; - valid = 1; - break; - } - } - } - } - - mutex_unlock(&key_queue_mutex); - - if (valid && !trimming) - write_keyboard_report(); -} - -static void queue_keycode_event(uint8_t keycode, int is_pressed) -{ - struct key_event ev = { - .time = __hw_clock_source_read(), - .keycode = keycode, - .pressed = is_pressed, - }; - - mutex_lock(&key_queue_mutex); - queue_add_unit(&key_queue, &ev); - mutex_unlock(&key_queue_mutex); - - keyboard_process_queue(); -} - -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#include "console.h" - -static void tablet_mode_change(void) -{ - queue_keycode_event(HID_KEYBOARD_TABLET_MODE_SWITCH, tablet_get_mode()); -} -DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT); -/* Run after tablet_mode_init. */ -DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1); -#endif - -void keyboard_state_changed(int row, int col, int is_pressed) -{ - uint8_t keycode = keycodes[col][row]; - - if (!keycode) { - CPRINTF("Unknown key at %d/%d\n", row, col); - return; - } - - queue_keycode_event(keycode, is_pressed); -} - -void clear_typematic_key(void) -{ } - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -void usb_hid_keyboard_init(void) -{ - if (board_has_keyboard_backlight()) { - hid_config_kb.report_desc = report_desc_with_backlight; - hid_config_kb.report_size = sizeof(report_desc_with_backlight); - - set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT, - &hid_desc_kb.desc[0].wDescriptorLength, - sizeof(report_desc_with_backlight)); - } -} -/* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */ -DECLARE_HOOK(HOOK_INIT, usb_hid_keyboard_init, HOOK_PRIO_DEFAULT - 1); -#endif diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c deleted file mode 100644 index 0ead660432..0000000000 --- a/chip/stm32/usb_hid_touchpad.c +++ /dev/null @@ -1,424 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "link_defs.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" -#include "usb_hid_touchpad.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -static const int touchpad_debug; - -static struct queue const report_queue = QUEUE_NULL(8, - struct usb_hid_touchpad_report); -static struct mutex report_queue_mutex; - -#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) - -/* - * Touchpad EP interval: Make sure this value is smaller than the typical - * interrupt interval from the trackpad. - */ -#define HID_TOUCHPAD_EP_INTERVAL_MS 2 /* ms */ - -/* Discard TP events older than this time */ -#define EVENT_DISCARD_MAX_TIME (1 * SECOND) - -/* HID descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_TOUCHPAD) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_HID_TOUCHPAD, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = 0, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_HID_TOUCHPAD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_TOUCHPAD_REPORT_SIZE, - .bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */ -}; - -#define FINGER_USAGE \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x22, /* Usage (Finger) */ \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x09, 0x47, /* Usage (Confidence) */ \ - 0x09, 0x42, /* Usage (Tip Switch) */ \ - 0x09, 0x32, /* Usage (In Range) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x03, /* Report Count (3) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ - 0x75, 0x04, /* Report Size (4) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x25, 0x0F, /* Logical Maximum (15) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - /* Logical Maximum of Pressure */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \ - 0x75, 0x09, /* Report Size (9) */ \ - 0x09, 0x30, /* Usage (Tip pressure) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x09, 0x48, /* Usage (WIDTH) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x49, /* Usage (HEIGHT) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x55, 0x0E, /* Unit Exponent (-2) */ \ - 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ - 0x09, 0x30, /* Usage (X) */ \ - 0x35, 0x00, /* Physical Minimum (0) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x09, 0x31, /* Usage (Y) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0xC0 /* End Collection */ - -/* - * HID: Report Descriptor - * TODO(b/35582031): There are ways to reduce flash usage, as the - * Finger Usage is repeated 5 times. - */ -static const uint8_t report_desc[] = { - /* Touchpad Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x05, /* Usage (Touch Pad) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ - /* Finger 0 */ - FINGER_USAGE, - /* Finger 1 */ - FINGER_USAGE, - /* Finger 2 */ - FINGER_USAGE, - /* Finger 3 */ - FINGER_USAGE, - /* Finger 4 */ - FINGER_USAGE, - /* Contact count */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x54, /* Usage (Contact count) */ - 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ - 0x75, 0x07, /* Report Size (7) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - /* Button */ - 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ - 0x05, 0x09, /* Usage (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x01, /* Usage Maximum (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - /* Timestamp */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x55, 0x0C, /* Unit Exponent (-4) */ - 0x66, 0x01, 0x10, /* Unit (Seconds) */ - 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ - 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ - 0x75, 0x10, /* Report Size (16) */ - 0x95, 0x01, /* Report Count (1) */ - 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - - 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ - 0x09, 0x55, /* Usage (Contact Count Maximum) */ - 0x09, 0x59, /* Usage (Pad Type) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - /* Page 0xFF, usage 0xC5 is device certificate. */ - 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ - 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ - 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ - 0x75, 0x08, /* Report Size (8) */ - 0x96, 0x00, 0x01, /* Report Count (256) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - 0xC0, /* End Collection */ -}; - -/* A 256-byte default blob for the 'device certification status' feature report. - * - * TODO(b/113248108): do we need a real certification? - */ -static const uint8_t device_cert_response[] = { - REPORT_ID_DEVICE_CERT, - - 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, - 0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88, - 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, - 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, - 0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43, - 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, - 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, - 0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71, - 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, - 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, - 0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9, - 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, - 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, - 0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B, - 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, - 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, - 0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1, - 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, - 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, - 0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35, - 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, - 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, - 0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF, - 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, - 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, - 0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13, - 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, - 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, - 0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89, - 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, - 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, - 0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2, -}; - -/* Device capabilities feature report. */ -static const uint8_t device_caps_response[] = { - REPORT_ID_DEVICE_CAPS, - - MAX_FINGERS, /* Contact Count Maximum */ - 0x00, /* Pad Type: Depressible click-pad */ -}; - -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, - hid, hid_desc_tp) = { - .bLength = 9, - .bDescriptorType = USB_HID_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0x00, /* Hardware target country */ - .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} -}; - -static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; - -/* - * Write a report to EP, must be called with queue mutex held, and caller - * must first check that EP is not busy. - */ -static void write_touchpad_report(struct usb_hid_touchpad_report *report) -{ - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf), - report, sizeof(*report)); - /* enable TX */ - STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0); - - /* - * Wake the host. This is required to prevent a race between EP getting - * reloaded and host suspending the device, as, ideally, we never want - * to have EP loaded during suspend, to avoid reporting stale data. - */ - usb_wake(); -} - -static void hid_touchpad_process_queue(void); -DECLARE_DEFERRED(hid_touchpad_process_queue); - -static void hid_touchpad_process_queue(void) -{ - struct usb_hid_touchpad_report report; - uint16_t now; - int trimming = 0; - - mutex_lock(&report_queue_mutex); - - /* EP is busy, or nothing in queue: do nothing. */ - if (queue_count(&report_queue) == 0) - goto unlock; - - now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT; - - if (usb_is_suspended() || - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) - == EP_TX_VALID) { - usb_wake(); - - /* Let's trim old events from the queue, if any. */ - trimming = 1; - } else { - hook_call_deferred(&hid_touchpad_process_queue_data, -1); - } - - if (touchpad_debug) - CPRINTS("TPQ t=%d (%d)", trimming, queue_count(&report_queue)); - - while (queue_count(&report_queue) > 0) { - int delta; - - queue_peek_units(&report_queue, &report, 0, 1); - - delta = (int)((uint16_t)(now - report.timestamp)) - * USB_HID_TOUCHPAD_TIMESTAMP_UNIT; - - if (touchpad_debug) - CPRINTS("evt t=%d d=%d", report.timestamp, delta); - - /* Drop old events */ - if (delta > EVENT_DISCARD_MAX_TIME) { - queue_advance_head(&report_queue, 1); - continue; - } - - if (trimming) { - /* - * If we stil fail to resume, this will discard the - * event after the timeout expires. - */ - hook_call_deferred(&hid_touchpad_process_queue_data, - EVENT_DISCARD_MAX_TIME - delta); - } else { - queue_advance_head(&report_queue, 1); - write_touchpad_report(&report); - } - break; - } - -unlock: - mutex_unlock(&report_queue_mutex); -} - -void set_touchpad_report(struct usb_hid_touchpad_report *report) -{ - static int print_full = 1; - - mutex_lock(&report_queue_mutex); - - /* USB/EP ready and nothing in queue, just write the report. */ - if (!usb_is_suspended() && - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID - && queue_count(&report_queue) == 0) { - write_touchpad_report(report); - mutex_unlock(&report_queue_mutex); - return; - } - - /* Else add to queue, dropping oldest event if needed. */ - if (touchpad_debug) - CPRINTS("sTP t=%d", report->timestamp); - if (queue_is_full(&report_queue)) { - if (print_full) - CPRINTF("TP queue full\n"); - print_full = 0; - - queue_advance_head(&report_queue, 1); - } else { - print_full = 1; - } - queue_add_unit(&report_queue, report); - - mutex_unlock(&report_queue_mutex); - - hid_touchpad_process_queue(); -} - -static void hid_touchpad_tx(void) -{ - hid_tx(USB_EP_HID_TOUCHPAD); - - if (queue_count(&report_queue) > 0) - hook_call_deferred(&hid_touchpad_process_queue_data, 0); -} - -static void hid_touchpad_event(enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) - hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf, - HID_TOUCHPAD_REPORT_SIZE, NULL, 0); - else if (evt == USB_EVENT_DEVICE_RESUME && - queue_count(&report_queue) > 0) - hook_call_deferred(&hid_touchpad_process_queue_data, 0); -} - -USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx, - hid_touchpad_event); - -static int get_report(uint8_t report_id, uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size) -{ - switch (report_id) { - case REPORT_ID_DEVICE_CAPS: - *buffer_ptr = device_caps_response; - *buffer_size = MIN(sizeof(device_caps_response), *buffer_size); - return 0; - case REPORT_ID_DEVICE_CERT: - *buffer_ptr = device_cert_response; - *buffer_size = MIN(sizeof(device_cert_response), *buffer_size); - return 0; - } - return -1; -} - -static const struct usb_hid_config_t hid_config_tp = { - .report_desc = report_desc, - .report_size = sizeof(report_desc), - .hid_desc = &hid_desc_tp, - .get_report = get_report, -}; - -static int hid_touchpad_iface_request(usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - return hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_tp); -} -USB_DECLARE_IFACE(USB_IFACE_HID_TOUCHPAD, hid_touchpad_iface_request) diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h deleted file mode 100644 index be2a88661e..0000000000 --- a/chip/stm32/usb_hw.h +++ /dev/null @@ -1,139 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_HW_H -#define __CROS_EC_USB_HW_H - -#include <stddef.h> -#include <stdint.h> - -/* Event types for the endpoint event handler. */ -enum usb_ep_event { - USB_EVENT_RESET, - USB_EVENT_DEVICE_RESUME, /* Device-initiated wake completed. */ -}; - -#if defined(CHIP_FAMILY_STM32F4) -#include "usb_dwc_hw.h" -#else - - -/* - * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads & - * writes are 16-bits wide). The endpoint tables and the data buffers live in - * this RAM. -*/ - -/* Primitive to access the words in USB RAM */ -typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint; -/* Linker symbol for start of USB RAM */ -extern usb_uint __usb_ram_start[]; - -/* Attribute to define a buffer variable in USB RAM */ -#define __usb_ram __attribute__((section(".usb_ram.99_data"))) - -struct stm32_endpoint { - volatile usb_uint tx_addr; - volatile usb_uint tx_count; - volatile usb_uint rx_addr; - volatile usb_uint rx_count; -}; - -extern struct stm32_endpoint btable_ep[]; - -/* Attribute to put the endpoint table in USB RAM */ -#define __usb_btable __attribute__((section(".usb_ram.00_btable"))) - -/* Read from USB RAM into a usb_setup_packet struct */ -struct usb_setup_packet; -void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet); - -/* - * Copy data to and from the USB dedicated RAM and take care of the weird - * addressing. These functions correctly handle unaligned accesses to the USB - * memory. They have the same prototype as memcpy, allowing them to be used - * in places that expect memcpy. The void pointer used to represent a location - * in the USB dedicated RAM should be the offset in that address space, not the - * AHB address space. - * - * The USB packet RAM is attached to the processor via the AHB2APB bridge. This - * bridge performs manipulations of read and write accesses as per the note in - * section 2.1 of RM0091. The upshot is that custom memcpy-like routines need - * to be employed. - */ -void *memcpy_to_usbram(void *dest, const void *src, size_t n); -void *memcpy_from_usbram(void *dest, const void *src, size_t n); - -/* - * Descriptor patching support, useful to change a few values in the descriptor - * (typically, length or bitfields) without having to move descriptors to RAM. - */ - -enum usb_desc_patch_type { -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - USB_DESC_KEYBOARD_BACKLIGHT, -#endif - USB_DESC_PATCH_COUNT, -}; - -/* - * Set patch in table: replace uint16_t at address (STM32 flash) with data. - * - * The patches need to be setup before _before_ usb_init is executed (or, at - * least, before the first call to memcpy_to_usbram_ep0_patch). - */ -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data); - -/* Copy to USB ram, applying patches to src as required. */ -void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); - -/* Compute the address inside dedicate SRAM for the USB controller */ -#define usb_sram_addr(x) ((x - __usb_ram_start) * sizeof(uint16_t)) - -/* Helpers for endpoint declaration */ -#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix) -#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx) -#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx) -#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt) -/* Used to check function types are correct (attribute alias does not do it) */ -#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck) -#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) -#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) - -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler - -/* arrays with all endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); -/* array with interface-specific control request callbacks */ -extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); - -/* - * Interface handler returns -1 on error, 0 if it wrote the last chunk of data, - * or 1 if more data needs to be transferred on the next control request. - */ -#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx, \ - usb_uint *epo_buf_tx) \ - __attribute__ ((alias(STRINGIFY(handler)))); - -#endif -#endif /* __CROS_EC_USB_HW_H */ diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c deleted file mode 100644 index 792507aa75..0000000000 --- a/chip/stm32/usb_isochronous.c +++ /dev/null @@ -1,163 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "stddef.h" -#include "common.h" -#include "config.h" -#include "link_defs.h" -#include "registers.h" -#include "util.h" -#include "usb_api.h" -#include "usb_hw.h" -#include "usb_isochronous.h" - - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -/* - * Currently, we only support TX direction for USB isochronous transfer. - * - * According to RM0091, isochronous transfer is always double buffered. - * Addresses of buffers are pointed by `btable_ep[<endpoint>].tx_addr` and - * `btable_ep[<endpoint>].rx_addr`. - * - * DTOG | USB Buffer | App Buffer - * -----+------------+----------- - * 0 | tx_addr | rx_addr - * 1 | rx_addr | tx_addr - * - * That is, when DTOG bit is 0 (see `get_tx_dtog()`), USB hardware will read - * from `tx_addr`, and our application can write new data to `rx_addr` at the - * same time. - * - * Number of bytes in each buffer shall be tracked by `tx_count` and `rx_count` - * respectively. - * - * `get_app_addr()`, `set_app_count()` help you to to select the correct - * variable to use by given DTOG value, which is available by `get_tx_dtog()`. - */ - -/* - * Gets current DTOG value of given `config`. - */ -static int get_tx_dtog(struct usb_isochronous_config const *config) -{ - return !!(STM32_USB_EP(config->endpoint) & EP_TX_DTOG); -} - -/* - * Gets buffer address that can be used by software (application). - * - * The mapping between application buffer address and current TX DTOG value is - * shown in table above. - */ -static usb_uint *get_app_addr(struct usb_isochronous_config const *config, - int dtog_value) -{ - return config->tx_ram[dtog_value]; -} - -/* - * Sets number of bytes written to application buffer. - */ -static void set_app_count(struct usb_isochronous_config const *config, - int dtog_value, - usb_uint count) -{ - if (dtog_value) - btable_ep[config->endpoint].tx_count = count; - else - btable_ep[config->endpoint].rx_count = count; -} - -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit) -{ - int dtog_value = get_tx_dtog(config); - usb_uint *buffer = get_app_addr(config, dtog_value); - uintptr_t ptr = usb_sram_addr(buffer); - - if (*buffer_id == -1) - *buffer_id = dtog_value; - else if (dtog_value != *buffer_id) - return -EC_ERROR_TIMEOUT; - - if (dst_offset > config->tx_size) - return -EC_ERROR_INVAL; - - n = MIN(n, config->tx_size - dst_offset); - memcpy_to_usbram((void *)(ptr + dst_offset), src, n); - - if (commit) - set_app_count(config, dtog_value, dst_offset + n); - - return n; -} - -void usb_isochronous_init(struct usb_isochronous_config const *config) -{ - int ep = config->endpoint; - - btable_ep[ep].tx_addr = usb_sram_addr(get_app_addr(config, 1)); - btable_ep[ep].rx_addr = usb_sram_addr(get_app_addr(config, 0)); - set_app_count(config, 0, 0); - set_app_count(config, 1, 0); - - STM32_USB_EP(ep) = ((ep << 0) | /* Endpoint Addr */ - EP_TX_VALID | /* start transmit */ - (2 << 9) | /* ISO EP */ - EP_RX_DISAB); -} - -void usb_isochronous_event(struct usb_isochronous_config const *config, - enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) - usb_isochronous_init(config); -} - -void usb_isochronous_tx(struct usb_isochronous_config const *config) -{ - /* - * Clear CTR_TX, note that EP_TX_VALID will *NOT* be cleared by - * hardware, so we don't need to toggle it. - */ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - /* - * Clear buffer count for buffer we just transmitted, so we do not - * transmit the data twice. - */ - set_app_count(config, get_tx_dtog(config), 0); - - config->tx_callback(config); -} - -int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - int ret = -1; - - if (ep0_buf_rx[0] == (USB_DIR_OUT | - USB_TYPE_STANDARD | - USB_RECIP_INTERFACE | - USB_REQ_SET_INTERFACE << 8)) { - ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]); - - if (ret == 0) { - /* ACK */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - } - } - return ret; -} diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h deleted file mode 100644 index efa4d94ab4..0000000000 --- a/chip/stm32/usb_isochronous.h +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_ISOCHRONOUS_H -#define __CROS_EC_USB_ISOCHRONOUS_H - -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -struct usb_isochronous_config; - -/* - * Currently, we only support TX direction for USB isochronous transfer. - */ - -/* - * Copy `n` bytes from `src` to USB buffer. - * - * We are using double buffering, therefore, we need to write to the buffer that - * hardware is not currently using. This function will handle this for you. - * - * Sample usage: - * - * int buffer_id = -1; // initialize to unknown - * int ret; - * size_t dst_offset = 0, src_offset = 0; - * const uint8_t* buf; - * size_t buf_size; - * - * while (1) { - * buf = ...; - * buf_size = ...; - * if (no more data) { - * buf = NULL; - * break; - * } else { - * ret = usb_isochronous_write_buffer( - * config, buf, buf_size, dst_offset, - * &buffer_id, - * 0); - * if (ret < 0) - * goto FAILED; - * dst_offset += ret; - * if (ret != buf_size) { - * // no more space in TX buffer - * src_offset = ret; - * break; - * } - * } - * } - * // commit - * ret = usb_isochronous_write_buffer( - * config, NULL, 0, dst_offset, - * &buffer_id, 1); - * if (ret < 0) - * goto FAILED; - * if (buf) - * // buf[src_offset ... buf_size] haven't been sent yet, send them - * // later. - * - * On the first invocation, on success, `ret` will be number of bytes that have - * been written, and `buffer_id` will be 0 or 1, depending on which buffer we - * are writing. And commit=0 means there are pending data, so buffer count - * won't be set yet. - * - * On the second invocation, since buffer_id is not -1, we will return an error - * if hardware has switched to this buffer (it means we spent too much time - * filling buffer). And commit=1 means we are done, and buffer count will be - * set to `dst_offset + num_bytes_written` on success. - * - * @return -EC_ERROR_CODE on failure, or number of bytes written on success. - */ -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit); - -struct usb_isochronous_config { - int endpoint; - - /* - * On TX complete, this function will be called in **interrupt - * context**. - * - * @param config the usb_isochronous_config of the USB interface. - */ - void (*tx_callback)(struct usb_isochronous_config const *config); - - /* - * Received SET_INTERFACE request. - * - * @param alternate_setting new bAlternateSetting value. - * @param interface interface number. - * @return int 0 for success, -1 for unknown setting. - */ - int (*set_interface)(usb_uint alternate_setting, usb_uint interface); - - /* USB packet RAM buffer size. */ - size_t tx_size; - /* USB packet RAM buffers. */ - usb_uint *tx_ram[2]; -}; - -/* Define an USB isochronous interface */ -#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - TX_SIZE, \ - TX_CALLBACK, \ - SET_INTERFACE, \ - NUM_EXTRA_ENDPOINTS) \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - /* Declare buffer */ \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \ - struct usb_isochronous_config const NAME = { \ - .endpoint = ENDPOINT, \ - .tx_callback = TX_CALLBACK, \ - .set_interface = SET_INTERFACE, \ - .tx_size = TX_SIZE, \ - .tx_ram = { \ - CONCAT2(NAME, _ep_tx_buffer_0), \ - CONCAT2(NAME, _ep_tx_buffer_1), \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 0, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_interface_descriptor \ - USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 1, \ - .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x01 /* Isochronous IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 1, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_isochronous_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_isochronous_event(&NAME, evt); \ - } \ - static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx) \ - { \ - return usb_isochronous_iface_handler(&NAME, rx, tx); \ - } \ - USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_event)); \ - -void usb_isochronous_tx(struct usb_isochronous_config const *config); -void usb_isochronous_event(struct usb_isochronous_config const *config, - enum usb_ep_event event); -int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx); -#endif /* __CROS_EC_USB_ISOCHRONOUS_H */ diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c deleted file mode 100644 index 426cac15d3..0000000000 --- a/chip/stm32/usb_pd_phy.c +++ /dev/null @@ -1,680 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "crc.h" -#include "dma.h" -#include "gpio.h" -#include "hwtimer.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_pd.h" -#include "usb_pd_config.h" - -#ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#else -#define CPRINTF(format, args...) -#define CPRINTS(format, args...) -#endif - -#define PD_DATARATE 300000 /* Hz */ - -/* - * Maximum size of a Power Delivery packet (in bits on the wire) : - * 16-bit header + 0..7 32-bit data objects (+ 4b5b encoding) - * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b) - * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5 - */ -#define PD_BIT_LEN 429 - -#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2) - -/* maximum number of consecutive similar bits with Biphase Mark Coding */ -#define MAX_BITS 2 - -/* alternating bit sequence used for packet preamble : 00 10 11 01 00 .. */ -#define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */ - -#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE))) - -/* threshold for 1 300-khz period */ -#define PERIOD 4 -#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD) -#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2) - -static struct pd_physical { - /* samples for the PD messages */ - uint32_t raw_samples[DIV_ROUND_UP(PD_MAX_RAW_SIZE, sizeof(uint32_t))]; - - /* state of the bit decoder */ - int d_toggle; - int d_lastlen; - uint32_t d_last; - int b_toggle; - - /* DMA structures for each PD port */ - struct dma_option dma_tx_option; - struct dma_option dma_tim_option; - - /* Pointers to timer register for each port */ - timer_ctlr_t *tim_tx; - timer_ctlr_t *tim_rx; -} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT]; - -/* keep track of RX edge timing in order to trigger receive */ -static timestamp_t - rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT]; -static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT]; - -/* keep track of transmit polarity for DMA interrupt */ -static int tx_dma_polarities[CONFIG_USB_PD_PORT_MAX_COUNT]; - -void pd_init_dequeue(int port) -{ - /* preamble ends with 1 */ - pd_phy[port].d_toggle = 0; - pd_phy[port].d_last = 0; - pd_phy[port].d_lastlen = 0; -} - -static int wait_bits(int port, int nb) -{ - int avail; - stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port)); - - avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE); - if (avail < nb) { /* no received yet ... */ - while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) - && !(pd_phy[port].tim_rx->sr & 4)) - ; /* optimized for latency, not CPU usage ... */ - if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) { - CPRINTS("PD TMOUT RX %d/%d", - dma_bytes_done(rx, PD_MAX_RAW_SIZE), nb); - return -1; - } - } - return nb; -} - -int pd_dequeue_bits(int port, int off, int len, uint32_t *val) -{ - int w; - uint8_t cnt = 0xff; - uint8_t *samples = (uint8_t *)pd_phy[port].raw_samples; - - while ((pd_phy[port].d_lastlen < len) && (off < PD_MAX_RAW_SIZE - 1)) { - w = wait_bits(port, off + 2); - if (w < 0) - goto stream_err; - cnt = samples[off] - samples[off-1]; - if (!cnt || (cnt > 3*PERIOD)) - goto stream_err; - off++; - if (cnt <= PERIOD_THRESHOLD) { - /* - w = wait_bits(port, off + 1); - if (w < 0) - goto stream_err; - */ - cnt = samples[off] - samples[off-1]; - if (cnt > PERIOD_THRESHOLD) - goto stream_err; - off++; - } - - /* enqueue the bit of the last period */ - pd_phy[port].d_last = (pd_phy[port].d_last >> 1) - | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); - pd_phy[port].d_lastlen++; - } - if (off < PD_MAX_RAW_SIZE) { - *val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len)) - >> (32 - len); - pd_phy[port].d_lastlen -= len; - return off; - } else { - return -1; - } -stream_err: - /* CPRINTS("PD Invalid %d @%d", cnt, off); */ - return -1; -} - -int pd_find_preamble(int port) -{ - int bit; - uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples; - - /* - * Detect preamble - * Alternate 1-period 1-period & 2-period. - */ - uint32_t all = 0; - stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port)); - - for (bit = 1; bit < PD_MAX_RAW_SIZE - 1; bit++) { - uint8_t cnt; - /* wait if the bit is not received yet ... */ - if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) { - while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) && - !(pd_phy[port].tim_rx->sr & 4)) - ; - if (pd_phy[port].tim_rx->sr & 4) { - CPRINTS("PD TMOUT RX %d/%d", - PD_MAX_RAW_SIZE - rx->cndtr, bit); - return -1; - } - } - cnt = vals[bit] - vals[bit-1]; - all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); - if (all == 0x36db6db6) - return bit - 1; /* should be SYNC-1 */ - if (all == 0xF33F3F3F) - return PD_RX_ERR_HARD_RESET; /* got HARD-RESET */ - if (all == 0x3c7fe0ff) - return PD_RX_ERR_CABLE_RESET; /* got CABLE-RESET */ - } - return -1; -} - -int pd_write_preamble(int port) -{ - uint32_t *msg = pd_phy[port].raw_samples; - - /* 64-bit x2 preamble */ - msg[0] = PD_PREAMBLE; - msg[1] = PD_PREAMBLE; - msg[2] = PD_PREAMBLE; - msg[3] = PD_PREAMBLE; - pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */ - return 2*64; -} - -int pd_write_sym(int port, int bit_off, uint32_t val10) -{ - uint32_t *msg = pd_phy[port].raw_samples; - int word_idx = bit_off / 32; - int bit_idx = bit_off % 32; - uint32_t val = pd_phy[port].b_toggle ^ val10; - pd_phy[port].b_toggle = val & 0x200 ? 0x3FF : 0; - if (bit_idx <= 22) { - if (bit_idx == 0) - msg[word_idx] = 0; - msg[word_idx] |= val << bit_idx; - } else { - msg[word_idx] |= val << bit_idx; - msg[word_idx+1] = val >> (32 - bit_idx); - /* side effect: clear the new word when starting it */ - } - return bit_off + 5*2; -} - -int pd_write_last_edge(int port, int bit_off) -{ - uint32_t *msg = pd_phy[port].raw_samples; - int word_idx = bit_off / 32; - int bit_idx = bit_off % 32; - - if (bit_idx == 0) - msg[word_idx] = 0; - - if (!pd_phy[port].b_toggle /* last bit was 0 */) { - /* transition to 1, another 1, then 0 */ - if (bit_idx == 31) { - msg[word_idx++] |= 1 << bit_idx; - msg[word_idx] = 1; - } else { - msg[word_idx] |= 3 << bit_idx; - } - } - /* ensure that the trailer is 0 */ - msg[word_idx+1] = 0; - - return bit_off + 3; -} - -#ifdef CONFIG_COMMON_RUNTIME -void pd_dump_packet(int port, const char *msg) -{ - uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples; - int bit; - - CPRINTF("ERR %s:\n000:- ", msg); - /* Packet debug output */ - for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { - int cnt = NB_PERIOD(vals[bit-1], vals[bit]); - if ((bit & 31) == 0) - CPRINTF("\n%03d:", bit); - CPRINTF("%1d ", cnt); - } - CPRINTF("><\n"); - cflush(); - for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { - if ((bit & 31) == 0) - CPRINTF("\n%03d:", bit); - CPRINTF("%02x ", vals[bit]); - } - CPRINTF("||\n"); - cflush(); -} -#endif /* CONFIG_COMMON_RUNTIME */ - -/* --- SPI TX operation --- */ - -void pd_tx_spi_init(int port) -{ - stm32_spi_regs_t *spi = SPI_REGS(port); - - /* Enable Tx DMA for our first transaction */ - spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8); - - /* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */ - spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST - | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE - | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; -} - -static void tx_dma_done(void *data) -{ - int port = (int)data; - int polarity = tx_dma_polarities[port]; - stm32_spi_regs_t *spi = SPI_REGS(port); - - while (spi->sr & STM32_SPI_SR_FTLVL) - ; /* wait for TX FIFO empty */ - while (spi->sr & STM32_SPI_SR_BSY) - ; /* wait for BSY == 0 */ - - /* Stop counting */ - pd_phy[port].tim_tx->cr1 &= ~1; - - /* put TX pins and reference in Hi-Z */ - pd_tx_disable(port, polarity); - -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC, 0); -#endif -} - -int pd_start_tx(int port, int polarity, int bit_len) -{ - stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX(port)); - -#ifndef CONFIG_USB_PD_TX_PHY_ONLY - /* disable RX detection interrupt */ - pd_rx_disable_monitoring(port); - - /* Check that we are not receiving a frame to avoid collisions */ - if (pd_rx_started(port)) - return -5; -#endif /* !CONFIG_USB_PD_TX_PHY_ONLY */ - - /* Initialize spi peripheral to prepare for transmission. */ - pd_tx_spi_init(port); - - /* - * Set timer to one tick before reset so that the first tick causes - * a rising edge on the output. - */ - pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1; - - /* update DMA configuration */ - dma_prepare_tx(&(pd_phy[port].dma_tx_option), - DIV_ROUND_UP(bit_len, 8), - pd_phy[port].raw_samples); - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dmb;"); - - /* Kick off the DMA to send the data */ - dma_clear_isr(DMAC_SPI_TX(port)); -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - tx_dma_polarities[port] = polarity; - if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) { - /* Only enable interrupt if not in circular mode */ - dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port), - &tx_dma_done, - (void *)port); - } -#endif - dma_go(tx); - - /* - * Drive the CC line from the TX block : - * - put SPI function on TX pin. - * - set the low level reference. - * Call this last before enabling timer in order to meet spec on - * timing between enabling TX and clocking out bits. - */ - pd_tx_enable(port, polarity); - - /* Start counting at 300Khz*/ - pd_phy[port].tim_tx->cr1 |= 1; - - return bit_len; -} - -void pd_tx_done(int port, int polarity) -{ -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - /* wait for DMA, DMA interrupt will stop the SPI clock */ - task_wait_event_mask(TASK_EVENT_DMA_TC, DMA_TRANSFER_TIMEOUT_US); - dma_disable_tc_interrupt(DMAC_SPI_TX(port)); -#else - tx_dma_polarities[port] = polarity; - tx_dma_done((void *)port); -#endif - - /* Reset SPI to clear remaining data in buffer */ - pd_tx_spi_reset(port); -} - -void pd_tx_set_circular_mode(int port) -{ - pd_phy[port].dma_tx_option.flags |= STM32_DMA_CCR_CIRC; -} - -void pd_tx_clear_circular_mode(int port) -{ - /* clear the circular mode bit in flag variable */ - pd_phy[port].dma_tx_option.flags &= ~STM32_DMA_CCR_CIRC; - /* disable dma transaction underway */ - dma_disable(DMAC_SPI_TX(port)); -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - tx_dma_done((void *)port); -#endif -} - -/* --- RX operation using comparator linked to timer --- */ - -void pd_rx_start(int port) -{ - /* start sampling the edges on the CC line using the RX timer */ - dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE, - pd_phy[port].raw_samples); - /* enable TIM2 DMA requests */ - pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */; - pd_phy[port].tim_rx->sr = 0; /* clear overflows */ - pd_phy[port].tim_rx->cr1 |= 1; -} - -void pd_rx_complete(int port) -{ - /* stop stampling TIM2 */ - pd_phy[port].tim_rx->cr1 &= ~1; - /* stop DMA */ - dma_disable(DMAC_TIM_RX(port)); -} - -int pd_rx_started(int port) -{ - /* is the sampling timer running ? */ - return pd_phy[port].tim_rx->cr1 & 1; -} - -void pd_rx_enable_monitoring(int port) -{ - /* clear comparator external interrupt */ - STM32_EXTI_PR = EXTI_COMP_MASK(port); - /* enable comparator external interrupt */ - STM32_EXTI_IMR |= EXTI_COMP_MASK(port); -} - -void pd_rx_disable_monitoring(int port) -{ - /* disable comparator external interrupt */ - STM32_EXTI_IMR &= ~EXTI_COMP_MASK(port); - /* clear comparator external interrupt */ - STM32_EXTI_PR = EXTI_COMP_MASK(port); -} - -uint64_t get_time_since_last_edge(int port) -{ - int prev_idx = (rx_edge_ts_idx[port] == 0) ? - PD_RX_TRANSITION_COUNT - 1 : - rx_edge_ts_idx[port] - 1; - return get_time().val - rx_edge_ts[port][prev_idx].val; -} - -/* detect an edge on the PD RX pin */ -void pd_rx_handler(void) -{ - int pending, i; - int next_idx; - pending = STM32_EXTI_PR; - -#ifdef CONFIG_USB_TYPEC_CTVPD - /* Charge-Through Side detach event */ - if (pending & EXTI_COMP2_MASK) { - task_set_event(PD_PORT_TO_TASK_ID(0), PD_EVENT_SM, 0); - /* Clear interrupt */ - STM32_EXTI_PR = EXTI_COMP2_MASK; - pending &= ~EXTI_COMP2_MASK; - } -#endif - - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (pending & EXTI_COMP_MASK(i)) { - rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val; - next_idx = (rx_edge_ts_idx[i] == - PD_RX_TRANSITION_COUNT - 1) ? - 0 : rx_edge_ts_idx[i] + 1; - -#if defined(CONFIG_LOW_POWER_IDLE) && \ -defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) - /* - * Do not deep sleep while waiting for more edges. For - * most boards, sleep is already disabled due to being - * in PD connected state, but boards which define - * CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED can - * sleep while connected. - */ - disable_sleep(SLEEP_MASK_USB_PD); -#endif - - /* - * If we have seen enough edges in a certain amount of - * time, then trigger RX start. - */ - if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val - - rx_edge_ts[i][next_idx].val) - < PD_RX_TRANSITION_WINDOW) { - /* start sampling */ - pd_rx_start(i); - /* - * ignore the comparator IRQ until we are done - * with current message - */ - pd_rx_disable_monitoring(i); - /* trigger the analysis in the task */ - pd_rx_event(i); - } else { - /* do not trigger RX start, just clear int */ - STM32_EXTI_PR = EXTI_COMP_MASK(i); - } - rx_edge_ts_idx[i] = next_idx; - } - } -} -#ifdef CONFIG_USB_PD_RX_COMP_IRQ -DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1); -#endif - -/* --- release hardware --- */ -void pd_hw_release(int port) -{ - __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 0); - __hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 0); - dma_disable(DMAC_SPI_TX(port)); -} - -/* --- Startup initialization --- */ - -void pd_hw_init_rx(int port) -{ - struct pd_physical *phy = &pd_phy[port]; - - /* configure registers used for timers */ - phy->tim_rx = (void *)TIM_REG_RX(port); - - /* configure RX DMA */ - phy->dma_tim_option.channel = DMAC_TIM_RX(port); - phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port)); - phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_16_BIT; - - /* --- set counter for RX timing : 2.4Mhz rate, free-running --- */ - __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1); - /* Timer configuration */ - phy->tim_rx->cr1 = 0x0000; - phy->tim_rx->cr2 = 0x0000; - phy->tim_rx->dier = 0x0000; - /* Auto-reload value : 16-bit free running counter */ - phy->tim_rx->arr = 0xFFFF; - - /* Timeout for message receive */ - phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000; - /* Timer ICx input configuration */ - if (TIM_RX_CCR_IDX(port) == 1) - phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0; - else if (TIM_RX_CCR_IDX(port) == 2) - phy->tim_rx->ccmr1 |= TIM_CCR_CS << 8; - else if (TIM_RX_CCR_IDX(port) == 4) - phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8; - else - /* Unsupported RX timer capture input */ - ASSERT(0); - - phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4); - /* configure DMA request on CCRx update */ - phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */; - /* set prescaler to /26 (F=1.2Mhz, T=0.8us) */ - phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1; - /* Reload the pre-scaler and reset the counter (clear CCRx) */ - phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port)); - /* clear update event from reloading */ - phy->tim_rx->sr = 0; - - /* --- DAC configuration for comparator at 850mV --- */ -#ifdef CONFIG_PD_USE_DAC_AS_REF - /* Enable DAC interface clock. */ - STM32_RCC_APB1ENR |= BIT(29); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* set voltage Vout=0.850V (Vref = 3.0V) */ - STM32_DAC_DHR12RD = 850 * 4096 / 3000; - /* Start DAC channel 1 */ - STM32_DAC_CR = STM32_DAC_CR_EN1; -#endif - - /* --- COMP2 as comparator for RX vs Vmid = 850mV --- */ -#ifdef CONFIG_USB_PD_INTERNAL_COMP -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* turn on COMP/SYSCFG */ - STM32_RCC_APB2ENR |= BIT(0); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ - STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED | - STM32_COMP_CMP1INSEL_INM6 | - CMP1OUTSEL | - STM32_COMP_CMP1HYST_HI | - STM32_COMP_CMP2MODE_LSPEED | - STM32_COMP_CMP2INSEL_INM6 | - CMP2OUTSEL | - STM32_COMP_CMP2HYST_HI; -#elif defined(CHIP_FAMILY_STM32L) - STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ - - STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 - | STM32_COMP_SPEED_FAST; - /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ - STM32_RI_ASCR2 |= BIT(4); -#else -#error Unsupported chip family -#endif -#endif /* CONFIG_USB_PD_INTERNAL_COMP */ - - /* comparator interrupt setup */ - EXTI_XTSR |= EXTI_COMP_MASK(port); - STM32_EXTI_IMR |= EXTI_COMP_MASK(port); - task_enable_irq(IRQ_COMP); -} - -void pd_hw_init(int port, int role) -{ - struct pd_physical *phy = &pd_phy[port]; - uint32_t val; - - /* Initialize all PD pins to default state based on desired role */ - pd_config_init(port, role); - - /* set 40 MHz pin speed on communication pins */ - pd_set_pins_speed(port); - - /* --- SPI init --- */ - - /* Enable clocks to SPI module */ - spi_enable_clock(port); - - /* Initialize SPI peripheral registers */ - pd_tx_spi_init(port); - - /* configure TX DMA */ - phy->dma_tx_option.channel = DMAC_SPI_TX(port); - phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr; - phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT; - dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE, - phy->raw_samples); - - /* configure registers used for timers */ - phy->tim_tx = (void *)TIM_REG_TX(port); - - /* --- set the TX timer with updates at 600KHz (BMC frequency) --- */ - __hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 1); - /* Timer configuration */ - phy->tim_tx->cr1 = 0x0000; - phy->tim_tx->cr2 = 0x0000; - phy->tim_tx->dier = 0x0000; - /* Auto-reload value : 600000 Khz overflow */ - phy->tim_tx->arr = TX_CLOCK_DIV; - /* 50% duty cycle on the output */ - phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2; - /* Timer channel output configuration */ - val = (6 << 4) | BIT(3); - if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */ - val <<= 8; - if (TIM_TX_CCR_IDX(port) <= 2) - phy->tim_tx->ccmr1 = val; - else - phy->tim_tx->ccmr2 = val; - - phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4); - phy->tim_tx->bdtr = 0x8000; - /* set prescaler to /1 */ - phy->tim_tx->psc = 0; - /* Reload the pre-scaler and reset the counter */ - phy->tim_tx->egr = 0x0001; -#ifndef CONFIG_USB_PD_TX_PHY_ONLY - /* Configure the reception side : comparators + edge timer + DMA */ - pd_hw_init_rx(port); -#endif /* CONFIG_USB_PD_TX_PHY_ONLY */ - - CPRINTS("USB PD initialized"); -} - -void pd_set_clock(int port, int freq) -{ - pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq); -} diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c deleted file mode 100644 index 90f0039c2c..0000000000 --- a/chip/stm32/usb_power.c +++ /dev/null @@ -1,733 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "dma.h" -#include "hooks.h" -#include "i2c.h" -#include "link_defs.h" -#include "registers.h" -#include "timer.h" -#include "usb_descriptor.h" -#include "usb_power.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -static int usb_power_init_inas(struct usb_power_config const *config); -static int usb_power_read(struct usb_power_config const *config); -static int usb_power_write_line(struct usb_power_config const *config); - -void usb_power_deferred_rx(struct usb_power_config const *config) -{ - int rx_count = rx_ep_pending(config->endpoint); - - /* Handle an incoming command if available */ - if (rx_count) - usb_power_read(config); -} - -void usb_power_deferred_tx(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - if (!tx_ep_is_ready(config->endpoint)) - return; - - /* We've replied, set up the next read. */ - if (!rx_ep_is_active(config->endpoint)) { - /* Remove any active dma region from output buffer */ - state->reports_xmit_active = state->reports_tail; - - /* Wait for the next command */ - usb_read_ep(config->endpoint, - config->ep->out_databuffer_max, - config->ep->out_databuffer); - return; - } -} - -/* Reset stream */ -void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - config->ep->out_databuffer = config->state->rx_buf; - config->ep->out_databuffer_max = sizeof(config->state->rx_buf); - config->ep->in_databuffer = config->state->tx_buf; - config->ep->in_databuffer_max = sizeof(config->state->tx_buf); - - epN_reset(config->endpoint); - - /* Flush any queued data */ - hook_call_deferred(config->ep->rx_deferred, 0); - hook_call_deferred(config->ep->tx_deferred, 0); -} - - -/* Write one or more power records to USB */ -static int usb_power_write_line(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_tail)); - /* status + size + timestamps + power list */ - size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count); - - /* Check if queue has active data. */ - if (config->state->reports_head != config->state->reports_tail) { - int recordcount = 1; - - /* We'll concatenate all the upcoming recrds. */ - if (config->state->reports_tail < config->state->reports_head) - recordcount = config->state->reports_head - - config->state->reports_tail; - else - recordcount = state->max_cached - - config->state->reports_tail; - - state->reports_xmit_active = state->reports_tail; - state->reports_tail = (state->reports_tail + recordcount) % - state->max_cached; - - usb_write_ep(config->endpoint, bytes * recordcount, r); - return bytes; - } - - return 0; -} - - -static int usb_power_state_reset(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - state->state = USB_POWER_STATE_OFF; - state->reports_head = 0; - state->reports_tail = 0; - state->reports_xmit_active = 0; - - CPRINTS("[RESET] STATE -> OFF"); - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_stop(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - /* Only a valid transition from CAPTURING */ - if (state->state != USB_POWER_STATE_CAPTURING) { - CPRINTS("[STOP] Error not capturing."); - return USB_POWER_ERROR_NOT_CAPTURING; - } - - state->state = USB_POWER_STATE_OFF; - state->reports_head = 0; - state->reports_tail = 0; - state->reports_xmit_active = 0; - state->stride_bytes = 0; - CPRINTS("[STOP] STATE: CAPTURING -> OFF"); - return USB_POWER_SUCCESS; -} - - - -static int usb_power_state_start(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - struct usb_power_state *state = config->state; - int integration_us = cmd->start.integration_us; - int ret; - - if (state->state != USB_POWER_STATE_SETUP) { - CPRINTS("[START] Error not setup."); - return USB_POWER_ERROR_NOT_SETUP; - } - - if (count != sizeof(struct usb_power_command_start)) { - CPRINTS("[START] Error count %d is not %d", (int)count, - sizeof(struct usb_power_command_start)); - return USB_POWER_ERROR_READ_SIZE; - } - - if (integration_us == 0) { - CPRINTS("[START] integration_us cannot be 0"); - return USB_POWER_ERROR_UNKNOWN; - } - - /* Calculate the reports array */ - state->stride_bytes = USB_POWER_RECORD_SIZE(state->ina_count); - state->max_cached = USB_POWER_MAX_CACHED(state->ina_count); - - state->integration_us = integration_us; - ret = usb_power_init_inas(config); - - if (ret) - return USB_POWER_ERROR_INVAL; - - state->state = USB_POWER_STATE_CAPTURING; - CPRINTS("[START] STATE: SETUP -> CAPTURING %dus", integration_us); - - /* Find our starting time. */ - config->state->base_time = get_time().val; - - hook_call_deferred(config->deferred_cap, state->integration_us); - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_settime(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - if (count != sizeof(struct usb_power_command_settime)) { - CPRINTS("[SETTIME] Error: count %d is not %d", - (int)count, sizeof(struct usb_power_command_settime)); - return USB_POWER_ERROR_READ_SIZE; - } - - /* Find the offset between microcontroller clock and host clock. */ - if (cmd->settime.time) - config->state->wall_offset = cmd->settime.time - get_time().val; - else - config->state->wall_offset = 0; - - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_addina(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - struct usb_power_state *state = config->state; - struct usb_power_ina_cfg *ina; - int i; - - /* Only valid from OFF or SETUP */ - if ((state->state != USB_POWER_STATE_OFF) && - (state->state != USB_POWER_STATE_SETUP)) { - CPRINTS("[ADDINA] Error incorrect state."); - return USB_POWER_ERROR_NOT_SETUP; - } - - if (count != sizeof(struct usb_power_command_addina)) { - CPRINTS("[ADDINA] Error count %d is not %d", - (int)count, sizeof(struct usb_power_command_addina)); - return USB_POWER_ERROR_READ_SIZE; - } - - if (state->ina_count >= USB_POWER_MAX_READ_COUNT) { - CPRINTS("[ADDINA] Error INA list full"); - return USB_POWER_ERROR_FULL; - } - - /* Transition to SETUP state if necessary and clear INA data */ - if (state->state == USB_POWER_STATE_OFF) { - state->state = USB_POWER_STATE_SETUP; - state->ina_count = 0; - } - - if ((cmd->addina.type < USBP_INA231_POWER) || - (cmd->addina.type > USBP_INA231_SHUNTV)) { - CPRINTS("[ADDINA] Error INA type 0x%x invalid", - (int)(cmd->addina.type)); - return USB_POWER_ERROR_INVAL; - } - - if (cmd->addina.rs == 0) { - CPRINTS("[ADDINA] Error INA resistance cannot be zero!"); - return USB_POWER_ERROR_INVAL; - } - - /* Select INA to configure */ - ina = state->ina_cfg + state->ina_count; - - ina->port = cmd->addina.port; - ina->addr_flags = cmd->addina.addr_flags; - ina->rs = cmd->addina.rs; - ina->type = cmd->addina.type; - - /* - * INAs can be shared, in that they will have various values - * (and therefore registers) read from them each cycle, including - * power, voltage, current. If only a single value is read, - * we an use i2c_readagain for faster transactions as we don't - * have to respecify the address. - */ - ina->shared = 0; -#ifdef USB_POWER_VERBOSE - ina->shared = 1; -#endif - - /* Check if shared with previously configured INAs. */ - for (i = 0; i < state->ina_count; i++) { - struct usb_power_ina_cfg *tmp = state->ina_cfg + i; - - if ((tmp->port == ina->port) && - (tmp->addr_flags == ina->addr_flags)) { - ina->shared = 1; - tmp->shared = 1; - } - } - - state->ina_count += 1; - return USB_POWER_SUCCESS; -} - -static int usb_power_read(struct usb_power_config const *config) -{ - /* - * If there is a USB packet waiting we process it and generate a - * response. - */ - uint8_t count = rx_ep_pending(config->endpoint); - uint8_t result = USB_POWER_SUCCESS; - union usb_power_command_data *cmd = - (union usb_power_command_data *)config->ep->out_databuffer; - - struct usb_power_state *state = config->state; - struct dwc_usb_ep *ep = config->ep; - - /* Bytes to return */ - int in_msgsize = 1; - - if (count < 2) - return EC_ERROR_INVAL; - - /* State machine. */ - switch (cmd->command) { - case USB_POWER_CMD_RESET: - result = usb_power_state_reset(config); - break; - - case USB_POWER_CMD_STOP: - result = usb_power_state_stop(config); - break; - - case USB_POWER_CMD_START: - result = usb_power_state_start(config, cmd, count); - if (result == USB_POWER_SUCCESS) { - /* Send back actual integration time. */ - ep->in_databuffer[1] = - (state->integration_us >> 0) & 0xff; - ep->in_databuffer[2] = - (state->integration_us >> 8) & 0xff; - ep->in_databuffer[3] = - (state->integration_us >> 16) & 0xff; - ep->in_databuffer[4] = - (state->integration_us >> 24) & 0xff; - in_msgsize += 4; - } - break; - - case USB_POWER_CMD_ADDINA: - result = usb_power_state_addina(config, cmd, count); - break; - - case USB_POWER_CMD_SETTIME: - result = usb_power_state_settime(config, cmd, count); - break; - - case USB_POWER_CMD_NEXT: - if (state->state == USB_POWER_STATE_CAPTURING) { - int ret; - - ret = usb_power_write_line(config); - if (ret) - return EC_SUCCESS; - - result = USB_POWER_ERROR_BUSY; - } else { - CPRINTS("[STOP] Error not capturing."); - result = USB_POWER_ERROR_NOT_CAPTURING; - } - break; - - default: - CPRINTS("[ERROR] Unknown command 0x%04x", (int)cmd->command); - result = USB_POWER_ERROR_UNKNOWN; - break; - } - - /* Return result code if applicable. */ - ep->in_databuffer[0] = result; - - usb_write_ep(config->endpoint, in_msgsize, ep->in_databuffer); - - return EC_SUCCESS; -} - - - -/****************************************************************************** - * INA231 interface. - * List the registers and fields here. - * TODO(nsanders): combine with the currently incompatible common INA drivers. - */ - -#define INA231_REG_CONF 0 -#define INA231_REG_RSHV 1 -#define INA231_REG_BUSV 2 -#define INA231_REG_PWR 3 -#define INA231_REG_CURR 4 -#define INA231_REG_CAL 5 -#define INA231_REG_EN 6 - - -#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) -#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) -#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) -#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) -#define INA231_MODE_OFF 0x0 -#define INA231_MODE_SHUNT 0x5 -#define INA231_MODE_BUS 0x6 -#define INA231_MODE_BOTH 0x7 - -int reg_type_mapping(enum usb_power_ina_type ina_type) -{ - switch (ina_type) { - case USBP_INA231_POWER: - return INA231_REG_PWR; - case USBP_INA231_BUSV: - return INA231_REG_BUSV; - case USBP_INA231_CURRENT: - return INA231_REG_CURR; - case USBP_INA231_SHUNTV: - return INA231_REG_RSHV; - - default: - return INA231_REG_CONF; - } -} - -uint16_t ina2xx_readagain(uint8_t port, uint16_t slave_addr_flags) -{ - int res; - uint16_t val; - - res = i2c_xfer(port, slave_addr_flags, - NULL, 0, (uint8_t *)&val, sizeof(uint16_t)); - - if (res) { - CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", - (int)port, (int)I2C_GET_ADDR(slave_addr_flags)); - return 0x0bad; - } - return (val >> 8) | ((val & 0xff) << 8); -} - - -uint16_t ina2xx_read(uint8_t port, uint16_t slave_addr_flags, - uint8_t reg) -{ - int res; - int val; - - res = i2c_read16(port, slave_addr_flags, reg, &val); - if (res) { - CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", - (int)port, (int)I2C_GET_ADDR(slave_addr_flags), - (int)reg); - return 0x0bad; - } - return (val >> 8) | ((val & 0xff) << 8); -} - -int ina2xx_write(uint8_t port, uint16_t slave_addr_flags, - uint8_t reg, uint16_t val) -{ - int res; - uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); - - res = i2c_write16(port, slave_addr_flags, reg, be_val); - if (res) - CPRINTS("INA2XX I2C write failed"); - return res; -} - - - -/****************************************************************************** - * Background tasks - * - * Here we setup the INAs and read them at the specified interval. - * INA samples are stored in a ringbuffer that can be fetched using the - * USB commands. - */ - -/* INA231 integration and averaging time presets, indexed by register value */ -#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) -static const int average_settings[] = { - 1, 4, 16, 64, 128, 256, 512, 1024}; -static const int conversion_time_us[] = { - 140, 204, 332, 588, 1100, 2116, 4156, 8244}; - -static int usb_power_init_inas(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - int i; - int shunt_time = 0; - int avg = 0; - int target_us = state->integration_us; - - if (state->state != USB_POWER_STATE_SETUP) { - CPRINTS("[ERROR] usb_power_init_inas while not SETUP"); - return -1; - } - - /* Find an INA preset integration time less than specified */ - while (shunt_time < (NELEMS(conversion_time_us) - 1)) { - if (conversion_time_us[shunt_time + 1] > target_us) - break; - shunt_time++; - } - - /* Find an averaging setting from the INA presets that fits. */ - while (avg < (NELEMS(average_settings) - 1)) { - if ((conversion_time_us[shunt_time] * - average_settings[avg + 1]) - > target_us) - break; - avg++; - } - - state->integration_us = - conversion_time_us[shunt_time] * average_settings[avg]; - - for (i = 0; i < state->ina_count; i++) { - int value; - int ret; - struct usb_power_ina_cfg *ina = state->ina_cfg + i; - -#ifdef USB_POWER_VERBOSE - { - int conf, cal; - - conf = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - cal = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", - i, ina->port, I2C_GET_ADDR(ina->addr_flags), - conf, cal); - } -#endif - /* - * Calculate INA231 Calibration register - * CurrentLSB = uA per div = 80mV / (Rsh * 2^15) - * CurrentLSB 100x uA = 100x 80000000nV / (Rsh mOhm * 0x8000) - */ - /* TODO: allow voltage readings if no sense resistor. */ - if (ina->rs == 0) - return -1; - - ina->scale = (100 * (80000000 / 0x8000)) / ina->rs; - - /* - * CAL = .00512 / (CurrentLSB * Rsh) - * CAL = 5120000 / (uA * mOhm) - */ - if (ina->scale == 0) - return -1; - value = (5120000 * 100) / (ina->scale * ina->rs); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CAL, value); - if (ret != EC_SUCCESS) { - CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret); - return ret; - } -#ifdef USB_POWER_VERBOSE - { - int actual; - - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", - ina->scale / 100, ina->scale*25/100, value, actual); - } -#endif - /* Conversion time, shunt + bus, set average. */ - value = INA231_CONF_MODE(INA231_MODE_BOTH) | - INA231_CONF_SHUNT_TIME(shunt_time) | - INA231_CONF_BUS_TIME(shunt_time) | - INA231_CONF_AVG(avg); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CONF, value); - if (ret != EC_SUCCESS) { - CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret); - return ret; - } -#ifdef USB_POWER_VERBOSE - { - int actual; - - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", - i, ina->port, I2C_GET_ADDR(ina->addr_flags), - value, actual); - } -#endif -#ifdef USB_POWER_VERBOSE - { - int busv_mv = - (ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV) - * 125) / 100; - - CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", - i, ina->port, I2C_GET_ADDR(ina->addr_flags), - busv_mv); - } -#endif - /* Initialize read from power register. This register address - * will be cached and all ina2xx_readagain() calls will read - * from the same address. - */ - ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); -#ifdef USB_POWER_VERBOSE - CPRINTS("[CAP] %d (%d,0x%02x): type:%d", (int)(ina->type)); -#endif - } - - return EC_SUCCESS; -} - - -/* - * Read each INA's power integration measurement. - * - * INAs recall the most recent address, so no register access write is - * necessary, simply read 16 bits from each INA and fill the result into - * the power record. - * - * If the power record ringbuffer is full, fail with USB_POWER_ERROR_OVERFLOW. - */ -static int usb_power_get_samples(struct usb_power_config const *config) -{ - uint64_t time = get_time().val; - struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_head)); - struct usb_power_ina_cfg *inas = state->ina_cfg; - int i; - - /* TODO(nsanders): Would we prefer to evict oldest? */ - if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count)) - == state->reports_xmit_active) { - CPRINTS("Overflow! h:%d a:%d t:%d (%d)", - state->reports_head, state->reports_xmit_active, - state->reports_tail, - USB_POWER_MAX_CACHED(state->ina_count)); - return USB_POWER_ERROR_OVERFLOW; - } - - r->status = USB_POWER_SUCCESS; - r->size = state->ina_count; - if (config->state->wall_offset) - time = time + config->state->wall_offset; - else - time -= config->state->base_time; - r->timestamp = time; - - for (i = 0; i < state->ina_count; i++) { - int regval; - struct usb_power_ina_cfg *ina = inas + i; - - /* Read INA231. - * ina2xx_read(ina->port, ina->addr, INA231_REG_PWR); - * Readagain cached this address so we'll save an I2C - * transaction. - */ - if (ina->shared) - regval = ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); - else - regval = ina2xx_readagain(ina->port, - ina->addr_flags); - r->power[i] = regval; -#ifdef USB_POWER_VERBOSE - { - int current; - int power; - int voltage; - int bvoltage; - - voltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_RSHV); - bvoltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV); - current = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CURR); - power = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_PWR); - { - int uV = ((int)voltage * 25) / 10; - int mV = ((int)bvoltage * 125) / 100; - int uA = (uV * 1000) / ina->rs; - int CuA = (((int)current * ina->scale) / 100); - int uW = (((int)power * ina->scale*25)/100); - - CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", - i, ina->port, I2C_GET_ADDR(ina->addr_flags), - uV/1000, ina->rs, uA/1000); - CPRINTS("[CAP] %duV %dmV %duA %dCuA " - "%duW v:%04x, b:%04x, p:%04x", - uV, mV, uA, CuA, uW, voltage, bvoltage, power); - } - } -#endif - } - - /* Mark this slot as used. */ - state->reports_head = (state->reports_head + 1) % - USB_POWER_MAX_CACHED(state->ina_count); - - return EC_SUCCESS; -} - -/* - * This function is called every [interval] uS, and reads the accumulated - * values of the INAs, and reschedules itself for the next interval. - * - * It will stop collecting frames if a ringbuffer overflow is - * detected, or a stop request is seen.. - */ -void usb_power_deferred_cap(struct usb_power_config const *config) -{ - int ret; - uint64_t timeout = get_time().val + config->state->integration_us; - uint64_t timein; - - /* Exit if we have stopped capturing in the meantime. */ - if (config->state->state != USB_POWER_STATE_CAPTURING) - return; - - /* Get samples for this timeslice */ - ret = usb_power_get_samples(config); - if (ret == USB_POWER_ERROR_OVERFLOW) { - CPRINTS("[CAP] usb_power_deferred_cap: OVERFLOW"); - return; - } - - /* Calculate time remaining until next slice. */ - timein = get_time().val; - if (timeout > timein) - timeout = timeout - timein; - else - timeout = 0; - - /* Double check if we are still capturing. */ - if (config->state->state == USB_POWER_STATE_CAPTURING) - hook_call_deferred(config->deferred_cap, timeout); -} - diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h deleted file mode 100644 index 68b7f75ca2..0000000000 --- a/chip/stm32/usb_power.h +++ /dev/null @@ -1,383 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_POWER_H -#define __CROS_EC_USB_POWER_H - -/* Power monitoring USB interface for Chrome EC */ - -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * Command: - * - * Commands are a 16 bit value, with optional command dependent data. - * +--------------+-----------------------------------+ - * | command : 2B | | - * +--------------+-----------------------------------+ - * - * Responses are an 8 bit status value, with optional data. - * +----------+-----------------------------------+ - * | res : 1B | | - * +----------+-----------------------------------+ - * - * reset: 0x0000 - * +--------+ - * | 0x0000 | - * +--------+ - * - * stop: 0x0001 - * +--------+ - * | 0x0001 | - * +--------+ - * - * addina: 0x0002 - * +--------+--------------------------+-------------+--------------+-----------+--------+ - * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs | - * +--------+--------------------------+-------------+--------------+-----------+--------+ - * - * start: 0x0003 - * +--------+----------------------+ - * | 0x0003 | 4B: integration time | - * +--------+----------------------+ - * - * start response: - * +-------------+-----------------------------+ - * | status : 1B | Actual integration time: 4B | - * +-------------+-----------------------------+ - * - * next: 0x0004 - * +--------+ - * | 0x0004 | - * +--------+ - * - * next response: - * +-------------+----------+----------------+----------------------------+ - * | status : 1B | size: 1B | timestamp : 8B | payload : may span packets | - * +-------------+----------+----------------+----------------------------+ - * - * settime: 0x0005 - * +--------+---------------------+ - * | 0x0005 | 8B: Wall clock time | - * +--------+---------------------+ - * - * - * Status: 1 byte status - * - * 0x00: Success - * 0x01: I2C Error - * 0x02: Overflow - * This can happen if data acquisition is faster than USB reads. - * 0x03: No configuration set. - * 0x04: No active capture. - * 0x05: Timeout. - * 0x06: Busy, outgoing queue is empty. - * 0x07: Size, command length is incorrect for command type.. - * 0x08: More INAs specified than board limit. - * 0x09: Invalid input, eg. invalid INA type. - * 0x80: Unknown error - * - * size: 1 byte incoming INA reads count - * - * timestamp: 4 byte timestamp associated with these samples - * - */ - -/* 8b status field. */ -enum usb_power_error { - USB_POWER_SUCCESS = 0x00, - USB_POWER_ERROR_I2C = 0x01, - USB_POWER_ERROR_OVERFLOW = 0x02, - USB_POWER_ERROR_NOT_SETUP = 0x03, - USB_POWER_ERROR_NOT_CAPTURING = 0x04, - USB_POWER_ERROR_TIMEOUT = 0x05, - USB_POWER_ERROR_BUSY = 0x06, - USB_POWER_ERROR_READ_SIZE = 0x07, - USB_POWER_ERROR_FULL = 0x08, - USB_POWER_ERROR_INVAL = 0x09, - USB_POWER_ERROR_UNKNOWN = 0x80, -}; - -/* 16b command field. */ -enum usb_power_command { - USB_POWER_CMD_RESET = 0x0000, - USB_POWER_CMD_STOP = 0x0001, - USB_POWER_CMD_ADDINA = 0x0002, - USB_POWER_CMD_START = 0x0003, - USB_POWER_CMD_NEXT = 0x0004, - USB_POWER_CMD_SETTIME = 0x0005, -}; - -/* Addina "INA Type" field. */ -enum usb_power_ina_type { - USBP_INA231_POWER = 0x01, - USBP_INA231_BUSV = 0x02, - USBP_INA231_CURRENT = 0x03, - USBP_INA231_SHUNTV = 0x04, -}; - -/* Internal state machine values */ -enum usb_power_states { - USB_POWER_STATE_OFF = 0, - USB_POWER_STATE_SETUP, - USB_POWER_STATE_CAPTURING, -}; - -#define USB_POWER_MAX_READ_COUNT 64 -#define USB_POWER_MIN_CACHED 10 - -struct usb_power_ina_cfg { - /* - * Relevant config for INA usage. - */ - /* i2c bus. TODO(nsanders): specify what kind of index. */ - int port; - /* 7-bit i2c addr */ - uint16_t addr_flags; - - /* Base voltage. mV */ - int mv; - - /* Shunt resistor. mOhm */ - int rs; - /* uA per div as reported from INA */ - int scale; - - /* Is this power, shunt voltage, bus voltage, or current? */ - int type; - /* Is this INA returning the one value only and can use readagain? */ - int shared; -}; - - -struct __attribute__ ((__packed__)) usb_power_report { - uint8_t status; - uint8_t size; - uint64_t timestamp; - uint16_t power[USB_POWER_MAX_READ_COUNT]; -}; - -/* Must be 4 byte aligned */ -#define USB_POWER_RECORD_SIZE(ina_count) \ - ((((sizeof(struct usb_power_report) \ - - (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) \ - + (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4) - -#define USB_POWER_DATA_SIZE \ - (sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1)) -#define USB_POWER_MAX_CACHED(ina_count) \ - (USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count)) - - -struct usb_power_state { - /* - * The power data acquisition must be setup, then started, in order to - * return data. - * States are OFF, SETUP, and CAPTURING. - */ - int state; - - struct usb_power_ina_cfg ina_cfg[USB_POWER_MAX_READ_COUNT]; - int ina_count; - int integration_us; - /* Start of sampling. */ - uint64_t base_time; - /* Offset between microcontroller timestamp and host wall clock. */ - uint64_t wall_offset; - - /* Cached power reports for sending on USB. */ - /* Actual backing data for variable sized record queue. */ - uint8_t reports_data_area[USB_POWER_DATA_SIZE]; - /* Size of power report struct for this config. */ - int stride_bytes; - /* Max power records storeable in this config */ - int max_cached; - struct usb_power_report *reports; - - /* Head and tail pointers for output ringbuffer */ - /* Head adds newly probed power data. */ - int reports_head; - /* Tail contains oldest records not yet sent to USB */ - int reports_tail; - /* Xmit_active -> tail is active usb DMA */ - int reports_xmit_active; - - /* Pointers to RAM. */ - uint8_t rx_buf[USB_MAX_PACKET_SIZE]; - uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4]; -}; - - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_power_config { - /* In RAM state of the USB power interface. */ - struct usb_power_state *state; - - /* USB endpoint state.*/ - struct dwc_usb_ep *ep; - - /* Interface and endpoint indicies. */ - int interface; - int endpoint; - - /* Deferred function to call to handle power request. */ - const struct deferred_data *deferred; - const struct deferred_data *deferred_cap; -}; - -struct __attribute__ ((__packed__)) usb_power_command_start { - uint16_t command; - uint32_t integration_us; -}; - -struct __attribute__ ((__packed__)) usb_power_command_addina { - uint16_t command; - uint8_t port; - uint8_t type; - uint8_t addr_flags; - uint8_t extra; - uint32_t rs; -}; - -struct __attribute__ ((__packed__)) usb_power_command_settime { - uint16_t command; - uint64_t time; -}; - -union usb_power_command_data { - uint16_t command; - struct usb_power_command_start start; - struct usb_power_command_addina addina; - struct usb_power_command_settime settime; -}; - - -/* - * Convenience macro for defining a USB INA Power driver. - * - * NAME is used to construct the names of the trampoline functions and the - * usb_power_config struct, the latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - */ -#define USB_POWER_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT) \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - static void CONCAT2(NAME, _deferred_cap_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ - struct usb_power_state CONCAT2(NAME, _state_) = { \ - .state = USB_POWER_STATE_OFF, \ - .ina_count = 0, \ - .integration_us = 0, \ - .reports_head = 0, \ - .reports_tail = 0, \ - .wall_offset = 0, \ - }; \ - static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_data = 0, \ - .out_databuffer = 0, \ - .out_databuffer_max = 0, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = 0, \ - .in_databuffer_max = 0, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - struct usb_power_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .ep = &CONCAT2(NAME, _ep_ctl), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 1, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_epN_tx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_epN_rx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_power_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { usb_power_deferred_tx(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { usb_power_deferred_rx(&NAME); } \ - static void CONCAT2(NAME, _deferred_cap_)(void) \ - { usb_power_deferred_cap(&NAME); } - - -/* - * Handle power request in a deferred callback. - */ -void usb_power_deferred_rx(struct usb_power_config const *config); -void usb_power_deferred_tx(struct usb_power_config const *config); -void usb_power_deferred_cap(struct usb_power_config const *config); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_power_tx(struct usb_power_config const *config); -void usb_power_rx(struct usb_power_config const *config); -void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt); - - - - -#endif /* __CROS_EC_USB_DWC_POWER_H */ - diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c deleted file mode 100644 index eaaaaf91d3..0000000000 --- a/chip/stm32/usb_spi.c +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "link_defs.h" -#include "registers.h" -#include "spi.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_spi.h" -#include "util.h" - -static int16_t usb_spi_map_error(int error) -{ - switch (error) { - case EC_SUCCESS: return USB_SPI_SUCCESS; - case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT; - case EC_ERROR_BUSY: return USB_SPI_BUSY; - default: return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); - } -} - -static uint16_t usb_spi_read_packet(struct usb_spi_config const *config) -{ - size_t i; - uint16_t bytes = btable_ep[config->endpoint].rx_count & 0x3ff; - size_t count = MAX((bytes + 1) / 2, USB_MAX_PACKET_SIZE / 2); - - /* - * The USB peripheral doesn't support DMA access to its packet - * RAM so we have to copy messages out into a bounce buffer. - */ - for (i = 0; i < count; ++i) - config->buffer[i] = config->rx_ram[i]; - - /* - * RX packet consumed, mark the packet as VALID. The master - * could queue up the next command while we process this SPI - * transaction and prepare the response. - */ - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); - - return bytes; -} - -static void usb_spi_write_packet(struct usb_spi_config const *config, - uint8_t count) -{ - size_t i; - - /* - * Copy read bytes and status back out of bounce buffer and - * update TX packet state (mark as VALID for master to read). - */ - for (i = 0; i < (count + 1) / 2; ++i) - config->tx_ram[i] = config->buffer[i]; - - btable_ep[config->endpoint].tx_count = count; - - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); -} - -static int rx_valid(struct usb_spi_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID; -} - -void usb_spi_deferred(struct usb_spi_config const *config) -{ - /* - * If our overall enabled state has changed we call the board specific - * enable or disable routines and save our new state. - */ - int enabled = (config->state->enabled_host && - config->state->enabled_device); - - if (enabled ^ config->state->enabled) { - if (enabled) usb_spi_board_enable(config); - else usb_spi_board_disable(config); - - config->state->enabled = enabled; - } - - /* - * And if there is a USB packet waiting we process it and generate a - * response. - */ - if (!rx_valid(config)) { - uint16_t count = usb_spi_read_packet(config); - uint8_t write_count = (config->buffer[0] >> 0) & 0xff; - uint8_t read_count = (config->buffer[0] >> 8) & 0xff; - - if (!config->state->enabled) { - config->buffer[0] = USB_SPI_DISABLED; - } else if (write_count > USB_SPI_MAX_WRITE_COUNT || - write_count != (count - 2)) { - config->buffer[0] = USB_SPI_WRITE_COUNT_INVALID; - } else if (read_count > USB_SPI_MAX_READ_COUNT) { - config->buffer[0] = USB_SPI_READ_COUNT_INVALID; - } else { - config->buffer[0] = usb_spi_map_error( - spi_transaction(SPI_FLASH_DEVICE, - (uint8_t *)(config->buffer + 1), - write_count, - (uint8_t *)(config->buffer + 1), - read_count)); - } - - usb_spi_write_packet(config, read_count + 2); - } -} - -void usb_spi_tx(struct usb_spi_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_NAK, 0); -} - -void usb_spi_rx(struct usb_spi_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_NAK, 0); - - hook_call_deferred(config->deferred, 0); -} - -void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) -{ - int endpoint; - - if (evt != USB_EVENT_RESET) - return; - - endpoint = config->endpoint; - - btable_ep[endpoint].tx_addr = usb_sram_addr(config->tx_ram); - btable_ep[endpoint].tx_count = 0; - - btable_ep[endpoint].rx_addr = usb_sram_addr(config->rx_ram); - btable_ep[endpoint].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - - STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ -} - -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf) -{ - struct usb_setup_packet setup; - - usb_read_setup_packet(rx_buf, &setup); - - if (setup.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) - return 1; - - if (setup.wValue != 0 || - setup.wIndex != config->interface || - setup.wLength != 0) - return 1; - - if (!config->state->enabled_device) - return 1; - - switch (setup.bRequest) { - case USB_SPI_REQ_ENABLE: - config->state->enabled_host = 1; - break; - - case USB_SPI_REQ_DISABLE: - config->state->enabled_host = 0; - break; - - default: return 1; - } - - /* - * Our state has changed, call the deferred function to handle the - * state change. - */ - hook_call_deferred(config->deferred, 0); - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT); - return 0; -} - -void usb_spi_enable(struct usb_spi_config const *config, int enabled) -{ - config->state->enabled_device = enabled; - - hook_call_deferred(config->deferred, 0); -} diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h deleted file mode 100644 index 15d20e7d6b..0000000000 --- a/chip/stm32/usb_spi.h +++ /dev/null @@ -1,240 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_SPI_H -#define __CROS_EC_USB_SPI_H - -/* STM32 USB SPI driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * Command: - * +------------------+-----------------+------------------------+ - * | write count : 1B | read count : 1B | write payload : <= 62B | - * +------------------+-----------------+------------------------+ - * - * write count: 1 byte, zero based count of bytes to write - * - * read count: 1 byte, zero based count of bytes to read - * - * write payload: up to 62 bytes of data to write, length must match - * write count - * - * Response: - * +-------------+-----------------------+ - * | status : 2B | read payload : <= 62B | - * +-------------+-----------------------+ - * - * status: 2 byte status - * 0x0000: Success - * 0x0001: SPI timeout - * 0x0002: Busy, try again - * This can happen if someone else has acquired the shared memory - * buffer that the SPI driver uses as /dev/null - * 0x0003: Write count invalid (> 62 bytes, or mismatch with payload) - * 0x0004: Read count invalid (> 62 bytes) - * 0x0005: The SPI bridge is disabled. - * 0x8000: Unknown error mask - * The bottom 15 bits will contain the bottom 15 bits from the EC - * error code. - * - * read payload: up to 62 bytes of data read from SPI, length will match - * requested read count - */ - -enum usb_spi_error { - USB_SPI_SUCCESS = 0x0000, - USB_SPI_TIMEOUT = 0x0001, - USB_SPI_BUSY = 0x0002, - USB_SPI_WRITE_COUNT_INVALID = 0x0003, - USB_SPI_READ_COUNT_INVALID = 0x0004, - USB_SPI_DISABLED = 0x0005, - USB_SPI_UNKNOWN_ERROR = 0x8000, -}; - -enum usb_spi_request { - USB_SPI_REQ_ENABLE = 0x0000, - USB_SPI_REQ_DISABLE = 0x0001, -}; - -#define USB_SPI_MAX_WRITE_COUNT 62 -#define USB_SPI_MAX_READ_COUNT 62 - -BUILD_ASSERT(USB_MAX_PACKET_SIZE == (1 + 1 + USB_SPI_MAX_WRITE_COUNT)); -BUILD_ASSERT(USB_MAX_PACKET_SIZE == (2 + USB_SPI_MAX_READ_COUNT)); - -struct usb_spi_state { - /* - * The SPI bridge must be enabled both locally and by the host to allow - * access to the SPI device. The enabled_host flag is set and cleared - * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device - * control endpoint. The enabled_device flag is set by calling - * usb_spi_enable. - */ - int enabled_host; - int enabled_device; - - /* - * The current enabled state. This is only updated in the deferred - * callback. Whenever either of the host or device specific enable - * flags is changed the deferred callback is queued, and it will check - * their combined state against this flag. If the combined state is - * different, then one of usb_spi_board_enable or usb_spi_board_disable - * is called and this flag is updated. This ensures that the board - * specific state update routines are only called from the deferred - * callback. - */ - int enabled; -}; - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_spi_config { - /* - * In RAM state of the USB SPI bridge. - */ - struct usb_spi_state *state; - - /* - * Interface and endpoint indicies. - */ - int interface; - int endpoint; - - /* - * Deferred function to call to handle SPI request. - */ - const struct deferred_data *deferred; - - /* - * Pointers to USB packet RAM and bounce buffer. - */ - uint16_t *buffer; - usb_uint *rx_ram; - usb_uint *tx_ram; -}; - -/* - * Convenience macro for defining a USB SPI bridge driver. - * - * NAME is used to construct the names of the trampoline functions and the - * usb_spi_config struct, the latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * SPI driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - */ -#define USB_SPI_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT) \ - static uint16_t CONCAT2(NAME, _buffer_)[USB_MAX_PACKET_SIZE / 2]; \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_spi_state CONCAT2(NAME, _state_) = { \ - .enabled_host = 0, \ - .enabled_device = 0, \ - .enabled = 0, \ - }; \ - struct usb_spi_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .buffer = CONCAT2(NAME, _buffer_), \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_spi_tx (&NAME); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_spi_rx (&NAME); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_spi_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_spi_interface(&NAME, rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_spi_deferred(&NAME); } - -/* - * Handle SPI request in a deferred callback. - */ -void usb_spi_deferred(struct usb_spi_config const *config); - -/* - * Set the enable state for the USB-SPI bridge. - * - * The bridge must be enabled from both the host and device side - * before the SPI bus is usable. This allows the bridge to be - * available for host tools to use without forcing the device to - * disconnect or disable whatever else might be using the SPI bus. - */ -void usb_spi_enable(struct usb_spi_config const *config, int enabled); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_spi_tx(struct usb_spi_config const *config); -void usb_spi_rx(struct usb_spi_config const *config); -void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt); -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf); - -/* - * These functions should be implemented by the board to provide any board - * specific operations required to enable or disable access to the SPI device. - */ -void usb_spi_board_enable(struct usb_spi_config const *config); -void usb_spi_board_disable(struct usb_spi_config const *config); - -#endif /* __CROS_EC_USB_SPI_H */ diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c deleted file mode 100644 index 067ea32aa6..0000000000 --- a/chip/stm32/watchdog.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * LSI oscillator frequency is typically 38 kHz, but it may be between 28-56 - * kHz and we don't calibrate it to know. Use 56 kHz so that we pick a counter - * value large enough that we reload before the worst-case watchdog delay - * (fastest LSI clock). - */ -#define LSI_CLOCK 56000 - -/* - * Use largest prescaler divider = /256. This gives a worst-case watchdog - * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) = - * 18.7 sec. - */ -#define IWDG_PRESCALER 6 -#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER) - -void watchdog_reload(void) -{ - /* Reload the watchdog */ - STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; - -#ifdef CONFIG_WATCHDOG_HELP - hwtimer_reset_watchdog(); -#endif -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ - /* Unlock watchdog registers */ - STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; - - /* Set the prescaler between the LSI clock and the watchdog counter */ - STM32_IWDG_PR = IWDG_PRESCALER & 7; - - /* Set the reload value of the watchdog counter */ - STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS * - (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); - - /* Start the watchdog (and re-lock registers) */ - STM32_IWDG_KR = STM32_IWDG_KR_START; - -#ifdef CONFIG_WATCHDOG_HELP - /* Use a harder timer to warn about an impending watchdog reset */ - hwtimer_setup_watchdog(); -#endif - - return EC_SUCCESS; -} |