diff options
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/config_chip.h | 4 | ||||
-rw-r--r-- | chip/g/config_std_flash.h | 32 | ||||
-rw-r--r-- | chip/host/config_chip.h | 18 | ||||
-rw-r--r-- | chip/host/flash.c | 2 | ||||
-rw-r--r-- | chip/it83xx/config_chip.h | 28 | ||||
-rw-r--r-- | chip/lm4/config_chip.h | 28 | ||||
-rw-r--r-- | chip/lm4/flash.c | 10 | ||||
-rw-r--r-- | chip/mec1322/config_chip.h | 1 | ||||
-rw-r--r-- | chip/mec1322/flash.c | 12 | ||||
-rw-r--r-- | chip/npcx/config_chip.h | 5 | ||||
-rw-r--r-- | chip/npcx/flash.c | 10 | ||||
-rw-r--r-- | chip/nrf51/config_chip.h | 21 | ||||
-rw-r--r-- | chip/stm32/config-stm32f03x.h | 23 | ||||
-rw-r--r-- | chip/stm32/config-stm32f07x.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32f100.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32f10x.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32f373.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32l100.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32l15x.h | 18 | ||||
-rw-r--r-- | chip/stm32/config-stm32ts60.h | 18 | ||||
-rw-r--r-- | chip/stm32/config_chip.h | 2 | ||||
-rw-r--r-- | chip/stm32/flash-f.c | 11 | ||||
-rw-r--r-- | chip/stm32/flash-stm32l.c | 3 |
23 files changed, 32 insertions, 304 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index d6dfe8fa13..79b44f4ddd 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -28,10 +28,8 @@ /* #define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024) */ #define CONFIG_FLASH_PHYSICAL_SIZE (256 * 1024) -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (128 * 1024) /* Compute the rest of the flash params from these */ -#include "config_std_flash.h" +#include "config_std_internal_flash.h" /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 diff --git a/chip/g/config_std_flash.h b/chip/g/config_std_flash.h deleted file mode 100644 index 86df29c4e4..0000000000 --- a/chip/g/config_std_flash.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_STD_FLASH_H -#define __CROS_EC_CONFIG_STD_FLASH_H - -/* RO firmware must start at beginning of flash */ -#define CONFIG_RO_MEM_OFF 0 - -/* - * The EC uses the one bank of flash to emulate a SPI-like write protect - * register with persistent state. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE - -/* PSTATE immediately follows RO, in the first half of flash */ -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ - - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE - -/* RW firmware is one firmware image offset from the start */ -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE - -/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */ -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE - -#endif /* __CROS_EC_CONFIG_STD_FLASH_H */ diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index df84143883..b809134e83 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -10,7 +10,6 @@ /* Memory mapping */ #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE]; #define CONFIG_FLASH_BASE ((uintptr_t)__host_flash) @@ -23,22 +22,7 @@ extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE]; #define CONFIG_FPU -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (64 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put this after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#include "config_std_internal_flash.h" /* Maximum number of deferrable functions */ #define DEFERRABLE_MAX_COUNT 8 diff --git a/chip/host/flash.c b/chip/host/flash.c index 2be40b37df..77639218aa 100644 --- a/chip/host/flash.c +++ b/chip/host/flash.c @@ -114,7 +114,7 @@ uint32_t flash_physical_get_protect_flags(void) int flash_physical_protect_now(int all) { - memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : RO_BANK_COUNT); + memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : WP_BANK_COUNT); return EC_SUCCESS; } diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index 5caf50562b..2c433262c9 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -56,33 +56,7 @@ /****************************************************************************/ /* Define our flash layout. */ -/* Size of one firmware image in flash */ -#ifndef CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) -#endif - -/* RO firmware must start at beginning of flash */ -#define CONFIG_RO_MEM_OFF 0 - -/* - * The EC uses the one bank of flash to emulate a SPI-like write protect - * register with persistent state. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE - -/* PSTATE immediately follows RO, in the first half of flash */ -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ - - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE - -/* RW firmware is one firmware image offset from the start */ -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE - -/* TODO: why 2 sets of configs with the same numbers? */ -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE +#include "config_std_internal_flash.h" /****************************************************************************/ /* Customize the build */ diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 433510d460..4bf6c75a18 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -69,33 +69,7 @@ /****************************************************************************/ /* Define our flash layout. */ -/* Size of one firmware image in flash */ -#ifndef CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) -#endif - -/* RO firmware must start at beginning of flash */ -#define CONFIG_RO_MEM_OFF 0 - -/* - * The EC uses the one bank of flash to emulate a SPI-like write protect - * register with persistent state. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE - -/* PSTATE immediately follows RO, in the first half of flash */ -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ - - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE - -/* RW firmware is one firmware image offset from the start */ -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE - -/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */ -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE +#include "config_std_internal_flash.h" /****************************************************************************/ /* Lock the boot configuration to prevent brickage. */ diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c index 6c6a01072b..6a5634f5b3 100644 --- a/chip/lm4/flash.c +++ b/chip/lm4/flash.c @@ -195,13 +195,9 @@ int flash_physical_protect_now(int all) all_protected = 1; protect_banks(0, CONFIG_FLASH_PHYSICAL_SIZE / CONFIG_FLASH_BANK_SIZE); - } else { - /* Protect the read-only section and persistent state */ - protect_banks(RO_BANK_OFFSET, RO_BANK_COUNT); -#ifdef PSTATE_BANK - protect_banks(PSTATE_BANK, 1); -#endif - } + } else + /* Protect the WP region (read-only section and pstate) */ + protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT); return EC_SUCCESS; } diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index ffdf0e56d4..aaf4feb6b8 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -131,7 +131,6 @@ which contains Loader and RO Images */ located at the end of the flash */ #define CONFIG_FLASH_BASE_SPI (CONFIG_SPI_FLASH_SIZE - (0x40000)) -#define CONFIG_RO_WP_SPI_OFF 0x20000 #define CONFIG_RO_STORAGE_OFF 0x20000 #define CONFIG_RW_STORAGE_OFF 0 #define CONFIG_RO_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \ diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c index 78beb72429..92a7dacb33 100644 --- a/chip/mec1322/flash.c +++ b/chip/mec1322/flash.c @@ -123,8 +123,8 @@ int flash_physical_protect_now(int all) offset = 0; size = CONFIG_FLASH_PHYSICAL_SIZE; } else { - offset = CONFIG_RO_MEM_OFF; - size = CONFIG_RO_SIZE; + offset = CONFIG_WP_OFF; + size = CONFIG_WP_SIZE; } spi_enable(1); @@ -145,9 +145,9 @@ uint32_t flash_physical_get_protect_flags(void) uint32_t flags = 0; spi_enable(1); - if (spi_flash_check_protect(CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE)) { + if (spi_flash_check_protect(CONFIG_RO_STORAGE_OFF, CONFIG_RO_SIZE)) { flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; - if (spi_flash_check_protect(CONFIG_RW_MEM_OFF, + if (spi_flash_check_protect(CONFIG_RW_STORAGE_OFF, CONFIG_RW_SIZE)) flags |= EC_FLASH_PROTECT_ALL_NOW; } @@ -206,8 +206,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range) offset = size = 0; break; case FLASH_WP_RO: - offset = CONFIG_RO_MEM_OFF; - size = CONFIG_RO_SIZE; + offset = CONFIG_WP_OFF; + size = CONFIG_WP_SIZE; break; case FLASH_WP_ALL: offset = 0; diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 560be8e6c9..272c5eebed 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -76,15 +76,16 @@ /* RO firmware offset of flash */ #define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 #define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE #define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE /* RW firmware is one firmware image offset from the start */ #define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE #define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */ -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF +#define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF #define CONFIG_WP_SIZE CONFIG_RO_SIZE /* diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index e551b0c977..30091a39f0 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -602,9 +602,9 @@ uint32_t flash_physical_get_protect_flags(void) { uint32_t flags = 0; - /* Check if RO section is protected in status register */ - if (flash_check_prot_reg(RO_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE, - RO_BANK_COUNT*CONFIG_FLASH_BANK_SIZE)) + /* Check if WP region is protected in status register */ + if (flash_check_prot_reg(WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE, + WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE)) flags |= EC_FLASH_PROTECT_RO_AT_BOOT; /* @@ -639,8 +639,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range) case FLASH_WP_RO: /* Protect read-only */ return flash_write_prot_reg( - RO_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE, - RO_BANK_COUNT*CONFIG_FLASH_BANK_SIZE); + WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE, + WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE); case FLASH_WP_ALL: default: return EC_ERROR_INVAL; diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index 104fceb0ca..78ee610601 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -41,33 +41,16 @@ /* Flash mapping */ #define CONFIG_FLASH_BASE 0x00000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (128 * 1024) - -/* Define the RO/RW offset */ -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect - * region contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - +#include "config_std_internal_flash.h" /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 /* Not that much RAM, set to smaller */ -#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 1024 - #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 2bd4da74cb..18c8806908 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00008000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,28 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00001000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (16 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#if defined(BOARD_ZINGER) || defined(BOARD_MINIMUFFIN) -/* Not using pstate but keep some space for the public key */ -#define CONFIG_FW_PSTATE_SIZE 544 -#else -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#endif -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h index d1d01824e9..45b340355c 100644 --- a/chip/stm32/config-stm32f07x.h +++ b/chip/stm32/config-stm32f07x.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE (128 * 1024) -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,23 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00004000 -/* Size of the first firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_SIZE / 2) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_FW_IMAGE_SIZE) -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE) -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 diff --git a/chip/stm32/config-stm32f100.h b/chip/stm32/config-stm32f100.h index 297da6b238..09a638c28f 100644 --- a/chip/stm32/config-stm32f100.h +++ b/chip/stm32/config-stm32f100.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,23 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00002000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (64 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 61 diff --git a/chip/stm32/config-stm32f10x.h b/chip/stm32/config-stm32f10x.h index e638fdd377..e568d7ea87 100644 --- a/chip/stm32/config-stm32f10x.h +++ b/chip/stm32/config-stm32f10x.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,22 +16,5 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE (10 * 1024) -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (64 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 68 diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index 05f50f9cdd..42857af2c9 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x2000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,23 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00008000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (128 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 81 diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h index ae063be847..e751e396cd 100644 --- a/chip/stm32/config-stm32l100.h +++ b/chip/stm32/config-stm32l100.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ @@ -26,23 +25,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00002800 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (64 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect - * region contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 4e5a9dca06..dc897253aa 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ @@ -26,23 +25,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00004000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (64 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_RO_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect - * region contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h index 85a78af6d5..540855c724 100644 --- a/chip/stm32/config-stm32ts60.h +++ b/chip/stm32/config-stm32ts60.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x0010000 /* Actually 0x8000 */ -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 /* TODO */ #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* TODO erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* TODO minimum write size */ @@ -17,23 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00002800 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (32 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 59 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index a8814df217..541b50d8a4 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -43,6 +43,8 @@ #error "Unsupported chip variant" #endif +#include "config_std_internal_flash.h" + /* System stack size */ #define CONFIG_STACK_SIZE 1024 diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index 1fa809a449..090e223ec7 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -342,12 +342,12 @@ int flash_physical_protect_at_boot(enum flash_wp_range range) for (i = 0; i < 4; ++i) original_val[i] = val[i] = read_optb(i * 2 + 8); - for (block = RO_BANK_OFFSET; - block < RO_BANK_OFFSET + PHYSICAL_BANKS; + for (block = WP_BANK_OFFSET; + block < WP_BANK_OFFSET + PHYSICAL_BANKS; block++) { int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4; - if (block >= RO_BANK_OFFSET + RO_BANK_COUNT + PSTATE_BANK_COUNT) + if (block >= WP_BANK_OFFSET + WP_BANK_COUNT) cur_range = FLASH_WP_ALL; else cur_range = FLASH_WP_RO; @@ -384,9 +384,8 @@ static int registers_need_reset(void) uint32_t flags = flash_get_protect(); int i; int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0; - int ro_wp_region_start = RO_BANK_OFFSET; - int ro_wp_region_end = - RO_BANK_OFFSET + RO_BANK_COUNT + PSTATE_BANK_COUNT; + int ro_wp_region_start = WP_BANK_OFFSET; + int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT; for (i = ro_wp_region_start; i < ro_wp_region_end; i++) if (flash_physical_get_protect_at_boot(i) != ro_at_boot) diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index 106e436c80..5a84d31f46 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -319,8 +319,7 @@ int flash_physical_get_protect(int block) int flash_physical_protect_at_boot(enum flash_wp_range range) { uint32_t prot; - uint32_t mask = ((1 << (RO_BANK_COUNT + PSTATE_BANK_COUNT)) - 1) - << RO_BANK_OFFSET; + uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; int rv; if (range == FLASH_WP_ALL) |