diff options
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/adc.c | 58 | ||||
| -rw-r--r-- | chip/it83xx/adc_chip.h | 1 | ||||
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 9 |
3 files changed, 15 insertions, 53 deletions
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 0af56e32a3..ba5f70e27e 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -24,41 +24,18 @@ static volatile task_id_t task_waiting; /* Data structure of ADC channel control registers. */ const struct adc_ctrl_t adc_ctrl_regs[] = { - {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL, - &IT83XX_GPIO_GPCRI0}, - {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL, - &IT83XX_GPIO_GPCRI1}, - {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL, - &IT83XX_GPIO_GPCRI2}, - {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL, - &IT83XX_GPIO_GPCRI3}, - {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL, - &IT83XX_GPIO_GPCRI4}, - {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL, - &IT83XX_GPIO_GPCRI5}, - {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL, - &IT83XX_GPIO_GPCRI6}, - {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL, - &IT83XX_GPIO_GPCRI7}, -#ifdef IT83XX_CHIP_ADC_PIN_ORDER_CHANGE - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, - &IT83XX_GPIO_GPCRL1}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, - &IT83XX_GPIO_GPCRL2}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, - &IT83XX_GPIO_GPCRL3}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, - &IT83XX_GPIO_GPCRL0}, -#else - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, - &IT83XX_GPIO_GPCRL0}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, - &IT83XX_GPIO_GPCRL1}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, - &IT83XX_GPIO_GPCRL2}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, - &IT83XX_GPIO_GPCRL3}, -#endif + {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL}, + {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL}, + {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL}, + {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL}, + {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL}, + {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL}, + {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL}, + {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL}, + {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL}, + {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL}, + {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL}, + {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL}, }; BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); @@ -340,18 +317,11 @@ static void adc_accuracy_initialization(void) /* ADC module Initialization */ static void adc_init(void) { - int index; - int ch; - /* ADC analog accuracy initialization */ adc_accuracy_initialization(); - for (index = 0; index < ADC_CH_COUNT; index++) { - ch = adc_channels[index].channel; - - /* enable adc channel[x] function pin */ - *adc_ctrl_regs[ch].adc_pin_ctrl = 0x00; - } + /* Enable alternate function */ + gpio_config_module(MODULE_ADC, 1); /* * bit7@ADCSTS : ADCCTS1 = 0 * bit5@ADCCFG : ADCCTS0 = 0 diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h index dd236994de..f843dca996 100644 --- a/chip/it83xx/adc_chip.h +++ b/chip/it83xx/adc_chip.h @@ -73,7 +73,6 @@ struct adc_ctrl_t { volatile uint8_t *adc_ctrl; volatile uint8_t *adc_datm; volatile uint8_t *adc_datl; - volatile uint8_t *adc_pin_ctrl; }; /* Data structure to define ADC channels. */ diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index a14a87ae03..19437e5154 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -33,14 +33,7 @@ #define CONFIG_FLASH_SIZE 0x00080000 #define CONFIG_RAM_BASE 0x80080000 #define CONFIG_RAM_SIZE 0x00010000 -/* - * ADC control pin order change: - * ADC13 control pin GPL0 GPL1 - * ADC14 control pin GPL1 change to GPL2 - * ADC15 control pin GPL2 ---------> GPL3 - * ADC16 control pin GPL3 GPL0 - */ -#define IT83XX_CHIP_ADC_PIN_ORDER_CHANGE + /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD /* Don't let internal flash go into deep power down mode. */ |