diff options
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/i2c_ite_flash_support.c | 8 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 2 |
2 files changed, 8 insertions, 2 deletions
diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c index fdf40f3b12..eca3c999af 100644 --- a/chip/stm32/i2c_ite_flash_support.c +++ b/chip/stm32/i2c_ite_flash_support.c @@ -274,13 +274,17 @@ static int command_enable_ite_dfu(int argc, char **argv) * Enable output compare 1 (or its N counterpart). Note that if only * OC1N is enabled, then it is not complemented. From datasheet: * "When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented" + * + * Note: we want the rising edge of SDA to be in the middle of SCL, so + * invert the SDA (faster) signal. */ if (ite_dfu_config.use_complement_timer_channel) { STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1NE; - STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1NE; + STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1NE | + STM32_TIM_CCER_CC1NP; } else { STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1E; - STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E; + STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; } /* Enable main output. */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index f323e10201..abd723a39c 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -89,7 +89,9 @@ #define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) #define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) #define STM32_TIM_CCER_CC1E BIT(0) +#define STM32_TIM_CCER_CC1P BIT(1) #define STM32_TIM_CCER_CC1NE BIT(2) +#define STM32_TIM_CCER_CC1NP BIT(3) #define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) #define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) #define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) |