diff options
Diffstat (limited to 'common')
-rw-r--r-- | common/i2c_controller.c | 12 | ||||
-rw-r--r-- | common/i2c_peripheral.c | 2 | ||||
-rw-r--r-- | common/i2c_wedge.c | 4 | ||||
-rw-r--r-- | common/i2cp_tpm.c | 20 |
4 files changed, 19 insertions, 19 deletions
diff --git a/common/i2c_controller.c b/common/i2c_controller.c index 5a8f58196f..ac65483185 100644 --- a/common/i2c_controller.c +++ b/common/i2c_controller.c @@ -775,13 +775,13 @@ int i2c_raw_mode(int port, int enable) * low). * * We attempt to unwedge the bus by doing: - * - If SCL is being held low, then a slave is clock extending. The only - * thing we can do is try to wait until the slave stops clock extending. - * - Otherwise, we will toggle the clock until the slave releases the SDA line. - * Once the SDA line is released, try to send a STOP bit. Rinse and repeat - * until either the bus is normal, or we run out of attempts. + * - If SCL is being held low, then a peripheral is clock extending. The only + * thing we can do is try to wait until the peripheral stops clock extending. + * - Otherwise, we will toggle the clock until the peripheral releases the SDA + * line. Once the SDA line is released, try to send a STOP bit. Rinse and + * repeat until either the bus is normal, or we run out of attempts. * - * Note this should work for most devices, but depending on the slaves i2c + * Note this should work for most devices, but depending on the i2c peripheral's * state machine, it may not be possible to unwedge the bus. */ int i2c_unwedge(int port) diff --git a/common/i2c_peripheral.c b/common/i2c_peripheral.c index 7e710b2ef4..20a4b4b0ae 100644 --- a/common/i2c_peripheral.c +++ b/common/i2c_peripheral.c @@ -3,7 +3,7 @@ * found in the LICENSE file. */ -/* I2C slave cross-platform code for Chrome EC */ +/* I2C peripheral cross-platform code for Chrome EC */ #include "host_command.h" #include "i2c.h" diff --git a/common/i2c_wedge.c b/common/i2c_wedge.c index f044b84dc3..0d930a7729 100644 --- a/common/i2c_wedge.c +++ b/common/i2c_wedge.c @@ -117,7 +117,7 @@ static int i2c_bang_in_bit(void) { int bit; - /* Let the slave drive data */ + /* Let the peripheral drive data */ i2c_raw_set_sda(I2C_PORT_HOST, 1); i2c_bang_delay(); @@ -134,7 +134,7 @@ static int i2c_bang_in_bit(void) return bit; } -/* Write a byte to I2C bus. Return 0 if ack by the slave. */ +/* Write a byte to I2C bus. Return 0 if ack by the peripheral. */ static int i2c_bang_out_byte(int send_start, int send_stop, unsigned char byte) { unsigned bit; diff --git a/common/i2cp_tpm.c b/common/i2cp_tpm.c index 48af3a22b3..4fbc27c899 100644 --- a/common/i2cp_tpm.c +++ b/common/i2cp_tpm.c @@ -19,9 +19,9 @@ * interrupts on the interrupt context. * * Each "write complete" interrupt is associated with some data receved from - * the master. If the package received from the master contains just one byte - * payload, the value of this byte is considered the address of the TPM2 - * register to reach, read or write. + * the controller. If the package received from the controller contains just + * one byte payload, the value of this byte is considered the address of the + * TPM2 register to reach, read or write. * * Real TPM register addresses can be two bytes in size (even within locality * zero), to keep the i2c protocol simple and efficient, the real TPM register @@ -34,7 +34,7 @@ * around to itself. Outside of the TPM fifo register, all other registers are * either 1 byte or 4 byte writes. * - * The master knows how many bytes to write into FIFO or to read from it by + * The controller knows how many bytes to write into FIFO or to read from it by * consulting the "burst size" field of the TPM status register. This happens * transparently for this layer. * @@ -48,13 +48,13 @@ * TODO (scollyer crosbug.com/p/56539): Should modify the register access code * so that the Host can access 1-4 bytes of a given register. * - * Master write accesses followed by data result in the register address + * Controller write accesses followed by data result in the register address * mapped, data converted, if necessary, and passed to the tpm register task. * - * Master write accesses requesting register reads result in the register + * Controller write accesses requesting register reads result in the register * address mappend and accessing the tpm task to retrieve the proper register - * data, converting it, if necessary, and passing it to the 12cs controller to - * make available for master read accesses. + * data, converting it, if necessary, and passing it to the i2cp driver to + * make available for controller read accesses. * * Again, both read and write accesses complete on the same interrupt context * they were invoked on. @@ -94,8 +94,8 @@ static void process_read_access(uint16_t reg_size, uint8_t reg_value[4]; /* - * The master wants to read the register, read the value and pass it - * to the controller. + * The controller wants to read the register, read the value and pass it + * to the interface. */ if (reg_size == 1 || reg_size == 4) { /* Always read regsize number of bytes */ |